Multi-channel ADC current signal acquisition and processing system and method

Abstract

The invention relates to the technical field of signal processing, and discloses a multichannel ADC current signal acquisition and processing system and method, and the system comprises a multichannel ADC analog-to-digital conversion module which is used for converting an input analog current signal into a digital signal; the FPGA main control unit is used for receiving and processing the digital signal output by the multi-channel ADC analog-to-digital conversion module; the clock synchronization module is used for generating multiple paths of homologous clock signals and respectively providing the multiple paths of homologous clock signals to the multi-channel ADC analog-to-digital conversion module and the FPGA main control unit; the signal conditioning circuit is used for carrying out amplification, filtering and differential conversion on the input current signal; and the data transmission interface is used for transmitting the data processed by the FPGA main control unit to an upper computer or external storage equipment. According to the invention, the FPGA main control unit and the multi-channel ADC analog-to-digital conversion module are combined, so that high-precision, high-transmission-rate, high-synchronization acquisition and high-speed digital information processing are realized under multi-channel analog signal transmission.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and particularly relates to a multi-channel ADC current signal acquisition and processing system and method. Background Art

[0002] With the rapid development of devices for measuring and acquiring analog signals, most of the current analog acquisition modules on the market still use ordinary single-chip high-speed ADC analog converters. The advantage of such ADC analog converters is high speed, but they have low resolution, poor anti-interference ability, and high requirements for the transmission process.

[0003] High-speed FPGAs have the advantages of high flexibility, low cost, and fast calculation in applications, and are applied to the fields of high-performance computing and control systems. However, there are still some deficiencies in the co-design of FPGA and ADC in existing solutions:

[0004] Most FPGAs do not deeply integrate high-speed serial interface protocols, resulting in low data transmission efficiency between the ADC and the FPGA, unable to fully utilize the performance potential of the high-speed ADC. At the same time, there is no temporary data cache module to optimize data calling and reading. Summary of the Invention

[0005] In view of the deficiencies of the existing technology, the present invention proposes a multi-channel ADC current signal acquisition and processing system and method to solve the above technical problems.

[0006] In a first aspect, a multi-channel ADC current signal acquisition and processing system is provided, including:

[0007] A multi-channel ADC analog-to-digital conversion module for converting the input analog current signal into a digital signal;

[0008] An FPGA main control unit for receiving and processing the digital signal output by the multi-channel ADC analog-to-digital conversion module;

[0009] A clock synchronization module for generating multiple paths of homologous clock signals and respectively providing them to the multi-channel ADC analog-to-digital conversion module and the FPGA main control unit;

[0010] A signal conditioning circuit for amplifying, filtering, and differential-converting the input current signal;

[0011] A data transmission interface for transmitting the data processed by the FPGA main control unit to the host computer or an external storage device;

[0012] A RAM storage chip for flexibly storing and retrieving the data generated by the multi-channel ADC analog-to-digital conversion module according to the actual needs of the host computer.

[0013] Further, the multi-channel ADC analog-to-digital conversion module includes multiple ADC chips, and each ADC chip corresponds to a current signal input channel.

[0014] Further, the signal conditioning circuit includes a differential amplifier and an anti-aliasing filter.

[0015] Further, the clock synchronization module adopts a dual-phase-locked loop structure.

[0016] Further, it further includes:

[0017] A power management module, which provides a regulated power supply for the multi-channel ADC analog-to-digital conversion module, the FPGA main control unit, the clock synchronization module, and the signal conditioning circuit.

[0018] Further, the power management module adopts a DC-DC converter.

[0019] In a second aspect, a multi-channel ADC current signal acquisition and processing method is provided. According to the multi-channel ADC current signal acquisition and processing system described in any one of the foregoing, it includes:

[0020] Performing differential amplification and anti-aliasing filtering on the multi-channel input current signals through the signal conditioning circuit;

[0021] Utilizing the multi-channel homologous clock signals generated by the clock synchronization module to trigger synchronous sampling of the multi-channel ADC analog-to-digital conversion module;

[0022] Transmitting the digital signals output by the multi-channel ADC analog-to-digital conversion module to the FPGA main control unit through a high-speed interface;

[0023] Performing real-time calibration, digital filtering, and frequency-domain analysis on the multi-channel data in the FPGA main control unit;

[0024] Sending the processing result to the host computer through a data transmission interface or temporarily storing the data in a RAM storage chip according to the requirements of the host computer.

[0025] Further, the signal processing algorithms in the FPGA main control unit include:

[0026] Performing real-time calibration on the digital signals output by the multi-channel ADC analog-to-digital conversion module;

[0027] Suppressing high-frequency noise through a digital filtering algorithm and extracting the effective signal frequency band;

[0028] Adopting a parallel processing architecture to perform time-domain or frequency-domain analysis on the multi-channel data, and generating comprehensive parameters including amplitude, frequency, and phase information.

[0029] The invention adopting the above technical solution has the following advantages:

[0030] The present invention combines an FPGA main control unit and a multi-channel ADC analog-to-digital conversion module, thereby achieving high-precision, high transmission rate, high synchronous acquisition, and high-speed digital information processing under multi-channel analog signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific embodiments of the present invention, the drawings required for the specific embodiments will be briefly introduced below. In all the drawings, the elements or parts are not necessarily drawn to actual scale.

[0032] Figure 1 It is a flowchart of a multi-channel ADC current signal acquisition and processing system of the present invention;

[0033] Figure 2 It is a simulation schematic diagram of a three-phase current source in a multi-channel ADC current signal acquisition and processing system of the present invention;

[0034] Figure 3 It is a simulation schematic diagram of VDS data transmission in a multi-channel ADC current signal acquisition and processing system of the present invention;

[0035] Figure 4 It is a diagram of an analog-to-digital conversion chip in a multi-channel ADC current signal acquisition and processing system of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0037] The terms "first", "second", etc. in the specification and claims of the present application and the above drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes unlisted steps or units, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0038] References to "embodiments" in this application mean that specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0039] As Figures 1 to 4 shown, a multi-channel ADC current signal acquisition and processing system of the present invention includes:

[0040] A multi-channel ADC analog-to-digital conversion module for converting an input analog current signal into a digital signal;

[0041] An FPGA main control unit for receiving and processing the digital signal output by the multi-channel ADC analog-to-digital conversion module;

[0042] A clock synchronization module for generating multiple channels of homologous clock signals and providing them to the multi-channel ADC analog-to-digital conversion module and the FPGA main control unit respectively;

[0043] A signal conditioning circuit for amplifying, filtering, and differential converting the input current signal;

[0044] A data transmission interface for transmitting the data processed by the FPGA main control unit to a host computer or an external storage device;

[0045] A ram storage chip for flexibly storing and dispatching (storing information and scheduling information) the data generated by the multi-channel ADC analog-to-digital conversion module according to the actual needs of the host computer.

[0046] In this embodiment, the multi-channel ADC analog-to-digital conversion module includes multiple ADC chips, and each ADC chip corresponds to a current signal input channel.

[0047] In this embodiment, the signal conditioning circuit includes a differential amplifier and an anti-aliasing filter.

[0048] In this embodiment, the clock synchronization module adopts a dual-phase-locked loop structure.

[0049] In this embodiment, it further includes:

[0050] A power management module for providing a regulated power supply to the multi-channel ADC analog-to-digital conversion module, the FPGA main control unit, the clock synchronization module, and the signal conditioning circuit.

[0051] In this embodiment, the power management module adopts a DC-DC converter.

[0052] Specifically, the design of this system mainly uses the Xilinx Vivado software as the development and programming platform, and the main control chip inside is the field programmable gate array of the Xilinx Artix-7 series (i.e., FPGA).

[0053] This chip can provide a high-performance power consumption ratio architecture and GTP high-speed transceivers for the program. The software part of the acquisition system mainly uses the high-speed FPGA chip to describe the language Verilog programming to implement the main functions of the system, including multi-chip high-speed ADC control module, clock chip module, system main control module and data parsing and mapping module.

[0054] This system uses the LMK04828 clock chip as the core circuit of the clock chip module. The LMK04828 clock chip internally uses a dual-phase-locked loop structure. This structure can make the generated clock have ultra-low jitter, the ability of radio frequency sampling, and can also simplify the system function. The supply voltage of this chip is 3.3V. The reference clock of the PLL is generated by the SiT910 crystal oscillator and input into the three pins of CLKINO, CLKIN1, and OSCin. The chip is configured through the SPI protocol to make the DCLKOUT pin generate multiple channels of homologous clocks, and respectively provide device clocks and synchronous clocks for the ADC and FPGA.

[0055] At the same time, the SDCLKout pin outputs the SYSREF synchronization signal to achieve clock alignment of the data link.

[0056] In the system design, this clock chip generates a total of 5 channels of differential clocks, and the differential traces are impedance-matched by connecting a 100Ω resistor. The CPout1 pin generates a high level to enable the backup crystal oscillator when the external clock source fails to maintain the chip's continuous operation.

[0057] The data collected by this system enters the multi-channel ADC analog-to-digital conversion module through the analog front-end circuit to generate differential signals. The multi-channel ADC analog-to-digital conversion module then converts the analog signals into digital signals, and then transmits them to the high-speed FPGA main control unit through JESD204B to achieve the function.

[0058] The main control module of the system is responsible for the transfer of flag bits and information transmission between modules, completes the reception and processing of digital signals through the JESD204B interface logic, transmits the processed data to the host computer to complete high-speed data acquisition, connects the multi-channel ADC analog-to-digital conversion module carrying the JESD204B protocol to the FPGA main control unit during transmission, and summarizes the transmitted information through VDS.

[0059] In some other embodiments, a method for collecting and processing multi-channel ADC current signals is provided. A multi-channel ADC current signal collection and processing system according to any one of the foregoing includes:

[0060] Step S01: Differentially amplify and anti-alias filter the multi-channel input current signals through a signal conditioning circuit;

[0061] Step S02: Use the multi-channel homologous clock signals generated by the clock synchronization module to trigger the multi-channel ADC analog-to-digital conversion module to synchronously sample;

[0062] Step S03: Transmit the digital signals output by the multi-channel ADC analog-to-digital conversion module to the FPGA main control unit through a high-speed interface;

[0063] Step S04: Perform real-time calibration, digital filtering, and frequency-domain analysis on the multi-channel data in the FPGA main control unit;

[0064] Step S05: When data comparison and analysis are required in the host computer, directly call the stored data of the ram storage chip without accessing the data in the memory, and send it to the host computer through the FPGA main control unit;

[0065] Step S06: Temporarily store special case data during data analysis in the host computer;

[0066] Step S07: Send the processing result to the host computer through a data transmission interface.

[0067] In this embodiment, the signal processing algorithm in the FPGA main control unit includes:

[0068] Perform real-time calibration on the digital signals output by the multi-channel ADC analog-to-digital conversion module;

[0069] Suppress high-frequency noise through a digital filtering algorithm and extract the effective signal frequency band;

[0070] Adopt a parallel processing architecture to perform time-domain or frequency-domain analysis on multi-channel data, and generate comprehensive parameters including amplitude, frequency, and phase information.

[0071] Specifically, the selected analog-to-digital conversion module in this design is ADC14X250, which follows the JESD204B protocol to construct a serial bus architecture. This device has the characteristic that its functions can be set through a 4-wire SPI. According to a series of parameters supported by the ADC, such as the number of channels, frame construction form, subclass mode, number of converters, and resolution, etc., the IP core is adaptively set according to the AXI bus protocol. The AXI bus protocol covers a total of five channels, which can generally be classified into two types of transactions: read operations and write operations.

[0072] The write operation transaction consists of a write address channel, a write data channel, and a write response channel, while the read operation transaction is composed of a read address channel and a read data channel. Each channel relies on the two handshake signals VAILD and EADY to achieve the data transmission control function. Only when both of these signals are at the high level, the data will start the transmission process.

[0073] The ram memory chip is hardware-connected with an FPGA. RAS is the row address strobe, CAS is the column address strobe, and A0 - A23 are the data port parts. Considering the actual hardware cost, this solution uses 3 pieces of 8x8192bit to be spliced and designed into a 24x8192bit memory.

[0074] Three pieces of ram use the same chip select and clock control signals, and the data port parts are designed differently. The data of the A0 - A7 part is stored and designed with the first piece of ram, the data of A8 - A15 is stored with the second piece of ram, and the data of A16 - A23 is stored with the second piece of ram.

[0075] Specific working principle: The master_flga_ram control signal is sent from the host computer (according to the actual program execution requirements) to the FPGA main control unit, and this part of the design is enabled by the FPGA main control unit. At the same time, the FPGA will send a feedback enable signal of slave_en to the host computer.

[0076] The actually collected information is stored in the ram memory chip, and then the stored data of the ram memory chip is selected and called according to the actual program requirements of the host computer and sent to the host computer.

[0077] The construction of this system takes the FPGA main control unit as the main control role. After the system is powered on and reset, the LMK clock chip is configured so that it can generate an appropriate working clock and synchronous clock. Subsequently, the setting operation of the ADC function parameters and the configuration process of the JESD204B IP core are carried out.

[0078] When the SYNC signal level is pulled low, the synchronization request immediately starts the sending process. Frame synchronization, code group synchronization, and initial channel synchronization are carried out in sequence one by one. After the SYNC signal synchronization request, a synchronization signal is generated after being triggered by the rising edge of the next clock. Among them, for the synchronization code design, two synchronization registers are used to re - synchronize the SYNC signal to avoid the generation of metastability. The synchronization code needs to be sent within 2 - 3 compliance cycles through the training sequence, and it is detected whether the signal generated by the actual hardware loopback works properly. If it does not work properly, the SYNC signal synchronization request is carried out 3 times. If it still does not work properly, an error message is generated and sent to the host computer for analysis and decision by the host computer.

[0079] The timing requirement is to use the global clock network of the FPGA master control unit to drive the SYNVC signal detection logic. After SYNC is pulled low, the first synchronization code needs to be sent within <= 1 microsecond to ensure a low-latency path. Since the output data of this multi-channel ADC analog-to-digital conversion module uses the binary complement coding form, the binary number after acquisition and conversion must first be converted into a signed decimal number, and then the analog voltage value is calculated according to the following formula.

[0080] After calculation, the result is consistent with the voltage amplitude output by the signal generator.

[0081]

[0082] Among them, VIN+ and VIN- are the differential analog input voltages of the ADC, Ndec is the signed decimal value after binary conversion, N is the data precision, and VREF is the reference voltage.

[0083] The original sampling data is processed by fast Fourier transform operation to obtain its spectrum. The data acquisition process first performs data preprocessing: verifying sampling (ensuring that the original data is a real sequence of equally spaced samples), detrending, and windowing. The post-processing analysis method of the spectrum after data acquisition is as follows: peak detection (identifying the main frequency part in the signal), frequency-amplitude mapping (combining the frequency axis and the amplitude spectrum to obtain a spectrogram), and finally visualizing the obtained data to get a spectrogram.

[0084] Frequency resolution Δf: Determines the minimum frequency interval that can be distinguished.

[0085] fs: Sampling frequency (unit: Hz), which represents the number of samples collected per second and needs to satisfy the Nyquist criterion (fs ≥ 2fmax);

[0086] N: Number of sampling points, usually taking an integer power of 2 to adapt to the FFT algorithm;

[0087] Δf: Frequency resolution (unit: Hz), which determines the minimum frequency interval of spectrum analysis.

[0088] (Example: When fs = 1000Hz and N = 1024, Δf ≈ 0.977Hz)

[0089] For the FFT module part, first satisfy the Nyquist theorem to avoid aliasing signals and causing errors in the sampled signals. Among them, for the number of sampling points N = 32768, which satisfies being a power of 2, it improves the FFT calculation efficiency. The efficient algorithm FFT is used for DFT to reduce the computational complexity from O(N^2) to O(log N). The DFT formula is:

[0090]

[0091] x[n]: discrete time-domain signal sequence, n ∈ [0, N - 1];

[0092] X[k]: complex spectrum component corresponding to the k-th frequency point;

[0093] j: imaginary unit (j^2 = -1);

[0094] k: frequency index number, corresponding to the actual frequency f = k·Δf.

[0095] The complex sequence X[k] is obtained through calculation and analysis, and then the amplitude and phase information therein is extracted.

[0096] Normalization is performed on |X[k]|, that is, the single-sided spectrum needs to be multiplied by 2 / N to obtain the amplitude spectrum:

[0097]

[0098] Re(X[k]): real part of the spectrum, reflecting the similarity between the signal and the cosine basis function;

[0099] Im(X[k]): imaginary part of the spectrum, reflecting the similarity between the signal and the sine basis function;

[0100] ∠X[k]: phase angle (unit: radian), characterizing the initial phase of the signal at the frequency point;

[0101] Considering that the signal model may be a sine wave F(x) = A sin(2πft + φ), where A is the amplitude and φ is the phase.

[0102] It can be seen from the spectrum analysis results that under the condition of normal operation of the system, the performance of the ADC analog-to-digital conversion module meets the requirements, the restored sine waveform is accurate, and the data acquisition function operates normally.

[0103] This design combines a high-speed FPGA main control unit and a multi-channel ADC analog-to-digital conversion module, so as to achieve high-precision, high transmission rate, high synchronous acquisition and high-speed digital information processing under the transmission of multi-channel analog signals. And the signal is transmitted and processed by VDS, so that it has a high transmission signal and anti-interference ability, the digital signal is not easy to make mistakes, and the repetition caused by verification errors can be avoided.

[0104] The differential signal output by the AC secondary voltage (current) conversion module ranges from -10V to +10V. Then, it first passes through a low-pass filter and is then connected to an analog-to-digital converter with a high sampling rate and low latency. After that, the obtained measurement values are transmitted to the FPGA master control unit through the JESD204B interface protocol. The data measured by the multi-channel ADC analog-to-digital conversion module is specifically designed by the FPGA master control unit and sent to the host through the VDS differential signal.

[0105] The single-chip ADC designed in this module has 24 analog input channels, with a maximum sampling rate of up to 200MHZ, a conversion accuracy of 24 bits, and a latency time within 5us. Through functional tests, the minimum acquisition and processing link latency time, that is, the time difference from the start of sampling by the acquisition and processing board, through data aggregation, analog-to-digital conversion, packetization, and data forwarding to JESD204B, does not exceed 40us, and the measurement accuracy is ±0.2%. This can fully meet the requirements in aspects such as DC protection and control, as well as fault recording, and can also reduce transmission errors caused by other factors during transmission.

[0106] This design can solve the data resource scheduling and optimization problems of the host computer:

[0107] When data comparison and analysis are required in the host computer, there is no need to access the data in the memory. Instead, the stored data of the ram storage chip can be directly called and sent to the host computer through the FPGA master control unit, reducing the time overhead of data reading and improving the overall operation efficiency.

[0108] When the host computer conducts data analysis, special case data is temporarily stored for convenient subsequent transfer.

[0109] It also utilizes the high reading speed of the ram storage chip. For example, the continuous reading speed of DDR4 can reach about 60GB / s to improve the overall program operation efficiency.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered by the scope of the claims and the description of the present invention.

Claims

1. A multi-channel ADC current signal acquisition and processing system, characterized in that Including: A multi-channel ADC analog-to-digital conversion module for converting the input analog current signal into a digital signal; An FPGA main control unit for receiving and processing the digital signal output by the multi-channel ADC analog-to-digital conversion module; A clock synchronization module for generating multiple channels of homologous clock signals and respectively providing them to the multi-channel ADC analog-to-digital conversion module and the FPGA main control unit; A signal conditioning circuit for amplifying, filtering and differential converting the input current signal; A data transmission interface for transmitting the data processed by the FPGA main control unit to a host computer or an external storage device; A ram storage chip for flexibly storing and retrieving the data generated by the multi-channel ADC analog-to-digital conversion module according to the actual requirements of the host computer.

2. The multi-channel ADC current signal acquisition and processing system according to claim 1, wherein The multi-channel ADC analog-to-digital conversion module includes multiple ADC chips, and each ADC chip corresponds to a current signal input channel.

3. A multi-channel ADC current signal acquisition and processing system according to claim 1, characterized in that, The signal conditioning circuit includes a differential amplifier and an anti-aliasing filter.

4. A multi-channel ADC current signal acquisition and processing system according to claim 1, characterized in that The clock synchronization module adopts a dual-phase-locked loop structure.

5. A multi-channel ADC current signal acquisition and processing system according to claim 1, characterized in that Also including: A power management module for providing a regulated power supply to the multi-channel ADC analog-to-digital conversion module, the FPGA main control unit, the clock synchronization module and the signal conditioning circuit.

6. A multi-channel ADC current signal acquisition and processing system according to claim 5, characterized in that, The power management module adopts a DC-DC converter.

7. A multi-channel ADC current signal acquisition and processing method, characterized in that A multi-channel ADC current signal acquisition and processing system according to any one of claims 1 to 6, including: Differentially amplifying and anti-aliasing filtering the multiple input current signals through a signal conditioning circuit; Triggering the multi-channel ADC analog-to-digital conversion module to synchronously sample by using the multiple channels of homologous clock signals generated by the clock synchronization module; Transmitting the digital signal output by the multi-channel ADC analog-to-digital conversion module to the FPGA main control unit through a high-speed interface; Performing real-time calibration, digital filtering and frequency-domain analysis on the multi-channel data in the FPGA main control unit; Sending the processing result to the host computer through the data transmission interface or temporarily storing the data in the ram storage chip according to the requirements of the host computer.

8. A method for collecting and processing multi-channel ADC current signals according to claim 7, characterized in that, The signal processing algorithm in the FPGA main control unit includes: Performing real-time calibration on the digital signal output by the multi-channel ADC analog-to-digital conversion module; Suppressing high-frequency noise through a digital filtering algorithm and extracting the effective signal frequency band; Performing time-domain or frequency-domain analysis on the multi-channel data by adopting a parallel processing architecture to generate comprehensive parameters including amplitude, frequency and phase information.

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