Resistance segmented digital-to-analog converter

Abstract

The embodiment of the invention discloses a resistor segmented digital-to-analog converter, which comprises a first resistor string, a first decoding circuit, a driving logic circuit and a first switch group, the first resistor string comprises a first level resistor string, a second level resistor string and a third level resistor string which are sequentially connected in series between the first power supply end and the second power supply end; the first output end of the first decoding circuit is connected with the input end of the driving logic circuit, the output end of the driving logic circuit is connected with the control end of the first switch group, the first switch group is connected with the second level resistor string, and the first decoding circuit forms a first logic control signal according to the digital control signal; the driving logic circuit boosts the first logic control signal to form a second logic control signal, and the first switch group controls the effective resistance of the second level resistor string according to the second logic control signal. The problem that the on-resistance of the switch at the middle part is too large is solved, the performance and stability of the digital-to-analog converter are ensured, and the cost is reduced at the same time.

Description

Technical Field

[0001] The present invention relates to the technical field of digital-to-analog converters, and particularly to a resistor segmented digital-to-analog converter. Background Art

[0002] A resistor segmented digital-to-analog converter (DAC) is crucial in a high-precision signal processing system. However, the switching resistance between the high-order resistor string and the low-order resistor string of the segmented DAC can affect the differential nonlinearity (DNL) of the DAC. As Figure 1 shown, when the switch is closed, an inherent resistance Rsw is generated. The voltage Vcd at both ends of the low-order resistor string c and d is not equal to the voltage Vab between the high-order resistor string a and b. Therefore, when the adjacent bits of the high-order resistor string are switched, if the two switches are turned on simultaneously, a part of the voltage will be divided by the switch's own resistance, affecting the DNL of the DAC.

[0003] Existing resistor segmented digital-to-analog converters are suitable for occasions where the power supply voltage range changes little. However, in many current application scenarios, the range of power supply voltage variation is quite large. Sometimes the power supply voltage can vary in the range of 2V - 5V or even lower or higher. When the low voltage, low temperature, and the transistor are in the slow process corner, since the threshold voltage of the transistor will increase significantly at low temperatures, when the switch in the middle position of the high-order resistor string is turned on, the on-resistance of the switch itself will be very large, which will affect the performance of the circuit. The method of simply increasing the transistor width-to-length ratio to reduce the on-resistance will result in a very large area of the switch and a high cost. Summary of the Invention

[0004] The present invention provides a resistor segmented digital-to-analog converter to solve the problem of excessive on-resistance of the switch in the middle part of the resistor segmented analog-to-digital converter.

[0005] According to one aspect of the present invention, there is provided a resistor segmented digital-to-analog converter, including: a first resistor string, a first decoding circuit, a driving logic circuit, and a first switch group;

[0006] The first resistor string includes a first-level resistor string, a second-level resistor string, and a third-level resistor string that are sequentially connected in series between a first power supply terminal and a second power supply terminal;

[0007] The first output terminal of the first decoding circuit is connected to the input terminal of the driving logic circuit. The output terminal of the driving logic circuit is connected to the control terminal of the first switch group. The first switch group is connected to the second-level resistor string. The first decoding circuit is configured to form a first logic control signal according to a digital control signal. The driving logic circuit is configured to boost the first logic control signal to form a second logic control signal. The first switch group is configured to control the effective resistance of the second-level resistor string according to the second logic control signal.

[0008] Optionally, it further includes a second switch group and a third switch group. The second switch group is connected to the first-level resistor string. The third switch group is connected to the third-level resistor string.

[0009] The second output terminal of the first decoding circuit is connected to the control terminal of the second switch group. The third output terminal of the first decoding circuit is connected to the control terminal of the third switch group. The first decoding circuit is configured to form a third logic control signal and a fourth logic control signal according to a digital control signal. The second switch group is configured to control the effective resistance of the first-level resistor string according to the third logic control signal. The third switch group is configured to control the effective resistance of the third-level resistor string according to the fourth logic control signal.

[0010] Optionally, it further includes a charge pump. The charge pump is connected to the power supply terminal of the driving logic circuit. The charge pump is configured to supply power to the driving logic circuit.

[0011] Optionally, the charge pump includes at least two stages of boosting units and a first inverter connected in sequence. Each stage of the boosting unit includes a first capacitor and a first switching transistor. The gate and the first pole of the first switching transistor of the first stage of the boosting unit are connected to a third power supply terminal. The second pole of the first switching transistor of the first stage of the boosting unit and the first end of the first capacitor of the first stage of the boosting unit are connected to the gate and the first pole of the first switching transistor of the next stage of the boosting unit. The second end of the first capacitor of the odd-stage boosting units and the input terminal of the first inverter are connected to a clock signal. The second end of the first capacitor of the even-stage boosting units is connected to the output terminal of the first inverter. The second pole of the first switching transistor of the last stage of the boosting unit is connected to the first end of the first capacitor of the last stage of the boosting unit and serves as the output terminal of the charge pump. The second end of the first capacitor of the last stage of the boosting unit is grounded.

[0012] Optionally, the maximum withstand voltage of the charge pump is less than or equal to 1.5 times the nominal voltage of the first switching transistor.

[0013] Optionally, the driving logic circuit includes a level conversion circuit and a buffer driving circuit. The input end of the level conversion circuit is connected to the first output end of the first decoding circuit. The output end of the level conversion circuit is connected to the input end of the buffer driving circuit. The power supply end of the level conversion circuit is connected to the output end of the charge pump. The level conversion circuit is used to boost the first logic control signal to form the second logic control signal. The output end of the buffer driving circuit is connected to the control end of the first switch group. The buffer driving circuit is used to improve the driving ability of the second logic control signal.

[0014] Optionally, the resistor segmented digital-to-analog converter further includes: a second resistor string, a fourth switch group, and a second decoding circuit;

[0015] The first end of the second resistor string is connected to one end of the effective resistance of the first resistor string through one switch in the first switch group, the second switch group, and the third switch group. The other end of the second resistor string is connected to the other end of the effective resistance of the first resistor string through another switch in the first switch group, the second switch group, and the third switch group;

[0016] The output end of the second decoding circuit is connected to the control end of the fourth switch group. The second decoding circuit is used to form a fifth logic control signal according to the digital control signal;

[0017] The fourth switch group is connected to the second resistor string. The fourth switch group is used to control the effective resistance of the second resistor string according to the fifth logic control signal.

[0018] Optionally, the sum of the number of switches in the first switch group, the second switch group, and the third switch group is equal to the number of resistors in the first resistor string. The first switch group, the second switch group, and the third switch group include at least two switches. The first end of each switch is connected to the first end of a resistor in the first resistor string. At least two of the switches are gated according to the second logic control signal, the third logic control signal, and the fourth logic control signal to select two switches. One of the switches has its second end connected to the first end of the second resistor string, and the other switch has its second end connected to the second end of the second resistor string.

[0019] Optionally, the switches in the first switch group adopt switches with a CMOS structure.

[0020] Optionally, the switches in the second switch group adopt switches with a PMOS transistor structure, and the switches in the third switch group adopt switches with an NMOS transistor structure.

[0021] In the technical solution of the embodiment of the present invention, each resistor in the first resistor string is correspondingly connected to a switch. By dividing the first resistor string into three groups, the corresponding switches are also divided into three groups. After the first decoding circuit decodes the digital control signal, a logic control signal for controlling the switch is generated. The first logic control signal of the first switch group, which is the most sensitive to the changes in the power supply voltage and temperature, is boosted by a driving logic circuit to form a second logic control signal. The driving logic circuit can increase the level of the switch control signal from the power supply voltage, and the voltage difference between the second logic control signal and the transmitted voltage increases, and the on-resistance of the switch decreases. Especially in the case of low voltage and low temperature, the effect is the most significant. The switches of the first switch group do not need to be designed with a large size after the control voltage increases. The problem of excessive on-resistance of the switches in the middle part of the resistor segmented analog-to-digital converter is solved, the performance and stability of the resistor segmented analog-to-digital converter are ensured, and the cost is reduced at the same time.

[0022] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0024] Figure 1 is a schematic diagram of the influence of the switch resistance on the segmented resistor type digital simulator in the related art;

[0025] Figure 2 is a schematic structural diagram of a resistor segmented digital-to-analog converter provided by an embodiment of the present invention;

[0026] Figure 3 is a schematic structural diagram of another resistor segmented digital-to-analog converter provided by an embodiment of the present invention;

[0027] Figure 4 is a schematic structural diagram of a charge pump circuit provided by an embodiment of the present invention;

[0028] Figure 5 is a schematic structural diagram of yet another resistor segmented digital-to-analog converter provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0031] Figure 2 is a schematic structural diagram of a resistor segmented digital-to-analog converter provided by an embodiment of the present invention. This embodiment is applicable to scenarios of generating high-performance and high-linearity analog signals, such as industrial control, automotive electronics, and consumer electronics and other fields. As Figure 2 shown, the resistor segmented digital-to-analog converter includes: a first resistor string 101, a first decoding circuit 102, a driving logic circuit 103, and a first switch group 104;

[0032] The first resistor string 101 includes a first-level resistor string 1011, a second-level resistor string 1012, and a third-level resistor string 1013 that are sequentially connected in series between a first power supply terminal AVDD and a second power supply terminal AGND;

[0033] The first output terminal of the first decoding circuit 102 is connected to the input terminal of the driving logic circuit 103, the output terminal of the driving logic circuit 103 is connected to the control terminal of the first switch group 104, the first switch group 104 is connected to the second-level resistor string 1012, the first decoding circuit 102 is configured to form a first logic control signal according to a digital control signal, the driving logic circuit 103 is configured to boost the first logic control signal to form a second logic control signal, and the first switch group 104 is configured to control the effective resistance of the second-level resistor string 1012 according to the second logic control signal.

[0034] Among them, the total number of bits of the DAC and the number of bits of the high-order resistor string and the low-order resistor string can be adjusted and determined according to actual needs. Taking a 12-bit DAC as an example, the high 7 bits are the first resistor string. The number of resistors in the first resistor string 101 can be 128, which are the first resistor R0 to the one hundred and twenty-eighth resistor R127 respectively. Each resistor is correspondingly connected to a switch, that is, the first switch SW0 - the one hundred and twenty-eighth switch SW127. The first resistor string 101 can be divided into three groups, and the corresponding switches are also divided into three groups. The first resistor string 101 includes the first-level resistor string 1011, the second-level resistor string 1012, and the third-level resistor string 1013. They are connected end to end and are integrally connected between the first power supply terminal AVDD and the second power supply terminal AGND. The first power supply terminal AVDD can be the power supply voltage, and the second power supply terminal AGND can be the ground. The first resistor string 101 forms a voltage dividing network. The current flows from the first power supply terminal AVDD through the entire resistor string to the second power supply terminal AGND. By controlling the conduction or cutoff of the switches corresponding to the resistors, different voltage drops can be generated at each resistor node. The first decoding circuit 102 can input multiple digital control signals. For example, if the first resistor string 101 has 128 resistors, the first decoding circuit 102 inputs seven digital control signals. After logical operations of the first decoding circuit 102, 128 logical control signals K0 - K127 are output, which are used to control the first switches SW0 - the one hundred and twenty-eighth switch SW127 corresponding to the first resistor string 101. The voltages transmitted by the eighty-fifth switch SW84 - the one hundred and twenty-eighth switch SW127 are close to the power supply voltage, and the voltages transmitted by the first switch SW0 - the fifty-fourth switch SW53 are close to the ground potential. Therefore, no special treatment is required for their control voltages. The first switch group 104 includes the fifty-fifth switch SW54 - the eighty-fourth switch SW83. Since the transmitted voltage is in the middle position between the power supply and the ground potential, the voltage difference between the voltage for controlling the switch to conduct and the voltage transmitted by the switch will be relatively small, which will result in a relatively large on-resistance of these switches, thus affecting the conversion rate and accuracy of the DAC. Especially when the power supply voltage is low and the temperature is low, the performance of the DAC will drop more significantly. In actual circuit applications, the number of switches in the first switch group 104 can be flexibly selected according to performance indicators such as the working environment and accuracy of the circuit. According to different working environments and performance indicators of the DAC, such as different working voltage ranges, temperature ranges, conversion rates, and conversion accuracies, the number of switches that need to increase the control voltage is adjusted to achieve the best compromise between performance and cost. The driving logic circuit 103 receives the first logical control signals K54 - K83 output from the first output terminal of the first decoding circuit 102, boosts the first logical control signals K54 - K83 output from the first output terminal, and obtains the second logical control signals KH54 - KH83. The boosting ensures that the switches in the first switch group 104 can achieve low-resistance conduction, improving the linearity and accuracy of the DAC.The conduction or cutoff of the first switch group 104 is controlled by the second logic control signals KH54-KH83, so as to connect the second-level resistor string 1012 in series to the circuit or disconnect it, thereby controlling the effective resistance of the second-level resistor string 1012.

[0035] Specifically, taking a 12-bit DAC as an example, the high seven bits are the first resistor string 101. The seven-bit digital control signal is input to the first decoding circuit 102 to generate 128 logic control signals K0-K127. The 128 logic control signals are divided into three groups. The logic control signals K0-K53 at the third output terminal of the first decoding circuit 102 are a group, which are used to directly control the first switch SW0 - the fifty-fourth switch SW53. The logic control signals K84-K127 at the second output terminal of the first decoding circuit 102 are a group, which are used to directly control the eighty-fifth switch SW84 - the one-hundred-and-twenty-eighth switch SW127. The first logic control signals K54-K83 at the first output terminal of the first decoding circuit 102 generate the second logic control signals KH54-KH83 after passing through the driving logic circuit 103, which are used to control the fifty-fifth switch SW54 - the eighty-fourth switch SW83. The first switch group 104 changes the state of its switches according to the second logic control signals KH54-KH83, thereby changing the effective resistance of the second-level resistor string 1012. Since the voltage of the second logic control signals KH54-KH83 has increased, the voltage difference between the second logic control signals KH54-KH83 and the transmitted voltage increases, and the on-resistance of the switches decreases.

[0036] In the technical solution of the embodiment of the present invention, each resistor in the first resistor string is correspondingly connected to a switch. By dividing the first resistor string into three groups, the corresponding switches are also divided into three groups. After the first decoding circuit decodes the digital control signal, it generates the logic control signal for controlling the switch. The first logic control signal of the first switch group that is most sensitive to the power supply voltage and temperature change is boosted by the driving logic circuit to form the second logic control signal. The driving logic circuit can raise the level of the switch control signal from the power supply voltage. The voltage difference between the second logic control signal and the transmitted voltage increases, and the on-resistance of the switch decreases. Especially, the effect is the most obvious in the case of low voltage and low temperature.. The switches of the first switch group do not need to be designed with a large size after the control voltage increases. It solves the problem that the on-resistance of the switches in the middle part of the resistor string type analog-to-digital converter is too large, ensures the performance and stability of the DAC, and reduces the cost at the same time.

[0037] Continue to refer to Figure 2, the resistor segmented digital-to-analog converter further includes a second switch group 105 and a third switch group 106. The second switch group 105 is connected to the first-level resistor string 1011, and the third switch group 106 is connected to the third-level resistor string 1013. The second output terminal of the first decoding circuit 102 is connected to the control terminal of the second switch group 105, and the third output terminal of the first decoding circuit 102 is connected to the control terminal of the third switch group 106. The first decoding circuit 102 is configured to form a third logic control signal and a fourth logic control signal according to the digital control signal; the second switch group 105 is configured to control the effective resistance of the first-level resistor string 1011 according to the third logic control signal, and the third switch group 106 is configured to control the effective resistance of the third-level resistor string 1013 according to the fourth logic control signal.

[0038] Among them, the second switch group 105 includes the eighty-fifth switch SW84 to the one-hundred-and-twenty-eighth switch SW127, which are connected to the resistors of the first-level resistor string 1011 in one-to-one correspondence, and its control terminal is connected to the second output terminal of the first decoding circuit 102. According to the third logic control signals K84-K127 output from the second output terminal of the first decoding circuit 102, the second switch group 105 can be directly controlled, so as to control the effective resistance of the first-level resistor string 1011. The third switch group 106 includes the first switch SW0 to the fifty-fourth switch SW53, which are connected to the resistors of the third-level resistor string 1013 in one-to-one correspondence, and its control terminal is connected to the third output terminal of the first decoding circuit 102. According to the fourth logic control signals K0-K53 output from the third output terminal of the first decoding circuit 102, the third switch group 106 can be directly controlled, so as to control the effective resistance of the third-level resistor string 1013. The third logic control signal and the fourth logic control signal can directly drive their corresponding switch groups, while the first logic control signal needs to be boosted by the driving logic circuit 103 before it can drive the first switch group 104. The first decoder 102 generates logic control signals according to the digital control signal, controls two switches to close and other switches to open, so as to control the effective resistance of the first resistor string 101.

[0039] Figure 3 is a schematic structural diagram of another resistor segmented digital-to-analog converter provided by an embodiment of the present invention. In some optional embodiments of the present invention, such as Figure 3 shown, the resistor segmented digital-to-analog converter further includes a charge pump 107. The charge pump 107 is connected to the power supply terminal of the driving logic circuit 103, and the charge pump 107 is used to supply power to the driving logic circuit 103.

[0040] Among them, the charge pump 107 can boost the power supply voltage and use the boosted voltage as the power supply for driving the logic circuit 103. The driving logic circuit 103 can convert the first logic control signals K54-K83 output from the first output terminal of the first decoding circuit 102 into the second logic control signals KH54-KH83 after boosting, which are used to control the fifty-fifth switch SW54 - the eighty-fourth switch SW83. Since the voltage of the second logic control signals KH54-KH83 has been boosted, the voltage difference between the control signal and the transmitted voltage increases, and the on-resistance of the switch decreases.

[0041] Figure 4 is a schematic structural diagram of a charge pump circuit provided by an embodiment of the present invention. In some alternative embodiments of the present invention, such as Figure 3 and Figure 4 shown, the charge pump 107 includes at least two stages of boosting units 1071 and a first inverter N1 connected in sequence; each stage of the boosting unit 1071 includes a first capacitor C1 and a first switching transistor S1; the gate and the first pole of the first switching transistor S1 of the first stage of the boosting unit are connected to the third power supply terminal VDD, the second pole of the first switching transistor S1 of the first stage of the boosting unit and the first end of the first capacitor C1 of the first stage of the boosting unit are connected to the gate and the first pole of the first switching transistor S1 of the next stage of the boosting unit, the second end of the first capacitor C1 of the odd-stage boosting unit and the input terminal of the first inverter N1 are connected to the clock signal CLK, the second end of the first capacitor C1 of the even-stage boosting unit is connected to the output terminal of the first inverter N1, the second pole of the first switching transistor S1 of the last stage of the boosting unit is connected to the first end of the first capacitor C1 of the last stage of the boosting unit and serves as the output terminal of the charge pump 107, and the second end of the first capacitor C1 of the last stage of the boosting unit is grounded.

[0042] Among them, the charge pump 107 can be a Dickson charge pump. Generally, a Dickson charge pump is cascaded in multiple stages. The more stages there are, the higher the voltage finally output by the charge pump 107. The voltage output by the charge pump 107 is also related to the frequency of the clock signal CLK of the charge pump 107. In actual use, the output voltage of the charge pump 107 can also be adjusted by adjusting the frequency of the clock signal CLK of the charge pump 107. Considering that if the output voltage of the charge pump 107 is too high, there is a risk that the switch it controls will be broken down by high voltage. The technical solution of the present invention can adopt a charge pump cascaded in two stages. The first pole of the first switching tube S1 can be the source electrode, and the second pole of the first switching tube S1 can be the drain electrode. When a clock signal CLK is input, the second end of the first capacitor C1 of the odd-stage boosting unit 1071 will periodically change its potential under the action of the clock signal CLK. In the first-stage boosting unit 1071, since the gate and the first pole of the first switching tube S1 are connected to the third power supply terminal VDD, when there is enough voltage to turn on the switching tube, the current flows from the third power supply terminal VDD to its second pole and the first end of the connected first capacitor C1, thereby affecting the voltage of the gate and the first pole of the first switching tube S1 in the next-stage boosting unit 1071. Under the action of the clock signal CLK, the first capacitor C1 and the first switching tube S1 in each boosting unit 1071 cooperate with each other to realize the transfer and accumulation of charges. The odd-stage boosting unit 1071 transfers charges to the next stage under the drive of the clock signal CLK, while the even-stage boosting unit 1071 further boosts the potential and transfers charges under the drive of the output signal of the first inverter N1, thereby gradually boosting the output voltage of the entire charge pump. The second end of the first capacitor C1 of the last-stage boosting unit 1071 is grounded to provide a reference potential for the accumulation and output of charges, and its output terminal outputs a higher voltage after being boosted in multiple stages. The frequency range and the number of stages selected in actual use should be selected according to factors such as voltage, power consumption, and cost in different scenarios. The charge pump 107 can change the level of the output voltage and the current driving ability of the output voltage of the charge pump 107 by changing the frequency of the clock signal CLK, while ensuring the performance of the DAC and avoiding too high voltage, thereby causing reliability problems.

[0043] In some alternative embodiments of the present invention, with continued reference to Figure 3 and Figure 4 , the maximum withstand voltage of the charge pump 107 is less than or equal to 1.5 times the nominal voltage of the first switching tube S1.

[0044] Among them, the voltage output by the charge pump 107 is related to the frequency of the clock signal CLK that drives the charge pump 107. When the frequency is high, the output voltage is relatively high; when the frequency is low, the output voltage is relatively low. Therefore, a suitable frequency needs to be selected to ensure that the output voltage of the charge pump 107 is high enough at low temperature and low voltage to ensure the stable performance of the DAC at this time. At the same time, it is necessary to consider that the voltage output by the charge pump 107 at high temperature and high voltage will not be too high to cause reliability problems of the transistor. The maximum tolerable voltage of the charge pump 107 is less than or equal to 1.5 times the nominal voltage of the first switching transistor S1, and no reliability problems of the device will be caused at this time.

[0045] In some alternative embodiments of the present invention, with continued reference to Figure 3 , the driving logic circuit 103 includes a level conversion circuit 1031 and a buffer driving circuit 1032. The input end of the level conversion circuit 1031 is connected to the first output end of the first decoding circuit 102. The output end of the level conversion circuit 1031 is connected to the input end of the buffer driving circuit 1032. The power supply end of the level conversion circuit 1031 is connected to the output end of the charge pump 107. The level conversion circuit 1031 is used to boost the first logic control signal to form a second logic control signal; the output end of the buffer driving circuit 1032 is connected to the control end of the first switch group 104, and the buffer driving circuit 1031 is used to improve the driving ability of the second logic control signal.

[0046] Among them, the output voltage of the charge pump circuit can be used as the power supply for the level conversion circuit 1031 and the buffer driving circuit 1032. At this time, the high level of the control signals output by the level conversion circuit 1031 and the buffer driving circuit 1032 is higher than the power supply voltage. The level conversion circuit 1031 can boost the first logic control signals K54 - K83 to form second logic control signals KH54 - KH83 for controlling the switches of the first switch group 104. The buffer driving circuit 1032 is used to improve the driving ability of the second logic control signals KH54 - KH83 to drive the switches of the first switch group 104. A control signal with a higher voltage will effectively reduce the on-resistance of the switch it controls, especially significant in the case of low voltage and low temperature. Moreover, after increasing the control voltage, the size of the switch does not need to be designed very large, and the area cost of the chip is smaller.

[0047] Figure 5 is a schematic structural diagram of another resistor segmented digital-to-analog converter provided by an embodiment of the present invention. In some alternative embodiments of the present invention, as Figure 5 shown, the resistor segmented digital-to-analog converter further includes: a second resistor string 201, a fourth switch group 202, and a second decoding circuit 203;

[0048] The first end of the second resistor string 201 is connected to one end of the effective resistance of the first resistor string 101 through one switch in the first switch group 104, the second switch group 105, and the third switch group 106, and the other end of the second resistor string 201 is connected to the other end of the effective resistance of the first resistor string 101 through another switch in the first switch group 104, the second switch group 105, and the third switch group 106;

[0049] The output end of the second decoding circuit 203 is connected to the control end of the fourth switch group 202, and the second decoding circuit 203 is used to form a fifth logic control signal OUT<0-32> according to the digital control signal;

[0050] The fourth switch group 202 is connected to the second resistor string 201, and the fourth switch group 202 is used to control the effective resistance of the second resistor string 201 according to the fifth logic control signal.

[0051] Among them, the second resistor string 201 is a low-order resistor string. Taking a 12-bit DAC as an example, the high seven bits are the first resistor string 101, and the number of resistors in the first resistor string 101 is 128; the low five bits are the second resistor string 201, and the number of resistors in the second resistor string 201 is 32. The first decoder 102 controls two switches to close and other switches to open according to the logic control signal generated by the digital control signal, so as to control the effective resistance of the first resistor string 101, and make the second resistor string 201 connected in parallel with the effective resistance of the first resistor string 101. The second decoder 203 controls one switch in the fourth switch group 202 to close and other switches to open according to the fifth logic control signal OUT<0-32> generated by the digital control signal, so as to control the effective resistance of the second resistor string 201. At the same time, combined with Figure 1 and Figure 5 , only one switch in the second resistor string 201 is closed. It is easy to see that when the d point is disconnected, the voltage at the c point is equal to the a point, so the influence of the switch resistance on the first resistor string 101 is reduced, thereby improving the linearity of the DAC.

[0052] In some alternative embodiments of the present invention, with continued reference to Figure 5 , the sum of the number of switches in the first switch group 104, the second switch group 105, and the third switch group 106 is equal to the number of resistors in the first resistor string 101. The first switch group 104, the second switch group 105, and the third switch group 106 include at least two switches. The first end of each switch is connected to the first end of a resistor in the first resistor string 101. At least two switches select two switches according to the second logic control signal, the third logic control signal, and the fourth logic control signal. The second end of one switch is connected to the first end of the second resistor string, and the second end of the other switch is connected to the second end of the second resistor string 201.

[0053] Among them, taking a 12-bit DAC as an example, the upper seven bits are the first resistor string 101. The number of resistors in the first resistor string 101 is 128. Each resistor node is configured with an independent switch, that is, the sum of the number of switches of the first switch group 104, the second switch group 105, and the third switch group 106 is 128. They are connected in one-to-one correspondence. The first end of each switch is connected to the first end of a resistor in the first resistor string 101, and the second end of each switch is connected to the output end of the first resistor string 101, so that current can flow through the conducting switch to the output end, thereby realizing the control of the output signal. When the switch is conducting, the current can flow through the corresponding resistor and be transmitted to the output end through the switch, thereby affecting the output voltage of the DAC.

[0054] In some alternative embodiments of the present invention, with continued reference to Figure 5 , the switches of the first switch group 104 adopt switches with a CMOS structure.

[0055] Among them, the first switch group 104 is sensitive to voltage and temperature and can adopt switches with a CMOS structure. The switches with a CMOS structure have the characteristics of low static power consumption and high input impedance. Due to the high input impedance characteristic of the CMOS switch, when it is connected to the resistor string, it will not change the voltage distribution of the resistor string due to its own on or off state. For example, during the digital-to-analog conversion process, the CMOS switch can accurately transfer the corresponding voltage on the resistor string to the output end without introducing additional voltage errors. The performance of the CMOS switch is relatively stable within a certain temperature range. Its parameters such as switching speed and on-resistance are less affected by temperature, ensuring that the switch can still work normally and maintain the accuracy of digital-to-analog conversion in different temperature environments. If other types of switches are used, the characteristics of the switch may change due to temperature changes, thereby affecting the result of digital-to-analog conversion.

[0056] In some alternative embodiments of the present invention, with continued reference to Figure 5 , the switches of the second switch group 105 adopt switches with a PMOS transistor structure, and the switches of the third switch group 106 adopt switches with an NMOS transistor structure.

[0057] Among them, the second switch group 105 is a switch close to the power supply level and always works near the power supply voltage AVDD. A single PMOS transistor can be used as the switch, and the on-resistance of the single PMOS is small enough. The third switch group 106 is a switch close to the ground level and always works near AGND. The gate drive can be fully turned on. A single NMOS transistor can be used as the switch, and the area of the single NMOS is smaller.

[0058] The technical solution of the embodiment of the present invention: With reference to Figure 5, taking a 12-bit DAC as an example, the upper seven bits are the first resistor string 101, the number of resistors in the first resistor string 101 is 128, the lower five bits are the second resistor string 201, and the number of resistors in the second resistor string 201 is 32. The first decoding circuit 102 generates 128 logic control signals K0-K127 according to the digital control signal, which are used to control the switches corresponding to the first resistor string 101. The 128 logic control signals are divided into three groups. The logic control signals K0-K53 at the third output terminal of the first decoding circuit 102 are in one group, which are used to directly control the first switch SW0 - the fifty-fourth switch SW53. The logic control signals K84-K127 at the second output terminal of the first decoding circuit 102 are in one group, which are used to directly control the eighty-fifth switch SW84 - the one-hundred-and-twenty-eighth switch SW127. The first logic control signals K54-K83 at the first output terminal of the first decoding circuit 102 pass through the driving logic circuit 103, and after boosting the first logic control signals K54-K83, second logic control signals KH54-KH83 are generated, which are used to control the fifty-fifth switch SW54 - the eighty-fourth switch SW83. The first switch group 104 changes the states of its switches according to the second logic control signal, thereby controlling the effective resistance of the second-level resistor string 1012. Since the voltage of the second logic control signals KH54-KH83 has increased, the voltage difference between the second logic control signals KH54-KH83 and the transmitted voltage increases, and the on-resistance of the switches decreases. According to the logic control signals generated by the first decoder 102 according to the digital control signal, two switches are controlled to be closed and other switches are opened, thereby controlling the effective resistance of the first resistor string 101, so that the effective resistance of the second resistor string 201 is connected in parallel with the effective resistance of the first resistor string 101. The fifth logic control signals OUT<0-32> generated by the second decoder 203 according to the digital control signal control one switch in the fourth switch group 202 to be closed and other switches to be opened, thereby controlling the effective resistance of the second resistor string 201. By using the charge pump 107 and the driving logic circuit 103 to increase the switch control voltage at the middle position between the power supply and the ground voltage in the resistor segmented DAC, the on-resistance of the switches is reduced, thereby ensuring that the performance of the DAC does not deteriorate at low voltage and low temperature. These switches do not need to be designed to be very large in size after the control voltage increases, reducing the cost.

[0059] It should be understood that various forms of the flow shown above can be used, steps can be reordered, added or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0060] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A resistor segmented digital-to-analog converter, characterized in that Comprising: A first resistor string, a first decoding circuit, a driving logic circuit, and a first switch group; The first resistor string includes a first-level resistor string, a second-level resistor string, and a third-level resistor string that are sequentially connected in series between a first power supply terminal and a second power supply terminal; A first output terminal of the first decoding circuit is connected to an input terminal of the driving logic circuit, an output terminal of the driving logic circuit is connected to a control terminal of the first switch group, the first switch group is connected to the second-level resistor string, the first decoding circuit is configured to form a first logic control signal according to a digital control signal, the driving logic circuit is configured to boost the first logic control signal to form a second logic control signal, and the first switch group is configured to control an effective resistance of the second-level resistor string according to the second logic control signal.

2. The resistor segmented digital-to-analog converter according to claim 1, wherein It further includes a second switch group and a third switch group, the second switch group is connected to the first-level resistor string, and the third switch group is connected to the third-level resistor string, A second output terminal of the first decoding circuit is connected to a control terminal of the second switch group, a third output terminal of the first decoding circuit is connected to a control terminal of the third switch group, and the first decoding circuit is configured to form a third logic control signal and a fourth logic control signal according to a digital control signal; The second switch group is configured to control an effective resistance of the first-level resistor string according to the third logic control signal, and the third switch group is configured to control an effective resistance of the third-level resistor string according to the fourth logic control signal.

3. The resistor segmented digital-to-analog converter according to claim 1, wherein It further includes a charge pump, the charge pump is connected to a power supply terminal of the driving logic circuit, and the charge pump is configured to supply power to the driving logic circuit.

4. The resistor segmented digital-to-analog converter according to claim 3, wherein The charge pump includes at least two stages of boosting units and a first inverter connected in sequence; each stage of the boosting unit includes a first capacitor and a first switching transistor; a gate and a first pole of the first switching transistor of the first stage of the boosting unit are connected to a third power supply terminal, a second pole of the first switching transistor of the first stage of the boosting unit and a first end of the first capacitor of the first stage of the boosting unit are connected to a gate and a first pole of the first switching transistor of the next stage of the boosting unit, a second end of the first capacitor of the odd-stage boosting unit and an input terminal of the first inverter are connected to a clock signal, a second end of the first capacitor of the even-stage boosting unit is connected to an output terminal of the first inverter, a second pole of the first switching transistor of the last stage of the boosting unit is connected to a first end of the first capacitor of the last stage of the boosting unit and serves as an output terminal of the charge pump, and a second end of the first capacitor of the last stage of the boosting unit is grounded.

5. The resistor segmented digital-to-analog converter according to claim 4, wherein A maximum withstand voltage of the charge pump is less than or equal to 1.5 times a nominal voltage of the first switching transistor.

6. The resistor segmented digital-to-analog converter according to claim 3, wherein The driving logic circuit includes a level conversion circuit and a buffer driving circuit. The input end of the level conversion circuit is connected to the first output end of the first decoding circuit. The output end of the level conversion circuit is connected to the input end of the buffer driving circuit. The power supply end of the level conversion circuit is connected to the output end of the charge pump. The level conversion circuit is used to boost the first logic control signal to form the second logic control signal. The output end of the buffer driving circuit is connected to the control end of the first switch group. The buffer driving circuit is used to improve the driving ability of the second logic control signal.

7. The resistor segmented digital-to-analog converter according to claim 2, characterized in that, It further includes: a second resistor string, a fourth switch group, and a second decoding circuit; One end of the first resistor string of the second resistor string is connected to one end of the effective resistor of the first resistor string through one switch among the first switch group, the second switch group, and the third switch group. The other end of the second resistor string is connected to the other end of the effective resistor of the first resistor string through another switch among the first switch group, the second switch group, and the third switch group. The output end of the second decoding circuit is connected to the control end of the fourth switch group. The second decoding circuit is used to form a fifth logic control signal according to the digital control signal. The fourth switch group is connected to the second resistor string. The fourth switch group is used to control the effective resistance of the second resistor string according to the fifth logic control signal.

8. The resistor segmented digital-to-analog converter according to claim 7, wherein The sum of the number of switches of the first switch group, the second switch group, and the third switch group is equal to the number of resistors of the first resistor string. The first switch group, the second switch group, and the third switch group include at least two switches. The first end of each switch is connected to the first end of one resistor in the first resistor string. At least two of the switches are gated according to the second logic control signal, the third logic control signal, and the fourth logic control signal. One of the switches has its second end connected to the first end of the second resistor string, and the other switch has its second end connected to the second end of the second resistor string.

9. The resistor segmented digital-to-analog converter according to claim 1, wherein, The first switch group uses switches with a CMOS structure.

10. The resistor segmented digital-to-analog converter according to claim 2, characterized in that, The second switch group uses switches with a PMOS transistor structure, and the third switch group uses switches with an NMOS transistor structure.

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