Signal processing method and device, electronic equipment, chip and storage medium

Abstract

The invention provides a signal processing method and device, electronic equipment, a chip and a storage medium, and relates to the field of communication, and the method comprises the steps: splicing a received signal vector and a channel matrix of a receiving end, so as to obtain a to-be-processed matrix; wherein the channel matrix is used for indicating the channel gain between the transmitting stream of the transmitting end and the plurality of receiving antennas of the receiving end, and the receiving channel vector is used for indicating the signals received by the plurality of receiving antennas; performing multi-round iteration on the to-be-processed matrix based on the target systolic array to obtain an upper triangular matrix and an equivalent receiving vector; and recovering the physical air interface signal sent by the sending end according to the upper triangular matrix and the equivalent receiving vector. Therefore, matrix decomposition is realized by executing at least one round of iteration by adopting an efficient parallel computing architecture, namely the target systolic array, so that the computing complexity can be simplified, the computing efficiency can be improved, high-throughput and low-delay computing can be realized, and the quality and the reliability of physical air interface signals recovered by a receiving end can also be improved.

Description

Technical Field

[0001] This application relates to the field of signal processing technologies, and in particular, to a signal processing method, apparatus, electronic device, chip, and storage medium. Background Art

[0002] In wireless communication systems or mobile communication systems, especially in cellular networks, Wireless Fidelity (Wi-Fi), and other wireless communication technologies, receive diversity techniques are widely used to improve the performance and reliability of the system. Higher-order receive diversity (such as 6 receive channels (Rx), 8Rx, etc.) can improve the coverage area, enhance the anti-interference ability, increase the data throughput, improve the system robustness, and enhance the user experience by increasing the number of receive channels. Summary of the Invention

[0003] This application aims to solve at least one of the technical problems in the related art to some extent.

[0004] To this end, this application provides a signal processing method, apparatus, electronic device, chip, and storage medium to simplify the complexity of signal detection and improve the calculation efficiency, achieve high-throughput and low-latency calculations, and improve the quality and reliability of the physical air interface signals recovered at the receiving end.

[0005] An embodiment of one aspect of this application provides a signal processing method, including:

[0006] Concatenate the received signal vector at the receiving end and the channel matrix to obtain a matrix to be processed; wherein, the channel matrix is used to indicate the channel gain between the transmitted streams at the transmitting end and the multiple receive antennas at the receiving end, and the received channel vector is used to indicate the signals received by the multiple receive antennas;

[0007] Perform iterations on the matrix to be processed based on a target systolic array to obtain an upper triangular matrix and an equivalent received vector;

[0008] Recover the physical air interface signals transmitted by the transmitting end according to the upper triangular matrix and the equivalent received vector.

[0009] An embodiment of another aspect of this application provides a signal processing apparatus, including:

[0010] A concatenation module, configured to concatenate the received signal vector at the receiving end and the channel matrix to obtain a matrix to be processed; wherein, the channel matrix is used to indicate the channel gain between the transmitted streams at the transmitting end and the multiple receive antennas at the receiving end, and the received channel vector is used to indicate the signals received by the multiple receive antennas;

[0011] An iterative module, configured to perform iteration on the to-be-processed matrix based on a target systolic array to obtain an upper triangular matrix and an equivalent received vector;

[0012] A recovery module, configured to recover the physical air interface signal transmitted by the transmitting end according to the upper triangular matrix and the equivalent received vector.

[0013] Another embodiment of this application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the signal processing method described in the foregoing aspect is implemented.

[0014] Another embodiment of this application provides a chip, which includes an interface circuit and a processing circuit coupled to each other. The interface circuit is used for inputting or outputting signals, and the processing circuit is configured to execute the signal processing method described in the foregoing aspect.

[0015] Another embodiment of this application provides a non-transitory computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the signal processing method described in the foregoing aspect is implemented.

[0016] Another embodiment of this application provides a computer program product, on which a computer program is stored. When the program is executed by a processor, the signal processing method described in the foregoing aspect is implemented.

[0017] The signal processing method, device, electronic device, chip, and storage medium provided by this application adopt an efficient parallel computing architecture - a target systolic array to perform at least one round of iteration to achieve matrix decomposition, thereby obtaining an upper triangular matrix R and an equivalent received vector z, which can simplify the computational complexity and improve the computational efficiency, achieving high throughput and low latency computing. And at least one round of iteration helps to better separate the signals between different transmission streams, reduce the influence of multipath effects and other interferences. This iterative method gradually improves the signal quality and enhances the anti-interference ability of the system, thereby improving the quality and reliability of the physical air interface signal recovered by the receiving end, and is applicable to complex wireless communication environments.

[0018] Additional aspects and advantages of this application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of this application. Description of the Drawings

[0019] The above and / or additional aspects and advantages of this application will become apparent and be readily understood from the following description of the embodiments in conjunction with the drawings, where:

[0020] Figure 1Schematic flowchart of the first signal processing method provided by the embodiments of the present application;

[0021] Figure 2 Schematic flowchart of the second signal processing method provided by the embodiments of the present application;

[0022] Figure 3 Schematic flowchart of the signal processing process at the receiving end provided by the embodiments of the present application;

[0023] Figure 4 Schematic flowchart of the third signal processing method provided by the embodiments of the present application;

[0024] Figure 5 Schematic flowchart of the fourth signal processing method provided by the embodiments of the present application;

[0025] Figure 6 Schematic diagram of the structure of the target systolic array provided by the embodiments of the present application;

[0026] Figure 7 Schematic diagram of the principle of matrix decomposition provided by the embodiments of the present application;

[0027] Figure 8 Schematic diagram of the structure of a signal processing device provided by the embodiments of the present application;

[0028] Figure 9 Schematic diagram of the structure of an electronic device provided by the embodiments of the present application;

[0029] Figure 10 Schematic diagram of the structure of a chip proposed by the embodiments of the present application. Detailed implementation manners

[0030] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application and should not be construed as a limitation to the present application.

[0031] In a Multiple-Input Multiple-Output (MIMO) wireless communication system, the number of antennas at the receiving end (Rx) directly affects the spatial multiplexing ability and throughput of the system. Compared with the traditional 4Rx in terms of spatial multiplexing, the number of scheduled streams increases from 4 streams to 6 streams for 6Rx, which can improve the throughput by 50%. However, correspondingly, as the number of streams increases, the complexity of signal detection will also increase significantly, especially when matrix operations are required, and the complexity shows an exponential growth. This is because each additional stream introduces more dimensions of calculation, resulting in a sharp increase in the complexity of matrix operations.

[0032] To effectively decode the received signal, it is usually necessary to perform QR decomposition on the channel matrix, decomposing the channel matrix H into an orthogonal matrix Q and an upper triangular matrix R, thereby simplifying the subsequent signal detection process.

[0033] In related technologies, QR decomposition of the channel matrix is usually achieved by using sorted Cholesky decomposition. Specifically, first, the columns of the channel matrix are sorted to minimize the correlation between columns as much as possible, thereby simplifying the subsequent decomposition process. Then, the sorted channel matrix is applied with Cholesky decomposition to convert it into the product of a lower triangular matrix and its transpose. Finally, the result of Cholesky decomposition is used to complete the QR decomposition.

[0034] As an example, the QR decomposition of the channel matrix H can be equivalently achieved by the Cholesky decomposition of the autocorrelation matrix, that is:

[0035]

[0036] Among them, H is the channel matrix, representing the channel gain between the transmit streams at the transmitting end (or called the sending end) and the receiving antennas at the receiving end; I is the identity matrix, used to expand the matrix for QR decomposition; Q is the orthogonal matrix, and its column vectors are orthogonal; R is the upper triangular matrix, used to represent the linear transformation of the channel matrix.

[0037] Among them, the autocorrelation matrix is:

[0038] G = H H H = H H H + I = (QR) H QR = R H R; (2)

[0039] Among them, G is the autocorrelation matrix, representing the conjugate transpose of the channel matrix (H H ) multiplied by the channel matrix H itself; H His the conjugate transpose of the channel matrix H; I is the identity matrix, which is used to expand the matrix for Cholesky decomposition.

[0040] The Cholesky decomposition of the autocorrelation matrix is:

[0041] G = LL H ; (3)

[0042] where L is a lower triangular matrix obtained through Cholesky decomposition; L H is the conjugate transpose of L.

[0043] According to formulas (2) and (3), it can be known that:

[0044] R = L H ; (4)

[0045] For the equivalent received vector, there is:

[0046] z = Q H y = R -H H H y; (5)

[0047] where z is the equivalent received vector, representing the received signal vector after transformation; y is the received signal vector.

[0048] The steps of Cholesky decomposition are as follows:

[0049]

[0050] where l jj is the diagonal element of the lower triangular matrix L, g jj is the diagonal element of the autocorrelation matrix G; l jk is the element in the lower triangular matrix L; u ij is the value for intermediate calculation; l ij is the non - diagonal element in the lower triangular matrix L; l' jk is the conjugate transpose of l jk .

[0051] Finally, signal detection can be performed based on the upper triangular matrix R and the equivalent received vector z to recover the physical air - interface signal transmitted by the transmitter.

[0052] Taking the number of transmission streams at the transmitter as 6 and the number of receiving antennas at the receiver as 6 as an example, the computational complexity of using Cholesky for QR decomposition is shown in Table 1:

[0053] Table 1 Computational complexity of using Cholesky for QR decomposition

[0054] Computational amount Complex multiplication Complex addition Real multiplication Real addition Division Square root <![CDATA[G = H H H + I]]> 90 75 72 66 0 0 <![CDATA[e = H H y]]> 36 30 0 0 0 0 LL decomposition 20 20 60 30 6 6 <![CDATA[z = Q H y]]> 15 15 10 6 0 0

[0055] Among them, one real number multiplication = 50 real number additions, one division or square root = 500 real number additions. The computational workload of performing QR decomposition using Cholesky is converted into real number additions in total: (90 + 36 + 20 + 15) * 200 + (90 + 36 + 20 + 15) * 2 + (75 + 30 + 20 + 15) * 2 + (72 + 60 + 10) * 50 + (66 + 30 + 6) + 6 * 500 + 6 * 500 = 46006.

[0056] In summary, although the sorting-based Cholesky decomposition can reduce the complexity to a certain extent, for high-dimensional matrices (such as a 6x6 channel matrix), this complexity is still quite high.

[0057] Therefore, in view of at least one problem existing in the above related technologies, the present application proposes a signal processing method, apparatus, electronic device, chip, and storage medium.

[0058] The signal processing method, apparatus, electronic device, chip, and storage medium according to the embodiments of the present application will be described below with reference to the accompanying drawings.

[0059] Figure 1 It is a schematic flowchart of the first signal processing method provided by the embodiments of the present application.

[0060] It should be noted that the signal processing method of the embodiments of the present application can be applied to a signal processing apparatus. In some possible embodiments, the signal processing apparatus can be configured in a receiving end or a chip so that the receiving end or the chip can perform signal processing functions. Additionally, in some possible embodiments, the signal processing apparatus can also be software in the receiving end, etc.

[0061] In any embodiment of the present application, the chip can be integrated into the receiving end. The chip includes a central processing unit (CPU), an image signal processing (ISP), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a system on a chip (SOC), a reduced instruction set computer (RISC), etc., which will not be listed one by one here.

[0062] It should be noted that the receiving end and the sending end are two different electronic devices, and their roles can be interchanged according to the direction of communication. Exemplarily, in a downlink communication scenario, the receiving end can be a terminal, and the sending end can be a network device. In an uplink communication scenario, the receiving end can be a network device, and the sending end can be a terminal.

[0063] Among them, a terminal is an entity on the user side for receiving or transmitting signals, such as a mobile phone. A terminal can also be referred to as a terminal device (terminal), user equipment (abbreviated as UE), mobile station (abbreviated as MS), mobile terminal (abbreviated as MT), etc. A terminal can be a car with communication functions, a smart car, a mobile phone, a wearable device, a tablet computer (Pad), a computer with wireless transceiver functions, a virtual reality (abbreviated as VR) terminal, an augmented reality (abbreviated as AR) terminal, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, and so on. Embodiments of the present application do not limit the specific technologies and specific device forms adopted by the terminal.

[0064] Among them, a network device is an entity on the network side for transmitting or receiving signals. For example, the network device may be an evolved NodeB (abbreviated as eNB), a transmission reception point (abbreviated as TRP), a next generation NodeB (abbreviated as gNB) in a 5G new radio (abbreviated as NR) system, a base station in other future mobile communication systems, or an access node in a wireless fidelity (abbreviated as WiFi) system, etc. Embodiments of the present application do not limit the specific technologies and specific device forms adopted by the network device. The network device provided by the embodiments of the present application may be composed of a central unit (abbreviated as CU) and a distributed unit (abbreviated as DU). Among them, the CU may also be referred to as a control unit. Adopting the CU-DU structure can split the protocol layer of the network device, such as a base station. The functions of some protocol layers are centrally controlled by the CU, and the functions of the remaining part or all protocol layers are distributed in the DU, and the DU is centrally controlled by the CU.

[0065] As Figure 1 shown, the signal processing method may include the following steps S101 to S103:

[0066] Step S101, concatenate the received signal vector and the channel matrix at the receiving end to obtain a matrix to be processed; among them, the channel matrix is used to indicate the channel gain between the transmit streams at the transmitting end and multiple receiving antennas at the receiving end, and the received channel vector is used to indicate the signals received by the multiple receiving antennas.

[0067] Among them, each transmit stream is a data stream transmitted through one or more transmitting antennas at the transmitting end. Among them, the transmit stream is a logical data stream, representing an independent signal path or channel, and can carry different data or information in the same time unit.

[0068] Among them, the time unit includes symbols, slots, and frames.

[0069] Among them, the transmitting end can simultaneously transmit multiple transmit streams through spatial multiplexing technology to improve the data transmission rate.

[0070] In any embodiment of the present application, the number of emission streams is N, and the number of receiving antennas is M. Both N and M are positive integers, and M ≥ N.

[0071] In any embodiment of the present application, the channel matrix is an M×N matrix. Among them, the element in the i-th row and j-th column of the channel matrix is used to indicate the channel gain experienced when the j-th emission stream from the transmitting end arrives at the i-th receiving antenna at the receiving end. Among them, i is a positive integer not greater than M, and j is a positive integer not greater than N.

[0072] In any embodiment of the present application, the received signal vector is an M×1 vector. Among them, the element in the i-th row of the received signal vector is used to indicate the signal or data received by the i-th receiving antenna.

[0073] In an embodiment of the present application, the M×1 received signal vector received at the receiving end and the M×N channel matrix can be concatenated to obtain a matrix to be processed.

[0074] Exemplarily, in the column dimension, the M×N channel matrix and the M×1 received signal vector can be concatenated to obtain a matrix to be processed.

[0075] Step S102: Based on the target systolic array, perform iteration on the matrix to be processed to obtain an upper triangular matrix and an equivalent received vector.

[0076] Among them, the target systolic array is an efficient parallel computing architecture, which is used to decompose a computing task into multiple small and repetitive computing units and process them in a pipeline manner, so as to achieve efficient parallel computing, and is applicable to scenarios such as matrix operations, signal processing, and convolutional neural networks. Among them, the target systolic array includes but is not limited to: sign inversion operation, right shift operation, and adder.

[0077] Exemplarily, the iteration may include one or more rounds of iteration operations.

[0078] Exemplarily, the target systolic array includes a Cordic (Coordinate Rotation Digital Computer) sorting systolic array. Among them, the Cordic sorting systolic array combines the Cordic algorithm with the systolic array architecture, aiming to efficiently process complex signal processing tasks. Among them, the Cordic algorithm approximates complex operations in rotation or vector mode through a series of simple shift and addition / subtraction operations, and it can be very efficiently implemented on hardware. The reason is that the Cordic algorithm only requires basic arithmetic logic units and does not require multipliers or dividers, which can greatly reduce the computational complexity. A systolic array is a parallel computing structure where data flows like waves between processors in the array. Among them, each processor performs the same operation and only communicates with adjacent processors. This architecture is very suitable for matrix operations and other regular data flow problems because it can provide high throughput and low latency characteristics.

[0079] In any embodiment of the present application, the number of iterations is the same as the number of streams of the transmission stream, both being N.

[0080] In the embodiment of the present application, based on the target systolic array, the to-be-processed matrix can be iterated N times to obtain the required matrix, and an N*N upper triangular matrix and an N*1 equivalent received vector can be extracted from the first N rows of the required matrix. Among them, in the i-th (i is a positive integer not greater than N) iteration, it is used to update the i-th element in the i-th column of the to-be-processed matrix to a real number, update each element before the i-th element in the i-th column to a complex number, and update each element after the i-th element in the i-th column to 0.

[0081] That is, in the first iteration, it is used to update the element in the first row and first column of the to-be-processed matrix to a real number, and update other elements in the first column except the element in the first row and first column to 0; in the second iteration, it is used to update the element in the first row and second column of the to-be-processed matrix to a complex number, update the element in the second row and second column to a real number, and update other elements in the second column except the element in the first row and second column and the element in the second row and second column to 0; in the third iteration, it is used to update the elements in the first row and third column and the second row and third column of the to-be-processed matrix to complex numbers, update the element in the third row and third column to a real number, and update other elements in the third column except the elements in the first row and third column, the second row and third column, and the third row and third column to 0, and so on.

[0082] Step S103, recover the physical air interface signal sent by the transmitting end according to the upper triangular matrix and the equivalent received vector.

[0083] In the embodiment of the present application, the physical air interface signal sent by the transmitting end can be recovered according to the N*N upper triangular matrix and the N*1 equivalent received vector.

[0084] The signal processing method according to the embodiment of the present application uses an efficient parallel computing architecture, namely, a target systolic array, to perform at least one round of iteration to achieve matrix decomposition, thereby obtaining an upper triangular matrix R and an equivalent received vector z. This can simplify the computational complexity and improve the computational efficiency, achieving high throughput and low latency computing. Moreover, at least one round of iteration helps to better separate the signals between different transmit streams, reduce the influence of multipath effects and other interferences. This iterative method gradually improves the signal quality, enhances the anti-interference ability of the system, and thus improves the quality and reliability of the physical air interface signal recovered at the receiving end, and is applicable to complex wireless communication environments.

[0085] The embodiment of the present application provides another signal processing method. Figure 2 It is a schematic flowchart of the second signal processing method provided by the embodiment of the present application.

[0086] It should be noted that this signal processing method can be executed alone, or can be executed in combination with any one of the embodiments in the present application or possible implementation manners in the embodiments, or can also be executed in combination with any one of the technical solutions in the related art. The embodiments of the present application do not limit this.

[0087] As Figure 2 shown, this signal processing method may include the following steps S201 to S204:

[0088] Step S201: Concatenate the received signal vector at the receiving end and the channel matrix to obtain a matrix to be processed; wherein, the channel matrix is used to indicate the channel gain between the transmit streams at the transmitting end and multiple receiving antennas at the receiving end, and the received channel vector is used to indicate the signals received by the multiple receiving antennas.

[0089] Step S202: Based on the target systolic array, perform iteration on the matrix to be processed to obtain an upper triangular matrix and an equivalent received vector.

[0090] It should be noted that the explanations of steps S201 to S202 can refer to the relevant descriptions in any embodiment of the present application and will not be elaborated here.

[0091] Step S203: Perform signal detection according to the upper triangular matrix and the equivalent received vector to obtain soft value information; wherein, the soft value information includes the soft values of the digital signals corresponding to the physical air interface signals in each time unit, and the soft value is determined according to the ratio of the probability that the digital signal takes the first value and the probability that the digital signal takes the second value in the corresponding time unit.

[0092] Wherein, the time unit includes symbol, slot, and frame.

[0093] Among them, the first value and the second value are preset values, and the first value is different from the second value. Taking the digital signal as a binary signal as an example, the first value can be 0, and the second value can be 1, or the first value can be 1, and the second value can be 0. The embodiments of the present application do not limit this.

[0094] As an example, the signal detection problem can be simplified to solve for X:

[0095] RX = z; (7)

[0096] Among them, R is an upper triangular matrix, and z is an equivalent received vector.

[0097] Therefore, in the present application, soft value information (soft information) can be calculated according to X. The soft value information can include the soft values of the digital signals corresponding to the physical air interface signals in each time unit. The soft value is determined according to the ratio of the probability that the digital signal takes the first value and the probability that the digital signal takes the second value in the corresponding time unit.

[0098] Exemplarily, taking the first value as 0 and the second value as 1 for exemplary illustration, assuming that the probability that the digital signal takes the value of 0 in a certain time unit is 90%, and the probability that the digital signal takes the value of 1 in this time unit is 10%, then the soft value of this time unit in the soft value information can be 9 or ln(9).

[0099] Step S204, perform signal decoding on the soft value information to restore the physical air interface signal sent by the sending end.

[0100] In the embodiments of the present application, a decoder can be used to perform signal decoding based on the soft value information to restore the physical air interface signal sent by the sending end.

[0101] As an example, taking the first value as 0, the second value as 1, and the soft value as ln (the ratio of the probability that the digital signal takes the value of 0 and the probability that the digital signal takes the value of 1) as an example, when the soft value of a certain time unit in the soft value information is positive, it indicates that the value of the digital signal corresponding to the physical air interface signal in this single time unit tends to be 0, and when the soft value of a certain time unit in the soft value information is negative, it indicates that the value of the digital signal corresponding to the physical air interface signal in this time unit tends to be 1. In the present application, a decoder can be used to decode the soft value information to restore the physical air interface signal actually sent by the sending end.

[0102] As an application scenario, taking the receiving end as a terminal and the sending end as a network device as an example, the signal processing flow of the receiving end can be as Figure 3As shown, the network device sends a physical air interface signal to the terminal. After being attenuated by the wireless channel, the physical air interface signal is received by the analog front end of the terminal, and the digital signal after analog-to-digital conversion is given to the baseband for demodulation and decoding, and finally the physical air interface signal sent by the network device is restored. Among them, the wireless channel is the medium connecting the network device and the terminal, and is used to transmit wireless signals. Exemplarily, the signal processing flow mainly includes the following parts:

[0103] 1. The Analog Front End (AFE for short) is an important component of a wireless communication system, mainly responsible for converting the wireless signal received by the antenna into a format suitable for subsequent processing. Among them, the main tasks of the analog front end include:

[0104] 1) Amplification: Amplify the received weak signal for subsequent processing;

[0105] 2) Filtering: Remove unnecessary frequency components and retain the signals within the frequency band of interest;

[0106] 3) Mixing / frequency conversion: Convert the high-frequency wireless signal into a lower intermediate frequency or baseband signal for easier digital processing.

[0107] 4) Analog to Digital Converter (ADC for short): Convert the analog signal into a digital signal for subsequent digital signal processing.

[0108] 2. Channel estimation: Used to calculate the channel matrix H. The purpose of channel estimation is to more accurately understand the state of the wireless channel, thereby improving the quality of the received signal.

[0109] 3. Signal detection: The purpose of signal detection is to predict the probability that the value of the signal is 0 and the probability that the value is 1 in each time unit.

[0110] 4. Soft value storage: Soft value storage is used to save the signal detection results. These soft values contain the ratio of the probability that the value of the signal is 0 to the probability that the value is 1 in each time unit, and they will be used in the subsequent decoding stage.

[0111] 5. Decoding: Used to restore the signal after a series of previous processes into the original information content. Decoding depends on the information provided by all previous steps, especially the data in the soft value storage.

[0112] The signal processing method of the embodiment of this application can realize signal detection according to the upper triangular matrix and the equivalent received vector, obtain soft value information, and perform signal decoding on the soft value information to accurately restore the physical air interface signal sent by the sending end.

[0113] Another signal processing method is provided in an embodiment of the present application. Figure 4 It is a schematic flowchart of the third signal processing method provided in an embodiment of the present application.

[0114] It should be noted that this signal processing method can be executed alone, or it can be executed together with any one of the embodiments in the present application or the possible implementation manners in the embodiments, or it can also be executed together with any one of the technical solutions in the related art. The embodiments of the present application do not limit this.

[0115] As Figure 4 shown, this signal processing method may include the following steps S401 to S404:

[0116] Step S401: Concatenate the channel matrix and the received signal vector at the receiving end in the column dimension to obtain an intermediate matrix.

[0117] Among them, the channel matrix is used to indicate the channel gain between the transmitted streams at the transmitting end and multiple receiving antennas at the receiving end, and the received channel vector is used to indicate the signals received by the multiple receiving antennas.

[0118] It should be noted that the explanations of the channel matrix and the received signal vector in the foregoing embodiments also apply to this embodiment and will not be elaborated here.

[0119] Exemplarily, taking N and M both being 6 as an example, mark the channel matrix as: The received signal vector is: Then the intermediate matrix can be:

[0120] Step S402: Concatenate the intermediate matrix and the identity matrix in the row dimension to obtain a matrix to be processed.

[0121] Among them, the identity matrix can be an N*N matrix.

[0122] Still taking the above example, the matrix to be processed can be:

[0123] Step S403: Perform N rounds of iteration on the matrix to be processed based on the target systolic array to obtain an upper triangular matrix and an equivalent received vector.

[0124] Among them, the number of rounds of iteration is the same as the number of transmitted streams, both being N.

[0125] In an embodiment of the present application, based on the target systolic array, multiple rounds of iteration can be performed on the matrix to be processed to obtain a required matrix, and an N*N upper triangular matrix and an N*1 equivalent received vector can be extracted from the first N rows of the required matrix.

[0126] Among them, in the i-th iteration, the i-th element in the i-th column of the matrix to be processed is updated to a real number, each element before the i-th element in the i-th column is updated to a complex number, and each element after the i-th element in the i-th column is updated to 0.

[0127] That is, in the first iteration, the element in the first row and first column of the matrix to be processed is updated to a real number, and the other elements in the first column except the element in the first row and first column are updated to 0; in the second iteration, the element in the first row and second column of the matrix to be processed is updated to a complex number, the element in the second row and second column is updated to a real number, and the other elements in the second column except the element in the first row and second column and the element in the second row and second column are updated to 0; in the third iteration, the elements in the first row and third column and the second row and third column of the matrix to be processed are updated to complex numbers, the element in the third row and third column is updated to a real number, and the other elements in the third column except the elements in the first row and third column, the second row and third column, and the third row and third column are updated to 0, and so on.

[0128] Step S404: Recover the physical air interface signal transmitted by the transmitting end according to the upper triangular matrix and the equivalent received vector.

[0129] It should be noted that the explanation of step S404 can be referred to the relevant description in any embodiment of this application, and will not be elaborated here.

[0130] The signal processing method of the embodiment of this application can improve the effectiveness and accuracy of obtaining the matrix to be processed by splicing the channel matrix, the received signal vector, and the identity matrix in different dimensions.

[0131] The embodiment of this application provides another signal processing method. Figure 5 It is a schematic flowchart of the fourth signal processing method provided by the embodiment of this application.

[0132] It should be noted that this signal processing method can be executed alone, or can be executed in combination with any one embodiment or possible implementation manner in this application, or can also be executed in combination with any one technical solution in the related art. The embodiment of this application does not limit this.

[0133] As Figure 5 shown, this signal processing method may include the following steps S501 to S505:

[0134] Step S501: Splice the M×1 received signal vector at the receiving end and the M×N channel matrix to obtain a (M + N)×(N + 1) matrix to be processed.

[0135] Among them, the channel matrix is used to indicate the channel gains between N transmit streams at the transmitter and M receive antennas at the receiver, and the received channel vector is used to indicate the signals received by multiple receive antennas at the receiver.

[0136] It should be noted that the explanation of step S501 can be referred to the relevant description in any embodiment of this application, and will not be elaborated here.

[0137] Step S502, perform the first round of iteration among N rounds of iteration on the matrix to be processed based on the target systolic array, including: determining a first target column from each column in the first M rows of the matrix to be processed according to the norms of each column in the first M rows; swapping the positions of the first target column and the first column in the first M rows to obtain an initial updated matrix in the first round of iteration; updating the initial updated matrix in the first round of iteration based on the target systolic array to obtain a target updated matrix updated in the first round of iteration.

[0138] Among them, the norms include but are not limited to: L1 norm (the sum of the absolute values of each element), L2 norm (also known as the Euclidean norm, which is the square root of the sum of the squares of each element), infinity norm (the maximum value of the absolute values of all elements), and Frobenius norm.

[0139] In the embodiment of this application, for the first round of iteration among N rounds of iteration, a first target column can be determined from each column in the first M rows of the matrix to be processed according to the norms of each column in the first M rows. Exemplarily, the column with the smallest norm among each column in the first M rows can be used as the first target column. Then, the positions of the first target column and the first column in the first M rows can be swapped to reduce the correlation between columns to obtain an initial updated matrix in the first round of iteration. Subsequently, the initial updated matrix in the first round of iteration can be updated based on the target systolic array to obtain a target updated matrix updated in the first round of iteration.

[0140] In any one of the embodiments of this application, the target systolic array can include a first systolic array and a second systolic array connected to each other. Each round of iteration can include M sub-iterations. Among them, the first sub-iteration among the M sub-iterations in the first round of iteration can include the following steps A to B:

[0141] Step A: Update the element in the Mth row and the first column and the element in the (M + 1)th row and the first column in the initial updated matrix in the first round of iteration based on the first systolic array.

[0142] As an example, the first target parameter of the first rotation process of the first systolic array can be determined according to the element in the first column of the (M + 1)-th row, and the first systolic array can be used to rotate the element in the first column of the M-th row and the element in the first column of the (M + 1)-th row based on the first target parameter of each round of the first rotation process, so that the rotated element in the first column of the (M + 1)-th row is 0 and the rotated element in the first column of the M-th row is a real number.

[0143] Among them, the first target parameter is used to control the rotation angle of the first rotation process.

[0144] Taking the first systolic array as Figure 6 the Cordic Master systolic array shown as an example, the following method can be used to rotate the element in the first column of the M-th row and the element in the first column of the (M + 1)-th row:

[0145] [Z, θ] = the first systolic array(x, y, D, K); / / x can be the element in the first column of the M-th row, y can be the element in the first column of the (M + 1)-th row, D is the set number of rounds of the first rotation process, K is the set correction coefficient, Z can be the final value of x after D rounds of rotation (i.e., the rotated element in the first column of the M-th row), the final value of y after D rounds of rotation is 0, and θ is the first target parameter of the last round of the first rotation process;

[0146]

[0147] Step B: Based on the second systolic array, update multiple first element pairs in the initial update matrix in the first round of iteration to obtain the initial update matrix updated after the first sub-iteration; among them, the first element pair includes: the element in the p-th column of the M-th row and the element in the p-th column of the (M + 1)-th row, where p = 2, …, N + 1.

[0148] As an example, the second target parameter of the second rotation process of the second systolic array can be determined according to the first target parameter of the first round of the first rotation process of multiple rounds, and the second systolic array can be used to rotate multiple first element pairs in the initial update matrix in the first round of iteration based on the second target parameter of each round of the second rotation process, so that the rotated first element pair is a complex number.

[0149] Among them, the second target parameter is used to control the rotation angle of the second rotation process.

[0150] Taking the second systolic array as Figure 6 the Cordic Slave systolic array shown as an example, the following method can be used to rotate the first element pair, that is, the element in the p-th column of the M-th row and the element in the p-th column of the (M + 1)-th row:

[0151] [x', y'] = Second Pulsating Array(x, y, θ, D, K); / / x can be the element in the p-th column of the M-th row, y can be the element in the p-th column of the (M + 1)-th row, x' can be the final value of x after D rounds of rotation (i.e., the element in the p-th column of the M-th row after rotation), y' can be the final value of y after D rounds of rotation (i.e., the element in the p-th column of the (M + 1)-th row after rotation), and θ is the parameter passed in by the First Pulsating Array;

[0152]

[0153]

[0154] Among them, in the non-first sub-iterations of the M sub-iterations in the first round of iteration, such as the n-th sub-iteration, it can include the following steps C to D:

[0155] Step C: Based on the First Pulsating Array, update the element in the first column of the (M - n + 1)-th row and the element in the first column of the (M - n + 2)-th row in the initial update matrix updated in the (n - 1)-th sub-iteration of the first round of iteration; where n = 2,..., M.

[0156] As an example, the first target parameter in the first rotation process of multiple rounds of the First Pulsating Array can be determined according to the element in the first column of the (M - n + 2)-th row, and the First Pulsating Array is used to rotate the element in the first column of the (M - n + 1)-th row and the element in the first column of the (M - n + 2)-th row based on the first target parameter in each round of the first rotation process, so that the element in the first column of the (M - n + 2)-th row after rotation is 0, and the element in the first column of the (M - n + 1)-th row after rotation is a real number. The implementation principle is similar to that of Step A and will not be elaborated here.

[0157] Among them, the first target parameter is used to control the rotation angle of the first rotation process.

[0158] Step D: Based on the Second Pulsating Array, update multiple pairs of second elements in the initial update matrix updated in the (n - 1)-th iteration of the first round of iteration to obtain the initial update matrix updated in the n-th sub-iteration; where the pair of second elements includes the element in the p-th column of the (M - n + 1)-th row and the element in the p-th column of the (M - n + 2)-th row, where p = 2,..., N + 1; where the target update matrix obtained by the first round of iteration update is the initial update matrix updated in the M-th sub-iteration of the first round of iteration.

[0159] As an example, based on the first target parameter of the first rotation process in multiple rounds, the second target parameter of the second rotation process in multiple rounds for the second systolic array can be determined, and the second systolic array can be used to rotate multiple second element pairs in the initial update matrix after the (n - 1)-th round of iterative update based on the second target parameter of each round of the second rotation process, so that the rotated second element pairs are complex numbers. The implementation principle is similar to that of step B and will not be elaborated here.

[0160] Among them, the second target parameter is used to control the rotation angle of the second rotation process.

[0161] Step S503, performing the k-th iteration in N rounds of iteration on the matrix to be processed based on the target systolic array, includes: determining a second target column from each column in the first (k + M - 1) rows according to the norms of each column in the first (k + M - 1) rows of the target update matrix updated in the (k - 1)-th iteration; swapping the positions of the second target column and the k-th column in the first (k + M - 1) rows to obtain the initial update matrix in the k-th iteration; and updating the initial update matrix in the k-th iteration based on the target systolic array to obtain the target update matrix updated in the k-th iteration.

[0162] In an embodiment of the present application, for non-first-round iterations in N rounds of iteration, such as the k-th iteration, where k = 2, …, N - 1, a second target column can be determined from each column in the first (k + M - 1) rows according to the norms of each column in the target update matrix updated in the (k - 1)-th iteration. Exemplarily, the column with the smallest norm among the k-th column, the (k + 1)-th column, …, the N-th column in the first (k + M - 1) rows can be used as the second target column. Then, the positions of the second target column and the k-th column in the first (k + M - 1) rows can be swapped to reduce the correlation between columns, obtaining the initial update matrix in the k-th iteration. Subsequently, the initial update matrix in the k-th iteration can be updated based on the target systolic array to obtain the target update matrix updated in the k-th iteration.

[0163] In any embodiment of the present application, the target systolic array may include a first systolic array and a second systolic array connected to each other. The k-th iteration includes M sub-iterations. The first sub-iteration among the M sub-iterations may include the following steps E to F:

[0164] Step E: Updating the element in the k-th column of the (k + M - 1)-th row and the element in the k-th column of the (k + M)-th row in the initial update matrix in the k-th iteration based on the first systolic array; where k = 2, …, N - 1.

[0165] As an example, the first target parameter of the first rotation process in multiple rounds of the first systolic array can be determined according to the element in the k-th column of the (k + M)-th row, and the first systolic array is used to rotate the element in the k-th column of the (k + M - 1)-th row and the element in the k-th column of the (k + M)-th row based on the first target parameter of each round of the first rotation process, so that the rotated element in the k-th column of the (k + M)-th row is 0, and the rotated element in the k-th column of the (k + M - 1)-th row is a real number. The implementation principle is similar to that of the above step A and will not be elaborated here.

[0166] Among them, the first target parameter is used to control the rotation angle of the first rotation process.

[0167] Step F: Based on the second systolic array, update multiple first element pairs in the initial update matrix in the k-th round of iteration to obtain the initial update matrix after the first sub-iteration update; among them, the first element pair includes: the element in the p-th column of the (k + M - 1)-th row and the element in the p-th column of the (k + M)-th row, where p = k + 1, …, N + 1.

[0168] As an example, the second target parameter of the second rotation process in multiple rounds of the second systolic array can be determined based on the first target parameter of multiple rounds of the first rotation process, and the second systolic array is used to rotate multiple first element pairs in the initial update matrix in the k-th round of iteration based on the second target parameter of each round of the second rotation process, so that the rotated first element pair is a complex number. Among them, the second target parameter is used to control the rotation angle of the second rotation process. The implementation principle is similar to that of the above step B and will not be elaborated here.

[0169] Among them, the non-first sub-iteration in the M sub-iterations of the k-th round of iteration, such as the n-th sub-iteration, may include the following steps G to step H:

[0170] Step G: Based on the first systolic array, update the element in the k-th column of the (k + M - n)-th row and the element in the k-th column of the (k + M - n + 1)-th row in the initial update matrix after the (n - 1)-th sub-iteration update in the k-th round of iteration; where n = 2, …, M.

[0171] As an example, the first target parameter of the first rotation process in multiple rounds of the first systolic array can be determined according to the element in the k-th column of the (k + M - n + 1)-th row, and the first systolic array is used to rotate the element in the k-th column of the (k + M - n)-th row and the element in the k-th column of the (k + M - n + 1)-th row based on the first target parameter of each round of the first rotation process, so that the rotated element in the k-th column of the (k + M - n + 1)-th row is 0, and the rotated element in the k-th column of the (k + M - n)-th row is a real number. The implementation principle is similar to that of step A and will not be elaborated here.

[0172] Step H: Based on the second systolic array, update multiple second element pairs in the initial update matrix after the (n - 1)-th round of iteration in the k-th round of iteration to obtain the initial update matrix after the n-th sub-iteration; wherein, the second element pair includes the element in the (k + M - n)-th row and the p-th column and the element in the (k + M - n + 1)-th row and the p-th column, where p = k + 1, …, N + 1; wherein, the target update matrix obtained by the k-th round of iteration update is the initial update matrix after the M-th sub-iteration in the k-th round of iteration.

[0173] As an example, the second target parameter in the second rotation process of multiple rounds can be determined based on the first target parameter of the first rotation process of multiple rounds, and the second systolic array can be used to rotate multiple second element pairs in the initial update matrix after the (n - 1)-th round of iteration based on the second target parameter of each round of the second rotation process, so that the rotated second element pairs are complex numbers. The implementation principle is similar to that of Step B and will not be elaborated here.

[0174] Among them, the second target parameter is used to control the rotation angle of the second rotation process.

[0175] Step S504, perform the N-th round of iteration in N rounds of iteration on the matrix to be processed based on the target systolic array, including: update the target update matrix obtained by the (N - 1)-th round of iteration based on the target systolic array to obtain the target update matrix obtained by the N-th round of iteration; extract the upper triangular matrix and the equivalent received vector from the first N rows of the target update matrix obtained by the N-th round of iteration.

[0176] In the embodiment of the present application, for the last round of iteration in N rounds of iteration, that is, the N-th round of iteration, the target update matrix obtained by the (N - 1)-th round of iteration can be directly updated based on the target systolic array to obtain the target update matrix obtained by the N-th round of iteration.

[0177] In any one of the embodiments of the present application, the target systolic array may include a first systolic array and a second systolic array connected to each other. The N-th round of iteration includes M sub-iterations. Among them, the first sub-iteration in the M sub-iterations may include the following Steps I to J:

[0178] Step I: Based on the first systolic array, update the element in the (N + M - 1)-th row and the N-th column and the element in the (N + M)-th row and the N-th column in the target update matrix obtained by the (N - 1)-th round of iteration. The implementation principle is similar to that of Step A and will not be elaborated here.

[0179] Step J: Based on the second systolic array, update multiple first element pairs in the target update matrix obtained after the (N - 1)-th round of iterative update to obtain the initial update matrix after the first sub-iteration update; wherein, the first element pair includes: the element in the (N + M - 1)-th row and the p-th column and the element in the (N + M)-th row and the p-th column, where p = N + 1. The implementation principle is similar to that of Step B and will not be elaborated here.

[0180] Among them, for the non-first sub-iterations in the M sub-iterations of the N-th round of iteration, such as the n-th sub-iteration, it may include the following Steps K to L:

[0181] Step K: Based on the first systolic array, update the element in the (N + M - n)-th row and the N-th column and the element in the (N + M - n + 1)-th row and the N-th column in the initial update matrix after the (n - 1)-th sub-iteration update in the N-th round of iteration; where n = 2,..., M. The implementation principle is similar to that of Step A and will not be elaborated here.

[0182] Step H: Based on the second systolic array, update multiple second element pairs in the initial update matrix after the (n - 1)-th round of iteration update in the N-th round of iteration to obtain the initial update matrix after the n-th sub-iteration update; wherein, the second element pair includes the element in the (N + M - n)-th row and the p-th column and the element in the (N + M - n + 1)-th row and the p-th column, where p = N + 1; wherein, the target update matrix obtained after the N-th round of iteration update is the initial update matrix after the N-th sub-iteration update in the N-th round of iteration.

[0183] In the embodiment of the present application, when the target update matrix obtained after the N-th round of iteration update is acquired, an N * N upper triangular matrix and an N * 1 equivalent received vector can be extracted from the first N rows of the target update matrix obtained after the N-th round of iteration update.

[0184] Step S505, recover the physical air interface signal sent by the transmitting end according to the upper triangular matrix and the equivalent received vector.

[0185] It should be noted that the explanation of Step S505 can refer to the relevant description in any embodiment of the present application and will not be elaborated here.

[0186] The signal processing method of the embodiment of the present application can accurately decompose the upper triangular matrix and the equivalent received vector through multiple rounds of iteration, so as to better separate the signals between different transmit streams, reduce the influence of multipath effects and other interferences. This iterative method gradually improves the signal quality, enhances the anti-interference ability of the system, and further improves the quality and reliability of the physical air interface signal recovered by the receiving end, and is applicable to complex wireless communication environments.

[0187] In any embodiment of the present application, by introducing a Cordic sorting systolic array to implement the Cholesky-based QR decomposition in the related art, the complexity of the solution is greatly reduced by converting multipliers, dividers, and square roots into adders, thereby reducing the power consumption at the receiving end. Taking N = M = 6 as an example for illustration, the structure of the systolic array can be as shown in Figure 6 As shown, where the Master systolic array is simply referred to as the M array, and the Slave systolic array is simply referred to as the S array. Then, the principle of matrix decomposition can be as shown in Figure 7 As shown, the matrix decomposition process mainly includes the following steps:

[0188] Step 1: Execute the first round of iteration in N rounds.

[0189] Step 1.1: Calculate the norms of each column in the first 6 rows of the matrix to be processed in step S402 above, that is, calculate the column norms of columns (1:6,1), (1:6,2), (1:6,3), (1:6,4), (1:6,5), and (1:6,6), and swap the column with the smallest column norm to (1:6,1).

[0190] Assume that the column with the smallest column norm is (1:6,1), then the updated matrix can also be as shown in step S402.

[0191] Step 1.2: Enter ((6,1),(7,1)) in the matrix into the Master systolic array, and enter ((6,2),(7,2)) to ((6,7),(7,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (6,1) becomes a real number R after cordic rotation, (7,1) becomes 0 after cordic rotation, and ((6,2),(7,2)) to ((6,7),(7,7)) become complex numbers C after cordic rotation:

[0192]

[0193] Step 1.3: Enter ((5,1),(6,1)) in the matrix into the Master systolic array, and enter ((5,2),(6,2)) to ((5,7),(6,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (5,1) becomes a real number R after cordic rotation, (6,1) becomes 0 after cordic rotation, and ((5,2),(6,2)) to ((5,7),(6,7)) become complex numbers C after cordic rotation:

[0194]

[0195] Step 1.4: Feed ((4,1),(5,1)) in the matrix into the Master systolic array, and feed ((4,2),(5,2)) to ((4,7),(5,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (4,1) becomes the real number R after cordic rotation, (5,1) becomes 0 after cordic rotation, and ((4,2),(5,2)) to ((4,7),(5,7)) become complex numbers C after cordic rotation:

[0196]

[0197] Step 1.5: Feed ((3,1),(4,1)) in the matrix into the Master systolic array, and feed ((3,2),(4,2)) to ((3,7),(4,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (3,1) becomes the real number R after cordic rotation, (4,1) becomes 0 after cordic rotation, and ((3,2),(4,2)) to ((3,7),(4,7)) become complex numbers C after cordic rotation:

[0198]

[0199] Step 1.6: Feed ((2,1),(3,1)) in the matrix into the Master systolic array, and feed ((2,2),(3,2)) to ((2,7),(3,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (2,1) becomes the real number R after cordic rotation, (3,1) becomes 0 after cordic rotation, and ((2,2),(3,2)) to ((2,7),(3,7)) become complex numbers C after cordic rotation:

[0200]

[0201] Step 1.7: Feed ((1,1),(2,1)) in the matrix into the Master systolic array, and feed ((1,2),(2,2)) to ((1,7),(2,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (1,1) becomes the real number R after cordic rotation, (2,1) becomes 0 after cordic rotation, and ((1,2),(2,2)) to ((1,7),(2,7)) become complex numbers C after cordic rotation:

[0202]

[0203] Step 2: Execute the second iteration in the N rounds.

[0204] Step 2.1: Calculate the column norms of columns (1:7,2), (1:7,3), (1:7,4), (1:7,5), and (1:7,6) in the matrix, and swap the column with the smallest column norm to (1:7,2). Assume the column with the smallest column norm is (1:7,2), then the updated matrix can also be as shown in Step 1.7.

[0205] Step 2.2: Feed ((7,2),(8,2)) in the matrix into the Master systolic array, and feed ((7,3),(8,3)) to ((7,7),(8,7)) into the Slave systolic array. After cordic operations, the following structure is obtained. Among them, (7,2) becomes the real number R after cordic rotation, (8,2) becomes 0 after cordic rotation, and ((7,3),(8,3)) to ((7,7),(8,7)) become complex numbers C after cordic rotation:

[0206]

[0207] Step 2.3: Feed ((6,2),(7,2)) in the matrix into the Master systolic array, and feed ((6,3),(7,3)) to ((6,7),(7,7)) into the Slave systolic array. After cordic operations, the following structure is obtained. Among them, (6,2) becomes the real number R after cordic rotation, (7,2) becomes 0 after cordic rotation, and ((6,3),(7,3)) to ((6,7),(7,7)) become complex numbers C after cordic rotation:

[0208]

[0209] Step 2.4: Feed ((5,2),(6,2)) in the matrix into the Master systolic array, and feed ((5,3),(6,3)) to ((5,7),(6,7)) into the Slave systolic array. After cordic operations, the following structure is obtained. Among them, (5,2) becomes the real number R after cordic rotation, (6,2) becomes 0 after cordic rotation, and ((5,3),(6,3)) to ((5,7),(6,7)) become complex numbers C after cordic rotation:

[0210]

[0211] Step 2.5: Feed ((4,2),(5,2)) in the matrix into the Master systolic array, and feed ((4,3),(5,3)) to ((4,7),(5,7)) into the Slave systolic array. After performing cordic operations, the following structure is obtained. Among them, (4,2) becomes the real number R after cordic rotation, (5,2) becomes 0 after cordic rotation, and ((4,3),(5,3)) to ((4,7),(5,7)) become the complex number C after cordic rotation:

[0212]

[0213] Step 2.6: Feed ((3,2),(4,2)) in the matrix into the Master systolic array, and feed ((3,3),(4,3)) to ((3,7),(4,7)) into the Slave systolic array. After performing cordic operations, the following structure is obtained. Among them, (3,2) becomes the real number R after cordic rotation, (4,2) becomes 0 after cordic rotation, and ((3,3),(4,3)) to ((3,7),(4,7)) become the complex number C after cordic rotation:

[0214]

[0215] Step 2.7: Feed ((2,2),(3,2)) in the matrix into the Master systolic array, and feed ((2,3),(3,3)) to ((2,7),(3,7)) into the Slave systolic array. After performing cordic operations, the following structure is obtained. Among them, (2,2) becomes the real number R after cordic rotation, (3,2) becomes 0 after cordic rotation, and ((2,3),(3,3)) to ((2,7),(3,7)) become the complex number C after cordic rotation:

[0216]

[0217] Step 3: Execute the third iteration in N rounds.

[0218] Step 3.1: Calculate the column norms of columns (1:8,3), (1:8,4), (1:8,5), and (1:8,6) in the matrix, and swap the column with the smallest column norm to (1:8,3). Assume the column with the smallest column norm is (1:8,3), then the updated matrix can also be as shown in Step 2.7.

[0219] Step 3.2: Feed ((8,3),(9,3)) in the matrix into the Master systolic array, and feed ((8,4),(9,4)) to ((8,7),(9,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (8,3) becomes the real number R after cordic rotation, (9,3) becomes 0 after cordic rotation, and ((8,4),(9,4)) to ((8,7),(9,7)) become the complex number C after cordic rotation:

[0220]

[0221] Step 3.3: Feed ((7,3),(8,3)) in the matrix into the Master systolic array, and feed ((7,4),(8,4)) to ((7,7),(8,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (7,3) becomes the real number R after cordic rotation, (8,3) becomes 0 after cordic rotation, and ((7,4),(8,4)) to ((7,7),(8,7)) become the complex number C after cordic rotation:

[0222]

[0223] Step 3.4: Feed ((6,3),(7,3)) in the matrix into the Master systolic array, and feed ((6,4),(7,4)) to ((6,7),(7,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (6,3) becomes the real number R after cordic rotation, (7,3) becomes 0 after cordic rotation, and ((6,4),(7,4)) to ((6,7),(7,7)) become the complex number C after cordic rotation:

[0224]

[0225] Step 3.5: Feed ((5,3),(6,3)) in the matrix into the Master systolic array, and feed ((5,4),(6,4)) to ((5,7),(6,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (5,3) becomes the real number R after cordic rotation, (6,3) becomes 0 after cordic rotation, and ((5,4),(6,4)) to ((5,7),(6,7)) become the complex number C after cordic rotation:

[0226]

[0227] Step 3.6: Input ((4,3),(5,3)) in the matrix into the Master systolic array, and input ((4,4),(5,4)) to ((4,7),(5,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (4,3) becomes the real number R after cordic rotation, (5,3) becomes 0 after cordic rotation, and ((4,4),(5,4)) to ((4,7),(5,7)) become the complex number C after cordic rotation:

[0228]

[0229] Step 3.7: Input ((3,3),(4,3)) in the matrix into the Master systolic array, and input ((3,4),(4,4)) to ((3,7),(4,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (3,3) becomes the real number R after cordic rotation, (4,3) becomes 0 after cordic rotation, and ((3,4),(4,4)) to ((3,7),(4,7)) become the complex number C after cordic rotation:

[0230]

[0231] Step 4: Execute the 4th iteration in N rounds.

[0232] Step 4.1: Calculate the column norms of columns (1:9,4), (1:9,5), and (1:9,6) in the matrix, and swap the column with the smallest column norm to (1:9,4). Assume the column with the smallest column norm is (1:9,4), then the updated matrix can also be as shown in Step 3.7.

[0233] Step 4.2: Input ((9,4),(10,4)) in the matrix into the Master systolic array, and input ((9,5),(10,5)) to ((9,7),(10,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (9,4) becomes the real number R after cordic rotation, (10,4) becomes 0 after cordic rotation, and ((9,5),(10,5)) to ((9,7),(10,7)) become the complex number C after cordic rotation:

[0234]

[0235] Step 4.3: Feed ((8,4),(9,4)) in the matrix into the Master systolic array, and feed ((8,5),(9,5)) to ((8,7),(9,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (8,4) becomes the real number R after cordic rotation, (9,4) becomes 0 after cordic rotation, and ((8,5),(9,5)) to ((8,7),(9,7)) become the complex number C after cordic rotation:

[0236]

[0237] Step 4.4: Feed ((7,4),(8,4)) in the matrix into the Master systolic array, and feed ((7,5),(8,5)) to ((7,7),(8,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (7,4) becomes the real number R after cordic rotation, (8,4) becomes 0 after cordic rotation, and ((7,5),(8,5)) to ((7,7),(8,7)) become the complex number C after cordic rotation:

[0238]

[0239] Step 4.5: Feed ((6,4),(7,4)) in the matrix into the Master systolic array, and feed ((6,5),(7,5)) to ((6,7),(7,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (6,4) becomes the real number R after cordic rotation, (7,4) becomes 0 after cordic rotation, and ((6,5),(7,5)) to ((6,7),(7,7)) become the complex number C after cordic rotation:

[0240]

[0241] Step 4.6: Feed ((5,4),(6,4)) in the matrix into the Master systolic array, and feed ((5,5),(6,5)) to ((5,7),(6,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (5,4) becomes the real number R after cordic rotation, (6,4) becomes 0 after cordic rotation, and ((5,5),(6,5)) to ((5,7),(6,7)) become the complex number C after cordic rotation:

[0242]

[0243] Step 4.7: Feed ((4,4),(5,4)) in the matrix into the Master systolic array, and feed ((4,5),(5,5)) to ((4,7),(5,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (4,4) becomes the real number R after cordic rotation, (5,4) becomes 0 after cordic rotation, and ((4,5),(5,5)) to ((4,7),(5,7)) become the complex number C after cordic rotation:

[0244]

[0245] Step 5: Execute the 5th iteration in N rounds.

[0246] Step 5.1: Calculate the column norms of columns (1:10,5) and (1:10,6) in the matrix, and swap the column with the smallest column norm to (1:10,5). Assume that the column with the smallest column norm is (1:10,5), then the updated matrix can be as shown in Step 4.7.

[0247] Step 5.2: Feed ((10,5),(11,5)) in the matrix into the Master systolic array, and feed ((10,6),(11,6)) to ((10,7),(11,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (10,5) becomes the real number R after cordic rotation, (11,5) becomes 0 after cordic rotation, and ((10,6),(11,6)) to ((10,7),(11,7)) become the complex number C after cordic rotation:

[0248]

[0249] Step 5.3: Feed ((9,5),(10,5)) in the matrix into the Master systolic array, and feed ((9,6),(10,6)) to ((9,7),(10,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (9,5) becomes the real number R after cordic rotation, (10,5) becomes 0 after cordic rotation, and ((9,6),(10,6)) to ((9,7),(10,7)) become the complex number C after cordic rotation:

[0250]

[0251] Step 5.4: Feed ((8,5),(9,5)) in the matrix into the Master systolic array, and feed ((8,6),(9,6)) to ((8,7),(9,7)) into the Slave systolic array. After cordic operations, the following structure is obtained. Among them, (8,5) becomes the real number R after cordic rotation, (9,5) becomes 0 after cordic rotation, and ((8,6),(9,6)) to ((8,7),(9,7)) become the complex number C after cordic rotation:

[0252]

[0253] Step 5.5: Feed ((7,5),(8,5)) in the matrix into the Master systolic array, and feed ((7,6),(8,6)) to ((7,7),(8,7)) into the Slave systolic array. After cordic operations, the following structure is obtained. Among them, (7,5) becomes the real number R after cordic rotation, (8,5) becomes 0 after cordic rotation, and ((7,6),(8,6)) to ((7,7),(8,7)) become the complex number C after cordic rotation:

[0254]

[0255] Step 5.6: Feed ((6,5),(7,5)) in the matrix into the Master systolic array, and feed ((6,6),(7,6)) to ((6,7),(7,7)) into the Slave systolic array. After cordic operations, the following structure is obtained. Among them, (6,5) becomes the real number R after cordic rotation, (7,5) becomes 0 after cordic rotation, and ((6,6),(7,6)) to ((6,7),(7,7)) become the complex number C after cordic rotation:

[0256]

[0257] Step 5.7: Feed ((5,5),(6,5)) in the matrix into the Master systolic array, and feed ((5,6),(6,6)) to ((5,7),(6,7)) into the Slave systolic array. After cordic operations, the following structure is obtained. Among them, (5,5) becomes the real number R after cordic rotation, (6,5) becomes 0 after cordic rotation, and ((5,6),(6,6)) to ((5,7),(6,7)) become the complex number C after cordic rotation:

[0258]

[0259] Step 6: Execute the 6th iteration in the N rounds.

[0260] Step 6.1: Since there is only the 6th column, there is no need to perform column update operations.

[0261] Step 6.2: Put ((11,6),(12,6)) in the matrix into the Master systolic array, and ((11,7),(12,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (11,6) becomes the real number R after cordic rotation, (12,6) becomes 0 after cordic rotation, and ((11,7),(12,7)) becomes the complex number C after cordic rotation:

[0262]

[0263] Step 6.3: Put ((10,6),(11,6)) in the matrix into the Master systolic array, and ((10,7),(11,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (10,6) becomes the real number R after cordic rotation, (11,6) becomes 0 after cordic rotation, and ((10,7),(11,7)) becomes the complex number C after cordic rotation:

[0264]

[0265] Step 6.4: Put ((9,6),(10,6)) in the matrix into the Master systolic array, and ((9,7),(10,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (9,6) becomes the real number R after cordic rotation, (10,6) becomes 0 after cordic rotation, and ((9,7),(10,7)) becomes the complex number C after cordic rotation:

[0266]

[0267] Step 6.5: Put ((8,6),(9,6)) in the matrix into the Master systolic array, and ((8,7),(9,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (8,6) becomes the real number R after cordic rotation, (9,6) becomes 0 after cordic rotation, and ((8,7),(9,7)) becomes the complex number C after cordic rotation:

[0268]

[0269] Step 6.6: Feed ((7,6),(8,6)) in the matrix into the Master systolic array and ((7,7),(8,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (7,6) becomes the real number R after cordic rotation, (8,6) becomes 0 after cordic rotation, and ((7,7),(8,7)) becomes the complex number C after cordic rotation:

[0270]

[0271] Step 6.7: Feed ((6,6),(7,6)) in the matrix into the Master systolic array and ((6,7),(7,7)) into the Slave systolic array. After cordic operation, the following structure is obtained. Among them, (6,6) becomes the real number R after cordic rotation, (7,6) becomes 0 after cordic rotation, and ((6,7),(7,7)) becomes the complex number C after cordic rotation:

[0272]

[0273] Step 7: The systolic operation ends. (1:6,1:6) in the matrix is a 6x6 upper triangular matrix, and (1:6,7) in the matrix is a 6x1 equivalent received vector. In this application, signal detection can be performed based on the decomposed upper triangular matrix and the equivalent received vector to recover the physical air interface signal transmitted by the transmitting end.

[0274] In summary, the operation amount of QR decomposition using the cordic sorting systolic array is shown in Table 2.

[0275] Table 2 Operation amount of QR decomposition using the cordic sorting systolic array

[0276] Computational amount Real addition Master systolic array 12 Slave systolic array 42

[0277] As can be seen from Table 2, the operation amount of QR decomposition using the cordic sorting systolic array is converted into real number additions in total: real number additions * cordic iteration times (i.e., the iteration times D of the first rotation process or the second rotation process). Exemplarily, taking D as 11 for example, the operation amount of QR decomposition using the cordic sorting systolic array is converted into real number additions in total = (12 + 42) * 11 = 54 * 11 = 594. Compared with Table 1, the complexity can be reduced by (46006 - 594) / 46006 = 98.7%, solving the problems of high signal detection power consumption and high cost in 6Rx 6MIMO.

[0278] To implement the above embodiments, an embodiment of the present application also proposes a signal processing device.

[0279] Figure 8 The structural schematic diagram of a signal processing device provided by an embodiment of the present application.

[0280] As Figure 8 shown, the signal processing device 800 may include: a splicing module 810, an iterative module 820, and a recovery module 830.

[0281] Among them, the splicing module 810 is used to splice the received signal vector at the receiving end and the channel matrix to obtain a matrix to be processed; among them, the channel matrix is used to indicate the channel gain between the transmitted streams at the transmitting end and multiple receiving antennas at the receiving end, and the received channel vector is used to indicate the signals received by multiple receiving antennas;

[0282] The iterative module 820 is used to perform iteration on the matrix to be processed based on the target systolic array to obtain an upper triangular matrix and an equivalent received vector;

[0283] The recovery module 830 is used to recover the physical air interface signal transmitted by the transmitting end according to the upper triangular matrix and the equivalent received vector.

[0284] Further, in an implementation manner of the embodiment of the present application, the recovery module 830 is used to: perform signal detection according to the upper triangular matrix and the equivalent received vector to obtain soft value information; among them, the soft value information includes the soft values of the digital signals corresponding to the physical air interface signals in each time unit, and the soft value is determined according to the ratio of the probability that the digital signal takes the first value and the probability that the digital signal takes the second value at the corresponding time unit; perform signal decoding on the soft value information to restore the physical air interface signal transmitted by the transmitting end.

[0285] In an implementation manner of the embodiment of the present application, the splicing module 810 is used to: splice the channel matrix and the received signal vector in the column dimension to obtain an intermediate matrix; splice the intermediate matrix with the identity matrix in the row dimension to obtain a matrix to be processed.

[0286] In an implementation manner of the embodiment of the present application, the number of receiving antennas is M, the number of transmitted streams is N, the channel matrix is a matrix of M*N, the element in the i-th row and j-th column of the channel matrix is used to indicate the channel gain experienced when the j-th transmitted stream from the transmitting end reaches the i-th receiving antenna at the receiving end, i is a positive integer not greater than M, j is a positive integer not greater than N, and M≥N; the received signal vector is a vector of M*1, and the element in the i-th row of the received signal vector is used to indicate the signal received by the i-th receiving antenna; the matrix to be processed is a matrix of (M + N)*(N + 1), and the number of iteration rounds is N rounds.

[0287] In an implementation manner of the embodiment of the present application, the iteration module 820 performs the first iteration among N rounds of iterations, specifically: determining a first target column from each column in the first M rows according to the norms of each column in the first M rows of the matrix to be processed; swapping the positions of the first target column and the first column in the first M rows to obtain an initial update matrix in the first iteration; and updating the initial update matrix in the first iteration based on the target systolic array to obtain a target update matrix updated in the first iteration.

[0288] In an implementation manner of the embodiment of the present application, the iteration module 820 performs the k-th iteration among N rounds of iterations, specifically: determining a second target column from each column in the first (k + M - 1) rows according to the norms of each column in the first (k + M - 1) rows of the target update matrix updated in the (k - 1)-th iteration; where k = 2,..., N - 1; swapping the positions of the second target column and the k-th column in the first (k + M - 1) rows to obtain an initial update matrix in the k-th iteration; and updating the initial update matrix in the k-th iteration based on the target systolic array to obtain a target update matrix updated in the k-th iteration.

[0289] In an implementation manner of the embodiment of the present application, the iteration module 820 performs the N-th iteration among N rounds of iterations, specifically: updating the target update matrix updated in the (N - 1)-th iteration based on the target systolic array to obtain a target update matrix updated in the N-th iteration; and extracting an upper triangular matrix and an equivalent received vector from the first N rows of the target update matrix updated in the N-th iteration.

[0290] In an implementation manner of the embodiment of the present application, the target systolic array includes a first systolic array and a second systolic array connected to each other. Each round of iteration includes M sub-iterations. The iteration module 820 performs the first sub-iteration among the M sub-iterations in the q-th iteration, specifically: updating the element in the (q + M - 1)-th row and the q-th column and the element in the (q + M)-th row and the q-th column of the initial update matrix in the q-th iteration based on the first systolic array; where q = 1,..., N - 1; updating a plurality of first element pairs in the initial update matrix in the q-th iteration based on the second systolic array to obtain an initial update matrix updated after the first sub-iteration; where the first element pair includes: the element in the (q + M - 1)-th row and the p-th column and the element in the (q + M)-th row and the p-th column, where p = q + 1,..., N + 1.

[0291] In an implementation manner of the embodiment of the present application, the iteration module 820 performs the nth sub-iteration in the M sub-iterations of the qth iteration, specifically: updating the element in the qth column of the (q + M - n)th row and the element in the qth column of the (q + M - n + 1)th row in the initial update matrix updated by the (n - 1)th sub-iteration based on the first systolic array; where n = 2, …, M; updating a plurality of second element pairs in the initial update matrix after the (n - 1)th iteration based on the second systolic array to obtain the initial update matrix updated by the nth sub-iteration; where the second element pair includes the element in the pth column of the (q + M - n)th row and the element in the pth column of the (q + M - n + 1)th row; where the target update matrix obtained by the qth iteration update is the initial update matrix updated by the Mth sub-iteration in the qth iteration.

[0292] In an implementation manner of the embodiment of the present application, the iteration module 820 is specifically configured to: determine a first target parameter of the first systolic array in multiple rounds of first rotation processes according to the element in the qth column of the (q + M)th row; where the first target parameter is used to control the rotation angle of the first rotation process; use the first systolic array to rotate the element in the qth column of the (q + M - 1)th row and the element in the qth column of the (q + M)th row based on the first target parameter of each round of the first rotation process, so that the rotated element in the qth column of the (q + M)th row is 0 and the rotated element in the qth column of the (q + M - 1)th row is a real number.

[0293] In an implementation manner of the embodiment of the present application, the iteration module 820 is specifically configured to: determine a second target parameter of the second systolic array in multiple rounds of second rotation processes based on the first target parameter of multiple rounds of first rotation processes; where the second target parameter is used to control the rotation angle of the second rotation process; use the second systolic array to rotate a plurality of first element pairs in the initial update matrix in the qth iteration based on the second target parameter of each round of the second rotation process, so that the rotated first element pair is a complex number.

[0294] It should be noted that the foregoing explanation of the signal processing method embodiment also applies to the signal processing device of this embodiment, and will not be elaborated here.

[0295] In the signal processing device of the embodiment of the present application, by adopting an efficient parallel computing architecture - the target systolic array, multiple rounds of iterations are performed to implement matrix decomposition, so as to obtain the upper triangular matrix R and the equivalent received vector z, which can simplify the computational complexity and improve the computational efficiency, and achieve high throughput and low latency computing. Moreover, multiple rounds of iterations help to better separate the signals between different transmit streams, reduce the influence of multipath effects and other interferences. This iterative method gradually improves the signal quality, enhances the anti-interference ability of the system, and further improves the quality and reliability of the physical air interface signal recovered at the receiving end, and is applicable to complex wireless communication environments.

[0296] To implement the above embodiments, the present application further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the signal processing method described in any of the foregoing embodiments is implemented.

[0297] Figure 9 FIG. 6 is a schematic structural diagram of an electronic device provided by an embodiment of the present application. For example, the electronic device 900 may be a vehicle, a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0298] Referring to Figure 9 , the electronic device 900 may include one or more of the following components: a processing component 902, a memory 904, a power component 906, a multimedia component 908, an audio component 910, an input / output (I / O) interface 912, a sensor component 914, and a communication component 916.

[0299] The processing component 902 generally controls the overall operation of the electronic device 900, such as operations associated with display, telephone calls, data communication, camera operations, and recording operations. The processing component 902 may include one or more processors 920 to execute instructions to complete all or part of the steps of the above method. In addition, the processing component 902 may include one or more modules to facilitate the interaction between the processing component 902 and other components. For example, the processing component 902 may include a multimedia module to facilitate the interaction between the multimedia component 908 and the processing component 902.

[0300] The memory 904 is configured to store various types of data to support the operation of the electronic device 900. Examples of such data include instructions for any application or method operating on the electronic device 900, contact data, phone book data, messages, pictures, videos, and the like. The memory 904 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0301] The power component 906 provides power for various components of the electronic device 900. The power component 906 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 900.

[0302] The multimedia component 908 includes a screen that provides an output interface between the electronic device 900 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can not only sense the boundaries of the touch or swipe actions, but also detect the duration and pressure associated with the touch or swipe operations. In some embodiments, the multimedia component 908 includes a front camera and / or a rear camera. When the electronic device 900 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.

[0303] The audio component 910 is configured to output and / or input audio signals. For example, the audio component 910 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 900 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 904 or transmitted via the communication component 916. In some embodiments, the audio component 910 further includes a speaker for outputting audio signals.

[0304] The I / O interface 912 provides an interface between the processing component 902 and a peripheral interface module, which may be a keyboard, a click wheel, buttons, etc. These buttons can include, but are not limited to: a home button, a volume button, a power button, and a lock button.

[0305] The sensor component 914 includes one or more sensors for providing an assessment of the state of various aspects of the electronic device 900. For example, the sensor component 914 can detect the open / closed state of the electronic device 900, the relative positioning of components, such as the display and keypad of the electronic device 900. The sensor component 914 can also detect a change in the position of the electronic device 900 or a component of the electronic device 900, the presence or absence of user contact with the electronic device 900, the orientation or acceleration / deceleration of the electronic device 900, and a change in the temperature of the electronic device 900. The sensor component 914 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor component 914 can also include a light sensor, such as a Complementary Metal-Oxide-Semiconductor (CMOS) or a Charge-Coupled Device (CCD) image sensor, for use in imaging applications. In some embodiments, the sensor component 914 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0306] The communication component 916 is configured to facilitate communication between the electronic device 900 and other devices in a wired or wireless manner. The electronic device 900 can access a communication standard-based wireless network, such as WiFi, 4G, or 5G, or a combination thereof. In an exemplary embodiment, the communication component 916 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 916 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra-Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0307] In an exemplary embodiment, the electronic device 900 can be implemented by one or more Application-Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field-Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above method.

[0308] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 904 including instructions, and the above instructions can be executed by a processor 920 of the electronic device 900 to complete the above method. For example, the non-transitory computer-readable storage medium can be a Read-Only Memory (ROM), Random Access Memory (RAM), Compact Disc Read-Only Memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0309] To implement the above embodiments, the present application also provides a chip. The chip includes an interface circuit and a processing circuit that are coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to execute the signal processing method provided in any of the foregoing embodiments.

[0310] Figure 10 It is a schematic structural diagram of a chip proposed in an embodiment of the present application. Reference may be made to Figure 10 the schematic structural diagram of the chip 1000 shown, but not limited thereto.

[0311] The chip 1000 includes a processing circuit 1001, and the processing circuit 1001 is configured to execute any of the above signal processing methods.

[0312] In some embodiments, the chip 1000 further includes one or more interface circuits 1002. Optionally, the interface circuit 1002 is connected to the memory 1003. The interface circuit 1002 can be used to receive signals from the memory 1003 or other devices, and the interface circuit 1002 can be used to send signals to the memory 1003 or other devices. For example, the interface circuit 1002 can read the instructions stored in the memory 1003 and send the instructions to the processing circuit 1001.

[0313] In some embodiments, the interface circuit 1002 executes at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 1001 executes other steps.

[0314] In some embodiments, terms such as interface circuit, interface, transceiver pin, transceiver, etc. can be replaced with each other.

[0315] In some embodiments, the chip 1000 further includes one or more memories 1003 for storing instructions. Optionally, all or part of the memory 1003 can be outside the chip 1000.

[0316] To implement the above embodiments, the present application also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the signal processing method described in any of the foregoing method embodiments is implemented.

[0317] To implement the above embodiments, the present application also provides a computer program product, on which a computer program is stored. When the computer program is executed by a processor, the signal processing method described in any of the foregoing method embodiments is implemented.

[0318] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc., mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0319] In addition, the terms "first" and "second" are used only for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0320] Any process or method description, either in a flowchart or described otherwise herein, can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logical function or process, and the scope of the preferred embodiments of this application includes additional implementations, where the functions may be executed in a substantially simultaneous manner or in a reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of this application pertain.

[0321] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a definable sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or used in conjunction with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: electrical connection parts with one or more wirings (electronic devices), portable computer disk cartridges (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber devices, and portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other suitable processing when necessary, and then stored in a computer memory.

[0322] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits having suitable combinational logic gate circuits, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0323] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the method of implementing the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0324] In addition, each functional unit in various embodiments of the present application may be integrated into a processing module, or each unit may exist physically alone, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0325] The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disc, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present application.

Claims

1. A signal processing method, characterized in that, including: concatenating a received signal vector and a channel matrix at a receiving end to obtain a matrix to be processed; wherein, the channel matrix is used to indicate a channel gain between a transmitted stream at a transmitting end and multiple receiving antennas at the receiving end, and the received channel vector is used to indicate signals received by the multiple receiving antennas; performing iteration on the matrix to be processed based on a target systolic array to obtain an upper triangular matrix and an equivalent received vector; restoring a physical air interface signal transmitted by the transmitting end according to the upper triangular matrix and the equivalent received vector.

2. The method according to claim 1, characterized in that, The restoring the physical air interface signal transmitted by the transmitting end according to the upper triangular matrix and the equivalent received vector includes: performing signal detection according to the upper triangular matrix and the equivalent received vector to obtain soft value information; wherein, the soft value information includes soft values of a digital signal corresponding to the physical air interface signal at each time unit, and the soft value is determined according to a ratio of a probability that the digital signal takes a first value and a probability that the digital signal takes a second value at a corresponding time unit; performing signal decoding on the soft value information to restore the physical air interface signal transmitted by the transmitting end.

3. The method according to claim 1, wherein The concatenating the received signal vector and the channel matrix at the receiving end to obtain the matrix to be processed includes: concatenating the channel matrix and the received signal vector in a column dimension to obtain an intermediate matrix; concatenating the intermediate matrix and an identity matrix in a row dimension to obtain the matrix to be processed.

4. The method according to claim 3, wherein The number of the receiving antennas is M, the number of the transmitted streams is N, the channel matrix is an M*N matrix, and an element in the i-th row and the j-th column of the channel matrix is used to indicate a channel gain experienced when the j-th transmitted stream from the transmitting end arrives at the i-th receiving antenna at the receiving end, where i is a positive integer not greater than M, j is a positive integer not greater than N, and M≥N; the received signal vector is an M*1 vector, and an element in the i-th row of the received signal vector is used to indicate a signal received by the i-th receiving antenna; the matrix to be processed is an (M+N)*(N+1) matrix, and the number of rounds of the iteration is N rounds.

5. The method according to claim 4, wherein The first round of iteration in the N rounds of iteration includes: determining a first target column from each column in the first M rows of the matrix to be processed according to the norm of each column in the first M rows; exchanging the positions of the first target column and the first column in the first M rows to obtain an initial updated matrix in the first round of iteration; updating the initial updated matrix in the first round of iteration based on the target systolic array to obtain a target updated matrix updated in the first round of iteration.

6. The method according to claim 5, wherein The k-th round of iteration in the N rounds of iteration includes: determining a second target column from each column in the first (k+M-1) rows of the target updated matrix updated in the (k-1)-th round of iteration according to the norm of each column in the first (k+M-1) rows; where k = 2,…,N-1; exchanging the positions of the second target column and the k-th column in the first (k+M-1) rows to obtain an initial updated matrix in the k-th round of iteration; Update the initial update matrix in the k-th iteration based on the target systolic array to obtain the target update matrix updated in the k-th iteration.

7. The method according to claim 6, characterized in that The N-th iteration among the N iterations includes: Update the target update matrix updated in the (N - 1)-th iteration based on the target systolic array to obtain the target update matrix updated in the N-th iteration; Extract the upper triangular matrix and the equivalent received vector from the first N rows of the target update matrix updated in the N-th iteration.

8. The method according to any one of claims 5-7, characterized in that, The target systolic array includes a first systolic array and a second systolic array connected to each other. Each iteration includes M sub-iterations. The first sub-iteration among the M sub-iterations in the q-th iteration includes: Update the element in the q-th column of the (q + M - 1)-th row and the element in the q-th column of the (q + M)-th row in the initial update matrix in the q-th iteration based on the first systolic array; where q = 1, …, N - 1; Update multiple first element pairs in the initial update matrix in the q-th iteration based on the second systolic array to obtain the initial update matrix after the first sub-iteration update; Wherein, the first element pair includes: the element in the p-th column of the (q + M - 1)-th row and the element in the p-th column of the (q + M)-th row, where p = q + 1, …, N + 1.

9. The method according to claim 8, characterized in that, The n-th sub-iteration among the M sub-iterations in the q-th iteration includes: Update the element in the q-th column of the (q + M - n)-th row and the element in the q-th column of the (q + M - n + 1)-th row in the initial update matrix after the (n - 1)-th sub-iteration update based on the first systolic array; where n = 2, …, M; Update multiple second element pairs in the initial update matrix after the (n - 1)-th iteration update based on the second systolic array to obtain the initial update matrix after the n-th sub-iteration update; Wherein, the second element pair includes the element in the p-th column of the (q + M - n)-th row and the element in the p-th column of the (q + M - n + 1)-th row; Wherein, the target update matrix updated in the q-th iteration is the initial update matrix after the M-th sub-iteration update in the q-th iteration.

10. The method according to claim 8, wherein The updating of the element in the q-th column of the (q + M - 1)-th row and the element in the q-th column of the (q + M)-th row in the initial update matrix in the q-th iteration based on the first systolic array includes: Determine the first target parameter of the first rotation process of the first systolic array in multiple rounds according to the element in the q-th column of the (q + M)-th row; wherein, the first target parameter is used to control the rotation angle of the first rotation process; Use the first systolic array to rotate the element in the q-th column of the (q + M - 1)-th row and the element in the q-th column of the (q + M)-th row based on the first target parameter of each round of the first rotation process, so that the element in the q-th column of the (q + M)-th row after rotation is 0, and the element in the q-th column of the (q + M - 1)-th row after rotation is a real number.

11. The method according to claim 10, characterized in that The updating of multiple first element pairs in the initial update matrix in the q-th iteration based on the second systolic array includes: Determine a second target parameter of the second rotation process of the multi-round based on a first target parameter of the first rotation process of the multi-round; wherein, the second target parameter is used to control a rotation angle of the second rotation process. Using the second pulsating array, rotate a plurality of first element pairs in an initial update matrix in the q-th iteration based on the second target parameter of each round of the second rotation process, so that the rotated first element pairs are complex numbers.

12. A signal processing device, characterized in that, Comprising: A splicing module, configured to splice a received signal vector and a channel matrix at a receiving end to obtain a matrix to be processed; wherein, the channel matrix is used to indicate a channel gain between a transmission stream at a transmitting end and multiple receiving antennas at the receiving end, and the received channel vector is used to indicate signals received by the multiple receiving antennas. An iterative module, configured to perform iteration on the matrix to be processed based on a target pulsating array to obtain an upper triangular matrix and an equivalent received vector. A recovery module, configured to recover a physical air interface signal transmitted by the transmitting end according to the upper triangular matrix and the equivalent received vector.

13. An electronic device, characterized in that, Comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, when the processor executes the program, implementing the steps of the method according to any one of claims 1 to 11.

14. A chip, characterized in that, The chip comprises an interface circuit and a processing circuit which are mutually coupled, the interface circuit is used for inputting or outputting signals, and the processing circuit is used for implementing the method according to any one of claims 1 to 11.

15. A non-transitory computer-readable storage medium storing computer program instructions thereon, characterized in that, When the program instruction is executed by the processor, implementing the steps of the method according to any one of claims 1 to 11.

16. A computer program product, characterized in that, Comprising a computer program, when the computer program is executed by the processor, implementing the steps of the method according to any one of claims 1 to 11.

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