Image processing chip, image acquisition equipment and vehicle

Abstract

The invention provides an image processing chip, image acquisition equipment and a vehicle, and the method comprises an image input interface which is connected with the output end of an image acquisition unit and is used for receiving image data outputted by the image acquisition unit; and the first end of the shunt processing module is connected with the other end of the image input interface, and the shunt processing module is used for distributing a shunt and a path for the image data, performing image processing on the image data according to the shunt and the path, and outputting target image data. Based on the connection relationship between the image input interface and the shunt processing module, the image data is received by using the image input interface, a plurality of image processing branches and paths are arranged according to different processing requirements, and the image data is sent to the corresponding branches and paths for image processing by using the shunt processing module according to required settings. According to the invention, multi-channel simultaneous processing is realized according to requirements, the flexibility and applicability of an image processing architecture and a link are improved, and the requirement of simultaneously and rapidly processing multiple processing images is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing, and in particular, to an image processing chip, an image acquisition device, and a vehicle. Background Art

[0002] In the related art, taking the application of an image processing chip in a vehicle as an example, after a camera on the vehicle, as an image acquisition device, acquires image data, an image input interface receives it and then sends it into a pipeline with image processing functions, and finally outputs it from the image output interface to a receiving unit such as a domain controller.

[0003] However, when using the above-mentioned image processing chip, there are problems of relatively large architectural limitations in processing image data and inflexible links, resulting in the inability to meet the rapid multi-processing image requirements and increasing the software and hardware costs for multi-image processing requirements. For example, when two domain controllers share a camera, the camera can only be connected to one domain controller first, and then a path of data is branched from this domain controller and forwarded to another domain controller. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0005] To this end, an object of the present invention is to provide an image processing chip, which enables multi-channel simultaneous processing of image data as required, improves the flexibility and applicability of the image processing architecture and links, and realizes simultaneous and rapid processing of various image processing requirements.

[0006] To this end, a second object of the present invention is to provide an image acquisition device.

[0007] To this end, a third object of the present invention is to provide a vehicle.

[0008] To achieve the above object, an embodiment of the first aspect of the present invention provides an image processing chip, which includes: an image input interface connected to the output end of an image acquisition unit for receiving image data output by the image acquisition unit; a splitting and processing module, the first end of the splitting and processing module is connected to the other end of the image input interface, for allocating splits and paths for the image data, and performing image processing on the image data according to the splits and paths, and outputting target image data.

[0009] According to the method of an embodiment of the present invention, based on the connection relationship between the image input interface and the shunt processing module, image data is received by using the image input interface, multiple image processing shunts and paths are set according to different processing requirements, and the shunt processing module is used to send the image data into the corresponding shunts and paths for image processing according to the required settings, realizing multi-channel simultaneous processing according to requirements, improving the flexibility and applicability of the image processing architecture and link, and realizing simultaneous and fast processing of various image processing requirements.

[0010] In some embodiments, the shunt processing module includes: a splitter and a processing unit, the input end of the splitter and the processing unit is connected to the other end of the image input interface, and is used to receive the image data and allocate the shunts and paths of the image data; a shunt processing output unit, the first end of the shunt processing output unit is connected to the output end of the splitter and the processing unit, and is used to obtain target image data according to the image data allocated by the shunts and paths, and output the target image data to the controller; a processor, the input end of the processor is connected to the second end of the shunt processing output unit, and is used to configure and control the splitter and the processing unit and the shunt processing output unit.

[0011] In some embodiments, the shunt processing output unit includes: an image processing pipeline, the input end of the image processing pipeline is connected to the output end of the splitter and the processing unit, and is used to perform image processing on the image data allocated by the shunts and paths to obtain target image data; an image output interface, the input end of the image output interface is connected to the output end of the image processing pipeline, and is used to output the target image data to the controller.

[0012] In some embodiments, the image processing pipeline consists of at least two and the image processing pipeline is correspondingly connected to the image output interface.

[0013] In some embodiments, the processor includes: a first control port, connected to the control port of the image acquisition unit, and is used to provide a control signal for the image acquisition unit; a first communication port, connected to the communication interface of the image acquisition unit, and is used to configure and drive the image acquisition unit to work.

[0014] In some embodiments, the processor further includes: a second control port, connected to the control interface of the controller, and is used to receive the control signal provided by the controller; a second communication port, connected to the communication interface of the controller, and is used to receive the operation information of the controller to configure and drive the image processing chip to work.

[0015] In some embodiments, when receiving the operation information of the controller to configure and drive the image processing chip, the processor is specifically configured to: obtain the operation information sent by the controller; if the operation information is greater than or equal to a preset information threshold, obtain the working priority of the controller; and configure and drive the image processing chip according to the working priority.

[0016] To achieve the above object, an embodiment of the second aspect of the present invention provides an image acquisition device, which includes: an image acquisition unit for acquiring image data; and an image processing chip as described in the above embodiment, connected to the image acquisition unit, for receiving the image data output by the image acquisition unit, allocating a branch and a path for the image data, and performing image processing on the image data according to the branch and the path, and outputting target image data.

[0017] In some embodiments, the image acquisition device further includes: a clock module connected to the clock interface of the image processing chip for providing a clock control signal for the image processing chip; a reset module connected to the reset interface of the image processing chip for providing a reset control signal for the image processing chip; a storage module connected to the storage interface of the image processing chip for storing the data of the image acquisition device; and a power management module connected to the power management interface of the image processing chip for supplying power to the image acquisition device.

[0018] According to the image acquisition device of the embodiment of the present invention, the image processing chip of the above embodiment is configured on the device. Based on the connection relationship between the image input interface and the branch processing module, the image data is received by using the image input interface, multiple image processing branches and paths are set according to different processing requirements, and the branch processing module is used to send the image data into the corresponding branches and paths for image processing according to the required settings, realizing multi-channel simultaneous processing according to requirements, improving the flexibility and applicability of the image processing architecture and link, and realizing simultaneous and fast processing of various image processing requirements.

[0019] To achieve the above object, an embodiment of the third aspect of the present invention provides a vehicle, which includes: an image acquisition device as described in the above embodiment.

[0020] A vehicle according to an embodiment of the present invention is equipped with the image acquisition device of the above embodiment. Based on the connection relationship between the image input interface and the branch processing module, image data is received through the use of the image input interface. Multiple image processing branches and paths are set according to different processing requirements, and the branch processing module is used to send the image data into the corresponding branches and paths for image processing according to the required settings, achieving multi-channel simultaneous processing according to requirements, improving the flexibility and applicability of the image processing architecture and link, and realizing the simultaneous and rapid processing of multiple image processing requirements.

[0021] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram of an image processing chip according to an embodiment of the present invention; Figure 2 is a block diagram of an image processing chip with different channels according to an embodiment of the present invention; Figure 3 is a block diagram of an image processing chip with the same channel according to an embodiment of the present invention; Figure 4 is a block diagram of an image acquisition device according to an embodiment of the present invention; Figure 5 is a block diagram of a vehicle according to an embodiment of the present invention.

[0023] REFERENCE NUMERALS: image acquisition unit 18; branch processing module 19; image input interface 20; image processing chip 100; splitter and processing unit 21; image processing pipeline 24; image output interface 27; processor 28; control interface 29 of the image sensor; communication interface 30 of the image sensor; control interface 31 of the receiving unit; communication interface 32 of the receiving unit; first image processing pipeline 22; second image processing pipeline 23; first image output interface 25; second image output interface 26; image acquisition device 53; Clock module 50; reset module 51; storage module 52; image sensor 54; serializer 55; power management module 56; first data bus 57; first general control pin 58; first communication control bus 59; second data bus 60; second general control pin 61; second communication control bus 62; third communication control bus 63; third general control pin 64; third data bus 65; first serialized data link 66; second serialized data link 67; Vehicle 102. Detailed implementation mode

[0024] The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention will be described in detail below.

[0025] In the related art, taking the application of an image processing chip in a vehicle as an example, for today's increasingly intelligent cars, many cameras are used on a single vehicle, installed at different positions for different functions. Among them, some cameras are used for the cockpit, and some are used for intelligent driving functions. In most applications, these two types of cameras have different application scenarios and requirements, and separate camera devices are used for each.

[0026] However, with the development of the solution, there has been some integration between the cockpit domain and the intelligent driving domain. Moreover, there are some overlapping positions between the cameras used in the cockpit and the intelligent driving cameras. Considering aspects such as project solutions and costs, a camera reuse solution has emerged. That is, the functions that are not completely the same between the cockpit domain and the intelligent driving domain use the same camera device in hardware. However, because the working characteristics such as the startup time of the cockpit domain and the intelligent driving domain are different, and their requirements for images are also different (such as data format, image size, field of view, noise reduction, etc.), many scenarios cannot simultaneously meet the requirements of both sides, and only some trade-offs can be made.

[0027] Generally, the image sensor of a camera outputs an image as a stream of RAW format data. There are mainly two solutions for the processing link of this data: The first is that the data given by the image sensor flows through the transmission link to the domain controller platform, and the image processor on the domain controller processes the image in terms of format, image quality, etc., and then further sends the data to the application program or algorithm; The second is that the data given by the image sensor is processed by the image processor inside the camera module to complete image quality adjustment, color space conversion, etc., and then flows through the transmission link to the domain controller. On the domain controller platform, no image processing is required, and it is directly sent to the application program or algorithm.

[0028] Here, for the second processing link, an image processor needs to be integrated inside the camera module. An independent image processor chip or a sensor integrated with an image processing functional unit can be used. For example, in the processing link, a pipeline with image processing capabilities is respectively connected to an image input interface, an image output interface, and a processor. For the main application scenarios, for example, if the domain controller uses image data in the YUV format, the camera needs to integrate an image processor to complete the conversion of the image color space and the optimization processing of various image qualities such as denoising, exposure, white balance, and sharpness.

[0029] However, in the first solution, an image processor is not used inside the camera. Instead, a single RAW data stream is directly transmitted to the domain controller. In the second solution, a general-purpose image processor is used, with a single RAW data stream input and a single image data stream output. Currently, both of these camera modules only output a single image data stream. For the solution of multiplexing the same camera for two (or more) domain controllers, a flexible configurable data link cannot be established. Instead, the camera can only be connected to one domain controller first, and then a data stream is split from this domain controller and forwarded to another domain controller. The architecture has significant limitations, the image processing cannot be flexibly configured, and the performance of the data link cannot be optimized. As a result, it cannot meet the requirements for rapid multi-image processing, increasing the software and hardware costs for multi-image processing requirements. Therefore, by using the image processing chip of the embodiment of the present invention, based on the connection relationship between the image input interface and the splitting processing module, the image input interface is used to receive image data. Multiple image processing branches and paths are set according to different processing requirements. The splitting processing module is used to send the image data into the corresponding branches and paths for image processing according to the required settings, achieving multi-channel simultaneous processing according to requirements, improving the flexibility and applicability of the image processing architecture and link, and realizing the simultaneous and rapid processing of multiple image processing requirements.

[0030] The following Figures 1-3 describes the image processing chip of the embodiment of the present invention.

[0031] As Figure 1 shown, it is a block diagram of the image processing chip of an embodiment of the present invention. The image processing chip 100 of the embodiment of the present invention includes: An image input interface 20, connected to the output end of the image acquisition unit 18, for receiving the image data output by the image acquisition unit 18.

[0032] In an embodiment, taking an image sensor as an example of the image acquisition unit 18, one frame of data of an image sensor is transmitted into the image processing chip 100 through the image input interface 20. The image input interface 20 includes a hardware controller of the data interface for receiving image data, preparing for the image processing chip 100 to perform multi-channel simultaneous processing on the received image data as required. Among them, for a separate image processor chip, the input data and input interface may include (but are not limited to) one of the camera data interfaces such as MIPI (Mobile Industry Processor Interface) and DVP (Digital Video Port).

[0033] The shunt processing module 19, the first end of the shunt processing module 19 is connected to the other end of the image input interface 20, and is used to allocate shunts and paths for the image data, perform image processing on the image data according to the shunts and paths, and output the target image data.

[0034] In an embodiment, the shunt processing module 19 can perform processing shunt division, processing, and output of the processed target image data according to image processing requirements. For example, the user has two image processing requirements, one is the image processing requirement applicable to the vehicle cockpit domain, and the other is the image processing requirement applicable to the vehicle intelligent driving domain.

[0035] For the image processing requirement applicable to the vehicle cockpit domain, a pipeline with complete image processing functions is set in the shunt processing module 19 to complete the processing of automatic exposure, denoising, white balance, color space conversion, cropping, scaling, etc. of the image data, and then the processed image data is output to the receiving unit connected to the vehicle cockpit domain for reception. The receiving unit is, for example, a domain controller, so as to complete the image processing requirement of the vehicle cockpit domain.

[0036] For the image processing requirement applicable to the vehicle intelligent driving domain, a pipeline with lightweight function image processing functions is set in the shunt processing module 19. It does not perform complete image processing and only has the minimum number of processing units. The processing unit may have a cropping function but is not limited to a cropping unit and can be configured as other functional units according to actual needs. After processing, the data is directly output in RAW format to the receiving unit connected to the vehicle intelligent driving domain for reception. The receiving unit is, for example, a domain controller, so as to complete the image processing requirement of the vehicle intelligent driving domain.

[0037] The pipeline pipelines of the above two image processing functions are simultaneously set in the branching processing module 19 and perform image processing simultaneously. It can be understood that the number of pipeline pipelines of image processing functions depends on requirements. If there are n (n = 1, 2... n) requirements, there will be corresponding n pipeline pipelines of image processing functions. These n pipeline pipelines of image processing functions are divided by the splitter and processing unit in the branching processing module 19 according to the corresponding relationship between branching and the pipeline pipelines of image processing functions. For example, in the above case, it is divided into 2 branches, and the image processing data is sent into the corresponding pipeline pipelines of image processing functions for image processing, and then output from the corresponding output interfaces to achieve multi-channel simultaneous processing according to requirements, improving the flexibility and applicability of the image processing architecture and link, and realizing simultaneous and fast processing of various image processing requirements. For example, when the image acquisition device (such as a camera) has two (or more) output interfaces on the hardware, the output interfaces can be respectively connected to different domain controllers. Each domain controller corresponds to the branching and the pipeline pipelines of image processing functions according to requirements. The branching can configure the size, frame rate, field of view, image quality, etc. of its own image according to requirements, so that each domain controller can respectively perform as many configurations and processing on the image data as possible to meet the image processing requirements of this domain. And the image data is divided into two or more paths inside the image acquisition unit (such as an image sensor), and the branching is completed inside the image processing chip, enabling the image acquisition device (camera) module to achieve two or more paths of output, without adding a special branching module in the backend link, making the entire link architecture more concise, not occupying additional space, and saving costs.

[0038] According to the image processing chip of an embodiment of the present invention, based on the connection relationship between the image input interface and the branching processing module, image data is received by using the image input interface, multiple image processing branches and paths are set according to different processing requirements, and the branching processing module is used to send the image data into the corresponding branches and paths for image processing according to the required settings, achieving multi-channel simultaneous processing according to requirements, improving the flexibility and applicability of the image processing architecture and link, and realizing simultaneous and fast processing of various image processing requirements.

[0039] In some embodiments, such as Figure 2 shown, is the block diagram of the image processing chip with different channels of an embodiment of the present invention. As Figure 3 shown, is the block diagram of the image processing chip with the same channel of an embodiment of the present invention. Combining Figures 1-3As shown in the figure, the shunt processing module 19 includes: a splitter and a processing unit 21. The input end of the splitter and the processing unit 21 is connected to the other end of the image input interface 20, and is used to receive image data and allocate the shunt and path of the image data; a shunt processing output unit. The first end of the shunt processing output unit is connected to the output end of the splitter and the processing unit 21, and is used to obtain target image data according to the image data allocated by the shunt and the path, and output the target image data to the controller; a processor 28. The input end of the processor 28 is connected to the second end of the shunt processing output unit, and is used to configure and control the splitter and the processing unit 21 and the shunt processing output unit.

[0040] In the embodiment, the splitter and the processing unit 21 is a splitter and a processing front end, which is used to receive image data and allocate the shunt and path of the image data according to the correspondence between the shunt and the pipeline of the image processing function, etc. For example, the user has two image processing requirements. One is the image processing requirement applicable to the vehicle cockpit domain, and the other is the image processing requirement applicable to the vehicle intelligent driving domain. Then, it is necessary to configure 2 shunts and 2 paths, as well as the correspondence between the shunts and the paths. Let shunt one correspond to path one, which is used to process and output the image processing requirements of the vehicle cockpit domain, and shunt two correspond to path two, which is used to process and output the image processing requirements of the vehicle intelligent driving domain. Then, the image data passes through the splitter and the processing unit 21, and 2 paths of image data will be obtained, which are respectively sent to path one corresponding to shunt one and path two corresponding to shunt two for image processing and output. According to the configured 2 shunts and 2 paths, where 2 paths are only examples. In practical applications, it can be divided into n paths corresponding to n paths according to requirements, so as to realize the division of shunts according to the configured requirements and send the image data into the paths corresponding to the corresponding shunts; the shunt processing output unit is a unit with paths, that is, a pipeline of image processing functions and corresponding output interfaces, which can perform image processing on the received image data according to the configured requirements and output it to the controller of the corresponding receiving unit. For example, path one is output to the domain controller corresponding to the vehicle cockpit domain, so as to realize the processing of image data according to requirements and improve the flexibility of data processing.

[0041] An independent shunt unit module is added to the software corresponding to the processor 28, which has no coupling with the existing software architecture. A shunt architecture and a configurable data structure are designed in the software to implement the design of a multi-channel architecture and a configuration file, mainly including a configuration file and corresponding parsing methods, as well as methods for adapting to multi-channel configurations in the process. The main configuration contents include: the number of shunts, the number of pipeline pipelines, the shunt model, the shunt configuration information, the shunt output port number, the pipeline number corresponding to the shunt's own output port, the pipeline type corresponding to the shunt's own output port, the pipeline configuration of the shunt's own output port, etc. The above configuration contents are written in a specific configuration file, which can be in file formats such as xml. The corresponding items and contents are written in the configuration file, and the configuration file is loaded and parsed during software operation to obtain the required configuration results. Usually, any common configuration file format can be used. From the configuration, the shunt output situation and the corresponding pipeline situation can be obtained. Among them, the number of shunts is configured according to actual requirements and hardware. When this value is 1, it is a conventional single-channel processor; if it is greater than 1, it means there are corresponding numbers of output ports. Correspondingly, relevant information such as the shunt output port number, the pipeline number corresponding to the shunt's own output port, the pipeline type corresponding to the shunt's own output port, and the pipeline configuration of the shunt's own output port also need to be configured in two or more copies.

[0042] In the actual software process, corresponding system resources are allocated according to the obtained configuration parameters, and a mapping connection relationship is established between the output ports of the shunt and the corresponding pipeline pipelines. In this way, when the image processor runs, the image data output by the shunt flows into the corresponding pipeline pipelines to perform corresponding processing.

[0043] Through the above configuration and control of the shunt, the processing unit, and the shunt processing output unit by the processor, it is ensured that the image data can be flexibly processed in multiple channels according to multiple requirements and output to the corresponding domain controller for reception and use.

[0044] In some embodiments, as shown in Figures 1-3 the shunt processing output unit includes: an image processing pipeline 24, the input end of the image processing pipeline 24 is connected to the output end of the shunt and processing unit 21, and is used to perform image processing on the image data distributed by the shunt and the channels to obtain target image data; an image output interface 27, the input end of the image output interface 27 is connected to the output end of the image processing pipeline 24, and is used to output the target image data to the controller.

[0045] In an embodiment, for example, the user has two image processing requirements. One is the image processing requirement applicable to the vehicle cockpit domain, and the other is the image processing requirement applicable to the vehicle intelligent driving domain. Then, the image processing pipeline 24 includes a first image processing pipeline 22 and a second image processing pipeline 23. The first image processing pipeline 22 is used to process the image processing requirements of the vehicle cockpit domain and is a pipeline with complete image processing functions to complete automatic exposure, denoising, white balance, color space conversion, cropping, scaling, etc. of image data, and generally outputs image data in the YUV (a color encoding method) format (but not limited to the YUV format). The second image processing pipeline 23 is used to process the image processing requirements of the vehicle intelligent driving domain and is a pipeline with lightweight functional image processing functions. It does not perform complete image processing and only has the minimum processing units. The processing units can include but are not limited to cropping units and can be configured as other functional units according to actual needs, and directly outputs the processed data in the RAW format. If both of the user's requirements are applicable to the image processing requirements of the vehicle intelligent driving domain, then the image processing pipeline 24 includes two second image processing pipelines 23. Each image processing pipeline in the image processing pipeline 24 performs image processing on the received image data to obtain target image data, so as to simultaneously process the user's multiple image processing requirements. The first image output interface 25 outputs the obtained target image to the domain controller corresponding to the vehicle cockpit domain, and the second image output interface 26 outputs the obtained target image to the domain controller corresponding to the vehicle intelligent driving domain. The image output interface 27 can be one of the camera data interfaces including but not limited to MIPI, DVP, etc. This part of the interface hardware is connected to the pins of the corresponding chip on the domain controller side. The on-vehicle camera is generally connected to the domain controller through a serializer-deserializer link and outputs the target image data to the domain controller host...

[0046] Among them, a usage scenario where both paths in the image processing pipeline 24 are the second image processing pipeline 23 is, for example, that the internal ones are all image processing pipelines with the minimum functions and there is no complete image processing pipeline. The situation that can be handled is that each domain controller connected to the camera accesses data in the RAW format, and the image processor integrated on the host domain controller is used to complete the image processing. Only the most basic functions such as cropping and scaling are performed in the image processor of the camera...

[0047] In some embodiments, as shown in combination with Figures 1-3 the image processing pipeline 24 is composed of at least two and the image processing pipeline is correspondingly connected to the image output interface...

[0048] In an embodiment, the image processing chip 100 has one image input interface and two (or more than two) image output interfaces. The number of internal image processing chips 100 is the same as the number of output interfaces and corresponds to each output interface respectively.

[0049] Each image processing pipeline in the image processing pipeline 24 corresponds to its own image output interface. For example, the first image processing pipeline 22 corresponds to the first image output interface 25, and the second image processing pipeline 23 corresponds to the second image output interface 26. It can be understood that the number of image processing pipelines included in the image processing pipeline 24 and the corresponding types of image processing pipelines are set according to requirements and hardware, not limited to 2. Here, different image processing pipelines correspond to their own image output interfaces because of image processing requirements and different domain controllers of the corresponding receiving units. Therefore, each path is independent. If the requirements are the same, the connection relationship can be adjusted according to actual needs to achieve the goal of outputting target image data that meets different image processing requirements of users.

[0050] In some embodiments, in combination with Figures 1-3 As shown, the processor 28 includes: a first control port connected to the control port of the image acquisition unit for providing a control signal to the image acquisition unit; a first communication port connected to the communication interface of the image acquisition unit for configuring and driving the image acquisition unit.

[0051] In an embodiment, taking the image sensor as an example of the image acquisition unit, the processor 28 includes: a first control port connected to the control interface 29 of the image sensor for providing a control signal to the image sensor. The control signal is, for example, a signal provided through the chip control pin, including signals provided by signal pins such as the clock and reset required to drive the image sensor chip, so as to ensure the clock and reset and other working requirements of the image sensor; a first communication port connected to the communication interface 30 of the image sensor for configuring and driving the image sensor. For example, the first communication port is connected to the communication interface 30 of the image sensor using a communication bus, and I2C (Inter-Integrated Circuit) or SPI (Serial Peripheral Interface), etc., which are required for setting the chip, are used. This part of the interface hardware circuit is connected to the corresponding pins of the image sensor to configure and drive the image sensor to ensure the normal configuration and driving of the image sensor.

[0052] In some embodiments, in combination with Figures 1-3As shown, the processor further includes: a second control port connected to the control interface of the controller for receiving the control signal provided by the controller; a second communication port connected to the communication interface of the controller for receiving the operation information of the controller to configure and drive the image processing chip.

[0053] In an embodiment, taking the receiving unit as the controller (domain controller) as an example, the processor 28 further includes: a second control port connected to the control interface 31 of the receiving unit for receiving the control signal provided by the domain controller. For example, the signal provided by the domain controller is received through the chip control pin, including the signals required for the signal pins such as the clock and reset needed to drive the image acquisition device (camera), so as to ensure the normal operation of the clock and reset control of the image acquisition device; a second communication port connected to the communication interface 32 of the receiving unit for receiving the operation information of the controller to configure and drive the image processing chip. For example, through the communication bus connected to the communication interface 32 of the receiving unit by the second communication port, I2C or SPI, etc. required for setting the image acquisition device (camera) is carried out. This part of the interface hardware circuit is connected to the pins of the corresponding chip on the domain controller side. The in-vehicle camera is generally connected to the domain controller through a serializer-deserializer link, and receives the configuration and driving work of the domain controller host for this image sensor to ensure the normal operation of the configuration and driving work of the image acquisition unit.

[0054] In some embodiments, in combination with Figures 1-3 As shown, when receiving the operation information of the controller to configure and drive the image processing chip 100, the processor is specifically configured to: obtain the operation information sent by the controller; if the operation information is greater than or equal to the preset information threshold, obtain the working priority of the controller; and configure and drive the image processing chip 100 according to the working priority.

[0055] In an embodiment, the preset information threshold is a critical value for determining whether two or more domain controllers are used as master devices to configure and drive the image processing chip 100; obtain the operation information sent by the controller. For example, obtain the operation information for configuring and driving the image processing chip 100 sent by the controller to identify the source of the operation information and determine whether to perform corresponding operations according to the operation information sent by the controller; the communication interface 32 of the receiving unit is connected to the domain control through a communication bus. The image processing chip 100 is hung on the communication bus as a slave device. The corresponding communication buses of the domain controllers that need to reuse this image acquisition device (such as a camera) are all connected to the communication interface 32 of the receiving unit. As the master device of the communication, in actual engineering applications, it is determined which domain controller operates the communication bus to set the image processing chip 100 according to the application scenario, and the priorities of each domain controller on this bus are set according to actual application requirements. If two or more domain controllers act as master devices to operate this communication bus at the same time and a conflict occurs, the communication bus performs arbitration to ensure that the master device with a higher priority effectively configures and drives the image processing chip 100.

[0056] It should be noted that, compared with current existing products, the image processing chip has two (or more) image processing pipelines and data output ports. Based on this image processing chip, an image acquisition device (such as a camera module) developed can be connected in parallel to different domain controller hosts, as Figure 4 shown, which is a block diagram of the image acquisition device according to an embodiment of the present invention and is a schematic diagram of the application of the image processing chip 100 in the image acquisition device 53 (camera). Specific implementation schemes may have some easily conceivable changes based on this block diagram, which should belong to the extension of the present invention. The image processing chip involved in the embodiment of the present invention can be an independent chip connected to an image sensor, or a module unit integrated inside the image sensor. If the image processing chip is integrated inside the image sensor as a functional module, this part of the interface is connected in the way of the inside of the image sensor.

[0057] Next, refer to Figure 4 to describe the image acquisition device according to an embodiment of the present invention.

[0058] As Figure 4 shown, the image acquisition device 53 according to an embodiment of the present invention includes: an image acquisition unit for acquiring image data; the image processing chip 100 as described in the above embodiment, connected to the image acquisition unit, for receiving the image data output by the image acquisition unit, allocating branches and paths for the image data, performing image processing on the image data according to the branches and paths, and outputting target image data.

[0059] In the embodiment, the image processing chip 100 represents Figure 2or Figure 3 the whole described Figure 2 or Figure 3 the image processing pipeline 24 and some functional units inside the image processor. The processor only works inside the image processor and has no external interface.

[0060] The first data bus 57 is the data bus for inputting data from the image sensor 54 to the image processing chip 100, and the input interface corresponds to the image input interface 20.

[0061] The first general control pin 58 is the control pin for the image processing chip 100 to connect to the image sensor 54, corresponding to the control interface 29 of the image sensor. It is the chip control pin part of the control interface 29 of the image sensor. When the camera starts to work, a drive control signal is provided to the image sensor chip through the control pin of the first general control pin 58. If the image processing chip 100 is integrated inside the image sensor, the overall image sensor solution can be followed, and the actual hardware may be different from the description of the first general control pin 58 part.

[0062] The first communication control bus 59 is the communication bus for the image processing chip 100 to connect to the image sensor 54, corresponding to the communication interface 30 of the image sensor. It is the communication bus part of the communication interface 30 of the image sensor. When the camera works, relevant settings such as initialization and exposure are sent to the image sensor chip through the first communication control bus 59. This communication bus includes but is not limited to one or several of the commonly used I2C and SPI buses. If the image processing chip 100 is integrated inside the image sensor, the overall image sensor solution can be followed, and the actual hardware may be different from the description of the first communication control bus 59 part.

[0063] The second communication control bus 62 and the third communication control bus 63 are the communication buses for this image processor to connect to the domain controller, corresponding to the communication interface 32 of the receiving unit.

[0064] The second data bus 60 is connected to the first output port of the image processing chip 100, corresponding to the first image output interface 25. The second data bus 60 is connected to the data interface of the corresponding domain controller. The vehicle-mounted camera needs to pass through the serializer 55 - deserializer link and is connected to the corresponding domain controller through the second serialized data link 67.

[0065] The third data bus 65 is connected to the second output port of the image processing chip 100, corresponding to the second image output interface 26. The third data bus 65 is connected to the data interface of the corresponding domain controller. The vehicle-mounted camera needs to pass through the serializer 55 - deserializer link and is connected to the corresponding domain controller through the first serialized data link 66.

[0066] In some embodiments, such as Figure 4 shown, the image acquisition device 53 further includes: a clock module 50 connected to the clock interface of the image processing chip 100 for providing a clock control signal to the image processing chip 100; a reset module 51 connected to the reset interface of the image processing chip 100 for providing a reset control signal to the image processing chip 100; a storage module 52 connected to the storage interface of the image processing chip 100 for storing data of the image acquisition device; and a power management module 56 connected to the power management interface of the image processing chip 100 for supplying power to the image acquisition device.

[0067] In an embodiment, the second general control pin 61 and the third general control pin 64 are control signal pins through which the image processing device 100 is connected to the domain controller side, including clocks, resets, etc. related to camera driving, corresponding to the control interface 31 of the receiving unit. These two pins can both be left unset, and instead, the clock module 50 and the reset module 51 integrated in the camera module are used to provide clock and reset signals.

[0068] The storage module 52 and the power management module 56 are the storage unit and the power management module in the camera module, and are basic components of the camera module. Among them, the storage module 52 can store image data, cache data, configuration files, and other data.

[0069] According to the image acquisition device 53 of the embodiment of the present invention, based on the connection relationship between the image input interface and the branch processing module, image data is received through the image input interface, multiple image processing branches and paths are set according to different processing requirements, and the branch processing module is used to send the image data into the corresponding branches and paths for image processing according to the required settings, realizing multi-channel simultaneous processing according to requirements, improving the flexibility and applicability of the image processing architecture and link, and realizing the simultaneous and fast processing of various image processing requirements.

[0070] Next, reference is made to Figure 5 describe the vehicle of the embodiment of the present invention.

[0071] Such as Figure 5 shown, is a block diagram of a vehicle according to an embodiment of the present invention. The vehicle 102 includes: the image acquisition device 53 as described in the above embodiment.

[0072] Vehicle 102 according to an embodiment of the present invention is configured with the image acquisition device 53 of the above embodiment. Based on the connection relationship between the image input interface and the branch processing module, image data is received through the use of the image input interface. Multiple image processing branches and paths are set according to different processing requirements. The branch processing module is used to send the image data into the corresponding branches and paths for image processing according to the required settings, achieving multi-channel simultaneous processing according to requirements, improving the flexibility and applicability of the image processing architecture and link, and realizing the simultaneous and rapid processing of various image processing requirements.

[0073] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example.

[0074] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and purposes of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims

1. An image processing chip, characterized in that Comprising: An image input interface, connected to the output end of the image acquisition unit, for receiving the image data output by the image acquisition unit; A shunt processing module, the first end of the shunt processing module is connected to the other end of the image input interface, for allocating shunts and paths for the image data, performing image processing on the image data according to the shunts and paths, and outputting target image data.

2. The image processing chip according to claim 1, wherein, The shunt processing module includes: A splitter and a processing unit, the input end of the splitter and the processing unit is connected to the other end of the image input interface, for receiving the image data and allocating the shunts and paths of the image data; A shunt processing output unit, the first end of the shunt processing output unit is connected to the output end of the splitter and the processing unit, for obtaining target image data according to the image data allocated by the shunts and paths, and outputting the target image data to the controller; A processor, the input end of the processor is connected to the second end of the shunt processing output unit, for configuring and controlling the splitter and the processing unit and the shunt processing output unit.

3. The image processing chip according to claim 2, wherein The shunt processing output unit includes: An image processing pipeline, the input end of the image processing pipeline is connected to the output end of the splitter and the processing unit, for performing image processing on the image data allocated by the shunts and paths to obtain target image data; An image output interface, the input end of the image output interface is connected to the output end of the image processing pipeline, for outputting the target image data to the controller.

4. The image processing chip according to claim 3, wherein The image processing pipeline consists of at least two and the image processing pipeline is correspondingly connected to the image output interface.

5. The image processing chip according to claim 2, wherein The processor includes: A first control port, connected to the control port of the image acquisition unit, for providing a control signal to the image acquisition unit; A first communication port, connected to the communication interface of the image acquisition unit, for configuring and driving the image acquisition unit to work.

6. The image processing chip according to claim 5, wherein The processor further includes: A second control port, connected to the control interface of the controller, for receiving the control signal provided by the controller; A second communication port, connected to the communication interface of the controller, for receiving the operation information of the controller to configure and drive the image processing chip to work.

7. The image processing chip according to claim 6, wherein When receiving the operation information of the controller to configure and drive the image processing chip to work, the processor is specifically used for: Obtaining the operation information issued by the controller; If the operation information is greater than or equal to a preset information threshold, obtaining the working priority of the controller; Configuring and driving the image processing chip to work according to the working priority.

8. An image acquisition device, characterized in that, Comprising: An image acquisition unit, for acquiring image data; The image processing chip according to any one of claims 1-7, connected to the image acquisition unit, for receiving the image data output by the image acquisition unit, allocating shunts and paths for the image data, performing image processing on the image data according to the shunts and paths, and outputting target image data.

9. The image acquisition device according to claim 8, wherein Further comprising: A clock module, connected to the clock interface of the image processing chip, for providing a clock control signal to the image processing chip; A reset module, connected to the reset interface of the image processing chip, for providing a reset control signal to the image processing chip; A storage module, connected to the storage interface of the image processing chip, for storing data of the image acquisition device; A power management module, connected to the power management interface of the image processing chip, for supplying power to the image acquisition device.

10. A vehicle, characterized in that, Comprising: The image acquisition device according to claim 8 or 9.

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