Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and electronic equipment. The semiconductor structure comprises a substrate; the multiple stacked storage unit arrays are located on the substrate, storage units in the storage unit arrays comprise write transistors and read transistors which are arranged in the first direction, and the first direction is parallel to the substrate; the write transistor comprises a first grid electrode which extends along a third direction vertical to the substrate, and a first semiconductor layer which at least partially surrounds the first grid electrode and is insulated from the first grid electrode; the reading transistor comprises a second grid electrode extending along the first direction and a second semiconductor layer at least partially surrounding the side wall and the end part of the second grid electrode; the read transistor further comprises a back gate at least partially surrounding the second semiconductor layer; the first source / drain electrode of the write transistor is connected with the second grid electrode of the read transistor. The device structure is simple in manufacturing process.

Description

Technical Field

[0001] This application relates to, but is not limited to, semiconductor technology, and particularly to a semiconductor structure, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly. As a result, any minor difference in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, it is desired to fabricate as many device units as possible on a limited substrate. Since Moore's Law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of this application.

[0005] In one aspect, some embodiments of this application provide a semiconductor structure, including:

[0006] A substrate;

[0007] A plurality of stacked memory cell arrays located on the substrate, each memory cell in the memory cell array including a write transistor and a read transistor arranged along a first direction, the first direction being parallel to the substrate;

[0008] The write transistor includes a first gate extending along a third direction perpendicular to the substrate, a first semiconductor layer at least partially surrounding the first gate and insulated from the first gate, and a first source / drain and a second source / drain respectively connected to the first semiconductor layer in the first direction;

[0009] The read transistor includes a second gate extending along the first direction, a second semiconductor layer at least partially surrounding the sidewalls and ends of the second gate, and a third source / drain and a fourth source / drain respectively connected to the second semiconductor layer;

[0010] The read transistor further includes a back gate at least partially surrounding the second semiconductor layer;

[0011] The first source / drain of the write transistor is connected to the second gate of the read transistor.

[0012] In some embodiments, the second gate extends in the first direction, and the region between the two ends in the extending direction is the sidewall of the second gate; the back gate extends in the first direction, and the back gate only surrounds the sidewall of the second gate.

[0013] In some embodiments, the back gate between the second gates adjacent in the second direction is separated by an insulating layer.

[0014] In some embodiments, the back gates of a plurality of the read transistors stacked at intervals along the third direction are of an integral structure and form a read word line extending along the third direction.

[0015] In some embodiments, the third source / drain electrodes of a plurality of the read transistors arranged at intervals along the second direction are interconnected and form a read bit line extending along the second direction. The read bit line is connected to the second semiconductor layer that wraps one end of the second gate at the end of the second gate away from the write transistor.

[0016] In some embodiments, the fourth source / drain electrodes of a plurality of the read transistors stacked at intervals along the third direction are connected to a reference signal line, and the reference signal line is of an integral structure.

[0017] In some embodiments, the reference signal line is grounded.

[0018] In some embodiments, the stacked multi-layer memory cell array includes insulating layers and conductive layers stacked alternately. The second gate is located in the conductive layer, and the back gate replaces the insulating layer and is insulated from the conductive layer.

[0019] In some embodiments, the third source / drain electrode is located in the conductive layer, and the fourth source / drain electrode is in the same layer as the back gate and insulated from each other.

[0020] In some embodiments, the first gates of a plurality of the write transistors stacked at intervals along the third direction are interconnected and form a write word line extending along the third direction.

[0021] In some embodiments, the second source / drain electrodes of a plurality of the write transistors arranged at intervals along a second direction parallel to the substrate are interconnected and form a write bit line extending along the second direction. The first direction intersects the second direction and is perpendicular to the third direction.

[0022] Some embodiments of the present application provide a method for manufacturing a semiconductor structure, including:

[0023] Forming a stacked structure of insulating layers and conductive layers distributed alternately along a third direction perpendicular to the substrate on the substrate;

[0024] Etch the stacked structure to form a vertical conductive portion extending in a second direction parallel to the substrate and a plurality of lateral sub-conductive portions separated by the vertical conductive portion and extending in a first direction parallel to the substrate, where the first direction intersects the second direction and both are perpendicular to the third direction;

[0025] In the word line preset area of the write transistor in each lateral sub-conductive portion, form a first hole penetrating the stacked structure, which disconnects each of the lateral sub-conductive portions into a first source / drain and a second source / drain of the write transistor; make the first source / drain shared with the second gate of the read transistor;

[0026] Form a first semiconductor layer and a first word line of the write transistor in the first hole;

[0027] Form a second hole extending in the direction towards the substrate near the write bit line between the second source / drains adjacent in the second direction;

[0028] Perform wet etching on the conductive layer in the second hole to form a first lateral groove, and fill the second hole and the first lateral groove;

[0029] Form a third hole extending in the direction towards the substrate between two adjacent lateral sub-conductive portions and on the side of the second hole close to the first hole, exposing the conductive layer and the insulating layer;

[0030] Perform wet etching on the insulating layer in the third hole to form a second lateral groove;

[0031] Remove the material in the first lateral groove so that the first lateral groove communicates with the second lateral groove, exposing the sidewall and end of the first source / drain;

[0032] Deposit an insulating material and a semiconductor material in sequence on the sidewall and end of the first source / drain to form a second semiconductor layer and a second gate insulating layer of the read transistor;

[0033] Form a back gate insulated from the second semiconductor layer and a reference signal line electrically connected to the second semiconductor layer on the sidewall of the first source / drain.

[0034] In some embodiments, after forming the second semiconductor layer and the second gate insulating layer of the read transistor, it further includes:

[0035] Fill the first lateral groove and the second lateral groove with a conductive material;

[0036] A fourth hole extending in the direction towards the substrate is formed between the adjacent lateral sub-conductive parts in the second direction and on the side of the second hole away from the first hole, and the conductive material, the second gate insulating layer, and the material of the second semiconductor layer in the first lateral groove are removed to expose the conductive layer and the insulating layer;

[0037] The fourth hole is filled with a conductive material;

[0038] A fifth hole extending in the direction towards the substrate is formed between the adjacent lateral sub-conductive parts in the second direction and in the region corresponding to the fourth hole. The size of the fifth hole in the first direction is larger than the size of the fourth hole in the first direction. The conductive material in the fourth hole is removed, and the fifth hole is filled with an insulating material to form a read bit line that is disconnected in the third direction.

[0039] In some embodiments, forming a back gate insulated from the second semiconductor layer and a reference signal line electrically connected to the second semiconductor layer on the sidewalls of the first source / drain includes:

[0040] A sixth hole extending in the direction towards the substrate is formed between the adjacent lateral sub-conductive parts in the second direction and on the side of the fifth hole close to the first hole;

[0041] By means of the sixth hole, a part of the conductive material in the second lateral groove is etched away to form a third lateral groove, and the size of the third lateral groove in the first direction is smaller than the size of the second lateral groove in the first direction;

[0042] An insulating material is deposited along the inner wall of the third lateral groove to form a dielectric layer, and the third lateral groove is filled with a conductive material to form a back gate;

[0043] The part of the second lateral groove that is not etched away forms a reference signal line.

[0044] In some embodiments, after a fourth hole extending in the direction towards the substrate is formed between the adjacent lateral sub-conductive parts in the second direction and on the side of the second hole away from the first hole, and the conductive material, the second gate insulating layer, and the material of the second semiconductor layer in the first lateral groove are removed to expose the conductive layer and the insulating layer, the method further includes the steps of:

[0045] A sixth hole extending in the direction towards the substrate is formed between the adjacent lateral sub-conductive parts in the second direction and on the side of the fifth hole close to the first hole;

[0046] Through the sixth hole, a part of the conductive material in the second lateral groove is etched away to form a third lateral groove, and the size of the third lateral groove in the first direction is smaller than the size of the second lateral groove in the first direction;

[0047] An insulating material is deposited along the inner wall of the third lateral groove to form a dielectric layer, and the third lateral groove is filled with a conductive material to form a back gate;

[0048] A fifth hole extending in the direction towards the substrate is formed between the lateral sub-conductive parts adjacent in the second direction and in the area corresponding to the fourth hole;

[0049] The fifth hole is filled with an insulating material to form a bit line that is disconnected in the third direction.

[0050] In some embodiments, an electronic device is provided, including the semiconductor structure described in any one of the above or the semiconductor structure fabricated by the above method.

[0051] Other features and advantages of the present application will be described in the subsequent specification, and in part, will be obvious from the specification, or will be understood by implementing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the specification and the accompanying drawings. Description of the Drawings

[0052] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0053] Figure 1A A schematic horizontal cross-sectional view taken along a plane parallel to the substrate (through the conductive layer) of a semiconductor structure provided for some embodiments of the present application;

[0054] Figure 1B For Figure 1A A schematic vertical cross-sectional view taken along the section line aa' in the structure shown;

[0055] Figure 1C For Figure 1A A schematic vertical cross-sectional view taken along the section line bb' in the structure shown;

[0056] Figure 1D For Figure 1A A schematic vertical cross-sectional view taken along the section line cc' in the structure shown;

[0057] Figure 1E For Figure 1A A schematic vertical cross-sectional view taken along the section line dd' in the structure shown;

[0058] Figure 2A A cross-sectional view perpendicular to the substrate taken along the cross-sectional line dd' of a semiconductor structure provided for some other embodiments of the present application; Figure 1A as shown in the figure;

[0059] Figure 2B A cross-sectional view perpendicular to the substrate taken along the cross-sectional line dd' of a semiconductor structure provided for some other embodiments of the present application; Figure 1A as shown in the figure;

[0060] Figure 3 An equivalent circuit diagram of a semiconductor structure provided for some embodiments of the present application;

[0061] Figure 4 A cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' of a stacked structure formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application; Figure 1A as shown in the figure;

[0062] Figure 5A A horizontal cross-sectional view taken along a plane parallel to the substrate (through the conductive layer) of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application;

[0063] Figure 5B A cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application; Figure 5A as shown in the figure;

[0064] Figure 5C A cross-sectional view perpendicular to the substrate taken along the cross-sectional line cc' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application; Figure 5A as shown in the figure;

[0065] Figure 6A A cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application; Figure 1A as shown in the figure;

[0066] Figure 6B A cross-sectional view perpendicular to the substrate taken along the cross-sectional line cc' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application; Figure 1A as shown in the figure;

[0067] Figure 7An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the structure shown;

[0068] Figures 8A - 8C An intermediate product formed in each step of forming a word line structure in a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the structure shown;

[0069] Figure 9A An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in the structure shown;

[0070] Figure 9B An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line dd' in the structure shown;

[0071] Figure 10A An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the structure shown;

[0072] Figure 10B An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in the structure shown;

[0073] Figure 10C An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line dd' in the structure shown;

[0074] Figure 11A An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the structure shown;

[0075] Figure 11B An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1ASchematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in the shown structure;

[0076] Figure 11C Intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line dd' in the shown structure;

[0077] Figure 12A Intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in the shown structure;

[0078] Figure 12B Intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line dd' in the shown structure;

[0079] Figure 13A Intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the shown structure;

[0080] Figure 13B Intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in the shown structure;

[0081] Figure 14A Intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the shown structure;

[0082] Figure 14B Intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in the shown structure;

[0083] Figure 15A Intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the shown structure;

[0084] Figure 15B An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the section line bb' in the structure shown;

[0085] Figure 15C An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the section line cc' in the structure shown;

[0086] Figure 15D An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the section line dd' in the structure shown;

[0087] Figure 16A An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the section line aa' in the structure shown;

[0088] Figure 16B An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the section line bb' in the structure shown;

[0089] Figure 16C An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the section line cc' in the structure shown;

[0090] Figure 16D An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the section line dd' in the structure shown;

[0091] Figure 17 An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the section line bb' in the structure shown;

[0092] Figure 18A An intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, alongFigure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the shown structure;

[0093] Figure 18B Intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in the shown structure;

[0094] Figure 19 Intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in the shown structure;

[0095] Figure 20 Intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in the shown structure;

[0096] Figure 21A Intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the shown structure;

[0097] Figure 21B Intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line bb' in the shown structure;

[0098] Figure 22A Intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line aa' in the shown structure; and

[0099] Figure 22B Intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application, along Figure 1A Schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line cc' in the shown structure. Detailed implementation manners

[0100] To make the objectives, technical solutions, and advantages of the present application clearer and more understandable, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments and features in the embodiments of the present application can be combined arbitrarily with each other.

[0101] The embodiments in this application can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the implementation methods and content can be transformed into various forms without departing from the spirit and scope of this application. Therefore, this application should not be construed as being limited only to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this application can be combined arbitrarily with each other.

[0102] The size and proportional relationships between the various film layers or components in the drawings of this application can be used as a reference in the actual process, which belongs to the embodiments with good technical effects, but is not limited thereto. For example: the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in this application are only schematic diagrams of the structure, and one embodiment of this application is not limited to the shape or values shown in the drawings.

[0103] In this specification, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the components with reference to the drawings, which are only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to this application. The positional relationships of the components are appropriately changed according to the directions describing each component. Therefore, it is not limited to the terms described in the specification, and can be appropriately replaced according to the situation.

[0104] In this specification, unless otherwise clearly specified and limited, the terms "arranged" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific situations.

[0105] In the description of this application, ordinal numbers such as "first" and "second" are set to avoid confusion of components, rather than to limit the quantity.

[0106] In this specification, "film" and "layer" can be interchanged. For example, sometimes "metal layer" can be changed to "metal film".

[0107] As used in this application, the term "first direction" X is defined as the direction parallel to the arrangement direction of the read transistor and the write transistor; the term "second direction" Y is defined as the direction parallel to the extension direction of the write bit line; the term "third direction" Z is defined as the direction perpendicular to the plane where the substrate is located, that is, the direction parallel to the extension direction of the write word line; the plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, "second direction" Y, and "third direction" Z can be as Figures 1A - 1E shown, etc.

[0108] As used in this application, the term "section line aa'" is a line parallel to the first direction X and passing through the source and drain electrodes of the write transistors arranged along the first direction; the term "section line bb'" is a line parallel to the first direction X and not passing through the source and drain electrodes of the write transistors; the term "section line cc'" is a line parallel to the second direction Y and passing through the second gate and the back gate of the read transistor; and the term "section line dd'" is a line parallel to the second direction Y and located between the back gate of the read transistor and the third source / drain electrode. The specific positions of these section lines can be as Figures 1A - 1E shown, etc.

[0109] As used in this application, the term "being an integral structure" may refer to that there is no obvious fault or gap or other obvious boundary interface between A and B in the micro-structure. Generally, the patterned and connected film layers formed on a film layer are integral. For example, A and B use the same material to form a film layer and are simultaneously formed into a structure with a connection relationship through the same patterning process.

[0110] As Figures 1A - 1E shown, the semiconductor structure provided by the exemplary embodiment of this application may include a substrate 10; a plurality of memory cell arrays located on the substrate, and each memory cell in the memory cell array includes a write transistor and a read transistor arranged along the first direction. The write transistor may include a first gate 150 extending along the third direction Z perpendicular to the substrate, a first semiconductor layer 130 at least partially surrounding the first gate 150, and a first source / drain electrode 110 and a second source / drain electrode 120 respectively connected to the first semiconductor layer 130. That is, in this application, the write transistor may include a surrounding channel structure; a first gate insulating layer 140 may be located between the first gate 150 and the first semiconductor layer 130 and may at least partially surround the first gate 150. The read transistor may include a second gate 250 extending along the first direction X, a second semiconductor layer 230 at least partially surrounding the second gate 250, and a third source / drain electrode 210 and a fourth source / drain electrode 220 respectively connected to the second semiconductor layer 230; a second gate insulating layer may be located between the second gate 250 and the second semiconductor layer 230.

[0111] By Figure 1AIt can be seen that the second gate 250 can be an integral structure with the first source / drain 110. In this application, by connecting the second gate of the read transistor to the first source / drain of the write transistor, a semiconductor structure of a capacitorless 2T memory cell is obtained.

[0112] The read transistor further includes a back gate 350 that at least partially surrounds the second gate 250. That is, in this application, the read transistor can include a gate-around structure.

[0113] In this application, "surround" can be understood as completely surrounding as a whole. The cross-section of the surrounded channel layer can be a closed ring, and the shape of the ring is adapted to the outer contour shape of the cross-section of the first gate 150 or the second gate 250. Exemplarily, the cross-section of the first gate 150 or the second gate 250 is, for example, a square, circular or elliptical structure, etc. The cross-section is intercepted along the direction perpendicular to the substrate. In an exemplary embodiment, the surround can be partial surround, and the cross-section after surround is not closed, such as a ring with an opening.

[0114] In an exemplary embodiment, as Figure 2A shown, the second gate 250 has two ends and sidewalls in the first direction. The back gate 350 of the read transistor only covers the second gate 250 in the third direction Z. It can be understood that the back gate surrounds the sidewalls of the second gate and does not wrap the ends. The longitudinal cross-section of the back gate is a closed ring.

[0115] Refer to Figure 2A etc. The back gates 350 of multiple read transistors stacked at intervals along the third direction Z are an integral structure, and the back gates 350 of multiple read transistors arranged at intervals along the second direction Y are disconnected.

[0116] In an exemplary embodiment, as Figure 2B shown, the back gate 350 between the second gates 250 adjacent in the second direction Y is separated by an insulating layer 20.

[0117] As Figure 1A and Figure 1C shown, the back gates 350 of multiple read transistors arranged at intervals along the third direction are connected to each other and form a second word line (read word line) 270 extending along the third direction.

[0118] As Figure 1A shown, the third source / drains 210 of multiple read transistors arranged at intervals along the second direction Y are connected to each other and form a second bit line (read bit line) 260 extending along the second direction Y.

[0119] Figure 1AIt is also shown that the third source / drain 210 contacts the second semiconductor layer 230 in the first direction X, and the fourth source / drain 220 contacts the second semiconductor layer 230 in the second direction Y.

[0120] In some embodiments, the third source / drain and the fourth source / drain may be part of the second semiconductor layer.

[0121] Figure 1C It is also shown that the fourth source / drains 220 of the plurality of read transistors stacked at intervals along the third direction Z are of an integral structure.

[0122] In an exemplary embodiment, the fourth source / drain of the read transistor may be grounded.

[0123] Continuing to refer to Figure 1A and Figure 1B , the second source / drains 120 of the plurality of write transistors arranged at intervals along the second direction Y parallel to the substrate are interconnected and form a first bit line (write bit line) 160 extending along the second direction Y.

[0124] Although the terms first source / drain, second source / drain, third source / drain, and fourth source / drain are used herein to refer to two separate and distinct source / drains, it is not intended that the source / drains referred to as the "first" source / drain, or "second" source / drain, and "third" source / drain and "fourth" source / drain have a unique meaning.

[0125] In some embodiments, the first source / drain and the second source / drain are independent of each other. In some embodiments, one of the first source / drain and the second source / drain may be the source of the write transistor and the other may be the drain of the write transistor. Similarly, the third source / drain and the fourth source / drain are independent of each other, and one of the third source / drain and the fourth source / drain may be the source of the read transistor and the other may be the drain of the read transistor.

[0126] Continuing to refer to Figure 1B , the first gates 150 of the plurality of write transistors stacked at intervals along the third direction Z may be interconnected and form a write word line 170; the write word line 170 may include a vertical portion 171 extending along the third direction Z and a protruding portion 172 protruding from the vertical portion 171.

[0127] Figure 1BIt is also shown that the write transistor may further include a first gate isolation layer 151. The first gate isolation layer 151 is located between the vertical portion 171 and the first semiconductor layer 130, and between the vertical portion 171 and the first gate insulating layer 140 in a direction parallel to the substrate 10. The first gate isolation layer 151 includes a material different from that of the first gate insulating layer 140.

[0128] This structural design of the write transistor can cause the first semiconductor layers 130 of at least some adjacent layers of the write transistor to be disconnected in the third direction Z, that is, the first semiconductor layers 130 of different write transistors sharing the same write word line 170 are separated from each other.

[0129] Therefore, the write word line configuration of the present application can more easily eliminate parasitic MOS and enhance the stability of the device by designing the extending portion 172 with a lateral extension.

[0130] Figure 3 An equivalent circuit diagram of a semiconductor structure provided for some embodiments of the present application. In Figure 3 wherein, SN represents a storage node, and WWL, WBL, RWL, and RBL are a write word line, a write bit line, a read word line, and a read bit line respectively. The third source / drain 210 of the read transistor can be electrically connected to the second bit line (read bit line RBL) 260, and the back gate 350 can be electrically connected to the second word line (read word line RWL) 270; the first gate 150 of the write transistor can be electrically connected to the write word line (WWL) 170, and the second source / drain 120 of the write transistor can be electrically connected to the first bit line (write bit line WBL) 160. The second gate 250 of the read transistor can be electrically connected to the first source / drain 110 of the write transistor, that is, the two form an integrated structure. The second gate 250 of the read transistor serves as a storage node, and at the same time, the control of the read transistor is strengthened through the back gate 350.

[0131] The present application uses the two gate terminals of the double gate to complete data storage and read / write operation control respectively. Based on the advantages of gate terminal control for reading and writing, the reading and writing of this double gate semiconductor structure are more flexible. The read word line can be free from the IR drop problem, and at the same time, the current sharing problem (that is, the multi-path effect in reading can be eliminated) is also suppressed.

[0132] The technical solution of the present application will be further described below through the manufacturing process of a semiconductor structure according to some embodiments of the present application. The "lithography process" mentioned in some embodiments includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in the related art. The "photolithography process" mentioned in some embodiments includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can use known coating processes, and etching can use known methods, which will not be specifically limited herein. In the description of some embodiments, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a lithography process or a photolithography process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" still requires a lithography process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process or the photolithography process contains at least one "pattern".

[0133] In some embodiments, the manufacturing process of the semiconductor structure may include:

[0134] S101: Form a stacked structure.

[0135] Exemplary steps may include: providing a substrate 10, and alternately depositing an insulating material and a conductive material on the substrate 10 along the third direction Z to form a stacked structure 1 including an insulating layer 20 and a conductive layer 30, as Figure 4 shown.

[0136] In some embodiments, chemical vapor deposition method or plasma enhanced chemical vapor deposition (PECVD) method can be used to deposit the insulating material and the conductive material.

[0137] In some embodiments, the substrate 10 can be a semiconductor substrate, such as a silicon substrate.

[0138] In some embodiments, the insulating layer 20 can be independently selected from any one or more of silicon oxide (e.g., SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), SiGe. In some embodiments, the insulating layer 20 can be silicon dioxide.

[0139] In some embodiments, the conductive layer 30 can be made of a metal material, such as tungsten, TiN or a composite material thereof.

[0140] Figure 4The shown stacked structure 1 may include 4 insulating layers 20 and 3 conductive layers 30. In some other embodiments, the stacked structure 1 may also include more or fewer alternately arranged insulating layers 20 and conductive layers 30.

[0141] S102: Form a preset pattern in the conductive layer.

[0142] Exemplary steps may include: depositing an isolation layer material on the stacked structure 1 to form an isolation layer 40; etching the stacked structure to form a preset pattern in the stacked structure, such as Figure 5A , Figure 5B and Figure 5C shown.

[0143] In some embodiments, as Figure 5A shown, the preset pattern may include 3 vertical conductive portions 31, 32, and 33 extending along the second direction Y and 4 horizontal conductive portions extending along the first direction X. The 1 vertical conductive portion 31 divides the 4 horizontal conductive portions into 8 horizontal sub-conductive portions 310. The horizontal sub-conductive portions 310 located on one side of the vertical conductive portion 31 along the first direction X terminate at the vertical conductive portion 32, while the horizontal sub-conductive portions 310 located on the opposite side of the vertical conductive portion 31 along the first direction X terminate at the vertical conductive portion 33. A first trench T1 is formed between two adjacent horizontal sub-conductive portions 310 in the second direction Y, for a total of 6 first trenches T1.

[0144] In some embodiments, the preset pattern may be in other shapes, such as having only 1 vertical conductive portion and multiple horizontal sub-conductive portions separated by the vertical conductive portion.

[0145] In some embodiments, the isolation layer 40 may be made of an insulating material different from that of the insulating layer 20, such as a nitride material, such as silicon nitride.

[0146] S103: Fill the first trenches.

[0147] Exemplary steps may include: depositing an insulating material film along the sidewalls and bottom walls of the first trenches T1 to form an isolation layer 40; filling each first trench T1 with the same insulating material as the insulating layer 20 to cover the isolation layer 40, and planarizing the upper surface of the stacked structure through a Chemical Mechanical Polishing (CMP) process to form a new insulating layer 20, such as Figure 6A and Figure 6B shown.

[0148] In some embodiments, each first trench T1 may also be filled with an insulating material different from that of the insulating layer 20.

[0149] S104: Form a first hole for the write transistor;

[0150] Exemplary steps may include: forming initial holes at preset positions of the writing lines (first word lines) of the writing transistors in each of the stacked lateral sub-conductive parts 310 by etching (such as dry etching), and exposing the inner sidewalls of the insulating layers 20 and the conductive layers 30; by means of the formed initial holes, laterally etching and removing part of the material of the conductive layer 30 along a direction parallel to the substrate to form a first word line lateral groove M1 that expands into the conductive layer, thereby exposing the upper and lower surfaces of the insulating layers 20 and the sidewalls of the conductive layer 30, and the length of the first word line lateral groove M1 along the first direction X is W; forming a plurality of first word line lateral grooves M1 in each initial hole, and the entire hole for forming the semiconductor layer and the word line is the first hole K1, that is, the first hole K1 may include the first word line lateral groove M1, as Figure 7 shown.

[0151] In some embodiments, the positive projection of the initial hole on a plane parallel to the substrate 10 may be a rectangle, a square, a circle, an ellipse, etc.

[0152] In some embodiments, the initial holes do not disconnect the lateral sub-conductive parts 310, and the first word line lateral grooves M1 may disconnect the lateral sub-conductive parts 310 into a first source / drain and a second source / drain.

[0153] S105: Form a first word line (writing line).

[0154] Exemplary steps may include: sequentially depositing semiconductor material, insulating material, and conductive material along the sidewalls of the initial holes and the inner walls of the first word line lateral grooves M1 to form a preset semiconductor layer 130', a preset gate insulating layer 140', and a preset writing line 170'; using wet etching to remove the material on the sidewalls of the conductive layer 30 and the insulating layer 20 inside the initial holes, and forming the initial holes again; continuing to laterally etch and remove part of the material of the preset semiconductor layer 130' and part of the material of the preset gate insulating layer 140' at each conductive layer 30 along a direction parallel to the substrate to form isolation grooves R (subsequently used to form a first gate isolation layer); filling insulating material into each isolation groove R and etching away the excess insulating material to make the sidewalls of the conductive layer 30 and the insulating layer 20 flush, forming a first gate isolation layer 151, and then forming a first semiconductor layer 130 and a first gate insulating layer 140; filling conductive material into the first hole K1 (including the first word line lateral groove M1), thereby forming a writing line 170, and the writing line 170 has a vertical portion 171 extending perpendicular to the substrate and an extending portion 172 extending from the vertical portion 171 along a direction parallel to the substrate, as Figures 8A - 8C shown.

[0155] Writing the first word line of the transistor to form this specific structure and having the first gate isolation layer makes it easier to remove parasitic MOS.

[0156] In an exemplary embodiment, the first gate isolation layer 151 may be made of the same material as the insulating layer 20, such as silicon dioxide.

[0157] In some embodiments, the first semiconductor layer 130 may be made of a metal oxide semiconductor material. In some embodiments, the metal oxide semiconductor material may be an amorphous or polycrystalline metal oxide semiconductor material, and the corrosion rate of the metal oxide semiconductor material in a weakly acidic or weakly alkaline solution is relatively slow. In some embodiments, the metal oxide semiconductor material may be an oxide of In, an oxide of Ga, an oxide of Zn, an oxide of Sn, etc. These metal oxide materials such as Indium Gallium Zinc Oxide (IGZO) may be used as channel materials.

[0158] In some embodiments, when the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15 A), thus ensuring a low refresh rate of the semiconductor structure. It should be noted that the metal oxide material may also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium - zinc - oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, which can be adjusted according to the actual situation.

[0159] In some embodiments, the first gate insulating layer 140 may be a high - dielectric - constant dielectric layer, that is, a dielectric layer with K≥3.9. The high - dielectric - constant dielectric layer can be used as a gate oxide. The first gate insulating layer 140 may be made of any one or more of silicon dioxide, aluminum oxide (Al2O3), hafnium oxide (HfO2).

[0160] In some embodiments, the writing word line 170 may be made of tungsten, titanium nitride or their composite materials, indium tin oxide ITO, etc.

[0161] S106: A second hole extending in a direction toward the substrate near the write bit line between second source / drain electrodes adjacent in a second direction.

[0162] Exemplary steps may include: at the intersection of cross-section line bb' and cross-section line dd', etching the stacked structure, i.e., etching away the insulating layer 20 and the isolation layer 40 at this position to form a second hole K2 extending along the third direction Z, as Figure 9A and Figure 9B shown.

[0163] S107: Wet-etching the conductive layer within the second hole to form a first lateral groove.

[0164] Exemplary steps may include: by means of the second hole K2, laterally etching (such as wet-etching) each conductive layer 30, removing a part of the conductive material of the conductive layer 30 along the first direction X and removing all of the material of the conductive layer 30 along the second direction Y to form a first lateral groove S1, as Figure 10A 、 Figure 10B and Figure 10C shown.

[0165] S108: Filling the second hole and the first lateral groove.

[0166] Exemplary steps may include: filling the first lateral groove S1 and the second hole K2 with a filling material and planarizing the upper surface of the stacked structure through a CMP process, as Figure 11A 、 Figure 11B and Figure 11C shown.

[0167] In an exemplary embodiment, the filling material may be a Spin-On Carbon (SOC) material or silicon nitride.

[0168] S109: Forming a third hole extending in a direction toward the substrate between two adjacent lateral sub-conductive portions and on a side of the second hole closer to the first hole, exposing the conductive layer and the insulating layer.

[0169] Exemplary steps may include: at the intersection of cross-section line bb' and cross-section line cc', etching the stacked structure, i.e., etching away the insulating layer 20 at this position to form a third hole K3 extending along the third direction Z, as Figure 12A and Figure 12B shown.

[0170] S110: Wet-etching the insulating layer within the third hole to form a second lateral groove.

[0171] Exemplary steps may include: By means of the formed third hole K3, laterally etching (wet etching) each insulating layer 20 to form a second lateral groove S2 at the insulating layer, as Figure 13A and Figure 13B shown.

[0172] In an exemplary embodiment, the dimension of the second lateral groove S2 in the first direction X may be the sum of the dimension of the subsequently formed back gate 350 in the first direction X and the dimension of the fourth source / drain 220 in the first direction X.

[0173] S111: Re-form the first lateral groove.

[0174] Remove the material in the first lateral groove so that the first lateral groove communicates with the second lateral groove, exposing the sidewalls and ends of the first source / drain.

[0175] Exemplary steps may include: Dry etching to remove the material in the first lateral groove S1, such as a spin-coated carbon material, and re-forming the first lateral groove S1 so that the first lateral groove S1 communicates with the second lateral groove S2 in the third direction Z, as Figure 14A and Figure 14B shown.

[0176] S112: Deposit an insulating material and a semiconductor material in sequence on the sidewalls and ends of the first source / drain to form a second gate insulating layer and a second semiconductor layer.

[0177] Exemplary steps may include: Sequentially depositing an insulating material and a semiconductor material along the inner walls of the first lateral groove S1 and the second lateral groove S2 by atomic layer deposition (ALD). The insulating materials on both sides in the third direction do not contact while the semiconductor materials contact and fill the gaps to form a second gate insulating layer 240 and a second semiconductor layer 230, as Figure 15A , Figure 15B , Figure 15C and Figure 15D shown.

[0178] Subsequent steps will form a back gate insulated from the second semiconductor layer on the sidewalls of the first source / drain and a reference signal line electrically connected to the second semiconductor layer.

[0179] S113: Fill the first lateral groove and the second lateral groove.

[0180] Exemplary steps may include: Filling the first lateral groove S1 and the second lateral groove S2 with a conductive metal material, as Figure 16A , Figure 16B , Figure 16C and Figure 16D shown.

[0181] S114: Form a fourth hole.

[0182] A fourth hole extending in the direction toward the substrate may be formed between the adjacent lateral sub-conductive parts in the second direction and on a side of the second hole away from the first hole.

[0183] Exemplary steps may include: etching the stacked structure along the bb' direction at a position close to the read bit line RBL or at a position where the cross-section line bb' intersects with the dd' to form a fourth hole K4, as Figure 17 shown.

[0184] S115: Remove the materials of the second gate insulating layer and the second semiconductor layer.

[0185] Remove the conductive material, the second gate insulating layer, and the materials of the second semiconductor layer in the first lateral groove, exposing the conductive layer and the insulating layer.

[0186] Exemplary steps may include: By means of the fourth hole K4, wet-etching to remove the materials of the second gate insulating layer and the second semiconductor layer in the first lateral groove S1 to form a trench, as Figure 18A and Figure 18B shown.

[0187] S116: Backfill with conductive metal material.

[0188] Exemplary steps may include: Backfilling the trench with conductive metal material, as Figure 19 shown.

[0189] S117: Form a fifth hole and fill it.

[0190] A fifth hole extending in the direction toward the substrate is formed between the adjacent lateral sub-conductive parts in the second direction and in a region corresponding to the fourth hole. The size of the fifth hole in the first direction is larger than the size of the fourth hole in the first direction. Remove the conductive material in the fourth hole and fill the fifth hole with an insulating material to form a read bit line that is disconnected in the third direction.

[0191] Exemplary steps may include: etching the stacked structure along the bb' direction at a position close to the read bit line RBL to form a fifth hole K5, thereby truncating the RBL to form a second bit line; backfilling the fifth hole K5 with an insulating material, as Figure 20 shown.

[0192] S118: Form a sixth hole and a third lateral groove.

[0193] A sixth hole extending in the direction toward the substrate is formed between the adjacent lateral sub-conductive parts in the second direction and on a side of the fifth hole close to the first hole.

[0194] Exemplary steps may include: etching the stacked structure along the bb' direction at a position where the back gate will be formed subsequently to form a sixth hole K6; by means of the sixth hole K6, isotropically etching the insulating layer 20 in the second direction Y laterally to remove a part of the insulating material to form a third lateral groove S3, as Figure 21A and Figure 21B shown.

[0195] In an exemplary embodiment, the size of the third lateral groove S3 along the first direction X may be the same as the size of the subsequently formed back gate 350 along the first direction X.

[0196] S119: Form a back gate.

[0197] Exemplary steps may include: sequentially depositing an insulating material and a conductive material along the inner wall of the third lateral groove S3 to form a dielectric layer 340 and a back gate 350, as Figure 22A and Figure 22B shown.

[0198] In an exemplary embodiment, the back gate 350 may be further etched along the first direction X to form a groove penetrating the stacked structure; an insulating material is filled into the groove so that the back gate 350 is disconnected in the second direction, forming a structure as Figure 22B shown.

[0199] In another exemplary embodiment, another manufacturing method of a semiconductor structure is also provided. Compared with the method including steps S101 - S119 above, after the step S116 of backfilling a conductive metal material, a back gate structure is formed first, and finally a fifth hole K5 is formed to truncate the RBL, forming a second bit line (read bit line).

[0200] In yet another exemplary embodiment, another manufacturing method of a semiconductor structure is also provided. Compared with the method including steps S101 - S119 above, after forming the fifth hole K5 to truncate the RBL, the inner wall of the fifth hole K5 is first deposited with a high - dielectric - constant High K material, and then the fifth hole K5 is backfilled with an insulating material to cover the High K material; finally, the back gate structure is formed according to S118 and S119.

[0201] An exemplary embodiment of the present application also provides an electronic device, including the semiconductor structure provided by the exemplary embodiment of the present application above, and the semiconductor structure may be a memory, such as a dynamic random access memory.

[0202] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply

[0203] Although the embodiments disclosed in this application are as above, the content described is only the embodiments adopted for the convenience of understanding this application and is not used to limit this application. Any person skilled in the art within the scope of this application can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the protection scope of this application shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A plurality of stacked memory cell arrays located on the substrate, each memory cell in the memory cell array comprising a write transistor and a read transistor arranged in a first direction, the first direction being parallel to the substrate; The write transistor comprises a first gate extending along a third direction perpendicular to the substrate, a first semiconductor layer at least partially surrounding the first gate and insulated from the first gate, and a first source / drain and a second source / drain respectively connected to the first semiconductor layer in the first direction; The read transistor comprises a second gate extending along the first direction, a second semiconductor layer at least partially surrounding the sidewalls and ends of the second gate, and a third source / drain and a fourth source / drain respectively connected to the second semiconductor layer; The read transistor further comprises a back gate at least partially surrounding the second semiconductor layer; The first source / drain of the write transistor is connected to the second gate of the read transistor.

2. The semiconductor structure according to claim 1, wherein The second gate extends in the first direction, and the region between the two ends in the extending direction is the sidewall of the second gate; the back gate extends in the first direction, and the back gate only surrounds the sidewall of the second gate.

3. The semiconductor structure according to claim 2, characterized in that, The back gates between the second gates adjacent in the second direction are separated by an insulating layer.

4. The semiconductor structure according to claim 2, wherein, The back gates of a plurality of the read transistors stacked at intervals along the third direction are of an integral structure and constitute a read word line extending along the third direction.

5. The semiconductor structure according to claim 1, wherein The third source / drains of a plurality of the read transistors arranged at intervals along the second direction are interconnected and constitute a read bit line extending along the second direction, the read bit line being connected to the second semiconductor layer wrapping one end of the second gate at the end of the second gate away from the write transistor.

6. The semiconductor structure according to claim 1, wherein The fourth source / drains of a plurality of the read transistors stacked at intervals along the third direction are connected to a reference signal line, the reference signal line being of an integral structure.

7. The semiconductor structure according to claim 6, wherein The reference signal line is grounded.

8. The semiconductor structure according to claim 1, wherein The stacked multi-layer memory cell arrays comprise alternately stacked insulating layers and conductive layers, the second gate being located in the conductive layer, and the back gate replacing the insulating layer and being insulated from the conductive layer.

9. The semiconductor structure according to claim 8, wherein, The third source / drain is located in the conductive layer, and the fourth source / drain is located in the same layer as the back gate and is insulated from each other.

10. The semiconductor structure according to claim 1, wherein The first gates of a plurality of the write transistors stacked at intervals along the third direction are interconnected and constitute a write word line extending along the third direction.

11. The semiconductor structure according to claim 1, characterized in that, The second source / drains of a plurality of the write transistors arranged at intervals along a second direction parallel to the substrate are interconnected and constitute a write bit line extending along the second direction, the first direction intersecting the second direction and both being perpendicular to the third direction.

12. A manufacturing method of a semiconductor structure, characterized in that, Including the following steps: Forming a stacked structure of alternately distributed insulating layers and conductive layers on the substrate along a third direction perpendicular to the substrate; Etch the stacked structure to form a vertical conductive portion extending in a second direction parallel to the substrate and a plurality of lateral sub-conductive portions separated by the vertical conductive portion and extending in a first direction parallel to the substrate, where the first direction intersects the second direction and both are perpendicular to the third direction; In the word line preset area of the write transistor in each lateral sub-conductive portion, form a first hole penetrating the stacked structure, and the first hole disconnects each of the lateral sub-conductive portions into a first source / drain and a second source / drain of the write transistor; Make the first source / drain share with the second gate of the read transistor; Form a first semiconductor layer and a first word line of the write transistor in the first hole; Form a second hole extending in the direction towards the substrate near the write bit line between the second source / drains adjacent in the second direction; Perform wet etching on the conductive layer in the second hole to form a first lateral groove, and fill the second hole and the first lateral groove; Form a third hole extending in the direction towards the substrate between two adjacent lateral sub-conductive portions and on the side of the second hole close to the first hole, exposing the conductive layer and the insulating layer; Perform wet etching on the insulating layer in the third hole to form a second lateral groove; Remove the material in the first lateral groove so that the first lateral groove communicates with the second lateral groove, exposing the sidewall and the end of the first source / drain; Deposit an insulating material and a semiconductor material in sequence on the sidewall and the end of the first source / drain to form a second semiconductor layer of the read transistor and a second gate insulating layer; Form a back gate insulated from the second semiconductor layer and a reference signal line electrically connected to the second semiconductor layer on the sidewall of the first source / drain.

13. The manufacturing method according to claim 12, characterized in that, After forming the second semiconductor layer of the read transistor and the second gate insulating layer, it further includes: Fill the first lateral groove and the second lateral groove with a conductive material; Form a fourth hole extending in the direction towards the substrate between the lateral sub-conductive portions adjacent in the second direction and on the side of the second hole away from the first hole, remove the conductive material in the first lateral groove, the material of the second gate insulating layer and the second semiconductor layer, exposing the conductive layer and the insulating layer; Fill the fourth hole with a conductive material; Form a fifth hole extending in the direction towards the substrate between the lateral sub-conductive portions adjacent in the second direction and in the area corresponding to the fourth hole, where the size of the fifth hole in the first direction is larger than the size of the fourth hole in the first direction, remove the conductive material in the fourth hole, and fill the fifth hole with an insulating material to form a read bit line disconnected in the third direction.

14. The manufacturing method according to claim 13, wherein forming a back gate insulated from the second semiconductor layer and a reference signal line electrically connected to the second semiconductor layer on the sidewall of the first source / drain includes: forming a sixth hole extending in the direction towards the substrate between the lateral sub-conductive portions adjacent in the second direction and on the side of the fifth hole close to the first hole; Through the sixth hole, part of the conductive material in the second transverse groove is etched away to form a third transverse groove, and the size of the third transverse groove in the first direction is smaller than the size of the second transverse groove in the first direction; An insulating material is deposited along the inner wall of the third transverse groove to form a dielectric layer, and the third transverse groove is filled with a conductive material to form a back gate; The unetched part in the second transverse groove forms a reference signal line.

15. The manufacturing method according to claim 14, characterized in that, A fourth hole extending in the direction towards the substrate is formed between the adjacent transverse sub-conductive parts in the second direction and on the side of the second hole away from the first hole. After removing the conductive material, the second gate insulating layer, and the material of the second semiconductor layer in the first transverse groove to expose the conductive layer and the insulating layer, the method further includes the steps of: A sixth hole extending in the direction towards the substrate is formed between the adjacent transverse sub-conductive parts in the second direction and on the side of the fifth hole close to the first hole; Through the sixth hole, part of the conductive material in the second transverse groove is etched away to form a third transverse groove, and the size of the third transverse groove in the first direction is smaller than the size of the second transverse groove in the first direction; An insulating material is deposited along the inner wall of the third transverse groove to form a dielectric layer, and the third transverse groove is filled with a conductive material to form a back gate; A fifth hole extending in the direction towards the substrate is formed between the adjacent transverse sub-conductive parts in the second direction and in the region corresponding to the fourth hole; The fifth hole is filled with an insulating material to form a read bit line that is disconnected in the third direction.

16. An electronic device, characterized in that, It includes a semiconductor structure according to any one of claims 1-11, or a semiconductor structure manufactured by the manufacturing method according to any one of claims 12-15.

Images