High-thermal-stability resistive random access memory and performance simulation method thereof

Abstract

The invention relates to a high-thermal-stability resistive random access memory and a performance simulation method thereof, and belongs to the technical field of resistive random access memories. The resistive random access memory comprises a top electrode, a bottom electrode and a resistive random layer located between the top electrode and the bottom electrode, and further comprises a heat insulation layer completely wrapping the top electrode, the bottom electrode and the resistive random layer. Wherein the resistive layer comprises a vanadium pentoxide layer and a titanium disulfide layer. The performance simulation process comprises the following steps: constructing a device model, and drawing or importing a geometric structure of the resistive random access memory; recording voltage, current, conductive filament radius, gap length and device minimum free energy under different scanning voltages; and two groups of current-voltage characteristic data related to SET and reset processes are obtained from the recorded data, and conductance is obtained by dividing corresponding voltage and current, so that a conductance-voltage characteristic curve is obtained. The thermal stability of the device is improved, and the problem that the application temperature range of the vanadium pentoxide resistive random access memory is narrow is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of resistive random access memory, and relates to a resistive random access memory with high thermal stability and a performance simulation method thereof. Background Art

[0002] With the rapid development of information technology, the demand for data storage in modern society is increasing day by day. As the cornerstone of the development of information technology, memories can be classified into read-only memory (ROM) and random access memory (RAM) according to their data read / write methods, and can be classified into volatile memory and non-volatile memory according to the data storage time. At present, the mainstream memories in the market are still mainly non-volatile memories, but the existing non-volatile memories have some inherent defects and it is difficult to meet the high requirements of information technology for memories in terms of read / write speed, storage density and power consumption. Therefore, there is an urgent need to develop new memory devices with faster read speed, larger storage density and lower power consumption.

[0003] To solve these problems, new non-volatile memories such as ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM), phase change random access memory (PRAM) and resistive random access memory (RRAM) have been widely studied. Especially for resistive random access memory, due to its advantages such as simple structure, fast read / write speed (up to sub-nanosecond level), strong scalability and compatibility with CMOS process, it is considered as one of the most potential alternative technologies for the next generation of non-volatile memories. Oxide semiconductor materials have become one of the main materials in the research of resistive random access memory due to their good material stability, diverse components, high yield and compatibility with CMOS process, and have broad application prospects.

[0004] As is well known, two-dimensional titanium disulfide layer has high thermal stability because it has a strong covalent bond structure, a firm layered structure, high metal-sulfur stability, excellent chemical stability, electronic structure and low defect density. Its stable d-orbital electron arrangement helps to reduce structural distortion, enabling it to maintain structural stability at high temperatures. Therefore, even under the influence of high temperatures, the material can still maintain integrity and is not prone to phase change or decomposition. This characteristic further improves the high thermal stability ability of the proposed memory device structure.

[0005] V2O5 is one of the most widely studied and important transition metal oxides. Vanadium pentoxide has broad application potential in many aspects such as chemical catalysis, battery technology, sensors, and optoelectronics. The application of V2O5 in resistive random access memory (RRAM) is mainly reflected in its adjustable conductivity, which can achieve the storage of "1" and "0" through pulse regulation, and synaptic plasticity is demonstrated in neuromorphic computing. These characteristics make V2O5-based RRAM not only suitable for traditional storage but also have potential applications in artificial intelligence, machine learning, and big data processing. With the development of technology, the application prospects of V2O5 and other oxide materials in RRAM are broad.

[0006] In summary, the present invention combines the high thermal stability of titanium disulfide to improve the electrical characteristics of vanadium pentoxide (V2O5) resistive random access memory, aiming to improve the device performance. Summary of the Invention

[0007] In view of this, the purpose of the present invention is to provide a resistive random access memory with high thermal stability and its performance simulation method. By stacking an ultra-thin two-dimensional titanium disulfide material in the vanadium pentoxide resistive random access memory device, the thermal stability of the resistive random access memory is improved, and the device performance is improved.

[0008] To achieve the above purpose, on the one hand, the present invention provides a resistive random access memory with high thermal stability. The resistive random access memory includes a top electrode, a bottom electrode, and a resistive layer located between the top electrode and the bottom electrode, and further includes a heat insulation layer that completely wraps the top electrode, the bottom electrode, and the resistive layer; wherein, the resistive layer includes a vanadium pentoxide layer and a titanium disulfide layer.

[0009] Further, the resistive layer includes a layer of titanium disulfide layer, and the titanium disulfide layer is located above the vanadium pentoxide layer.

[0010] Furthermore, the titanium disulfide layer in the resistive layer can be overlapping multiple layers of titanium disulfide, such as two or three overlapping layers of titanium disulfide, and the overlapping titanium disulfide layers are located above the vanadium pentoxide layer.

[0011] Further, the materials of the top electrode and the bottom electrode are both aluminum, and the material of the heat insulation layer is silicon dioxide.

[0012] On the other hand, the present invention provides a performance simulation method for a resistive random access memory, and the method includes:

[0013] S1. Construct a two-dimensional axisymmetric model of the resistive random access memory, and draw or import the geometric structure of the resistive random access memory;

[0014] S2. For the geometric structure, add the top electrode material, resistive switching layer material, bottom electrode material, and thermal insulation layer material of the resistive random access memory (RRAM), and define the material properties of each region.

[0015] S3. Add current, solid heat transfer, and circuit modules, and set boundary conditions.

[0016] S4. Mesh the constructed model and set the parametric sweep voltage.

[0017] S5. Calculate the free energy of the device when changing the filament radius, and determine the change in free energy corresponding to the conductive filament radius and gap length under a constant voltage.

[0018] S6. Repeat step S5 at different sweep voltages, and record the voltage, current, conductive filament radius, gap length, and minimum free energy of the device.

[0019] S7. Obtain two sets of current-voltage characteristic data related to the SET and reset processes from the recorded data, and divide the corresponding voltage by the current to obtain the conductance, thereby obtaining the conductance-voltage characteristic curve.

[0020] Further, in step S4, the meshing includes: performing extremely fine meshing on the regions of the conductive filament, top electrode, and bottom electrode in the model, and performing meshing with larger element sizes on other regions of the model.

[0021] The beneficial effects of the present invention are as follows:

[0022] (1) The present invention provides a resistive random access memory (RRAM) which uses vanadium pentoxide as the main material of the resistive switching layer, and at the same time combines the ultra-thin two-dimensional transition metal chalcogenide material TiS2 in the resistive switching layer. By utilizing the chemical stability and excellent electrothermal properties of titanium disulfide, the RRAM can maintain the device performance even at high temperatures, improving the thermal stability of the device and solving the problem of narrow application temperature range of the vanadium pentoxide RRAM.

[0023] (2) The present invention uses the multi-physics field finite element analysis software COMSOL, combines the current continuity equation, Joule heat model equation, and oxygen vacancy migration equation, and simulates the dynamic process of the formation and rupture of oxygen vacancy conductive filaments in the RRAM under the electrothermal modeling effect, obtaining an electrothermal modeling simulation model of the RRAM with high thermal stability. At the same time, by setting different sweep voltages and recording parameters such as the voltage, current, conductive filament radius, gap length, and minimum free energy of the model under different sweep voltages, the voltage-current characteristic curve of the device is obtained, and the conductance-voltage characteristic curve is obtained based on the voltage-current characteristic curve, realizing the simulation of the performance of the RRAM, so as to quickly determine the device performance of the RRAM under different structures and provide data support for device parameter optimization.

[0024] Other advantages, objects, and features of the present invention will be set forth in part in the following description, and in part will be obvious to those skilled in the art upon examination of the following, or may be learned by practice of the present invention. The objects and other advantages of the present invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to make the objects, technical solutions, and advantages of the present invention more clear, the present invention will be described in detail with reference to the accompanying drawings, where:

[0026] Figure 1 It is a two-dimensional model of the resistive random access memory (Al / V2O5 / Al) in Example 1. Figure 1 (a) It is a two-dimensional model of the resistive random access memory under a positive voltage. Figure 1 (b) It is a two-dimensional model of the resistive random access memory under a negative voltage, where conductive filaments appear at V2O5 under the negative voltage.

[0027] Figure 2 It is a schematic diagram of the mesh division of the resistive random access memory (Al / V2O5 / Al) without a thermal insulation layer in Example 1.

[0028] Figure 3 It is the C-V characteristic simulation curve of the resistive random access memory (Al / V2O5 / Al) in Example 1.

[0029] Figure 4 It is a two-dimensional model of the resistive random access memory (Al / V2O5 / Al) in Examples 2, 3, and 4. Figure 4 (a) It is a two-dimensional model of the resistive random access memory under a negative voltage, where conductive filaments appear at V2O5 under the negative voltage. Figure 4 (b) It is a two-dimensional model of the resistive random access memory under a positive voltage.

[0030] Figure 5 It is a schematic diagram of the mesh division of the resistive random access memory (Al / TiS2 / V2O5 / Al) with a stacked layered TiS2 in Examples 2, 3, and 4.

[0031] Figure 6 It is the C-V characteristic simulation curve of the resistive random access memory (Al / TiS2 / V2O5 / Al) with one layer of TiS2 stacked in Example 2 of the present invention.

[0032] Figure 7 It is the C-V characteristic simulation curve of the resistive random access memory (Al / TiS2 / V2O5 / Al) with two layers of TiS2 stacked in Example 3.

[0033] Figure 8C-V characteristic simulation curve of the resistive memory (Al / TiS2 / V2O5 / Al) with three layers of TiS2 stacked in Example 3. Detailed implementation manners

[0034] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0035] Among them, the drawings are only for illustrative purposes, showing only schematic diagrams, not physical diagrams, and cannot be understood as a limitation to the present invention; in order to better illustrate the embodiments of the present invention, some components in the drawings will be omitted, enlarged or reduced, and do not represent the dimensions of actual products; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0036] In the drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc. indicating the orientation or positional relationship, they are based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the drawings are only for illustrative purposes and cannot be understood as a limitation to the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0037] The properties of various materials used in the following embodiments are shown in Table 1:

[0038] Table 1

[0039]

[0040]

[0041] The simulation formulas used in the following embodiments are as follows:

[0042] The current module equation of the device is as follows:

[0043]

[0044] J = σE (2)

[0045]

[0046] The equations of the solid heat transfer module are as follows:

[0047]

[0048] Where k is the thermal conductivity.

[0049] The equations of the circuit module are as follows:

[0050] Q S = J·E (5)

[0051] The balanced on and off states of a resistive random access memory (RRAM) are due to the formation and rupture of conductive filaments. The laws of thermodynamics dictate that these states correspond to the minimum of the free energy. Based on this, a numerical model is proposed to determine the conductive filament parameters and thus the current by minimizing the free energy at a given voltage. The thermodynamic numerical analysis model used relies on the principle of minimizing the free energy (FE) within the memory device, as the FE changes under the influence of an external voltage. At the same time, the memory device also utilizes phase transitions in the oxide material to reduce its free energy, including breaking chemical bonds. The free energy within this memory device is expressed as:

[0052]

[0053] Where ρ is the mass density of the material used in the memory device, C P is the specific heat capacity of the material used in the memory device, δT is the change in temperature with the internal thermal gradient of the memory device, ε is the dielectric constant, E is the electric field, r is the radius of the conductive filament (CF), h is the height of the SET process of the CF, l is the gap length of the reset (RESET) process, σ s is the interfacial energy, and δμ is the chemical potential difference between the unstable conductive and insulating phases during the SET process and between the unstable conductive and metastable conductive phases during the reset process.

[0054] The conductivity of the conductive filament is calculated using the following formula:

[0055]

[0056] The thermal conductivity of the conductive filament is expressed by the following formula:

[0057] k1 = σ c (T,V)TL (8)

[0058] The gap conductivity is expressed by the following formula:

[0059]

[0060] The thermal conductivity of the gap is expressed by the following formula:

[0061] k2 = k eff σ c (T,V)TL(10)

[0062] In the simulation experiments of the following examples, the following algorithm is used to determine the minimum free energy configuration of the device and its corresponding current-voltage (I-V) characteristics:

[0063] 1) Construct a device model.

[0064] 2) Apply the source voltage and calculate the free energy of the device when changing the filament radius.

[0065] 3) Determine the free energy corresponding to the filament radius and the gap length under a constant source voltage change.

[0066] 4) Repeat steps 2) and 3) at different source voltages.

[0067] 5) Record the voltage, current, conductive filament radius, gap length and minimum free energy of the device model.

[0068] 6) Obtain two sets of current-voltage (I-V) characteristics related to the SET and reset processes in step 5).

[0069] 7) Divide the voltage by the current to obtain the conductance and obtain the conductance-voltage (C-V) characteristics.

[0070] Among them, the SET process includes two key sub-processes: rapid shunting of the electrode and radial expansion of the conductive filaments (CFs). The rapid shunting of the electrode has different stages: nucleation and longitudinal growth of the CFs, both of which are characterized by their random behavior. Similarly, the radial expansion of the conductive filaments (CFs) consists of two basic sub-processes: initiating a gap through CF rupture and then random growth of this gap.

[0071] Example 1

[0072] This example provides a resistive random access memory, as Figure 1 shown, which sequentially includes a SiO2 upper thermal insulation layer (radius 500 nm, thickness 300 nm), an Al top electrode (radius 10 nm, thickness 30 nm), a V2O5 resistive switching layer (radius 10 nm, thickness 5 nm), an Al bottom electrode (radius 10 nm, thickness 60 nm), and a SiO2 lower thermal insulation layer (radius 500 nm, thickness 300 nm) from top to bottom.

[0073] For the resistive random access memory (RRAM) with V2O5 as the resistive switching layer, a thermoelectric modeling and simulation model of Al / V2O5 / Al was established using the multi-physics finite element analysis software COMSOL. Combining the current continuity equation, the Joule heat model equation, and the free energy equation, the dynamic process of the formation and rupture of conductive filaments under the thermoelectric modeling effect was simulated in detail. The specific implementation steps are as follows:

[0074] (1) Construct a two-dimensional axisymmetric model (as shown in Figure 1 ) and draw or import the geometric structure of the resistive random access memory.

[0075] (2) For the geometric structure, add material properties to the device, including the top electrode of Al material, the resistive switching layer of V2O5 material, the bottom electrode of Al material, and the thermal insulation layer of SiO2 material.

[0076] (3) Add current, solid heat transfer, and circuit modules, and set the boundary conditions. The parameter values used in the simulation are shown in Table 2:

[0077] Table 2

[0078]

[0079] (4) For mesh generation, in finite element analysis, each mesh is called an element. When performing finite element analysis, a set of equations will be solved for each mesh. As the mesh is continuously refined, the obtained solution is closer to the true solution. Since the conductive filaments and the upper and lower electrodes of the model are the key research areas, the conductive filaments and the upper and lower electrode areas are selected for extremely fine refinement, and larger sizes are selected for other areas. The device mesh generation is as shown in Figure 2 .

[0080] The simulated C-V characteristic curve of the resistive random access memory (Al / V2O5 / Al) in this embodiment in the logarithmic coordinate system is as shown in Figure 3 , Figure 3 showing the transition of the device between the high-resistance state and the low-resistance state.

[0081] Example 2

[0082] Since TiS2 has a thin-layer structure, its high specific surface area and small size help to improve the storage density and reduce power consumption. At the same time, TiS2 exhibits good chemical stability and environmental adaptability, ensuring long-term reliability. It can provide high performance, low power consumption, and high reliability in RRAM devices and is a strong candidate material for future storage technologies.

[0083] Therefore, in this embodiment, two-dimensional TiS2 is selected as the stack layer, and a layer of TiS2 is added on the basis of the device proposed in Example 1 to establish a resistive random access memory device with an Al / TiS2 / V2O5 / Al stack layer, as shown in Figure 4As shown, the device successively includes a SiO2 upper thermal insulation layer (with a radius of 500 nm and a thickness of 300 nm), an Al top electrode (with a radius of 10 nm and a thickness of 40 nm), a TiS2 resistive switching layer (with a radius of 10 nm and a thickness of 0.65 nm), a V2O5 resistive switching layer (with a radius of 10 nm and a thickness of 5 nm), an Al bottom electrode (with a radius of 10 nm and a thickness of 60 nm), and a SiO2 lower thermal insulation layer (with a radius of 500 nm and a thickness of 300 nm) from top to bottom.

[0084] The same steps as in Example 1 were used to perform electrothermal modeling and simulation on the device to explore the changes in device performance. The specific simulation method is as follows:

[0085] (1) Construct a two-dimensional axisymmetric model and draw or import the geometric structure of the resistive random access memory.

[0086] (2) For the geometric structure, add material properties to the device. When the voltage exceeds the threshold voltage, the device enters the SET process, and the conductive filament begins to form. By calculating and comparing the free energy, the radius of the conductive filament at the minimum energy is found. Subsequently, the conductive filament is completely formed, and the device changes to the low-resistance state.

[0087] (3) Mesh the device (in the same way as in Example 1), and the meshing result is as Figure 5 shown.

[0088] (4) Add current, solid heat transfer, and circuit modules, and set the boundary conditions. The parameter values used in the simulation are the same as those in Example 1.

[0089] In this example, the simulated C-V characteristic curve of the resistive random access memory (Al / TiS2 / V2O5 / Al) in the logarithmic coordinate system is as Figure 6 shown. Compared with Example 1, for the V2O5 resistive random access memory with an additional layer of TiS2, the temperature at which the maximum conductance in the low-resistance state undergoes a sudden change is increased to 300 °C.

[0090] Example 3

[0091] Compared with Example 2, in this example, a double-layer TiS2 is used as the stack. The resistive random access memory device provided in this example successively includes a SiO2 upper thermal insulation layer (with a radius of 500 nm and a thickness of 300 nm), an Al top electrode (with a radius of 10 nm and a thickness of 40 nm), a TiS2 resistive switching layer (with a radius of 10 nm and a thickness of 1.3 nm), a V2O5 resistive switching layer (with a radius of 10 nm and a thickness of 5 nm), an Al bottom electrode (with a radius of 10 nm and a thickness of 60 nm), and a SiO2 lower thermal insulation layer (with a radius of 500 nm and a thickness of 300 nm) from top to bottom.

[0092] The same steps as in Example 1 were used to perform electrothermal modeling and simulation on the device to explore the changes in device performance. The specific simulation method is as follows:

[0093] (1) Construct a two-dimensional axisymmetric model and draw or import the geometric structure of the resistive random access memory (RRAM).

[0094] (2) For the above geometric structure, add material properties to the device. The basic material parameters are the same as those in Example 1, and the simulation materials include the properties of V2O5 and filaments in addition.

[0095] (3) Mesh the device (in the same way as in Example 1).

[0096] (4) Add current, solid heat transfer, and circuit modules, and set the boundary conditions. The parameter values used in the simulation are the same as those in Example 1.

[0097] In this embodiment, the simulated I-V characteristic curve of the resistive random access memory (Al / bilayer TiS2 / V2O5 / Al) in the coordinate system is as Figure 7 shown. Compared with Example 1, the temperature at which the maximum conductance mutates in the low resistance state is delayed to 500 °C.

[0098] Example 4

[0099] Based on Example 1, the influence of the resistive switching performance of the stacked device was further explored. Three layers of TiS2 were added on the basis of Example 1. The resistive random access memory includes a SiO2 upper thermal insulation layer (radius of 500 nm and thickness of 300 nm), an Al top electrode (radius of 10 nm and thickness of 40 nm), a TiS2 resistive switching layer (radius of 10 nm and thickness of 1.95 nm), a V2O5 resistive switching layer (radius of 10 nm and thickness of 5 nm), an Al bottom electrode (radius of 10 nm and thickness of 60 nm), and a SiO2 lower thermal insulation layer (radius of 500 nm and thickness of 300 nm) from top to bottom.

[0100] The same steps as in Example 1 were used to perform electrothermal modeling and simulation on the device to explore the changes in device performance. The specific simulation method is as follows:

[0101] (1) Construct a two-dimensional axisymmetric model and draw or import the geometric structure of the resistive random access memory (RRAM).

[0102] (2) For the above geometric structure, add material properties to the device. Among the material properties of the device, TiS2 and V2O5 are the same as those in Example 2 and Example 3.

[0103] (3) Mesh the device (in the same way as in Example 2).

[0104] (4) Add current, solid heat transfer, and circuit modules, set boundary conditions, and the parameter values used in the simulation are the same as those in Embodiment 1.

[0105] In this embodiment, the C-V characteristic simulation curve of the resistive random access memory (Al / three-layer TiS2 / V2O5 / Al) with three layers of TiS2 stacked is as Figure 8 shown. Compared with Embodiment 1, the resistive random access memory with three layers of TiS2 stacked has higher thermal stability.

[0106] In summary, the present invention proposes a resistive random access memory, which uses V2O5 as the resistive layer and simultaneously adds TiS2 as a stacked layer. The chemical stability and excellent electrothermal performance of TiS2 are utilized to improve the thermal stability of the resistive random access memory, thereby improving the problem of the narrow application temperature range of the V2O5 resistive random access memory.

[0107] In addition, the present invention uses the multi-physics field finite element analysis software COMSOL, combines the current continuity equation, the Joule heat model equation, and the oxygen vacancy migration equation, and simulates the dynamic process of the formation and fracture of oxygen vacancy conducting filaments under the electrothermal modeling effect. The dynamic process of the formation and fracture of oxygen vacancy conducting filaments under the electrothermal modeling effect is simulated to obtain an electrothermal modeling simulation model of the resistive random access memory with high thermal stability. The present invention effectively observes the dynamic change process of conductance by applying a voltage to the vanadium pentoxide resistive random access memory, and then simulates the formation and fracture of the conducting filaments, verifying the resistive switching characteristics of vanadium oxide.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the present technical solution, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A resistive random access memory with high thermal stability, characterized in that, The resistive random access memory includes a top electrode, a bottom electrode, and a resistive switching layer located between the top electrode and the bottom electrode, and further includes a thermal insulation layer that completely wraps the top electrode, the bottom electrode, and the resistive switching layer; wherein, the resistive switching layer includes a vanadium pentoxide layer and a titanium disulfide layer.

2. The resistive random access memory according to claim 1, wherein The resistive switching layer includes a layer of titanium disulfide layer, and the titanium disulfide layer is located above the vanadium pentoxide layer.

3. The resistive random access memory according to claim 1, characterized in that, The resistive switching layer includes two overlapping layers of titanium disulfide layer, and the two overlapping layers of titanium disulfide layer are located above the vanadium pentoxide layer.

4. The resistive random access memory according to claim 1, characterized in that, The resistive switching layer includes three overlapping layers of titanium disulfide layer, and the three overlapping layers of titanium disulfide layer are located above the vanadium pentoxide layer.

5. The resistive random access memory according to claim 1, characterized in that, The materials of the top electrode and the bottom electrode are both aluminum, and the material of the thermal insulation layer is silicon dioxide.

6. A performance simulation method for the resistive random access memory according to any one of claims 1 to 5, characterized in that, The method includes: S1. Construct a two-dimensional axisymmetric model of the resistive random access memory, and draw or import the geometric structure of the resistive random access memory; S2. For the geometric structure, add the materials of the top electrode, the resistive switching layer, the bottom electrode, and the thermal insulation layer of the resistive random access memory, and define the material properties of each region; S3. Add current, solid heat transfer, and circuit modules, and set boundary conditions; S4. Perform mesh division on the constructed model, and set the parametric sweep voltage; S5. Calculate the free energy of the device when changing the radius of the filament, and determine the change in free energy corresponding to the radius of the conductive filament and the gap length under a constant voltage; S6. Repeat step S5 under different sweep voltages, and record the voltage, current, radius of the conductive filament, gap length, and the minimum free energy of the device; S7. Obtain two sets of current-voltage characteristic data related to the SET and reset processes from the recorded data, and divide the corresponding voltage and current to obtain the conductance, so as to obtain the conductance-voltage characteristic curve.

7. The method according to claim 6, characterized in that In step S4, performing mesh division includes: performing extremely fine mesh division on the regions of the conductive filament, the top electrode, and the bottom electrode in the model, and performing larger-size mesh division on other regions of the model.

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