Short-circuit protection method for P-GaN gate enhanced GaN + HEMT device

Abstract

The invention discloses a short-circuit protection method for a P-GaN gate enhanced GaN + HEMT device, and the method comprises the steps: manufacturing a wafer of a P-GaN layer, removing the P-GaN layer outside a gate through an etching technology, obtaining a gate metal region, and preparing a source electrode and a drain electrode at the two sides of the gate metal region respectively; and selective deposition is carried out in the reserved grid metal area to obtain multiple sections of SCP grids which are separated from one another, and finally the P-GaN grid enhanced GaN HEMT device is obtained. The short-circuit protection capability of PGaN E-mode GaN is enhanced through a method of selectively depositing gate metal on a P-GaN layer, the saturation current of the enhanced gallium nitride device is greatly reduced through selective gate metal deposition, so that the short-circuit protection capability is enhanced, and meanwhile, the method does not increase the normal on-resistance of the device. Compared with an E-GaN device which does not use the technology, the reliability and the stability of the enhanced gallium nitride device in the fields of motor driving and the like can be remarkably improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a short-circuit protection method for a P-GaN gate-enhanced GaN+HEMT device. Background Art

[0002] Gallium nitride high electron mobility transistor (GaN HEMT) devices are emerging semiconductor devices that have been widely used in multiple fields due to their excellent performance. High-efficiency GaN power devices are penetrating multiple power electronics markets, including adapters, power units, photovoltaic inverters, battery chargers, and motor drivers. When used in motor drive applications, GaN power devices must not only pass strict JEDEC or AEC-Q0101 reliability tests, but also be able to withstand momentary short-circuit currents. GaN devices need to survive short-circuit events caused by overload, through-conduction, software errors, current surges, or external fault conditions. When a short-circuit event occurs, the system must detect the fault and safely turn off the power device to prevent catastrophic failure. Fault detection can be achieved by adding protection circuits (such as desaturation detection (DESAT) or overcurrent detection (OC)) in the gate driver. To ensure safe operation, the power device and the gate driver must work together. The response time of the protection circuit must be carefully adjusted: if the response time is too fast, the protection circuit may have poor noise immunity and may be erroneously activated due to noise, interference, and switching transients. If the response time is too slow, the power device may fail before the protection system has been activated, posing a dangerous hazard to the system and the user.

[0003] Commercial gate drivers typically have a sufficient response time, in the range of about 1 microsecond. During this period, the power device must be able to withstand short-circuit conditions without failure. Therefore, it is necessary to define an important device requirement: the short-circuit withstand time (SCWT, Short-Circuit Withstanding Time), which is the minimum time that the device can withstand a short-circuit event. One of the main influencing factors of the short-circuit withstand time for any given device technology is thermally induced catastrophic failure. Under short-circuit conditions, the device will withstand high voltage and high current, resulting in a huge instantaneous power loss and a rapid temperature rise until one or more failure mechanisms are triggered and catastrophic failure occurs. Therefore, to increase the SCWT, it is important to limit the power loss during a short-circuit event so that the protection circuit can intervene before reaching the fault critical temperature. The biggest challenge is to simultaneously maintain high device performance (low on-resistance, low capacitance, and fast switching) and long-term reliability.

[0004] Wide bandgap (WBG) devices such as SiC MOSFETs or GaN HEMTs have a higher SCWT, which is more challenging. Due to their own characteristics and advantages, WBG devices can provide higher power density in a smaller area than traditional silicon devices. Therefore, during a short-circuit event, their temperature rise may be steeper, resulting in a shorter SCWT than silicon-based devices. In silicon-based power devices such as Si IGBTs, the SCWT can exceed 10 microseconds. There is a strong trade-off between the SCWT and performance in SiC devices: SiC devices optimized for low on-resistance (Ron,sp) typically have a shorter SCWT. A three-fold reduction in Ron,sp (from 21.5 mΩ·cm 2 to 7.5 mΩ·cm 2 ) also results in a three-fold reduction in the SCWT (from 9 μs to 2.7 μs). A similar situation has been observed in GaN devices. When 600 V GaN devices are designed with a Ron,sp that competes with silicon devices, they show an SCWT limited to less than 0.5 microseconds at 400 V, which is not sufficient to provide reliable short-circuit protection.

[0005] Although the failure mechanism remains the subject of research, one of the reasons for the limitation of the SCWT in commercial GaN HEMTs is still the high current density. The 2DEG formed at the AlGaN / GaN interface has a charge density of about 1x10^13 electrons / cm² and a mobility of up to 2000 cm² / V·s, resulting in a high current density of up to 1 A / mm, which leads to a sharp rise in power density and temperature during a short circuit. If the industry relies on traditional GaN HEMTs, non-ideal constraints are required to implement an ultra-fast short-circuit protection circuit. TI has released a short-circuit protection circuit with a response speed at the ns level in this case, leaving very little room for turn-off time and having a higher risk of false triggering in noisy industrial and automotive environments. More ideally, an engineering solution can be implemented at the device level to increase the SCWT while maintaining high performance (low specific on-resistance and low switching time) and high reliability.

[0006] As a leader in the field of gallium nitride power technology, Transphorm has created a D-mode GaN power device with a short-circuit current limiter (SCCL) to achieve a sufficiently long SCWT while maintaining competitive on-resistance and maximum reliability. By inserting a specially designed barrier layer in the channel layer, the saturation current can be significantly reduced without changing the on-resistance and switching time, achieving a short-circuit protection time of about 800ns. However, this method cannot work on another equally common E-mode GaN power device. The current traditional E-mode GaN short-circuit protection is still achieved by reducing the driving voltage. This method effectively reduces the saturation current while greatly enhancing the channel resistance. Therefore, in the prior art, a more optimized short-circuit protection method for E-mode GaN power devices has become a technical problem that needs to be solved urgently in this field. Summary of the invention

[0007] In order to solve the above technical problems, the present invention provides a short-circuit protection method for a P-GaN gate enhanced GaN+HEMT device, comprising:

[0008] A wafer of a P-GaN layer is manufactured, and the P-GaN layer outside the gate is removed by an etching process to obtain a gate metal region, and a source electrode and a drain electrode are respectively prepared on both sides of the gate metal region;

[0009] Selectively depositing on the reserved gate metal region, a plurality of SCP gates spaced apart from each other are obtained, and finally a P-GaN gate enhanced GaN HEMT device is obtained.

[0010] Preferably, the process of manufacturing a wafer of a P-GaN layer includes manufacturing an epitaxial structure of the wafer of the P-GaN layer;

[0011] The epitaxial structure includes a substrate, a nucleation layer, a buffer layer, a channel layer, and an AIGaN / AIN barrier layer.

[0012] Preferably, the nucleation layer is provided on the substrate of the epitaxial structure, the buffer layer is provided on the nucleation layer, the channel layer is provided on the buffer layer, and the AIGaN / AIN barrier layer is provided on the channel layer.

[0013] Preferably, the material of the substrate includes one or more of gallium nitride, silicon, silicon carbide, and sapphire;

[0014] The thickness of the substrate is not less than 300 μm;

[0015] The material of the nucleation layer includes one or more of aluminum nitride and aluminum gallium nitride;

[0016] The thickness of the nucleation layer is 1 to 3 μm;

[0017] The material of the buffer layer includes one or more of aluminum nitride, aluminum gallium nitride, and gallium nitride;

[0018] The thickness of the buffer layer is 2 - 4 um.

[0019] Preferably, the channel layer includes gallium nitride;

[0020] The thickness of the channel layer is 2 um.

[0021] Preferably, the barrier layer is aluminum nitride or aluminum gallium nitride;

[0022] The thickness of the barrier layer is 20 nm.

[0023] Preferably, the P-GaN layer uses magnesium as a dopant, and the doping concentration is not less than 2×1018 cm-3. The threshold voltage is usually 1.5 - 3.0 V;

[0024] Preferably, the source electrode is a combination system of Ti / Al materials or a combination system of Ti / Al / Ni / Au materials;

[0025] The drain electrode is a Ti / Al material system or a Ti / Al / Ni / Au material system.

[0026] Preferably, the gate electrode includes a gate Schottky electrode made of Schottky metal;

[0027] The gate Schottky electrode is a TiN / Al material system or a Ni / Au material system.

[0028] Preferably, selective deposition is performed in the reserved gate metal region to obtain multiple segmented SCP gates spaced apart from each other, specifically including:

[0029] By selectively depositing in the gate metal region, a whole strip of gate metal is segmented to different degrees, and partial conduction under gate control is performed to obtain the SCP gate.

[0030] Compared with the prior art, the present invention has the following advantages and technical effects:

[0031] By selectively depositing gate metal on the P-GaN layer, the present invention realizes the protection of the short-circuit ability of P-GaN E-mode GaN. By selectively depositing gate metal, the saturation current of the enhancement-mode gallium nitride device is significantly reduced, thereby enhancing the short-circuit protection ability. At the same time, this method does not significantly increase the normal on-resistance of the device. Compared with E-GaN devices that do not use this technology, the reliability and stability of enhancement-mode gallium nitride devices in fields such as motor drive can be significantly improved.

[0032] The preparation method of the present invention has a simple process, and the optimization of the short-circuit capability is achieved only through simple selective regional deposition, and the stability of the device can be enhanced without performing a special process on the channel layer;

[0033] The preparation method of the present invention reduces the influence on the on-resistance of the device to the greatest extent without affecting the performance of the device, and does not need to sacrifice the on-resistance per unit area (Ronsp) in exchange for the short circuit withstand time (SCWT).

[0034] The preparation method of the present invention has commercial cost advantages and is easy to be used commercially on a large scale. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0036] Figure 1 This is a schematic diagram of enhanced GaN epitaxy according to an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of a GaN HEMT with a gate, source and drain prepared on a P-GaN layer according to an embodiment of the present invention;

[0038] Figure 3 A schematic diagram of preparing a SCP gate according to an embodiment of the present invention;

[0039] Figure 4 It is a comparative analysis diagram of short-circuit protection of GaN HEMT devices according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0041] like Figures 1-3 As shown, this embodiment provides a short-circuit protection method for a P-GaN gate enhanced GaN+HEMT device, including:

[0042] A wafer of a P-GaN layer is manufactured, and the P-GaN layer outside the gate is removed by an etching process to obtain a gate metal region, and a source electrode and a drain electrode are respectively prepared on both sides of the gate metal region;

[0043] Selectively depositing on the reserved gate metal region, a plurality of SCP gates spaced apart from each other are obtained, and finally a P-GaN gate enhanced GaN HEMT device is obtained.

[0044] Prepare an SCP gate on the P-GAN layer, partially covering the PGAN. It can be a multi-segment SCP gate, such as 2 segments, 3 segments, 4 segments or even more segments. The various segments of the SCP gate are separated from each other. The channel under the SCP gate will conduct when the threshold voltage is exceeded, and the rest will not conduct. Through such an operation, the short-circuit ability protection of the PGaN E-mode GaN is achieved. By selectively depositing gate metal, the saturation current of the enhancement-mode gallium nitride device is significantly reduced, thereby enhancing the short-circuit protection ability. At the same time, this method does not significantly increase the normal on-resistance of the device.

[0045] Reference Figure 4 As shown, the conventional I DS and V DS curves are short SCWT curves, and the I DS and V DS curves provided by the embodiments of the present invention are long SCWT. It can be seen from these two curves that their slopes (on-resistances) are basically the same, with little difference, but the GaN HEMT provided by the embodiments of the present invention greatly reduces the saturation current.

[0046] A more preferred solution is that the process of fabricating the wafer for the P-GaN layer includes fabricating the epitaxial structure of the wafer for the P-GaN layer; the epitaxial structure includes a substrate, a nucleation layer, a buffer layer, a channel layer, an AlGaN / AIN barrier layer, and an outer P-GaN layer. Among them, the connection relationship of the epitaxial structure is as follows: a nucleation layer is provided on the substrate, a buffer layer is provided on the nucleation layer, a channel layer is provided on the buffer layer, an AlGaN / AIN barrier layer is provided on the channel layer, and an outer P-GaN layer is provided on the AlGaN / AIN barrier layer.

[0047] Among them, the material of the substrate includes one or more of gallium nitride, silicon, silicon carbide, and sapphire; the thickness of the substrate is not less than 300 μm.

[0048] A further solution is that the substrate material of this embodiment is selected as silicon, and the specific thickness is 300 μm.

[0049] The material of the nucleation layer includes one or more of aluminum nitride and aluminum gallium nitride; the thickness of the nucleation layer is 1 - 3 μm.

[0050] A further solution is that the material of the nucleation layer of this embodiment is selected as a combination of AlN and AlGaN, and the thickness is 2 μm.

[0051] The material of the buffer layer includes one or more of aluminum nitride, aluminum gallium nitride, and gallium nitride; the thickness of the buffer layer is 2 - 4 μm.

[0052] A further solution is that the material of the buffer layer of this embodiment is selected as a combination of AlN, AlGaN, and GaN, and the thickness is 2 μm.

[0053] Among them, the channel layer includes gallium nitride; the thickness of the channel layer is 2 μm.

[0054] The barrier layer is aluminum nitride or aluminum gallium nitride; the thickness of the barrier layer is 20 nm.

[0055] The P-GaN layer uses magnesium as a dopant, and the doping concentration is not less than 2×10 18 cm -3 . The threshold voltage is usually 1.5 - 3.0 V.

[0056] The source electrode is a combined system of Ti / Al materials or a combined system of Ti / Al / Ni / Au materials; the drain electrode is a Ti / Al material system or a Ti / Al / Ni / Au material system.

[0057] In a further solution, the gate electrode includes a gate Schottky electrode made of Schottky metal; the gate Schottky electrode is a TiN / Al material system or a Ni / Au material system.

[0058] In a further step, this embodiment uses selective deposition of gate metal to improve the short-circuit protection ability of the P-GaN enhancement device. The specific steps include: photolithography, selective deposition, removal of photoresist, gate metal segmentation, and final cleaning and inspection.

[0059] Among them, photolithography is used to define the area for gate metal deposition; it includes the following steps:

[0060] 1. Coat a layer of photoresist on the P-GaN layer, which can be positive photoresist or negative photoresist.

[0061] 2. Use a mask to expose the gate pattern onto the photoresist. The mask includes transparent and opaque regions, where the transparent regions allow ultraviolet light to pass through and expose the photoresist to cause chemical changes.

[0062] 3. Develop the exposed photoresist. For positive photoresist, the exposed part will be dissolved to form an opening consistent with the mask pattern; for negative photoresist, the unexposed part will be dissolved to form a pattern.

[0063] 4. Check the quality of the photolithography pattern to ensure that the size and position of the pattern meet the design requirements.

[0064] Selective deposition is used to deposit gate metal on the area defined by photolithography; it includes the following steps:

[0065] 1. Selective deposition technology: This embodiment uses physical vapor deposition (PVD) or chemical vapor deposition (CVD) technology to precisely control the deposition area and deposition thickness, and realizes selective deposition by adjusting process parameters. The process parameters include temperature, pressure, power of the deposition source, etc.

[0066] 2. Deposited Material: The gate Schottky electrode adopts the TiN / Al material system or the Ni / Au material system.

[0067] 3. Deposition Process: In the deposition equipment, place the wafer in the deposition chamber. By controlling the parameters of the deposition source (such as evaporation source or chemical vapor source), deposit the metal material in the photoresist opening area. During the deposition process, the photoresist area will block the metal deposition, so it is necessary to ensure that the metal is only deposited in the defined gate area and control the deposition thickness according to the design requirements.

[0068] Remove the remaining photoresist to expose the area where the metal is not deposited; including the following steps:

[0069] 1. Use wet chemical methods, such as using acetone or a dedicated photoresist remover to remove the photoresist.

[0070] 2. Clean the wafer to ensure that the photoresist is completely removed without damaging the deposited gate metal.

[0071] The gate metal segmentation is to segment the gate metal to different degrees. By adjusting the spacing and length between segments, precise control of the saturation current is achieved. In this embodiment, partial conduction is achieved to reduce the saturation current; including the following steps:

[0072] 1. Second lithography: Perform lithography again on the area where the gate metal has been deposited to define the area to be segmented.

[0073] 2. Etching: Use wet or dry etching techniques to etch the gate metal into the required segmented structure. During the etching process, it is necessary to precisely control the etching time to avoid over-etching.

[0074] 3. Remove the photoresist: Remove the photoresist of the second lithography to expose the segmented gate metal structure.

[0075] Final cleaning and inspection are used to ensure the cleanliness of the wafer surface and check whether the structure of the gate metal segmentation meets the design requirements; including the following steps:

[0076] 1. Clean the wafer using deionized water (DIWater) and an ultrasonic cleaning device.

[0077] 2. Use equipment such as a scanning electron microscope (SEM) or an atomic force microscope (AFM) to check the segmented structure and surface quality of the gate metal.

[0078] 3. Conduct electrical tests to verify whether the conductivity and segmentation effect of the gate metal meet the design requirements.

[0079] Furthermore, the process of fabricating the gate electrode includes:

[0080] By selectively depositing in the gate metal region, a whole gate metal is segmented to different extents, and partial conduction under gate control is performed to obtain a multi-segmented and spaced SCP gate, thereby reducing the maximum saturation current without affecting the Ron characteristic, and obtaining a gate electrode.

[0081] In this embodiment, by selectively depositing the gate metal on the P-GaN layer, the short-circuit capability of the PGaN E-mode GaN is protected. By selectively depositing the gate metal, the saturation current of the enhancement-mode gallium nitride device is significantly reduced, thereby enhancing the short-circuit protection capability. At the same time, this method does not increase the normal on-resistance of the device. Compared with the E-GaN device without using this technology, the reliability and stability of the enhancement-mode gallium nitride device in fields such as motor drive can be significantly improved.

[0082] The above is only a preferred specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A short-circuit protection method for a P-GaN gate-enhanced GaN+HEMT device, characterized in that, Including: A wafer with a P-GaN layer is fabricated. The P-GaN layer except for the gate is removed through an etching process to obtain a gate metal region, and a source electrode and a drain electrode are respectively fabricated on both sides of the gate metal region. Selective deposition is carried out on the remaining gate metal region to obtain multiple segments of SCP gates spaced apart from each other, and finally a P-GaN gate enhanced GaN HEMT device is obtained.

2. The short-circuit protection method for the P-GaN gate enhanced GaN+HEMT device according to claim 1, characterized in that The process of fabricating the wafer with the P-GaN layer includes fabricating the epitaxial structure of the wafer with the P-GaN layer. The epitaxial structure includes a substrate, a nucleation layer, a buffer layer, a channel layer, and an AlGaN / AIN barrier layer.

3. The short-circuit protection method for the P-GaN gate enhanced GaN+HEMT device according to claim 2, characterized in that The nucleation layer is provided on the substrate of the epitaxial structure, the buffer layer is provided on the nucleation layer, the channel layer is provided on the buffer layer, and the AlGaN / AIN barrier layer is provided on the channel layer.

4. The short-circuit protection method for the P-GaN gate enhanced GaN+HEMT device according to claim 2, characterized in that The material of the substrate includes one or more of gallium nitride, silicon, silicon carbide, and sapphire; The thickness of the substrate is not less than 300μm; The material of the nucleation layer includes one or more of aluminum nitride and aluminum gallium nitride; The thickness of the nucleation layer is 1 - 3μm; The material of the buffer layer includes one or more of aluminum nitride, aluminum gallium nitride, and gallium nitride; The thickness of the buffer layer is 2 - 4μm.

5. The short-circuit protection method for the P-GaN gate enhanced GaN+HEMT device according to claim 2, characterized in that The channel layer includes gallium nitride; The thickness of the channel layer is 2μm.

6. The short-circuit protection method for the P-GaN gate enhanced GaN+HEMT device according to claim 2, characterized in that The barrier layer is aluminum nitride or aluminum gallium nitride; The thickness of the barrier layer is 20nm.

7. The short-circuit protection method for the P-GaN gate enhanced GaN+HEMT device according to claim 1, characterized in that The P-GaN layer uses magnesium as a dopant, the doping concentration is not less than 2×1018 cm-3, and the threshold voltage is 1.5 - 3.0V.

8. The short-circuit protection method for the P-GaN gate enhanced GaN+HEMT device according to claim 1, characterized in that The source electrode is a combination system of Ti / Al materials or a combination system of Ti / Al / Ni / Au materials; The drain electrode is a Ti / Al material system or a Ti / Al / Ni / Au material system.

9. The short-circuit protection method for the P-GaN gate enhanced GaN+HEMT device according to claim 1, characterized in that The gate electrode includes a gate Schottky electrode made of Schottky metal; The gate Schottky electrode is a TiN / Al material system or a Ni / Au material system.

10. The short-circuit protection method for the P-GaN gate-enhanced GaN+HEMT device according to claim 1, wherein, Selectively depositing in the reserved gate metal region to obtain multiple segments of SCP gates spaced apart from each other, specifically including: By selectively depositing in the gate metal region, a whole strip of gate metal is segmented to different extents, and partial conduction under gate control is performed to obtain the SCP gate.

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