Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof, and relates to the field of integrated circuits. According to the manufacturing method disclosed by the invention, after the gate dielectric layer is formed, the protective layer is formed on the first region, then the metal oxide layer is formed, the metal oxide layer is in contact with the gate dielectric layer of the second region and is separated from the gate dielectric layer of the first region through the protective layer, and elements in the metal oxide layer are introduced into the gate dielectric layer of the second region through heat treatment; and the protection layer can reduce elements in the metal oxide layer introduced into the gate dielectric layer in the first region, so that the performance of the device in the first region is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technologies, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of Complementary Metal Oxide Semiconductor (CMOS) technology, the thickness of the gate dielectric layer has been continuously reduced and the gate length has been continuously shrunk. The quantum tunneling effect has become more and more significant, and the depletion effect of the polysilicon gate has also become more and more serious. The silicon dioxide gate dielectric and polysilicon gate transistors have gradually approached their physical limits.

[0003] The semiconductor field has introduced High-K Metal Gate (HKMG) technology. By replacing the silicon dioxide gate dielectric with a high-K dielectric material and using a metal gate instead of a polysilicon gate, the gate leakage current can be improved, the gate control ability can be enhanced, and the carrier mobility can be increased.

[0004] During the manufacturing process of HKMG technology, especially when forming the gate structures of NMOS devices and PMOS devices simultaneously, due to the differences in the structures of NMOS devices and PMOS devices, these differences increase the complexity and difficulty in the device preparation process. Summary of the Invention

[0005] Based on this, it is necessary to provide a semiconductor structure and a manufacturing method thereof for the problems in the prior art.

[0006] In a first aspect, the present disclosure provides a manufacturing method of a semiconductor structure, including:

[0007] Providing a substrate, where the substrate includes a first region and a second region;

[0008] Forming a gate dielectric layer on the substrate;

[0009] Forming a protective layer on the gate dielectric layer in the first region;

[0010] Forming a metal oxide layer on the gate dielectric layer and extending onto the protective layer;

[0011] Performing a heat treatment process to introduce elements in the metal oxide layer into the gate dielectric layer in the second region;

[0012] Removing at least a part of the protective layer.

[0013] Optionally, after performing the heat treatment process, it further includes:

[0014] Remove the remaining metal oxide layer;

[0015] Deposit a conductive layer on the gate dielectric layer after the heat treatment process and on the remaining protective layer.

[0016] Optionally, the protective layer includes a barrier layer and a mask layer, and the material of the barrier layer is the same as that of the conductive layer; at least partially removing the protective layer is to remove the mask layer.

[0017] Optionally, after forming the metal oxide layer, the metal oxide layer also covers the side surfaces of the protective layer.

[0018] Optionally, the gate dielectric layer includes an insulating dielectric layer and a high-k dielectric layer;

[0019] Elements in the metal oxide layer are introduced into the high-k dielectric layer located in the second region.

[0020] Optionally, the first region is a PMOS region and the second region is an NMOS region.

[0021] Optionally, before forming the gate dielectric layer, it further includes: forming a stress adjustment layer on the first region, and the stress adjustment layer is in direct contact with the substrate of the first region.

[0022] In a second aspect, the present application provides a semiconductor structure, including:

[0023] A substrate, the substrate including a first region and a second region;

[0024] A first gate structure disposed in the first region, the first gate structure including a stacked stress adjustment layer, a gate dielectric layer, a barrier layer, and a conductive layer;

[0025] A second gate structure disposed in the second region, the second gate structure including a gate dielectric layer and a conductive layer stacked on the second region, wherein elements of the metal oxide layer are included in the gate dielectric layer of the second gate structure.

[0026] Optionally, the first region is a PMOS region and the second region is an NMOS region.

[0027] Optionally, the substrate includes an active region and an isolation structure disposed adjacent to the active region;

[0028] The first gate structure extends to the isolation structure;

[0029] Alternatively, the second gate structure extends to the isolation structure.

[0030] In a third aspect, the present application provides a semiconductor structure, including:

[0031] Substrate;

[0032] A first gate structure located on the substrate, the first gate structure comprising:

[0033] A gate dielectric layer, comprising:

[0034] A first part that is in direct contact with the substrate;

[0035] A second part located on one side of the first part, the top surface of the second part being higher than the top surface of the first part;

[0036] A metal doped layer located on the first part and in contact with the side surface of the second part.

[0037] Optionally, the first gate structure further comprises a barrier layer located on the gate dielectric layer.

[0038] Optionally, the barrier layer further extends onto the metal doped layer.

[0039] Optionally, the first gate structure further comprises:

[0040] A conductive layer covering the metal doped layer, the conductive layer comprising a stepped bottom surface.

[0041] Optionally, the first gate structure further comprises:

[0042] A conductive layer covering at least a part of the surface of the metal doped layer, the top surface and the side walls of the barrier layer, the conductive layer comprising a stepped bottom surface.

[0043] Optionally, the first part comprises an insulating dielectric layer; the second part comprises an insulating dielectric layer and a high-k dielectric layer stacked in sequence from bottom to top.

[0044] Optionally, the metal doped layer comprises:

[0045] A horizontal part, the upper surface of the horizontal part not being higher than the upper surface of the high-k dielectric layer in a direction perpendicular to the substrate;

[0046] A protruding part located above the horizontal part, the upper surface of the protruding part not being lower than the upper surface of the high-k dielectric layer in a direction perpendicular to the substrate.

[0047] Optionally, further comprising:

[0048] A second gate structure, the second gate structure comprising the metal doped layer.

[0049] Optionally, the metal-doped layer comprises the same material as the high-k dielectric layer.

[0050] Optionally, the metal-doped layer is formed by doping a metal into a high-k material, the high-k material being selected from at least one of hafnium silicate, hafnium silicon oxynitride, and hafnium dioxide, and the metal being selected from at least one of lanthanum, aluminum, and tantalum.

[0051] Optionally, the substrate comprises an active region and an isolation structure disposed adjacent to the active region;

[0052] The first gate structure is disposed on the active region and extends to the isolation structure.

[0053] Optionally, the substrate comprises a PMOS region and an NMOS region; the first gate structure overlaps the active region in the PMOS region and extends onto the isolation structure.

[0054] In an embodiment of the semiconductor structure and its manufacturing method of the present disclosure, after forming a gate dielectric layer, a protective layer is formed on a first region, and then a metal oxide layer is formed. The metal oxide layer contacts the gate dielectric layer in a second region and is separated from the gate dielectric layer in the first region by the protective layer. Elements in the metal oxide layer are introduced into the gate dielectric layer in the second region through heat treatment to form a high-k gate dielectric layer for the device in the second region. The protective layer can reduce the introduction of elements in the metal oxide layer into the gate dielectric layer in the first region and improve the device performance in the first region. Description of the Drawings

[0055] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0056] Figure 1 It is a process flow chart of a manufacturing method of a semiconductor structure provided in an embodiment;

[0057] Figure 2 It is a schematic structural diagram after forming a gate dielectric layer and a barrier layer on a substrate in an embodiment;

[0058] Figure 3 It is a schematic structural diagram after forming a mask layer and a pattern layer in an embodiment;

[0059] Figure 4 It is a schematic structural diagram after etching away the mask layer in the second region according to the pattern layer in an embodiment;

[0060] Figure 5Schematic diagram of the structure after forming a protective layer in some embodiments;

[0061] Figure 6 Schematic diagram of the structure after forming a metal oxide layer in an embodiment;

[0062] Figure 7 Schematic diagram of the structure after heat treatment to form a metal-doped layer in the second region in an embodiment;

[0063] Figure 8 Schematic diagram of the structure after removing the remaining metal oxide layer in an embodiment;

[0064] Figure 9 Schematic diagram of the structure after removing the mask layer of the protective layer in an embodiment;

[0065] Figure 10 Schematic diagram of the structure after forming a conductive layer in an embodiment;

[0066] Figure 11 Schematic diagram of a semiconductor structure formed in an embodiment;

[0067] Figure 12a Schematic diagram of a semiconductor structure formed in another embodiment;

[0068] Figure 12b For Figure 12a Local enlarged view of region A in

[0069] Figure 13 Schematic diagram of the structure after forming a metal oxide layer in another embodiment;

[0070] Figure 14 Schematic diagram of the structure after heat treatment to form a metal-doped layer in the second region in another embodiment;

[0071] Figure 15 Schematic diagram of the structure after forming a conductive layer in another embodiment;

[0072] Figure 16 Schematic diagram of a semiconductor structure formed in another embodiment;

[0073] Figure 17 Schematic diagram of a semiconductor structure formed in yet another embodiment.

[0074] Explanation of reference numerals:

[0075] 10. Substrate; 11. Active region; 12. Isolation structure; 20. Gate dielectric layer; 201. First part; 202. Second part; 21. Insulating dielectric layer; 22. High-k dielectric layer; 30. Protective layer; 31. Barrier layer; 32. Mask layer; 41. Metal oxide layer; 40. Metal doped layer; 401. Horizontal part; 402. Protruding part; 50. Conductive layer; 70. Pattern layer; 110. First gate structure; 210. Second gate structure;

[0076] A1. First region; A2. Second region; 81. Isolation material layer; 82. Insulating sidewall; CT1. First contact plug; CT2. Second contact plug; CT3. Third contact plug; CT4. Fourth contact plug; 90. Interlayer dielectric layer. Detailed implementation manners

[0077] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0078] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0079] In the High-K Metal Gate (HKMG) technology, when depositing the high-k dielectric gate dielectric layer of NMOS in the NMOS region, it will also be deposited on the PMOS region. Therefore, it is necessary to remove the high-k dielectric gate dielectric layer of NMOS located on the PMOS region. The high-k dielectric gate dielectric layer of NMOS can adopt a lanthanum oxide metal layer. The lanthanum oxide metal layer will hydrolyze when encountering water, and the high-k dielectric gate dielectric layer of NMOS is usually deposited very thinly. If a photoresist is directly formed on the lanthanum oxide metal layer to define the NMOS region and the PMOS region, during the subsequent process of removing the photoresist, the lanthanum oxide metal layer in the NMOS region may be damaged, affecting the performance of the NMOS device.

[0080] According to an exemplary embodiment, the present embodiment provides a method for manufacturing a semiconductor structure, as Figure 1 shows a process flow chart of the method for manufacturing the semiconductor structure of the present embodiment, as Figure 1 shown, the method for manufacturing the semiconductor structure includes the following steps:

[0081] Step S101: Provide a substrate 10, where the substrate 10 includes a first region A1 and a second region A2.

[0082] Step S102: Form a gate dielectric layer 20 on the substrate 10.

[0083] Step S103: Form a protective layer 30 on the gate dielectric layer 20 in the first region A1.

[0084] Step S104: Form a metal oxide layer 41 on the gate dielectric layer 20 and extend it onto the protective layer 30.

[0085] Step S105: Perform a heat treatment process to introduce elements in the metal oxide layer 41 into the gate dielectric layer 20 in the second region A2.

[0086] Step S106: Remove at least part of the protective layer 30.

[0087] For the semiconductor structure and its manufacturing method of this embodiment, after forming the gate dielectric layer 20, by forming the protective layer 30 on the first region A1 and then forming the metal oxide layer 41, the metal oxide layer 41 is made to contact the gate dielectric layer 20 in the second region A2, and the metal oxide layer 41 is separated from the gate dielectric layer 20 in the first region A1 by the protective layer 30. Then, through the heat treatment process, elements in the metal oxide layer 41 are introduced into the gate dielectric layer 20 in the second region A2 to form a high-k gate dielectric layer with doped elements in the second region A2. The protective layer 30 can reduce the introduction of elements in the metal oxide layer 41 into the gate dielectric layer 20 in the first region A1 and improve the device performance of the first region A1.

[0088] In this embodiment, the metal oxide layer 41 is first formed, and then immediately followed by the heat treatment process to introduce elements in the metal oxide layer 41 into the gate dielectric layer 20 in the second region A2. Then, the remaining metal oxide layer 41 in the first region A1 is removed. In this way, since the heat treatment process is executed immediately after forming the metal oxide layer 41, during the process of removing the metal oxide layer 41 in the first region A1, elements in the metal oxide layer 41 in the second region A2 have been introduced into the gate dielectric layer 20 in the second region A2, which can reduce the damage to the metal oxide layer 41 in the second region A2 and is beneficial to improving the performance of the semiconductor structure.

[0089] Next, each step of the manufacturing method of the semiconductor structure of this exemplary embodiment will be described in detail.

[0090] In step S101, as Figure 2As shown, the substrate 10 may be a semiconductor substrate, and the material of the semiconductor substrate may include silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), or other III / V semiconductor materials or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate may be a layered substrate including, such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0091] The substrate 10 includes an active region 11 and an isolation structure 12 disposed adjacent to the active region 11. The isolation structure 12 may include a first isolation layer (not shown in the figure) and a second isolation layer (not shown in the figure). The first isolation layer covers the sidewalls of the isolation trench, and the second isolation layer covers the first isolation layer and fills the isolation trench. Exemplarily, the material of the first isolation layer may include silicon oxide, and the material of the second isolation layer may include silicon nitride.

[0092] The substrate 10 includes a first region A1 and a second region A2. In some embodiments, the first region A1 is a PMOS region, and the active region 11 of the first region A1 has a P-type doping type. The active region 11 of the first region A1 is doped with P-type doping ions, such as group III ions such as boron (B) ions, aluminum (Al) ions, gallium (Ga) ions, or indium (In) ions. The second region A2 is an NMOS region, and the active region 11 of the second region A2 has an N-type doping type. The active region 11 of the second region A2 is doped with N-type doping ions, such as group V ions such as phosphorus (P) ions, bismuth (Bi) ions, antimony (Sb) ions, or arsenic (As) ions. The P-type doping ions may be group III ions such as boron (B) ions, aluminum (Al) ions, gallium (Ga) ions, or indium (In) ions.

[0093] In step S102, as Figure 2 shown, a gate dielectric layer 20 is formed on the substrate 10, and the gate dielectric layer 20 covers the top surface of the substrate 10. The gate dielectric layer 20 may include a single-layer structure or a multi-layer structure. Exemplarily, the gate dielectric layer 20 may be formed by an atomic layer deposition (ALD) process.

[0094] In step S103, referring to Figures 2 - 5 shown, a protective layer 30 covers the top surface of the gate dielectric layer 20 in the first region A1, and exposes the top surface of the gate dielectric layer 20 in the second region A2. The protective layer 30 may include a single-layer structure or a multi-layer structure. The protective layer 30 is used to isolate the metal oxide layer 41 from the gate dielectric layer 20 in the first region A1, and reduce the introduction of elements in the metal oxide layer 41 into the gate dielectric layer 20 in the first region A1.

[0095] In step S104, as Figure 6As shown, any one of Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), and Physical Vapor Deposition (PVD) can be used to deposit and form a metal oxide layer 41. The metal oxide layer 41 covers the upper surface of the gate dielectric layer 20 in the second region A2, and covers the top surface and sidewalls of the protective layer 30. Exemplarily, the material of the metal oxide layer 41 may include at least one of lanthanum oxide (La2O3), aluminum oxide (AlO), and tantalum oxide (TaO), and preferably lanthanum oxide (La2O3).

[0096] In step S105, as Figure 7 shown, a heat treatment process is performed to introduce an element in the metal oxide layer 41 into the gate dielectric layer 20 in the second region A2. This element may be a metal element, such as lanthanum (La), to form a metal-doped layer 40 in the second region A2. The metal-doped layer 40 serves as the high-K gate dielectric layer of the NMOS device, that is, the metal-doped layer 40 is obtained by introducing the element lanthanum (La) into the gate dielectric layer 20. The protective layer 30 is used to prevent the elements in the metal oxide layer 41 from diffusing into the gate dielectric layer 20 in the first region A1, which is beneficial to improving the performance of the PMOS device and enhancing the performance of the semiconductor structure.

[0097] In step S106, as Figure 8 、 Figure 9 shown, at least a part of the protective layer 30 on the first region A1 is etched away to remove the film layer that may introduce the metal oxide layer 41 on the first region A1, and reduce the elements of the metal oxide layer 41 remaining on the first region A1. Exemplarily, at least a part of the protective layer 30 on the first region A1 and the remaining metal oxide layer 41 on the protective layer 30 can be removed by dry etching.

[0098] According to an exemplary embodiment, the method for manufacturing the semiconductor structure of this embodiment includes the following steps:

[0099] Please refer to Figures 2 - 11, a substrate 10 is provided. The substrate 10 includes an active region 11 and an isolation structure 12 disposed adjacent to the active region 11; the substrate 10 has a first region A1 and a second region A2. Among them, the first region A1 can be a PMOS region, and the second region A2 can be an NMOS region. An insulating dielectric layer 21, a high-k dielectric layer 22, a barrier layer 31, and a mask layer 32 are sequentially formed on the substrate 10. A pattern layer 70 is formed on the mask layer 32 located in the PMOS region. The pattern layer 70 can be a photo-etching material, and a bottom anti-reflection coating (BARC) can be selectively included below the pattern layer 70. The mask layer 32 located in the NMOS region is removed by using the pattern layer 70; then the barrier layer 31 in the NMOS region and the pattern layer 70 in the PMOS region are removed. The remaining barrier layer 31 and the remaining mask layer 32 serve as a protective layer 30 for the high-k dielectric layer in the PMOS region. A metal oxide layer 41 is formed on the gate dielectric layer 20. The metal oxide layer 41 also covers the side surfaces of the protective layer 30 and extends onto the protective layer 30. The metal oxide layer 41 can be lanthanum oxide (La2O3). A heat treatment process is performed to introduce the lanthanum element in the metal oxide layer 41 into the high-k dielectric layer 22 located in the NMOS region to form a metal-doped layer 40 in the NMOS region, that is, the metal-doped layer 40 is obtained by introducing the element lanthanum (La) into the high-k dielectric layer 22; the remaining metal oxide layer 41 and the remaining mask layer 32 are removed by using a dry etching or wet etching process; then a conductive layer 50 can be formed by using a metal organic chemical vapor deposition, atomic layer deposition, or physical vapor deposition process. The conductive layer 50 is located on the metal-doped layer 40 and the remaining barrier layer 31. The material of the barrier layer 31 is the same as the material included in the conductive layer 50, such as titanium nitride, tungsten. The conductive layer 50 can be a single layer or multiple layers. A mask pattern layer (not shown in the figure) is formed on the conductive layer 50. According to the pattern of the mask pattern layer, the stack on the substrate 10 can be patterned to form a first gate structure 110 in the PMOS region and a second gate structure 210 in the NMOS region.

[0100] Exemplarily, the material of the barrier layer 31 can also include at least one of titanium, tantalum, or tantalum nitride. Exemplarily, the material of the mask layer 32 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the metal oxide layer 41 can include at least one of lanthanum oxide (La2O3), aluminum oxide (AlO), and tantalum oxide (TaO). Exemplarily, the material of the insulating dielectric layer 21 can include at least one of silicon dioxide or silicon oxynitride. Exemplarily, the material of the high-k dielectric layer 22 can include hafnium silicate (HfSiO x)、at least one of hafnium silicon oxynitride (HfSiON), hafnium silicate oxide compound (HfSiO4), or hafnium dioxide (HfO2). In this embodiment, the material of the high-k dielectric layer 22 includes hafnium silicate. The high dielectric constant of hafnium silicate can reduce the influence of the gate voltage on the substrate 10 and reduce the gate-induced drain current effect of the PMOS device.

[0101] For the manufacturing method of the semiconductor structure of this embodiment, by protecting the high-k dielectric layer 22 in the PMOS region through the protection layer 30, the pollution of the PMOS region by lanthanum elements can be reduced; by introducing the elements in the metal oxide layer 41 into the high-k dielectric layer 22 in the NMOS region through a heat treatment process, a metal-doped layer 40 is formed in the NMOS region as the high-k gate dielectric layer of the NMOS device, improving the performance of the high-k gate dielectric layer of the NMOS device.

[0102] In this embodiment, when removing the remaining metal oxide layer 41 located in the PMOS region, the lanthanum elements in the metal oxide layer 41 located in the NMOS region have been introduced into the gate dielectric layer 20 located in the NMOS region, which can reduce the damage to the metal oxide layer 41 in the NMOS region, that is, the metal-doped layer 40 in the NMOS region will not be affected, which is beneficial to improving the performance of the semiconductor structure. The barrier layer 31 is used to block the diffusion of the lanthanum elements in the metal oxide layer 41 into the high-k dielectric layer 22 in the PMOS region. The mask layer 32 is used as a hard mask during the etching of the barrier layer 31 and is also used to block the diffusion of the elements in the metal oxide layer 41 into the barrier layer 31, reducing the diffusion of the elements in the metal oxide layer 41 into the barrier layer 31.

[0103] The following will describe different embodiments of the present invention. For simplicity of description, the following description mainly details the different parts of each embodiment and will not repeat the same parts. In addition, the same components in the embodiments of the present invention are labeled with the same reference numerals for convenient comparison between the embodiments.

[0104] The manufacturing method of the semiconductor structure of this embodiment further includes the following steps: forming a stress adjustment layer 61 on the first region A1 of the substrate 10. The stress adjustment layer 61 is sandwiched between the insulating dielectric layer 21 and the substrate 10 and is in direct contact with the insulating dielectric layer 21 and the substrate 10. The first region A1 can be the PMOS region, and the second region A2 is the NMOS region. The stress adjustment layer 61 is used to adjust the stress of the substrate 10 in the PMOS region. The material of the stress adjustment layer 61 is germanium silicon. Germanium has a higher carrier mobility, and the lattice constant of germanium silicon is greater than that of silicon. The substrate 10 applies compressive stress to the stress adjustment layer 61, and this compressive stress can increase the mobility of the carriers (electrons or holes) in the stress adjustment layer 61, which is beneficial to improving the drive current and response speed of the PMOS device.

[0105] Since the stress adjustment layer 61 of this embodiment is only formed in the PMOS region, there will be a height difference in the gate dielectric layer 20 subsequently formed on the substrate. The top surface of the gate dielectric layer 20 located in the PMOS region is higher than the top surface of the gate dielectric layer 20 located in the NMOS region in the direction perpendicular to the substrate 10. Refer to Figure 6 As shown, the top surface of the metal oxide layer 41 located in the NMOS region is higher than the top surface of the high-k dielectric layer 22 located in the PMOS region, and the metal oxide layer 41 covers a part of the top surface, the side surface of the high-k dielectric layer 22, and the side surface and the top surface of the protective layer 30. The top surface of the high-k dielectric layer 22 located in the NMOS region is higher than the top surface of the insulating dielectric layer 21 located in the PMOS region in the direction perpendicular to the substrate 10. Please refer to Figure 7 , after the heat treatment process, a metal doped layer 40 is formed. The metal doped layer 40 has a protrusion 402 higher than the top surface of the high-k dielectric layer 22 and a horizontal portion 401 lower than the top surface of the high-k dielectric layer 22.

[0106] In some other embodiments, the difference between this embodiment and the above embodiments is that, refer to Figure 13 As shown, the top surface of the metal oxide layer 41 located in the NMOS region is not higher than the top surface of the high-k dielectric layer 22 located in the PMOS region. The top surface of the high-k dielectric layer 22 located in the NMOS region is not higher than the top surface of the insulating dielectric layer 21 located in the PMOS region in the direction perpendicular to the substrate 10. After the heat treatment process, a metal doped layer 40 is formed. Refer to Figure 14 As shown, the metal doped layer 40 has a protrusion 402 not higher than the top surface of the high-k dielectric layer 22 and a horizontal portion 401 lower than the top surface of the high-k dielectric layer 22. The aforementioned "not higher than" includes "lower than or equal to".

[0107] The present disclosure also provides a semiconductor structure. Refer to Figure 11, the semiconductor structure includes a substrate 10, which includes an active region 11 and an isolation structure 12 disposed adjacent to the active region 11. The substrate 10 includes a first region A1 and a second region A2. A first gate structure 110 is disposed in the first region A1 and overlaps with the active region 11 located in the first region A1. The first gate structure 110 includes a stacked stress adjustment layer 61, a gate dielectric layer 20, a barrier layer 31, and a conductive layer 50. A second gate structure 210 is disposed in the second region A2 and overlaps with the active region 11 located in the second region A2. The second gate structure 210 includes a gate dielectric layer 20 and a conductive layer 50 stacked on the second region A2, wherein the gate dielectric layer 20 of the second gate structure 210 includes elements of a metal oxide layer 41. The gate dielectric layer 20 of the first gate structure 110 includes an insulating dielectric layer 21 and a high-k dielectric layer 22 stacked in sequence on the stress adjustment layer 61. The gate dielectric layer 20 of the second gate structure 110 includes an insulating dielectric layer 21 on the substrate 10 of the second region A2 and a metal doped layer 40, and the metal doped layer 40 is obtained by introducing elements from the metal oxide layer 40 into the high-k dielectric layer 22.

[0108] The material of the metal oxide layer 41 may include at least one of lanthanum oxide (La2O3), aluminum oxide (AlO), and tantalum oxide (TaO); preferably lanthanum oxide (La2O3), and the metal doped layer 40 is obtained by introducing lanthanum from the metal oxide layer 40 into the high-k dielectric layer 22. The material of the stress adjustment layer 61 of the first gate structure 110 includes germanium silicon. The material of the insulating dielectric layer 21 includes at least one of silicon dioxide or silicon oxynitride. The high-k dielectric layer 22 includes at least one of tantalum oxide, hafnium oxide, hafnium silicon oxynitride (HfSiON), yttrium oxide, zirconium dioxide, strontium titanate, or zirconium silicate oxide compound. The material of the metal doped layer 40 may include lanthanum-doped hafnium silicon oxynitride (HfSiON). The material of the barrier layer 31 is the same as the material of the conductive layer 50, and the material of the barrier layer 31 includes at least one of titanium, titanium nitride, tantalum, or tantalum nitride. The first region is a PMOS region, and the second region is an NMOS region.

[0109] It can be understood that during the process of fabricating the semiconductor structure, the film layer at the junction of the NMOS region and the PMOS region may be etched and retained for forming the first gate structure 110 or for forming the second gate structure 210. This results in the film layer arrangement of the first gate structure 110 at the junction of the NMOS region and the PMOS region being different from that of other first gate structures 110, or the film layer arrangement of the second gate structure 210 at the junction of the NMOS region and the PMOS region being different from that of other second gate structures 210.

[0110] Refer to Figure 11, during the process of fabricating a semiconductor structure, after forming a first gate structure 110 and a second gate structure 120, it further includes the steps of forming an isolation material layer 81 and forming an insulating sidewall 82. The isolation material layer 81 covers the surfaces of the first gate structure 110 and the second gate structure 120, and the insulating sidewall 82 covers the isolation material layer 81. Exemplarily, the material of the isolation material layer 81 may include silicon oxide; the material of the insulating sidewall 82 may include silicon nitride. The isolation material layer 81 and the insulating sidewall 82 are used to protect the first gate structure 110 and the second gate structure 210, reducing the risk of device-to-device short circuit.

[0111] After forming the isolation material layer 81 and the insulating sidewall 82, the steps of doping the substrate 10 on both sides of the first gate structure 110 to form a first source region (not shown in the figure) and a first drain region (not shown in the figure), and doping the substrate 10 on both sides of the second gate structure 120 to form a second source region (not shown in the figure) and a second drain region (not shown in the figure). Then, a interlayer dielectric layer 90 is deposited. The interlayer dielectric layer 90 covers the first gate structure 110 and the second gate structure 210 and fills the space between the first gate structure 110 and the second gate structure 210. Exemplarily, the material of the interlayer dielectric layer 90 may include silicon oxide. Subsequently, a first contact plug CT1 and a second contact plug CT2 are formed on both sides of the first gate structure 110. One of the first contact plug CT1 and the second contact plug CT2 passes through the interlayer dielectric layer 90 to contact and connect with the first source region for leading out the first source region, and the other passes through the interlayer dielectric layer 90 to contact and connect with the first drain region for leading out the first drain region; a third contact plug CT3 and a fourth contact plug CT4 are formed on both sides of the second gate structure 210. One of the third contact plug CT3 and the fourth contact plug CT4 passes through the interlayer dielectric layer 90 to contact and connect with the second source region for leading out the second source region, and the other passes through the interlayer dielectric layer 90 to contact and connect with the second drain region for leading out the second drain region.

[0112] This disclosure also includes another semiconductor structure. Please refer to Figure 12a , Figure 12b , the semiconductor structure includes a substrate 10, and the substrate 10 includes an active region 11 and an isolation structure 12 disposed adjacent to the active region 11. The semiconductor structure further includes a first gate structure 110 located on the substrate 10. The first gate structure 110 includes a gate dielectric layer 20 and a metal doped layer 40. The gate dielectric layer 20 includes a first portion 201 in direct contact with the substrate 10, and a second portion 202 located on one side of the first portion 201. The top surface of the second portion 202 is higher than the top surface of the first portion 201; the metal doped layer 40 is located on the first portion 201 and contacts the side surface of the second portion 202.

[0113] In some embodiments, please continue to refer to Figure 12a ,Figure 12b Moreover, the first gate structure 110 further includes a barrier layer 31 located on the gate dielectric layer 20. The material of the barrier layer 31 includes at least one of titanium, titanium nitride, tantalum, or tantalum nitride. In some embodiments, the barrier layer 20 also extends onto the metal-doped layer 40.

[0114] In some embodiments, with continued reference to Figure 12a and Figure 12b , the first gate structure 110 further includes a conductive layer 50 covering the metal-doped layer 40, and the conductive layer 40 includes a stepped bottom surface. The material of the conductive layer 50 includes at least one of titanium, titanium nitride, tantalum, or tantalum nitride.

[0115] In other embodiments, with continued reference to Figure 12a and Figure 12b , the first gate structure 110 further includes a conductive layer 50 covering at least a partial surface of the metal-doped layer 40, the top surface and sidewalls of the barrier layer 31, and the conductive layer 50 includes a stepped bottom surface. In this embodiment, the material of the conductive layer 50 is the same as that of the barrier layer 31.

[0116] In some embodiments, with continued reference to Figure 12a and Figure 12b , the first portion 201 includes an insulating dielectric layer 21; the second portion 202 includes the insulating dielectric layer 21 and a high-k dielectric layer 22 stacked in sequence from bottom to top. The material of the insulating dielectric layer 21 includes at least one of silicon dioxide or silicon oxynitride. The high-k dielectric layer 22 includes at least one of tantalum oxide, hafnium oxide, hafnium silicon oxynitride (HfSiON), yttrium oxide, zirconium dioxide, strontium titanate, or zirconium silicate oxide compound.

[0117] In some embodiments, with continued reference to Figure 12a and Figure 12b , the metal-doped layer 40 includes a horizontal portion 401 and a protruding portion 402. The upper surface of the horizontal portion 401 is not higher than the upper surface of the high-k dielectric layer 22 in a direction perpendicular to the substrate 10; the protruding portion 402 is located above the horizontal portion 401, and the upper surface of the protruding portion 402 is not lower than the upper surface of the high-k dielectric layer 22 in a direction perpendicular to the substrate 10.

[0118] In some embodiments, with reference to Figure 11 or Figure 12a and Figure 12b , the semiconductor structure further includes a second gate structure 210, and the second gate structure 210 includes a metal-doped layer 40.

[0119] In some embodiments, the metal-doped layer 40 includes the same material as the high-k dielectric layer 22. The metal-doped layer 40 is obtained by doping a metal into a high-k material (such as doping the high-k dielectric layer 22). The high-k material is selected from at least one of hafnium silicate, hafnium silicon oxynitride, or hafnium dioxide, and the doped metal is selected from at least one of lanthanum, aluminum, and tantalum. Exemplarily, the high-k material may include hafnium silicon oxynitride (HfSiON), the doped metal may be lanthanum (La), and the material of the metal-doped layer 40 may include lanthanum-doped hafnium silicon oxynitride (HfSiON).

[0120] In some embodiments, the substrate 10 includes an active region 11 and an isolation structure 12 disposed adjacent to the active region 11; the first gate structure 110 is disposed on the active region 11 and extends to the isolation structure 12.

[0121] The different embodiments of the present invention will be described below. For the sake of simplicity, the following description mainly details the different parts of each embodiment and will not repeat the same parts. In addition, the same components in the various embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the embodiments.

[0122] In some other embodiments, the difference between this embodiment and the above embodiment is that, referring to Figure 12a 、 Figure 12b the first gate structure 110 overlaps with the active region 11 located in the PMOS region and extends onto the isolation structure 12. The first gate structure 110 includes a metal-doped layer 40. The metal-doped layer 40 is located on the insulating dielectric layer 21 and covers the side surface of the insulating dielectric layer 21. The metal-doped layer 40 is also in direct contact with the high-k dielectric layer 22. The metal-doped layer 40 overlaps with the isolation structure 12 in a direction perpendicular to the substrate 10. The metal-doped layer 40 has a protruding portion 402 higher than the top surface of the high-k dielectric layer 22 and a horizontal portion 401 lower than the top surface of the high-k dielectric layer 22. The metal-doped layer 40 also has a stepped surface. The conductive layer 50 covers the stepped surface of the metal-doped layer, the top surface and the side surface of the barrier layer 31.

[0123] In some other embodiments, the difference between this embodiment and the above embodiment is that, referring to Figure 16 、 Figure 17, the first gate structure 110 overlaps with the active region 11 in the PMOS region and extends onto the isolation structure 12; specifically, the stress adjustment layer 61 overlaps with the active region in the PMOS region, the insulating dielectric layer 21 is located on the stress adjustment layer 61 and covers the side edges of the stress adjustment layer 61, and the bottom surface of the insulating dielectric layer 21 directly contacts the isolation structure. The first gate structure 110 includes a metal doped layer 40, the metal doped layer 40 is located on the insulating dielectric layer 21 and covers the side surfaces of the insulating dielectric layer 21 and the high-k dielectric layer 22. The metal doped layer 40 has a protruding portion 402 higher than the top surface of the high-k dielectric layer 22 and a horizontal portion 401 lower than the top surface of the high-k dielectric layer 22. The barrier layer 31 is located on the high-k dielectric layer 22 and extends to the surface of the protruding portion 402. The metal doped layer 40 also has a stepped surface. The conductive layer 50 covers the stepped surface of the metal doped layer, the top surface and the side surfaces of the barrier layer 31.

[0124] Among them, the semiconductor structure of the above embodiment can be a Dynamic Random Access Memory (DRAM), a Static Random-Access Memory (SRAM), a flash EPROM, a Ferroelectric Random Access Memory (FeRAM), a Magnetic Random-Access Memory (MRAM), or other types of memories.

[0125] According to an exemplary embodiment, this embodiment provides an electronic device including the semiconductor structure in the above embodiment. The electronic device can be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0126] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0127] The above embodiments only represent several implementation manners of the present disclosure. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure patent should be subject to the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that Comprising: Providing a substrate, the substrate including a first region and a second region; Forming a gate dielectric layer on the substrate; Forming a protective layer on the gate dielectric layer in the first region; Forming a metal oxide layer on the gate dielectric layer and extending onto the protective layer; Performing a heat treatment process to introduce elements in the metal oxide layer into the gate dielectric layer in the second region; Removing at least part of the protective layer.

2. The manufacturing method of the semiconductor structure according to claim 1, wherein After performing the heat treatment process, further comprising: Removing the remaining metal oxide layer; Depositing a conductive layer on the gate dielectric layer after the heat treatment process and on the remaining protective layer.

3. The manufacturing method of the semiconductor structure according to claim 2, wherein The protective layer includes a barrier layer and a mask layer, the material of the barrier layer being the same as the material of the conductive layer; removing at least part of the protective layer is removing the mask layer.

4. The method for fabricating a semiconductor structure according to claim 1, wherein, After forming the metal oxide layer, the metal oxide layer also covers the side surfaces of the protective layer.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein The gate dielectric layer includes an insulating dielectric layer and a high-k dielectric layer; Elements in the metal oxide layer are introduced into the high-k dielectric layer in the second region.

6. The method for fabricating a semiconductor structure according to claim 1, wherein The first region is a PMOS region and the second region is an NMOS region.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein, Before forming the gate dielectric layer, further comprising: forming a stress adjustment layer on the first region, the stress adjustment layer being in direct contact with the substrate in the first region.

8. A semiconductor structure, characterized in that, Comprising: A substrate, the substrate including a first region and a second region; A first gate structure disposed in the first region, the first gate structure including a stacked stress adjustment layer, gate dielectric layer, barrier layer, and conductive layer; A second gate structure disposed in the second region, the second gate structure including a gate dielectric layer and a conductive layer stacked on the second region, wherein elements of the metal oxide layer are included in the gate dielectric layer of the second gate structure.

9. The semiconductor structure according to claim 8, wherein The first region is a PMOS region and the second region is an NMOS region.

10. The semiconductor structure according to claim 8, wherein The substrate includes an active region and an isolation structure disposed adjacent to the active region; The first gate structure extends to the isolation structure; Alternatively, the second gate structure extends to the isolation structure.

11. A semiconductor structure, characterized in that, Comprising: A substrate; A first gate structure on the substrate, the first gate structure including: A gate dielectric layer including: A first portion in direct contact with the substrate; A second portion on one side of the first portion, the top surface of the second portion being higher than the top surface of the first portion; A metal doped layer on the first portion and contacting the side surface of the second portion.

12. The semiconductor structure according to claim 11, wherein The first gate structure further includes a barrier layer on the gate dielectric layer.

13. The semiconductor structure according to claim 12, wherein, The barrier layer also extends onto the metal doped layer.

14. The semiconductor structure according to claim 11, wherein, The first gate structure further includes: A conductive layer covering the metal doped layer, the conductive layer including a stepped bottom surface.

15. The semiconductor structure according to claim 12, wherein The first gate structure further includes: A conductive layer covering at least part of the surface of the metal doped layer, the top surface and sidewalls of the barrier layer, the conductive layer including a stepped bottom surface.

16. The semiconductor structure according to claim 11, wherein, The first part includes an insulating dielectric layer; the second part includes an insulating dielectric layer and a high-k dielectric layer stacked in sequence from bottom to top.

17. The semiconductor structure according to claim 16, wherein, The metal-doped layer includes: a horizontal portion, the upper surface of the horizontal portion not being higher than the upper surface of the high-k dielectric layer in a direction perpendicular to the substrate; a protruding portion located above the horizontal portion, the upper surface of the protruding portion not being lower than the upper surface of the high-k dielectric layer in a direction perpendicular to the substrate.

18. The semiconductor structure according to claim 11, wherein, It further includes: a second gate structure, the second gate structure including the metal-doped layer.

19. The semiconductor structure according to claim 16, wherein, The metal-doped layer is made of the same material as the high-k dielectric layer.

20. The semiconductor structure according to claim 11, wherein The metal-doped layer is formed by doping a metal in a high-k material, the high-k material being selected from at least one of hafnium silicate, hafnium silicon oxynitride, or hafnium dioxide, and the metal being selected from at least one of lanthanum, aluminum, or tantalum.

21. The semiconductor structure according to claim 11, wherein, The substrate includes an active region and an isolation structure disposed adjacent to the active region; The first gate structure is disposed on the active region and extends to the isolation structure.

22. The semiconductor structure according to claim 21, wherein, The substrate includes a PMOS region and an NMOS region; the first gate structure overlaps with the active region located in the PMOS region and extends onto the isolation structure.

Images