Composite Darlington transistor device structure and manufacturing method thereof
Through the composite Darlington transistor device structure, the two-stage current gain and conductance modulation effects of parasitic NPN and PNP transistors are used to solve the on-resistance and switching speed problems of traditional LDMOS and Darlington transistors, and high-efficiency energy conversion in high-frequency and high-voltage applications are achieved.
Patent Information
- Application Number
- CN202510512664.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-23
- Publication Date
- 2025-07-25
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Traditional LDMOS devices have a restrictive relationship between on-resistance and breakdown voltage, and traditional Darlington transistors have slow switching speed and high power consumption, which limits their application in high-frequency circuits.
A composite Darlington transistor device structure is designed to form a two-stage current gain through parasitic NPN and PNP transistors, combined with the conductance modulation effect, reduce the on-resistance and enhance the current capability.
It achieves high input impedance, low on-resistance and high current density, suitable for high frequency circuits and high voltage applications, and is compatible with standard BCD processes.
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Figure CN120379334A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of power semiconductor devices, and particularly to a composite Darlington transistor device structure and a manufacturing method thereof. Background Art
[0002] With the continuous progress of modern electronic technology and the field of automation control, power semiconductor devices are continuously evolving towards miniaturization and integration. In multiple fields such as power electronics, automotive electronics, and renewable energy, power semiconductor devices are increasingly widely used and have become an important technical pillar for the development of various industries. However, with the improvement of device integration and the continuous reduction of size, traditional power semiconductor devices face increasingly severe challenges in terms of switching characteristics, heat dissipation performance, and current capacity. Therefore, designing planar semiconductor power devices with high current density and low on-resistance is of great significance for improving energy conversion efficiency and chip integration.
[0003] Currently, the traditional laterally diffused metal oxide semiconductor transistor (LDMOS), as the most widely used power semiconductor device, still has certain limitations in practical applications. The on-resistance and breakdown voltage of LDMOS are closely related to the thickness of the drift region and have a restrictive relationship. Increasing the thickness of the drift region can improve the breakdown voltage of LDMOS. However, a thicker drift region will result in a higher on-resistance. In addition, as a unipolar device in which majority carriers participate in conduction, LDMOS discharges through the surface channel and has a weak current capacity. To achieve a high current gain, researchers proposed the traditional Darlington transistor by combining two bipolar transistors, and its amplification factor is the product of the amplification factors of the two triodes. However, as a current-controlled device, the traditional Darlington transistor has a slow switching speed, which limits its application in high-frequency circuits. In addition, due to the high saturation voltage drop and large input capacitance, the traditional Darlington transistor has a high power consumption.
[0004] The device structure and equivalent circuit of the traditional LDMOS are as Figure 1As shown in the figure. When the anode is connected to a high potential, the cathode is grounded, and the gate voltage is higher than the threshold voltage, the gate and P-Sub, PW are equivalent to a parallel plate capacitor with silicon dioxide as the dielectric. Under the action of the gate voltage, a vertical electric field pointing from the gate to the substrate is formed in the dielectric. This electric field repels holes and attracts electrons. Therefore, the holes in P-Sub and PW under the gate are repelled, leaving immobile acceptor ions. At the same time, the minority electrons in P-Sub and PW are attracted to the area under the gate, forming an N-type conductive channel connecting the N-Drift region and the cathode N+. Under the action of the anode voltage, the electrons in the cathode N+ flow through the N-type conductive channel to the N-Drift region, forming a MOS current. However, while ensuring the breakdown voltage of the device, the wide drift region of the LDMOS increases the resistance of the current path through this region, and the large on-state voltage drop limits its current capacity and high-power applications. Summary of the Invention
[0005] To solve the above technical problems, based on the research on LDMOS and traditional Darlington transistors, the present invention proposes a composite Darlington transistor device structure with a simple hierarchy, high input impedance, strong current capacity, and low on-resistance, and provides a manufacturing method thereof.
[0006] The technical solution of the present invention to solve the above problems is: a composite Darlington transistor device structure, characterized in that it includes a substrate P-Sub; first to second N-Drift regions are provided in the substrate P-Sub; a first NW region, a first PW region, and a second NW region are provided above the N-Drift region; a first field oxide isolation region, a first N+ implantation region, a second field oxide isolation region, a first polysilicon gate, a second N+ implantation region, a first P+ implantation region, a third field oxide isolation region, a second P+ implantation region, a third N+ implantation region, a second polysilicon gate, a fourth field oxide isolation region, a third P+ implantation region, and a fifth field oxide isolation region are provided above the NW region and the PW region in sequence from left to right. The first N+ implantation region is provided in the first NW region; the second N+ implantation region, the first P+ implantation region, the second P+ implantation region, and the third N+ implantation region are provided in the first PW region; the third P+ implantation region is provided in the second NW region. The first N+ implantation region and the third P+ implantation region are connected as the anode of the device; the second P+ implantation region and the third N+ implantation region are connected as the cathode of the device; the first polysilicon gate and the second polysilicon gate are connected as the gate of the device.
[0007] In the above composite Darlington transistor device structure, when the anode of the device is connected to a high potential, the cathode is grounded, and the gate voltage is greater than the threshold voltage of the MOSFET, the device operates in the forward conduction mode. Under the action of the gate voltage, a strong inversion layer is formed in the channel regions under the first polysilicon gate and the second polysilicon gate. The electron channel under the first polysilicon gate connects the first N-Drift region and the second N+ implantation region; the electron channel under the second polysilicon gate connects the third N+ implantation and the second N-Drift region. Since the voltage of the anode is higher than that of the cathode, the electrons in the second N+ implantation region flow through the electron channel under the first polysilicon gate to the first N-Drift region, forming the MOS current I Mn1 . The MOS current I Mn1 flows into the first P+ implantation region and the first PW region through the third metal layer of metal layer 1, the fourth metal layer of metal layer 1, the third metal via, and the third metal layer of metal layer 2. The MOS current I Mn1 provides the base current to turn on the parasitic NPN transistor composed of the first N+ implantation region, the first NW region, the first N-Drift region, the first P-Sub region, the first PW region, and the third N+ implantation region. The MOS current I Mn1 is amplified by the current gain of the parasitic NPN transistor. Under the action of the anode voltage, the electrons in the third N+ implantation region flow through the electron channel under the second polysilicon gate to the second N-Drift region to form the MOS current I Mn2 . The MOS current I Mn2 provides the base current to turn on the parasitic PNP transistor composed of the second P+ implantation region, the first PW region, the first P-Sub region, the second N-Drift region, the second NW region, and the third P+ region. The MOS current I Mn2 is amplified by the parasitic PNP transistor to form the first-stage current gain. The collector current of the parasitic PNP transistor further constitutes the base current of the parasitic NPN transistor to turn on the parasitic NPN transistor composed of the first N+ implantation region, the first NW region, the first N-Drift region, the first P-Sub region, the first PW region, and the third N+ implantation region. The collector current of the parasitic PNP transistor is further amplified by the parasitic NPN transistor to form the second-stage current gain. Thus, a composite Darlington transistor device structure is formed, and the MOS current is amplified through the two-stage current gain of the parasitic NPN transistor and PNP transistor, enhancing the current capacity of the device. In addition, when the emitter junction of the parasitic PNP transistor is forward-biased, the third P+ implantation region injects holes into the second N-Drift region to form a conductivity modulation effect, and the conductivity of the drift region is greatly increased, effectively reducing the on-resistance of the device.
[0008] A manufacturing method of a composite Darlington transistor device structure includes the following steps:
[0009] Step 1: Form the first to second N-Drift regions in the substrate P-Sub;
[0010] Step 2: Form the first to fifth field oxide isolation regions on the substrate P-Sub by photolithography;
[0011] Step 3: Form the first to second NW regions in the N-Drift region and the first PW region in the P-Sub by photolithography;
[0012] Step 4: Form the first polysilicon gate between the first NW region and the first PW region, and form the second polysilicon gate between the first PW and the second NW regions;
[0013] Step 5: Form the first P+ implantation region and the second P+ implantation region in the first PW region, and form the third P+ implantation region in the second NW region by photolithography;
[0014] Step 6: Form the first N+ implantation region in the first NW region, and form the second N+ implantation region and the third N+ implantation region in the first PW region by photolithography.
[0015] The technical solution of the present invention to solve the above problems is:
[0016] 1. The present invention constitutes a composite Darlington transistor device structure, which amplifies the MOS current through the two-stage current gain provided by the Darlington structure formed by the parasitic NPN and PNP transistors. The on and off of the device are controlled by changing the polysilicon gate voltage, which has high input impedance, low power consumption and excellent noise performance. Due to the Darlington structure, the device has high current gain and low output impedance, and can amplify weak signals.
[0017] 2. The present invention introduces the conductivity modulation effect, which effectively reduces the on-resistance and forward on-voltage drop of the device. When the voltage drop generated by the MOS current I Mn2 makes the parasitic PNP transistor forward-biased on the second N-Drift region, the third P+ implantation region injects a large number of minority carrier holes into the drift region. To maintain electrical neutrality, a dynamic balance is formed between the minority and majority carrier concentrations in the drift region, and the carrier concentration and conductivity are greatly increased, thereby significantly reducing the on-voltage drop of the device.
[0018] 3. The present invention does not need to introduce additional process steps and is compatible with the standard BCD process. In addition, the device is a bipolar device, and both electrons and holes participate in conduction, so it has a high current density and is suitable for high-efficiency energy conversion in high-voltage application fields. Description of the Drawings
[0019] Figure 1 It is a cross-sectional view and an equivalent circuit schematic diagram of a conventional LDMOS.
[0020] Figure 2 The cross-sectional view and circuit connection diagram of the composite Darlington transistor device structure in the embodiment of the present invention.
[0021] Figure 3 The three-dimensional structure schematic diagram of the composite Darlington transistor device structure in the embodiment of the present invention.
[0022] Figure 4 The equivalent circuit diagram of the composite Darlington transistor device structure in the embodiment of the present invention.
[0023] Figure 5 The top view of the composite Darlington transistor device structure in the embodiment of the present invention. Detailed implementation manners
[0024] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.
[0025] As Figures 2 - 5 shown, a composite Darlington transistor device structure includes a substrate P-Sub; first to second N-Drift regions are provided in the substrate P-Sub; a first NW region, a first PW region and a second NW region are provided above the N-Drift regions; above the NW regions and PW regions, a first field oxide isolation region, a first N+ implantation region, a second field oxide isolation region, a first polysilicon gate, a second N+ implantation region, a first P+ implantation region, a third field oxide isolation region, a second P+ implantation region, a third N+ implantation region, a second polysilicon gate, a fourth field oxide isolation region, a third P+ implantation region and a fifth field oxide isolation region are provided in sequence from left to right. The first N+ implantation region is provided in the first NW region; the second N+ implantation region, the first P+ implantation region, the second P+ implantation region and the third N+ implantation region are provided in the first PW region; the third P+ implantation region is provided in the second NW region.
[0026] The first N+ implantation region 501 is connected to the first metal layer 901 of the metal layer 1 through a contact hole, the first polysilicon gate 801 is connected to the second metal layer 902 of the metal layer 1 through a contact hole, the second N+ implantation region 502 is connected to the third metal layer 903 of the metal layer 1 through a contact hole, the first P+ implantation region 601 is connected to the fourth metal layer 904 of the metal layer 1 through a contact hole, the second P+ implantation region 602 is connected to the fifth metal layer 905 of the metal layer 1 through a contact hole, the third N+ implantation region 503 is connected to the sixth metal layer 906 of the metal layer 1 through a contact hole, the second polysilicon gate 802 is connected to the seventh metal layer 907 of the metal layer 1 through a contact hole, and the third P+ implantation region 603 is connected to the eighth metal layer 908 of the metal layer 1 through a contact hole.
[0027] The first metal layer 901 and the eighth metal layer 908 of the metal layer 1 are connected to the first metal layer 1001 of the metal layer 2 through the metal via 1001 and serve as the anode of the device.
[0028] The second metal layer 902 and the seventh metal layer 907 of the metal layer 1 are connected to the second metal layer 1002 of the metal layer 2 through the metal via 1002 and serve as the gate of the device.
[0029] The fifth metal layer 905 and the sixth metal layer 906 of the metal layer 1 are connected to the fourth metal layer 1004 of the metal layer 2 through the metal via 1004 and serve as the cathode of the device.
[0030] A manufacturing method of a composite Darlington transistor device structure includes the following steps:
[0031] Step 1: Form a first N-Drift region 201 and a second N-Drift region 202 in the substrate P-Sub101. Specifically:
[0032] Manufacture the first N-Drift region 201 and the second N-Drift region 202 on the surface of the substrate P-Sub101. Then, a layer of silicon dioxide film is formed by thermal oxidation to relieve the stress damage caused by the silicon nitride formed in the subsequent process steps. A layer of silicon nitride is deposited by chemical vapor deposition (LPCVD) technology as the stop layer for CMP in the subsequent process steps.
[0033] The photoresist is evenly coated on the wafer, and the photoresist is exposed and developed. This step is used to define the shallow trench isolation (STI). Then, the silicon nitride, silicon dioxide, and isolation trench are etched, the photoresist layer is removed, a layer of silicon dioxide is deposited by chemical vapor deposition (LPCVD), and then chemical mechanical polishing is carried out until the silicon nitride film layer. The silicon nitride film layer is removed by wet etching with hot phosphoric acid.
[0034] Step 2: Form a first field oxide isolation region 701, a second field oxide isolation region 702, a third field oxide isolation region 703, a fourth field oxide isolation region 704, and a fifth field oxide isolation region 705 on the substrate P-Sub101 through lithography. Specifically:
[0035] Using the local oxidation of silicon (LOCOS) isolation technology, a silicon dioxide film layer is grown as a buffer layer by thermal oxidation method. Then, a layer of silicon nitride is deposited by chemical vapor deposition (LPCVD) technology. The photoresist is coated on the wafer, and the silicon nitride on the first field oxide isolation region 701, the second field oxide isolation region 702, the third field oxide isolation region 703, the fourth field oxide isolation region 704, and the fifth field oxide isolation region 705 is defined by lithography technology. Subsequently, field implantation is carried out to prevent the field from turning on.
[0036] Step 3: Through photolithography, form the first PW region 401 on the substrate P-Sub101, and sequentially form the first NW region 301 and the second NW region 302 in the first N-Drift region 201 and the second N-Drift region 202. Specifically:
[0037] Apply photoresist on the wafer for the definition of the first PW region 401, then perform high-energy boron ion implantation to form a lightly doped P-type region, and remove the photoresist layer.
[0038] Apply photoresist on the wafer for the definition of the first NW region 301 and the second NW region 302, then perform high-energy phosphorus ion implantation to form a local N-type region, and remove the photoresist layer.
[0039] Anneal the first PW region 401, the first NW region 301, and the second NW region 302 to repair the crystal damage on the silicon surface caused by ion implantation, activate the implanted impurities, and use the RTP process to eliminate the further diffusion of impurities.
[0040] Step 4: Form the first polysilicon gate 801 between the second field oxide isolation region 702 and the second N+ implantation region 502; form the second polysilicon gate 802 between the third N+ implantation region 503 and the fourth field oxide isolation region 704. Specifically:
[0041] Grow a sacrificial oxide layer to capture the defects on the silicon surface. Grow a gate oxide layer to be used as the gate insulating layer of the transistor. Deposit the first polysilicon gate 801 and the second polysilicon gate 802 by low-pressure chemical vapor deposition (LPCVD), form the shape with photoresist, etch the polysilicon, and require to precisely obtain the specific shape of the polysilicon from the photoresist, then remove the photoresist layer. Oxidize the polysilicon to buffer and isolate the polysilicon from the silicon nitride formed in the subsequent steps. Deposit a layer of silicon nitride by low-pressure chemical vapor deposition (LPCVD), etch the silicon nitride, leave the isolation sidewall, and precisely position the ion implantation for the source and drain regions of the transistor.
[0042] Step 5: Through photolithography, form the first P+ implantation region 601 and the second P+ implantation region 602 in the first PW region 401, and form the third P+ implantation region 603 in the second NW region 302. Specifically:
[0043] Form the shape with photoresist to control the ion implantation, perform shallow-depth and high-dose boron ion implantation, remove the photoresist layer, and form the first P+ implantation region 601, the second P+ implantation region 602, and the third P+ implantation region 603.
[0044] Step 6: Through photolithography, form the first N+ implantation region 501 in the first NW region 301, and form the second N+ implantation region 502 and the third N+ implantation region 503 in the first PW region 401. Specifically:
[0045] Photoresist patterning is used to control ion implantation. Arsenic ions with a shallow depth and high doping are implanted. The photoresist layer is removed to form the first N+ implantation region 501, the second N+ implantation region 502, and the third N+ implantation region 503.
[0046] The present invention constitutes a composite Darlington transistor device structure. The MOSFET channel current is amplified through two-stage current gain, and the gate is used to turn on and off the device, thereby realizing a fully controlled power device with high input impedance, low on-state voltage drop, and high current density. The two-dimensional cross-sectional view and three-dimensional structure schematic diagram are respectively as Figure 2 and Figure 3 shown. Thus, a composite Darlington transistor is formed. The MOS current is amplified through the two-stage current gain provided by the Darlington structure formed by parasitic NPN and PNP transistors. The present invention adopts a composite Darlington transistor device structure, and its equivalent circuit diagram and top view are respectively as Figure 4 and Figure 5 shown. Specifically:
[0047] When the anode of the device is connected to a high potential, the cathode is grounded, and the gate voltage is greater than the threshold voltage of the MOSFET, the device operates in the forward conduction mode. Under the action of the gate voltage, a strong inversion layer is formed in the channel regions under the first polysilicon gate and the second polysilicon gate. The electron channel under the first polysilicon gate connects the first N-Drift region and the second N+ implantation region; the electron channel under the second polysilicon gate connects the third N+ implantation and the second N-Drift region. Since the voltage of the anode is higher than that of the cathode, the electrons in the second N+ implantation region flow through the electron channel under the first polysilicon gate to the first N-Drift region, forming the MOS current I Mn1 . The MOS current I Mn1 flows into the first P+ implantation region and the first PW region through the third metal layer of metal layer 1, the fourth metal layer of metal layer 1, the third metal via, and the third metal layer of metal layer 2. The MOS current I Mn1 provides the base current to turn on the parasitic NPN transistor composed of the first N+ implantation region, the first NW region, the first N-Drift region, the first P-Sub region, the first PW region, and the third N+ implantation region. The MOS current I Mn1 is amplified through the current gain of the parasitic NPN transistor. Under the action of the anode voltage, the electrons in the third N+ implantation region flow through the electron channel under the second polysilicon gate to the second N-Drift region to form the MOS current I Mn2 . The MOS current I Mn2 provides the base current to turn on the parasitic PNP transistor composed of the second P+ implantation region, the first PW region, the first P-Sub region, the second N-Drift region, the second NW region, and the third P+ region. The MOS current IMn2 The first-stage current gain is formed by the amplification of the parasitic PNP transistor. The collector current of the parasitic PNP transistor further constitutes the base current of the parasitic NPN transistor, turning on the parasitic NPN transistor composed of the first N+ implantation region, the first NW region, the first N-Drift region, the first P-Sub region, the first PW region, and the third N+ implantation region. The collector current of the parasitic PNP transistor is further amplified by the parasitic NPN transistor to form the second-stage current gain. Thus, a composite Darlington transistor device structure is formed, and the MOS current is amplified through the two-stage current gains of the parasitic NPN transistor and the PNP transistor, enhancing the current capacity of the device. In addition, when the emitter junction of the parasitic PNP transistor is forward-biased, the third P+ implantation region injects holes into the second N-Drift region to form a conductivity modulation effect, greatly increasing the conductivity of the drift region and effectively reducing the on-resistance of the device.
[0048] Based on all the above content, the present invention provides a composite Darlington transistor device structure and its manufacturing method, which have a simple structure and do not require breaking the process design rules. The fabricated composite Darlington transistor device structure is fully compatible with the standard BCD process and does not use masks outside the standard process, enabling the composite Darlington transistor to have a high input impedance, a low on-resistance, and a high current density, and can be used in fields such as power electronics, automotive electronics, and renewable energy.
Claims
1. A compound Darlington transistor device structure, characterized in that, Including: Substrate P-Sub; A first N-Drift region and a second N-Drift region are provided in the substrate P-Sub; Above the first N-Drift region and the second N-Drift region, a first NW region, a first PW region and a second NW region are provided; Above the first NW region, the first PW region and the second NW region, a first field oxide isolation region, a first N+ implantation region, a second field oxide isolation region, a first polysilicon gate, a second N+ implantation region, a first P+ implantation region, a third field oxide isolation region, a second P+ implantation region, a third N+ implantation region, a second polysilicon gate, a fourth field oxide isolation region, a third P+ implantation region and a fifth field oxide isolation region are provided in sequence from left to right; The first N+ implantation region is provided in the first NW region; the second N+ implantation region, the first P+ implantation region, the second P+ implantation region and the third N+ implantation region are provided in the first PW region; The third P+ implantation region is provided in the second NW region; The first N+ implantation region and the third P+ implantation region are connected to serve as the anode of the device; The second P+ implantation region and the third N+ implantation region are connected to serve as the cathode of the device; The first polysilicon gate and the second polysilicon gate are connected to serve as the gate of the device.
2. The structure of a composite Darlington transistor device according to claim 1, wherein When the anode of the device is connected to a high potential, the cathode is grounded, and the gate voltage is greater than the threshold voltage of the MOSFET, the device operates in the forward conduction mode. Under the action of the gate voltage, a strong inversion layer is formed in the channel region under the first polysilicon gate and the second polysilicon gate.
3. A composite Darlington transistor device structure according to claim 2, wherein, The electron channel under the first polysilicon gate connects the first N-Drift region and the second N+ implantation region; the electron channel under the second polysilicon gate connects the third N+ implantation and the second N-Drift region. Since the voltage of the anode is higher than that of the cathode, electrons in the second N+ implantation region flow through the electron channel under the first polysilicon gate to the first N-Drift region, forming a MOS current I Mn1 , the MOS current I Mn1 flows into the first P+ implantation region and the first PW region through the third metal layer of Metal Layer 1, the fourth metal layer of Metal Layer 1, the third metal via, and the third metal layer of Metal Layer 2.
4. A composite Darlington transistor device structure according to claim 3, characterized in that, MOS current I Mn1 Provide base current to turn on the parasitic NPN transistor composed of the first N+ injection region, the first NW region, the first N-Drift region, the first P-Sub region, the first PW region, and the third N+ injection region, MOS current I Mn1 Amplified by the current gain of the parasitic NPN transistor, under the action of the anode voltage, electrons in the third N+ injection region flow through the electron channel under the second polysilicon gate to the second N-Drift region to form MOS current I Mn2 , MOS current I Mn2 Provide base current to turn on the parasitic PNP transistor composed of the second P+ injection region, the first PW region, the first P-Sub region, the second N-Drift region, the second NW region, and the third P+ region, MOS current I Mn2 Amplified by the parasitic PNP transistor to form the first-stage current gain.
5. A composite Darlington transistor device structure according to claim 4, characterized in that, The collector current of the parasitic PNP transistor constitutes the base current of the parasitic NPN transistor, turning on the parasitic NPN transistor composed of the first N+ implantation region, the first NW region, the first N-Drift region, the first P-Sub region, the first PW region and the third N+ implantation region. The collector current of the parasitic PNP transistor is amplified by the parasitic NPN transistor to form a second-stage current gain, forming a composite Darlington transistor device structure.
6. A composite Darlington transistor device structure according to claim 5, characterized in that: When the emitter junction of the parasitic PNP transistor is forward-biased, the third P+ implantation region injects holes into the second N-Drift region to form a conductivity modulation effect, improving the conductivity of the drift region.
7. A manufacturing method of a composite Darlington transistor device structure including the composite Darlington transistor device structure described in any one of claims 1-6, comprising the following steps: Step 1: Form the first to second N-Drift regions in the substrate P-Sub; Step 2: Form the first to fifth field oxide isolation regions on the substrate P-Sub by photolithography; Step 3: Form the first to second NW regions in the N-Drift region and form the first PW region in the P-Sub by photolithography; Step 4: Form a first polysilicon gate between the second field oxide isolation region and the second N+ implantation region, and form a second polysilicon gate between the third N+ implantation region and the fourth field oxide isolation region; Step 5: Form the first P+ implantation region and the second P+ implantation region in the first PW region and form the third P+ implantation region in the second NW region by photolithography; Step 6: Form the first N+ implantation region in the first NW region and form the second N+ implantation region and the third N+ implantation region in the first PW region by photolithography.