Display panel

Abstract

The invention provides a display panel, and belongs to the technical field of display. The display panel comprises a substrate, a first driving layer, a pixel electrode layer and a second driving layer which are sequentially arranged in a stacked mode. Wherein the pixel electrode layer is provided with a pixel electrode of a light-emitting element; the display panel is further provided with a pixel driving circuit used for driving the light-emitting elements. The pixel driving circuit comprises a plurality of thin film transistors, and the thin film transistors comprise a first thin film transistor located on the first driving layer and a second thin film transistor located on the second driving layer. The display panel can improve the pixel density.

Description

Technical Field

[0001] The present disclosure relates to the technical field of display panels, and more particularly, to a display panel. Background Art

[0002] With the advent of the metaverse and the popularization of AR / VR (Augmented Reality / Virtual Reality) technology, high-PPI (Pixels Per Inch) display devices have become a trend.

[0003] In related technologies, display devices formed by TFT (Thin Film Transistor) devices on glass-based and PI (Polyimide)-based substrates are approximately in the range of 500 - 600 PPI, which cannot meet the requirements of VR near-eye displays with a PPI higher than 1000. LTPO (Low Temperature Polycrystalline Silicon Oxide) devices formed by combining the leakage current of Oxide TFT (Metal Oxide Thin Film Transistor) and the high mobility characteristics of LTPS (Low Temperature Polycrystalline Silicon) cannot continue to increase the PPI due to the increase in vias.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] An object of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel to improve the pixel density of the display panel.

[0006] According to one aspect of the present disclosure, there is provided a display panel including a substrate, a first driving layer, a pixel electrode layer, and a second driving layer stacked in sequence; wherein, the pixel electrode layer is provided with pixel electrodes for light-emitting elements; the display panel is further provided with a pixel driving circuit for driving the light-emitting elements; the pixel driving circuit includes a plurality of thin film transistors, and the thin film transistors include a first thin film transistor located in the first driving layer and a second thin film transistor located in the second driving layer.

[0007] According to an embodiment of the present disclosure, the type of the first thin film transistor is different from the type of the second thin film transistor.

[0008] According to an embodiment of the present disclosure, the first thin film transistor is a low temperature polycrystalline silicon thin film transistor; the second thin film transistor is a metal oxide thin film transistor.

[0009] According to an embodiment of the present disclosure, the second driving layer includes a metal light-shielding layer, a metal oxide semiconductor layer, and a third gate layer that are stacked on a side of the pixel electrode layer away from the substrate; a positive projection of a channel region of the second thin-film transistor on the metal light-shielding layer is located within the metal light-shielding layer; and a gate of the second thin-film transistor is located in the third gate layer.

[0010] According to an embodiment of the present disclosure, the metal light-shielding layer is disposed on the same layer as the pixel electrode layer.

[0011] According to an embodiment of the present disclosure, the first driving layer includes a low-temperature polycrystalline silicon semiconductor layer, a first gate layer, and a second gate layer that are sequentially stacked.

[0012] The channel region of the first thin-film transistor is located in the low-temperature polycrystalline silicon semiconductor layer.

[0013] The gate of the first thin-film transistor is located in the first gate layer; the pixel driving circuit further includes a storage capacitor; and two electrodes of the storage capacitor are respectively located in the first gate layer and the second gate layer.

[0014] According to an embodiment of the present disclosure, the first thin-film transistor is a metal oxide thin-film transistor; and the second thin-film transistor is a low-temperature polycrystalline silicon thin-film transistor.

[0015] According to an embodiment of the present disclosure, the first driving layer further includes a first source-drain metal layer, and the first source-drain metal layer is electrically connected to the first thin-film transistor through a via.

[0016] The second driving layer further includes a second source-drain metal layer, and the second source-drain metal layer is electrically connected to the second thin-film transistor through a via.

[0017] At least one of the first source-drain metal layer and the second source-drain metal layer is electrically connected to the pixel electrode.

[0018] According to an embodiment of the present disclosure, the display panel further includes:

[0019] A pixel definition layer, located on a side of the second driving layer away from the pixel electrode layer; the pixel definition layer has pixel openings corresponding to the pixel electrodes one by one, and the pixel openings cover or partially cover the pixel electrodes.

[0020] According to an embodiment of the present disclosure, the light-emitting element is one of an OLED, a Micro LED, a Mini LED, or a QLED.

[0021] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit the present disclosure. Brief Description of the Drawings

[0022] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0023] Figure 1 In the first exemplary embodiment of the present disclosure, it is a schematic diagram of the film layer structure of a display panel in the prior art.

[0024] Figure 2 In the first exemplary embodiment of the present disclosure, it is a schematic diagram of the film layer structure of a display panel.

[0025] Figure 3 In the first exemplary embodiment of the present disclosure, it is a schematic diagram of a pixel driving circuit in a display panel.

[0026] Figure 4 In the first exemplary embodiment of the present disclosure, it is a schematic diagram of a pixel driving circuit in a display panel.

[0027] Description of the Reference Numerals:

[0028] SBT, substrate; DRL, driving layer; SCL, semiconductor layer; SD, source-drain metal layer; PIXL, pixel layer; PEL, pixel electrode layer; PE, pixel electrode; PDL, pixel definition layer; EFL, light-emitting functional layer; COML, common electrode layer; PVX, passivation layer; PLN, planarization layer; ILD, interlayer dielectric layer; BUF1, first buffer layer; BUF2, second buffer layer; DRL1, first driving layer; DRL2, second driving layer; LS, metal light-shielding layer; OSCL, metal-oxide semiconductor layer; GT1, first gate layer; GT2, second gate layer; GT3, third gate layer; SD1, first source-drain metal layer; SD2, second source-drain metal layer; LSCL, polysilicon semiconductor layer; GI1, first gate insulating layer; GI2, second gate insulating layer; GI 3, third gate insulating layer; ILD1, first interlayer dielectric layer; ILD2, second interlayer dielectric layer; T1, first reset transistor; T2, threshold compensation transistor; T3, driving transistor; T4, first data writing transistor; T5, first light-emitting transistor; T6, second light-emitting transistor; T7, first electrode reset transistor; Cs t1, first storage capacitor; Cs t2, second storage capacitor; T8, pulse signal writing transistor; T9, light-emitting signal writing transistor; T10, second data writing transistor; C1, storage capacitor; Vini t, initialization voltage; Vref, sensing signal; Data, data signal; SREF, first switching switch; SSAMP, second switching switch; SCAN1, scanning signal; VDD, power supply voltage; HF, pulse signal; EM, light-emitting signal; GP, second scanning signal; VSS, reference voltage power supply; N1, first node; N2, second node; N3, third node; N4, fourth node; N5, fifth node; N6, sixth node; N7, seventh node; N8, eighth node; N9, ninth node; N10, tenth node; N11, eleventh node; N12, twelfth node. Detailed implementation manners

[0029] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0030] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the drawings. It can be understood that if the device of the icon is flipped so that it is upside down, the component described as "upper" will become the component described as "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0031] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0032] The structural layer A is located on the side of the structural layer B away from the substrate. It can be understood that the structural layer A is formed on the side of the structural layer B away from the substrate. When the structural layer B is a patterned structure, a part of the structure of the structural layer A can also be located at the same physical height as the structural layer B or at a physical height lower than the structural layer B, where the substrate is the height reference.

[0033] In an embodiment of the present disclosure, the thin film transistor includes an active layer, a gate insulating layer, and a gate that are stacked. Among them, the active layer is located in the semiconductor layer, and the active layer includes a channel region and a source electrode and a drain electrode respectively located on both sides of the channel region. Among them, the channel region maintains semiconductor characteristics, and both the source electrode and the drain electrode are conductorized. In an embodiment of the present disclosure, in the case of using transistors with opposite polarities or in the case of a change in the current direction during the operation of the circuit, etc., the functions of the "source electrode" and the "drain electrode" sometimes swap with each other, that is, the "source electrode" and the "drain electrode" can swap with each other. In an embodiment of the present disclosure, for any one transistor, one of the "source electrode" and the "drain electrode" is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor.

[0034] Figure 1 In a related art, it is a schematic structural diagram of an OLED display panel. Refer to Figure 1 , the display panel includes a substrate SBT, a driving layer DRL, and a pixel layer PIXL (only part is shown) that are sequentially stacked. Among them, sub-pixels for display are provided in the pixel layer PIXL, and a pixel driving circuit for driving the sub-pixels is provided in the driving layer DRL. Refer to Figure 1 , the pixel driving circuit includes a plurality of thin film transistors and also includes a storage capacitor ( Figure 1(not shown in the figure). Components such as thin-film transistors and storage capacitors are disposed in the same driving layer DRL; a first source-drain metal layer SD1 for electrical connection is also disposed in the driving layer DRL, and the first source-drain metal layer SD1 is electrically connected to the components in the driving layer DRL through vias. Since the thin-film transistors and storage capacitors are disposed in the same driving layer DRL, the number of vias in the same driving layer DRL is large and occupies a large layout area. Especially when the number of transistors in the pixel driving circuit is large, for example, when the number of transistors in the pixel driving circuit reaches 7 or 8, it will cause a large layout area of the pixel driving circuit. This results in a certain limitation on the resolution of the display panel. For example, it is difficult to exceed 600 PPI.

[0035] For example, in Figure 1 the related art shown in the example, the OLED display panel includes a substrate SBT, a first buffer layer BUF1, a polysilicon semiconductor layer LSCL, a first gate insulating layer GI1, a first gate layer GT1, a second gate insulating layer GI2, a second gate layer GT2, a first interlayer dielectric layer ILD1, a second buffer layer BUF2, a metal oxide semiconductor layer OSCL, a third gate insulating layer GI 3, a third gate layer GT3, a second interlayer dielectric layer ILD2, a first source-drain metal layer SD1, a first planarization layer PLN1, a second source-drain metal layer SD2, a second planarization layer PLN2, and a pixel layer PIXL, which are sequentially stacked. In Figure 1 the example of, the pixel electrode layer PEL and the pixel definition layer PDL in the pixel layer PIXL are illustrated, and the pixel electrode layer PEL has a pixel electrode PE. The pixel electrode PE is electrically connected to the pixel driving circuit located in the driving layer DRL through a via.

[0036] Embodiments of the present disclosure provide a display panel. Refer to Figure 2 , the display panel includes a substrate SBT, a first driving layer DRL1, a pixel electrode layer PEL, and a second driving layer DRL2, which are sequentially stacked; wherein, the pixel electrode layer PEL is provided with a pixel electrode PE for a light-emitting element (as a sub-pixel). When the sub-pixel of the display panel is a thin-film light-emitting element, such as OLED, QLED, PLED, QD-OLED, etc., the light-emitting functional material of the light-emitting element can be deposited on the pixel electrode PE.

[0037] For example, the pixel layer PIXL includes a pixel electrode layer PEL, a pixel definition layer PDL, a light-emitting functional layer, a common electrode layer, etc., which are sequentially stacked. In this embodiment, the second driving layer DRL2 can be prepared later than the pixel electrode layer PEL, or simultaneously with some film layers of the second driving layer DRL2. The light-emitting functional layer can be prepared later than the second driving layer DRL2. For example, in Figure 2In the example, the pixel electrode layer PEL and the bottommost film layer in the second driving layer DRL2 are prepared simultaneously, or the pixel electrode layer PEL is prepared first and then the preparation of the second driving layer DRL2 is started. After the second driving layer DRL2 is prepared, the pixel definition layer PDL, the light-emitting functional layer, the common electrode layer, etc. are prepared.

[0038] It can be understood that when the sub-pixels of the display panel are surface-mounted light-emitting elements, such as Micro LED, Mini LED, LED, etc., the pixel electrode PE can be used as a pad when mounting the light-emitting element; or a pad for mounting the light-emitting element is prepared above the pixel electrode layer PEL, and at least one pad is electrically connected to the pixel electrode PE.

[0039] In the embodiment of the present disclosure, the display panel is further provided with a pixel driving circuit for driving the light-emitting element; the pixel driving circuit includes a plurality of thin film transistors, and the thin film transistors include a first thin film transistor located in the first driving layer DRL1 and a second thin film transistor located in the second driving layer DRL2.

[0040] It should be noted that the first thin film transistor mentioned in the example of the present disclosure refers to any thin film transistor located in the first driving layer DRL1, and does not limit the number of thin film transistors in the first driving layer DRL1. Similarly, the second thin film transistor refers to any thin film transistor in the second driving layer DRL2, and does not limit the number of thin film transistors in the second driving layer DRL2.

[0041] In the display panel provided by the present disclosure, by distributing the first thin film transistor in the first driving layer DRL1, the second thin film transistor in the second driving layer DRL2, and the first driving layer DRL1 and the second driving layer DRL2 are respectively arranged on both sides of the pixel electrode layer PEL, the number of transistors in the same film layer is reduced, and further the number of vias for electrical connection is reduced, which helps to further improve the PPI in the display panel.

[0042] The display panel and each component provided by the present disclosure will be described in detail below with reference to the drawings and specific embodiments:

[0043] See Figure 2 , the exemplary display panel includes a substrate SBT, a first driving layer DRL1, a pixel electrode layer PEL, and a second driving layer DRL2.

[0044] The substrate SBT can be a substrate SBT of inorganic material, or a substrate of organic material; of course, it can also be a composite substrate formed by laminating a substrate of inorganic material and a substrate of organic material.

[0045] For example, in some embodiments of the present disclosure, the material of the substrate SBT can be glass materials such as soda-lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can include polyimide.

[0046] It can be understood that the above examples of the substrate SBT are only one possible way of the substrate SBT in the embodiments of the present disclosure. In other embodiments of the present disclosure, the substrate SBT can also be other structures, for example, the substrate SBT can also be a passive driving glass substrate, a silicon-based driving substrate, etc.

[0047] In the embodiments of the present disclosure, both the first driving layer DRL1 and the second driving layer DRL2 are provided with pixel driving circuits for driving the light-emitting elements; each light-emitting element can emit light under the drive of the pixel driving circuit to display an image. Any one of the pixel driving circuits can include a thin-film transistor and a storage capacitor.

[0048] Further, the thin-film transistor can be selected from a top-gate thin-film transistor, a bottom-gate thin-film transistor or a double-gate thin-film transistor; the material of the active layer of the thin-film transistor can be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material or other types of semiconductor materials; the thin-film transistor can be an N-type thin-film transistor or a P-type thin-film transistor.

[0049] It can be understood that among the transistors in the pixel driving circuit, the types of any two transistors can be the same or different. Exemplarily, in some embodiments, in a pixel driving circuit, some transistors can be N-type transistors and some transistors can be P-type transistors. Another example is that in some other embodiments, in a pixel driving circuit, the material of the active layer of some transistors can be low-temperature polycrystalline silicon semiconductor material, and the material of the active layer of some transistors can be metal oxide semiconductor material. In some embodiments of the present disclosure, the thin-film transistor is a low-temperature polycrystalline silicon transistor. In some other embodiments of the present disclosure, some thin-film transistors are low-temperature polycrystalline silicon transistors and some thin-film transistors are metal oxide transistors.

[0050] In one embodiment of the present disclosure, the type of the first thin film transistor is different from that of the second thin film transistor. Specifically, the type of the first thin film transistor is a low-temperature polysilicon thin film transistor, and the type of the second thin film transistor is a metal oxide thin film transistor; or the type of the first thin film transistor is a metal oxide thin film transistor; the type of the second thin film transistor is a low-temperature polysilicon thin film transistor.

[0051] Of course, the type of the first thin film transistor may also be the same as that of the second thin film transistor. The type of the first thin film transistor is a low-temperature polysilicon thin film transistor, and the type of the second thin film transistor is also a low-temperature polysilicon thin film transistor; or the type of the first thin film transistor is a metal oxide thin film transistor; the type of the second thin film transistor is also a metal oxide thin film transistor.

[0052] In this embodiment, for example, the first thin film transistor is a low-temperature polysilicon thin film transistor; the second thin film transistor is a metal oxide thin film transistor. Thus, only one semiconductor layer can be provided in the first driving layer DRL1, and only one semiconductor layer can also be provided in the second driving layer DRL2.

[0053] In an example of this embodiment, refer to Figure 2 、 Figure 3 , the first driving layer DRL1 includes a substrate SBT, a first buffer layer BUF1, a polysilicon semiconductor layer LSCL, a first gate insulating layer GI1, a first gate layer GT1, a second gate insulating layer GI2, a second gate layer GT2, a first interlayer dielectric layer ILD1, and a first source-drain metal layer SD1 that are sequentially stacked; the channel region of the first thin film transistor is located in the polysilicon semiconductor layer LSCL; the gate of the first thin film transistor is located in the first gate layer GT1; the pixel driving circuit further includes a storage capacitor; the two electrodes of the storage capacitor are respectively located in the first gate layer GT1 and the second gate layer GT2.

[0054] In an example of this embodiment, the second driving layer DRL2 includes a metal light-shielding layer LS, a metal oxide semiconductor layer OSCL, a third gate insulating layer GI 3, a third gate layer GT3, a second interlayer dielectric layer ILD2, and a second source-drain metal layer SD2 that are stacked on the side of the pixel electrode layer PEL away from the substrate SBT; the projection of the channel region of the second thin film transistor on the metal light-shielding layer LS is located within the metal light-shielding layer LS; the gate of the second thin film transistor is located in the third gate layer GT3.

[0055] In an example of this embodiment, the metal light-shielding layer LS is provided on the same layer as the pixel electrode layer PEL. In other words, when forming the metal light-shielding layer LS, the pixel electrode PE can be formed simultaneously.

[0056] In one embodiment of the present disclosure, refer to Figure 2 , the first driving layer DRL1 further includes a first source-drain metal layer SD1 and a planarization layer PLN; the first source-drain metal layer SD1 is disposed on a side of the first interlayer dielectric layer ILD1 away from the substrate SBT and is electrically connected to the first thin-film transistor through a via. The planarization layer PLN is located on a side of the first source-drain metal layer SD1 away from the substrate SBT. The second driving layer DRL2 is disposed on a side of the planarization layer PLN away from the substrate SBT and further includes a second source-drain metal layer SD2; the second source-drain metal layer SD2 is located on a side of the second interlayer dielectric layer ILD2 away from the substrate SBT and is electrically connected to the second thin-film transistor through a via. At least one of the first source-drain metal layer SD1 and the second source-drain metal layer SD2 is electrically connected to the pixel electrode PE.

[0057] Optionally, in the embodiment of the present disclosure, the material of the polysilicon semiconductor layer LSCL may be polysilicon; the material of the first buffer layer BUF1 may be a stacked material of silicon nitride and silicon oxide; the material of the first gate insulating layer GI1 may be a stacked material of silicon nitride and silicon oxide; the material of the first gate layer GT1 may be molybdenum; the material of the second gate insulating layer GI2 may be silicon nitride; the material of the second gate layer GT2 may be molybdenum; the material of the first interlayer dielectric layer ILD1 may be silicon nitride; the material of the first source-drain metal layer SD1 may be a stacked structure of a titanium layer, an aluminum layer, and a titanium layer; the material of the planarization layer PLN is an inorganic film layer; the material of the pixel electrode layer PEL is a stacked structure of an indium tin oxide layer, a silver layer, and an indium tin oxide layer, or the material of the pixel electrode layer PEL is copper; the material of the metal oxide semiconductor layer OSCL may be indium gallium zinc oxide; the material of the second buffer layer BUF2 may be silicon oxide; the material of the third gate insulating layer GI3 may be silicon oxide; the material of the third gate layer GT3 may be a stacked structure of a tin layer and a film layer or a stacked structure of a titanium layer, an aluminum layer, and a titanium layer; the material of the second interlayer dielectric layer ILD2 may be a stacked structure of silicon nitride and silicon oxide; the material of the second source-drain metal layer SD2 may be a stacked structure of a titanium layer, an aluminum layer, and a titanium layer or copper; the material of the pixel definition layer PDL may be resin or silicon oxide.

[0058] In one example, refer to Figure 2 , both the first source-drain metal layer SD1 and the second source-drain metal layer SD2 are electrically connected to the pixel electrode layer PEL, thereby connecting the first thin-film transistor and the second thin-film transistor to each other. In other examples of the present disclosure, both the first source-drain metal layer SD1 and the second source-drain metal layer SD2 may also be electrically connected to the metal light-shielding layer LS, thereby connecting the first thin-film transistor and the second thin-film transistor to each other.

[0059] Optionally, the first driving layer DRL1 may further include a first passivation layer (not shown in the accompanying drawings of this specification); the second driving layer DRL2 may further include a second passivation layer (not shown in the accompanying drawings of this specification). The first passivation layer may be disposed on the surface of the first source-drain metal layer SD1 away from the substrate SBT to protect the first source-drain metal layer SD1. The second passivation layer may be disposed on the surface of the second source-drain metal layer SD2 away from the substrate SBT to protect the second source-drain metal layer SD2 (not shown in the accompanying drawings of this specification).

[0060] Figure 3 This is an equivalent circuit diagram of a pixel driving circuit in an embodiment of the present disclosure.

[0061] See Figure 3 , the pixel driving circuit includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, and a storage capacitor C1. The drain of the first reset transistor T1, the gate of the driving transistor T3, and the first electrode plate of the storage capacitor C1 are all electrically connected to the first node N1; the drain of the driving transistor T3, the drain of the threshold compensation transistor T2, the second electrode plate of the storage capacitor C1, and the pixel electrode PE are all electrically connected to the second node N2; the source of the driving transistor T3 and the power supply voltage trace for loading the power supply voltage VDD are both electrically connected to the third node N3; the source of the first reset transistor T1, the data voltage trace for loading the data signal Data, and the fourth node N4 are electrically connected; the source of the threshold compensation transistor T2 and the sensing trace for loading the sensing signal Vref are both electrically connected to the fifth node N5. The channel regions of the first reset transistor T1 and the threshold compensation transistor T2 are both used to load the scan signal SCAN1, so that the first reset transistor T1 and the threshold compensation transistor T2 can be turned on in response to the scan signal SCAN1. The sensing trace connected to the pixel driving circuit can load different signals in different operating modes. In the display mode, the sensing trace can load the sensing signal Vref; in the sensing mode, the sensing trace can be electrically connected to the detection circuit so that the detection circuit can detect the driving current generated by the pixel driving circuit.

[0062] Optionally, see Figure 3 , the display device is provided with a mode switching unit, which includes two different switches, a first switching switch SREF and a second switching switch SSAMP; the first switching switch SREF is disposed between the reference voltage power supply VSS and the sensing trace for controlling whether the sensing signal Vref can be loaded onto the sensing trace. The second switching switch SSAMP is disposed between the current detection circuit and the sensing trace for controlling whether the current detection current can detect the driving current of the pixel driving circuit. The first switching switch SREF and the second switching switch SSAMP are selectively turned on to enable the pixel driving circuit to switch between the display mode and the sensing mode.

[0063] In Figure 3 In the illustrated pixel driving circuit, the first reset transistor T1 and the driving transistor T3 are low-temperature polysilicon thin-film transistors, and the threshold compensation transistor T2 is a metal oxide thin-film transistor. On the display panel, the first reset transistor T1 and the driving transistor T3 are provided as the first thin-film transistors in the first driving layer DRL1, and the threshold compensation transistor T2 is provided as the second thin-film transistors in the second driving layer DRL2.

[0064] In this example, the first driving layer DRL1 includes a first buffer layer BUF1, a polysilicon semiconductor layer LSCL, a first gate insulating layer GI1, a first gate layer GT1, a second gate insulating layer GI2, a second gate layer GT2, a first interlayer dielectric layer ILD1, a first source-drain metal layer SD1, and a planarization layer PLN, which are sequentially stacked on one side of the substrate SBT. The second driving layer DRL2 includes a metal light-shielding layer LS, a second buffer layer BUF2, a metal oxide semiconductor layer OSCL, a third gate insulating layer GI3, a third gate layer GT3, a second interlayer dielectric layer ILD2, and a second source-drain metal layer SD2, which are sequentially stacked on the side of the planarization layer PLN away from the substrate SBT. The planarization layer PNL further includes a pixel electrode layer PEL sandwiched between the first driving layer DRL1 and the second driving layer DRL2. The pixel electrode layer PEL is provided on the same layer as the metal light-shielding layer LS, that is, they have the same material and are prepared simultaneously. The pixel layer PIXL further includes a pixel definition layer PDL, and the pixel definition layer PDL can cover the second driving layer DRL2 and expose at least a part of the pixel electrode PE.

[0065] In this example, the active layer of the first reset transistor T1 and the active layer of the driving transistor T3 are provided in the polysilicon semiconductor layer LSCL. The first electrode plate of the storage capacitor C1 and the first reset transistor T1 are provided in GT1, and the second electrode plate of the storage capacitor C1 is provided in GT2. The first driving layer DRL1 needs to be provided with vias to achieve electrical connection.

[0066] At the first node N1, a first metal structure is provided on the first source-drain metal layer SD1; the first metal structure is electrically connected to the drain of the first reset transistor T1 through a first via, and is electrically connected to the first electrode plate of the storage capacitor C1 through a second via. Among them, the first via penetrates through the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1 to expose the drain of the first reset transistor T1; the second via penetrates through the first interlayer dielectric layer ILD1 and the second gate insulating layer GI2 to expose the first electrode plate of the storage capacitor C1 located in the first gate layer GT1.

[0067] At the second node N2, a second metal structure is provided in the first source-drain metal layer SD1; the second metal structure is electrically connected to the drain of the driving transistor T3 through a third via; the second metal structure is electrically connected to the metal light-shielding layer LS through a fourth via; and is electrically connected to the second gate layer GT2 through the fourth via. Among them, the third via penetrates through the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1 to expose the drain of the driving transistor T3; the fourth via penetrates through the planarization layer PLN to expose the second metal structure. The second metal structure is electrically connected to the second electrode plate of the storage capacitor C1 through a fifth via; the fifth via penetrates through the second interlayer dielectric layer ILD2 to expose the second electrode plate of the storage capacitor C1. The fifth via penetrates through the first interlayer dielectric layer ILD1 to expose ILD1.

[0068] The drain of the threshold compensation transistor T2 is electrically connected to a first conductive structure located in the second source-drain metal layer SD2 through a via, and the first conductive structure is electrically connected to the metal light-shielding layer LS.

[0069] At the third node N3, a power supply voltage trace for loading the power supply voltage VDD is provided in the first source-drain metal layer SD1, and the power supply voltage trace is electrically connected to the source of the driving transistor T3 through a sixth via. Among them, the fifth via penetrates through the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1 to expose the source of the driving transistor T3.

[0070] At the fourth node N4, a data signal trace for loading the data signal Data is provided in the first source-drain metal layer SD1, and the data signal trace is electrically connected to the source of the first reset transistor T1 through a seventh via. Among them, the seventh via penetrates through the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1 to expose the source of the first reset transistor T1.

[0071] As follows, in this example, the first driving layer DRL1 only needs to be provided with 7 vias in one circuit region to meet the requirements of electrical connection; while in the related art, in order to achieve this electrical connection, the driving layer DRL needs to be provided with 9 vias. This example reduces the layout area occupied by the vias by reducing the number of vias in the first driving layer DRL1, and thus can reduce the area of the circuit region, which is beneficial to improving the resolution or the aperture ratio.

[0072] Figure 4 It is an equivalent circuit diagram of a pixel driving circuit in another example.

[0073] See Figure 4 , this pixel driving circuit includes the first reset transistor T1 to the second data writing transistor T10, the first storage capacitor Cst1, and the second storage capacitor Cst2.

[0074] Among them, the first node N1 is electrically connected to the first electrode plate of the first storage capacitor Cst1, the drain of the threshold compensation transistor T2, the drain of the first reset transistor T1, and the gate of the driving transistor T3; the second node N2 is electrically connected to the drain of the first light-emitting transistor T5, the drain of the first data writing transistor T4, and the source of the driving transistor T3; the third node N3 is electrically connected to the drain of the driving transistor T3, the source of the threshold compensation transistor T2, and the source of the second light-emitting transistor T6; the fourth node N4 is electrically connected to the power supply voltage trace for loading the power supply voltage VDD, the second electrode plate of the first storage capacitor Cst1, and the source of the first light-emitting transistor T5; the fifth node N5 is electrically connected to the data signal trace for loading the data signal Data and the source of the first data writing transistor T4; the sixth node N6 is electrically connected to the initialization voltage trace for loading the initialization voltage Vinit, the source of the first reset transistor T1, and the source of the first electrode reset transistor T7; the seventh node N7 is electrically connected to the drain of the second light-emitting transistor T6, the drain of the first electrode reset transistor T7, and the pixel electrode PE; the eighth node N8 is electrically connected to the drain of the pulse signal writing transistor T8, the drain of the light-emitting signal writing transistor T9, and the gate of the second light-emitting transistor T6; the ninth node N9 is electrically connected to the pulse signal trace for loading the pulse signal HF and the source of the pulse signal writing transistor T8; the tenth node N10 is electrically connected to the light-emitting signal trace for loading the light-emitting signal EM and the source of the light-emitting signal writing transistor T9; the eleventh node N11 is electrically connected to the first electrode plate of the second storage capacitor Cst2, the gate of the pulse signal writing transistor T8, the gate of the light-emitting signal writing transistor T9, and the drain of the second data writing transistor T10; the second electrode plate of the second storage capacitor Cst2 is electrically connected to the initialization voltage trace for loading the initialization voltage Vinit; N12 is electrically connected to the data signal trace for loading the data signal Data and the source of the second data writing transistor T10.

[0075] The gate of the first reset transistor T1 is electrically connected to the reset signal trace for loading the reset signal RN; the gate of the threshold compensation transistor T2 is electrically connected to the scan signal trace for loading the first scan signal GN; the gate of the first data writing transistor T4 is electrically connected to the data writing trace for loading the second scan signal GP; the gate of the first light-emitting transistor T5 is electrically connected to the light-emitting signal trace for loading the light-emitting signal EM; the gate of the second light-emitting transistor T6 is electrically connected to the drain of the pulse signal writing transistor T8 and the drain of the light-emitting signal writing transistor T9; the gate of the first electrode reset transistor T7 is electrically connected to the reset signal trace for loading the reset signal RN; the gate of the second data writing transistor T10 is electrically connected to the scan signal trace for loading the reset signal RN.

[0076] In this example, the first driving layer DRL1 includes a first buffer layer BUF1, a polysilicon semiconductor layer LSCL, a first gate insulating layer GI1, a first gate layer GT1, a second gate insulating layer GI2, a second gate layer GT2, a first interlayer dielectric layer ILD1, a first source-drain metal layer SD1, and a planarization layer PLN, which are sequentially stacked on one side of the substrate SBT. The second driving layer DRL2 includes a metal light-shielding layer LS, a second buffer layer BUF2, a metal oxide semiconductor layer OSCL, a third gate insulating layer GI3, a third gate layer GT3, a second interlayer dielectric layer ILD2, and a second source-drain metal layer SD2, which are sequentially stacked on the side of the planarization layer PLN away from the substrate SBT.

[0077] The display panel further includes a pixel electrode layer PEL sandwiched between the first driving layer DRL1 and the second driving layer DRL2. The pixel electrode layer PEL is disposed on the same layer as the metal light-shielding layer LS, that is, they have the same material and are prepared simultaneously. The pixel layer further includes a pixel definition layer PDL, which may cover the second driving layer DRL2 and expose at least a partial region of the pixel electrode PE.

[0078] In Figure 4 In the pixel driving circuit shown in the example, the first reset transistor T1, the threshold compensation transistor T2, the first electrode reset transistor T7, the light-emitting signal writing transistor T9, and the second data writing transistor T10 are metal oxide thin film transistors, and the driving transistor T3, the first data writing transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, and the pulse signal writing transistor T8 are polysilicon thin film transistors.

[0079] At the first node N1, the first source-drain metal layer SD1 is provided with a first metal structure. The first metal structure is electrically connected to a first electrode plate of a first storage capacitor Cst1 located in the first gate layer GT1 through a first via; the first metal structure is electrically connected to the metal light-shielding layer LS through a second via; the first via penetrates through the first interlayer dielectric layer ILD1 and the second gate insulating layer GI2 to expose the first storage capacitor Cst1 in the first gate layer GT1; the second via penetrates through the planarization layer PLN to expose the first metal structure. The drain of the threshold compensation transistor T2 and the drain of the first reset transistor T1 are electrically connected to a first conductive structure located in the second source-drain metal layer SD2 through a via, and the first conductive structure is electrically connected to the metal light-shielding layer LS.

[0080] At the third node N3, the first source-drain metal layer SD1 is provided with a second metal structure. The second metal structure is electrically connected to the drain of the driving transistor T3 through a third via hole and is electrically connected to the metal light-shielding layer LS through a fourth via hole. Among them, the third via hole penetrates through the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1 to expose the drain of the driving transistor T3. The fourth via hole penetrates through the planarization layer PLN to expose the second metal structure. The source of the threshold compensation transistor T2 and the source of the second light-emitting transistor T6 are electrically connected to a second conductive structure located in the second source-drain metal layer SD2 through a via hole, and the second conductive structure is electrically connected to the metal light-shielding layer LS.

[0081] At the fourth node N4, the first source-drain metal layer SD1 is provided with a power supply voltage trace for loading the power supply voltage VDD. The power supply voltage trace is electrically connected to the source of the first light-emitting transistor T5 through a fifth via hole. Among them, the fifth via hole penetrates through the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1 to expose the source of the first light-emitting transistor T5. The first source-drain metal layer SD1 is further provided with a third metal structure. The third metal structure is located on the power supply voltage trace, and the third metal structure is electrically connected to the second electrode plate of the first storage capacitor Cst1 through a sixth via hole. The sixth via hole penetrates through the first interlayer dielectric layer ILD1 to expose the second electrode plate of the first storage capacitor Cs t1.

[0082] At the fifth node N5, the first source-drain metal layer SD1 is provided with a data trace for loading the data signal Data. The data trace is electrically connected to the source of the first data writing transistor T4 through a seventh via hole. Among them, the seventh via hole penetrates through the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI 1 to expose the source of the first data writing transistor T4.

[0083] At the sixth node N6, the first source-drain metal layer SD1 is provided with a fourth metal structure. The second gate layer GT2 is provided with an initialization voltage trace for loading the initialization voltage Vini t. The fourth metal structure is electrically connected to the initialization voltage trace located in the second gate layer GT2 through an eighth via hole. The fourth metal structure is electrically connected to the metal light-shielding layer LS through a ninth via hole. Among them, the eighth via hole penetrates through the first interlayer dielectric layer ILD1 to expose the second gate layer GT2. The ninth via hole penetrates through the planarization layer PLN to expose the fourth metal structure. The source of the first reset transistor T1 and the source of the first electrode reset transistor T7 are electrically connected to a third conductive structure located in the second source-drain metal layer SD2 through a via hole, and the third conductive structure is electrically connected to the metal light-shielding layer LS.

[0084] At the seventh node N7, a fifth metal structure is provided in the first source-drain metal layer SD1. The fifth metal structure is electrically connected to the metal light-shielding layer LS through a tenth via; the fifth metal structure is electrically connected to the drain of the second light-emitting transistor T6 through an eleventh via. Among them, the tenth via penetrates the planarization layer PLN to expose the fifth metal structure; the eleventh via penetrates the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1 to expose the drain of the second light-emitting transistor T6. The drain of the first electrode reset transistor T7 is electrically connected to a fourth conductive structure located in the second source-drain metal layer SD2 through a via, and the fourth conductive structure is electrically connected to the metal light-shielding layer LS.

[0085] At the eighth node N8, a sixth metal structure is provided in the first source-drain metal layer SD1. The sixth metal structure is electrically connected to the drain of the pulse signal writing transistor T8 through a twelfth via; the sixth metal structure is electrically connected to the metal light-shielding layer LS through a thirteenth via. Among them, the twelfth via penetrates the first interlayer dielectric layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1 to expose the drain of the second light-emitting transistor T6; the thirteenth via penetrates the planarization layer PLN to expose the sixth metal structure. The drain of the light-emitting signal writing transistor T9 is electrically connected to a fifth conductive structure located in the second source-drain metal layer SD2 through a via, and the fifth conductive structure is electrically connected to the metal light-shielding layer LS.

[0086] At the ninth node N9, a pulse signal trace for loading the pulse signal HF is provided in the second gate layer GT2, and a seventh metal structure is provided in the first source-drain metal layer SD1. The seventh metal structure is electrically connected to the pulse signal trace located in the second gate layer GT2 through a fourteenth via. Among them, the fourteenth via penetrates the first interlayer dielectric layer ILD1 to expose the pulse signal trace located in the second gate layer GT2.

[0087] At the eleventh node N11, an eighth metal structure is provided in the first source-drain metal layer SD1. The eighth metal structure is electrically connected to the first electrode plate of the second storage capacitor Cst2 located in the second gate layer GT2 through a fifteenth via; the eighth metal structure is electrically connected to the metal light-shielding layer LS through a sixteenth via. Among them, the fifteenth via penetrates the first interlayer dielectric layer ILD1 to expose the first electrode plate of the second storage capacitor Cst2; the sixteenth via penetrates the planarization layer PLN to expose the eighth metal structure. The gate of the light-emitting signal writing transistor T9 and the drain of the second data writing transistor T10 are electrically connected to a sixth conductive structure located in the second source-drain metal layer SD2 through a via, and the sixth conductive structure is electrically connected to the metal light-shielding layer LS.

[0088] In this example, the first driving layer DRL1 only needs to set 16 vias in a circuit area to meet the requirements of electrical connection; while in the related art, in order to achieve this electrical connection, the driving layer DRL needs to set 22 vias. By reducing the number of vias in the first driving layer DRL1, this example reduces the layout area occupied by the vias, and thus can reduce the area of the circuit area, which is beneficial to improving the resolution or the aperture ratio.

[0089] In the related art, as the metal for conducting signals up and down, the first source-drain metal layer SD1 also needs to route the data signal Data and the sense signal Vref. In the embodiments of the present disclosure, the data signal trace is arranged on the first source-drain metal layer SD1, and the sense signal trace is arranged on the second source-drain metal layer SD2, separating the data signal Data and the sense signal Vref in the vertical dimension. At the same time, using the first source-drain metal layer SD1 for the data signal trace reduces the additional vias and traces; the source and drain electrodes of the metal oxide semiconductor layer OSCL use the second source-drain metal layer SD2, without adding additional vias and traces either. The first source-drain metal layer SD1 and the second source-drain metal layer SD2 are connected by the pixel electrode PE, without adding additional vias either, which can further improve the PPI.

[0090] As another example, the first thin-film transistor can be a metal-oxide thin-film transistor; the second thin-film transistor can be a low-temperature polycrystalline silicon thin-film transistor (not specifically shown in the drawings of this application).

[0091] Optionally, referring to Figure 2 , the display panel may further include a pixel definition layer PDL, and the pixel definition layer PDL is located on the side of the second driving layer DRL2 away from the pixel electrode layer PEL; the pixel definition layer PDL has pixel openings corresponding one by one to the pixel electrodes PE, and the pixel openings cover or partially cover the pixel electrodes PE. So that the pixel definition layer PDL can effectively define the actual effective area of the pixel electrode PE (the area directly connected to the light-emitting element), and thus define the light-emitting area and the light-emitting area of the light-emitting element LD. At the same time, the orthographic projection of the pixel opening on the substrate SBT can be circular, elliptical, irregular polygon, etc., and the specific form is not disclosed and not limited.

[0092] In one embodiment of the present disclosure, the light-emitting element is one of OLED, Micro LED, Mini LED or QLED. It can be understood that when the types of light-emitting elements are different, the materials and film layers of the light-emitting functional units are different. For example, when the light-emitting element is an OLED, the light-emitting functional unit may include an organic light-emitting layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Further, the organic light-emitting layer may include a light-emitting layer host material and a light-emitting layer guest material, and the light-emitting layer guest material may be a fluorescent dopant or a phosphorescent dopant, especially a thermally activated delayed fluorescence material.

[0093] Further, the light-emitting element may include light-emitting elements of multiple different colors. For example, the light-emitting element includes a red light-emitting element for emitting red light, a blue light-emitting element for emitting green light, and a green light-emitting element for emitting green light. It can be understood that in other embodiments of the present disclosure, the light-emitting elements in the display area may also be light-emitting elements of only one color, or may also have light-emitting elements of other colors (such as a yellow light-emitting element for emitting yellow light, a cyan light-emitting element for emitting cyan light, a white light-emitting element for emitting white light, etc.).

[0094] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A display panel, characterized in that, It includes a substrate, a first driving layer, a pixel electrode layer, and a second driving layer which are sequentially stacked; wherein, the pixel electrode layer is provided with pixel electrodes of light-emitting elements; the display panel is further provided with a pixel driving circuit for driving the light-emitting elements; the pixel driving circuit includes a plurality of thin film transistors, and the thin film transistors include a first thin film transistor located in the first driving layer and a second thin film transistor located in the second driving layer.

2. The display panel according to claim 1, wherein The type of the first thin film transistor is different from that of the second thin film transistor.

3. The display panel according to claim 2, wherein The first thin film transistor is a low-temperature polycrystalline silicon thin film transistor; the second thin film transistor is a metal oxide thin film transistor.

4. The display panel according to claim 3, wherein The second driving layer includes a metal light-shielding layer, a metal oxide semiconductor layer, and a third gate layer which are stacked on the side of the pixel electrode layer away from the substrate; the orthographic projection of the channel region of the second thin film transistor on the metal light-shielding layer is located within the metal light-shielding layer; the gate of the second thin film transistor is located in the third gate layer.

5. The display panel according to claim 4, wherein The metal light-shielding layer is provided on the same layer as the pixel electrode layer.

6. The display panel according to claim 3, wherein The first driving layer includes a low-temperature polycrystalline silicon semiconductor layer, a first gate layer, and a second gate layer which are sequentially stacked. The channel region of the first thin film transistor is located in the low-temperature polycrystalline silicon semiconductor layer. The gate of the first thin film transistor is located in the first gate layer; the pixel driving circuit further includes a storage capacitor; the two electrodes of the storage capacitor are respectively located in the first gate layer and the second gate layer.

7. The display panel according to claim 2, wherein The first thin film transistor is a metal oxide thin film transistor; the second thin film transistor is a low-temperature polycrystalline silicon thin film transistor.

8. The display panel according to any one of claims 1-7, characterized in that, The first driving layer further includes a first source-drain metal layer, and the first source-drain metal layer is electrically connected to the first thin film transistor through a via. The second driving layer further includes a second source-drain metal layer, and the second source-drain metal layer is electrically connected to the second thin film transistor through a via. At least one of the first source-drain metal layer and the second source-drain metal layer is electrically connected to the pixel electrode.

9. The display panel according to any one of claims 1-7, characterized in that, The display panel further includes: A pixel definition layer, located on the side of the second driving layer away from the pixel electrode layer; the pixel definition layer has pixel openings corresponding to the pixel electrodes one by one, and the pixel openings cover or partially cover the pixel electrodes.

10. The display panel according to any one of claims 1-7, characterized in that, The light-emitting element is one of OLED, Micro LED, Mini LED, or QLED.

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