Image sensor

Abstract

An image sensor is provided. The image sensor includes: a first substrate; a plurality of photoelectric conversion units in the first substrate; the first connecting layer is arranged on the first substrate; a plurality of first pixel pads disposed on the first connection layer; a plurality of first peripheral pads disposed on the first substrate; the plurality of second pixel bonding pads are respectively positioned on the plurality of first pixel bonding pads; a plurality of second peripheral pads respectively located on the plurality of first peripheral pads; a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads; a device disposed on the second connection layer; and a second substrate disposed on the second connection layer and the device, in which a pitch of the plurality of first pixel pads is substantially the same as a pitch of the plurality of pixel regions of the first substrate.

Description

[0001] This application is a divisional application of the patent application for "Image Sensor" with the filing date of August 12, 2020, application number 202010805347.9, and invention name.

[0002] Cross-reference to related applications

[0003] This application claims priority to Korean Patent Application No. 10-2019-0098327, filed with the Korean Intellectual Property Office on August 12, 2019, the entire disclosure of which is incorporated herein by reference. Technical field

[0004] The present inventive concept relates to an image sensor. More particularly, the present inventive concept relates to a stacked image sensor including a stacked structure. Background art

[0005] An image sensor is a device for converting an optical image into an electrical signal. Examples of image sensors include charge-coupled devices (CCDs) and active pixel sensors (CMOS sensors). An image sensor can be used in cameras of portable electronic devices such as smart phones or tablet computers. However, due to the size of the image sensor, it may be difficult to reduce the size of portable electronic devices.

[0006] Stacked image sensors have been developed to reduce the size of portable electronic devices and improve the performance of cameras. Stacked image sensors can achieve a reduction in planar area, an improvement in resolution, and an improvement in signal processing speed. Summary of the invention

[0007] At least one embodiment of the present inventive concept provides a stacked image sensor.

[0008] According to an exemplary embodiment of the inventive concept, there is provided an image sensor including: a first substrate including a pixel array region including a plurality of pixel regions and a peripheral region around the pixel array region; a plurality of photoelectric conversion units respectively located in the plurality of pixel regions of the first substrate; a first connection layer disposed on the pixel array region and the peripheral region of the first substrate; a plurality of first pixel pads disposed on a part of the first connection layer on the pixel array region of the first substrate; a plurality of first peripheral pads disposed on a part of the first connection layer on the peripheral region of the first substrate; a plurality of second pixel pads respectively located on the plurality of first pixel pads; a plurality of second peripheral pads respectively located on the plurality of first peripheral pads; a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads; a device disposed on the second connection layer; and a second substrate disposed on the second connection layer and the device, wherein a pitch of the plurality of first pixel pads in a first horizontal direction is substantially the same as a pitch of the plurality of pixel regions of the first substrate in the first horizontal direction, and wherein a center of each of the plurality of first pixel pads is spaced apart from a center of each of the plurality of pixel regions of the first substrate by a predetermined distance in a second horizontal direction.

[0009] According to an exemplary embodiment of the inventive concept, there is provided an image sensor including a first structure and a second structure. The first structure includes: a first substrate including a plurality of pixel regions; a plurality of photoelectric conversion units respectively located in the plurality of pixel regions of the first substrate; a first connection layer disposed on the first substrate; and a plurality of first pixel pads disposed on the first connection layer. The second structure includes: a second substrate; a device disposed on the second substrate; a second connection layer disposed on the second substrate and the device; and a plurality of second pixel pads disposed on the second connection layer, wherein the plurality of first pixel pads are respectively in contact with the plurality of second pixel pads, wherein the first connection layer includes an insulating layer disposed on the first substrate and a conductive pattern disposed in the insulating layer, wherein a part of the first connection layer located on the plurality of pixel regions of the first substrate includes: a plurality of overlapping portions respectively overlapping the plurality of first pixel pads in a plan view; and a plurality of non-overlapping portions not overlapping the plurality of first pixel pads in the plan view, and wherein a ratio of a total volume of a plurality of portions of the conductive pattern respectively located in the plurality of overlapping portions of the first connection layer to a total volume of a plurality of portions of the insulating layer respectively located in the plurality of overlapping portions of the first connection layer is less than a ratio of a total volume of a plurality of portions of the conductive pattern respectively located in the plurality of non-overlapping portions of the first connection layer to a total volume of a plurality of portions of the insulating layer respectively located in the plurality of non-overlapping portions of the first connection layer.

[0010] According to an exemplary embodiment of the inventive concept, there is provided an image sensor including a first structure and a second structure. The first structure includes: a first substrate including a plurality of shared pixel regions, each shared pixel region including a first pixel region and a second pixel region; a plurality of first photoelectric conversion units, each located in the first pixel region of each of the plurality of shared pixel regions of the first substrate; a plurality of second photoelectric conversion units, each located in the second pixel region of each of the plurality of shared pixel regions of the first substrate; a plurality of shared floating diffusion regions located on the first pixel region and the second pixel region of each of the plurality of shared pixel regions; a first connection layer disposed on the first substrate; and a plurality of first pixel pads and a plurality of second pixel pads disposed on the first connection layer. The second structure includes: a second substrate; devices disposed on the second substrate; a second connection layer on the second substrate and the devices; and a plurality of third pixel pads and a plurality of fourth pixel pads on the second connection layer. Herein, the first structure contacts the second structure such that the plurality of first pixel pads respectively contact the plurality of third pixel pads, and the plurality of second pixel pads respectively contact the plurality of fourth pixel pads. Herein, a pitch of the plurality of first pixel pads in a first horizontal direction and a pitch of the plurality of second pixel pads in the first horizontal direction are substantially the same as a pitch of the plurality of shared pixel regions in the first horizontal direction, and a distance within a shared pixel region in a second horizontal direction between the plurality of first pixel pads and the plurality of second pixel pads is substantially different from a distance between shared pixel regions in the second horizontal direction between the plurality of first pixel pads and the plurality of second pixel pads.

[0011] According to an exemplary embodiment of the inventive concept, there is provided an image sensor including: a first substrate having a pixel region including a photoelectric conversion unit; a first connection layer disposed on the pixel region; a first pixel pad including a conductive and reflective material disposed on the first connection layer within the pixel region and not overlapping with the photoelectric conversion unit in a plan view; a second pixel pad located on the first pixel pad; a second connection layer disposed on the second pixel pad; devices disposed on the second connection layer to control the photoelectric conversion unit; and a second substrate disposed on the second connection layer and the devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram of an image sensor according to an exemplary embodiment of the inventive concept;

[0014] Figure 2 is a circuit diagram of a pixel circuit included in an image sensor according to an exemplary embodiment of the inventive concept;

[0015] Figure 3 is a plan view of a first structure included in an image sensor according to an exemplary embodiment of the inventive concept;

[0016] Figure 4 is along Figure 3 is a cross-sectional view of an image sensor according to an exemplary embodiment of the inventive concept taken along line BB′;

[0017] Figure 5 is along Figure 3 is a cross-sectional view of an image sensor according to an exemplary embodiment of the inventive concept taken along line BB′;

[0018] Figure 6 is a plan view of a first structure included in an image sensor according to an exemplary embodiment of the inventive concept;

[0019] Figure 7 is along Figure 6 is a cross-sectional view of an image sensor according to an exemplary embodiment of the inventive concept taken along line BB′;

[0020] Figure 8 is a circuit diagram of a shared pixel circuit included in an image sensor according to an exemplary embodiment of the inventive concept;

[0021] Figure 9 is a plan view of a first structure included in an image sensor according to an exemplary embodiment of the inventive concept;

[0022] Figure 10 is along Figure 9 is a cross-sectional view of an image sensor according to an exemplary embodiment of the inventive concept taken along line BB′;

[0023] Figure 11 is a circuit diagram of a shared pixel circuit included in an image sensor according to an exemplary embodiment of the inventive concept; and

[0024] Figure 12 is a plan view of a first structure included in an image sensor according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0025] In this specification, the Z direction shown in the drawings may be referred to as the vertical direction, and any direction perpendicular to the Z direction, for example, the X direction or the Y direction, may be referred to as the horizontal direction. Further, in a plan view, objects overlapping each other in the Z direction may be referred to as overlapping each other. In an exemplary embodiment, the X direction is substantially perpendicular or completely perpendicular to the Y direction.

[0026] In this specification, the overlap of the first object and the second object in the Z direction means that the projection of the first object on a plane perpendicular to the Z direction (e.g., the XY plane) overlaps with the projection of the second object on the same plane.

[0027] In this specification, two values described as being substantially the same mean that the difference between the two values is within the difference between two values designed or intended to be the same but which may occur due to manufacturing process variations. For example, two values being substantially the same means that the difference between the two values is within 10% of each of the two values, such as within 5%. As used herein, two values being substantially different means that the difference between the two values is greater than the difference between two values designed or intended to be the same but which may occur due to manufacturing process variations. For example, two values being substantially different means that the difference between the two values is greater than 10%.

[0028] In this specification, the distance between the first object and the second object can be defined as the distance between the center of the first object and the center of the second object.

[0029] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Throughout this application, like reference numerals refer to like elements.

[0030] Figure 1 is a block diagram of an image sensor 1000 according to an exemplary embodiment of the inventive concept.

[0031] Referring to Figure 1 , the image sensor 1000 includes a control register block 1100 (e.g., a control circuit), a timing generator 1200 (e.g., a timing controller or control circuit), a ramp generator 1300 (e.g., a voltage generator), a buffer unit 1400 (e.g., a buffer or buffer circuit), an active pixel sensor array 1500, a row driver 1600 (e.g., a driver circuit), a correlated double sampler 1700, a comparator 1800 (e.g., a comparison circuit), and an analog-to-digital converter 1900.

[0032] The control register block 1100 can generally control the operation of the image sensor 1000. For example, the control register block 1100 can send operation signals to the timing generator 1200, the ramp generator 1300, and the buffer unit 1400. The timing generator 1200 can generate an operation timing reference signal and send the operation timing reference signal to the row driver 1600, the correlated double sampler 1700, the comparator 1800, and / or the analog-to-digital converter 1900. The ramp generator 1300 can generate a ramp signal (or ramp voltage) and send the ramp signal (or ramp voltage) to the correlated double sampler 1700 and / or the comparator 1800. The buffer unit 1400 can temporarily store the image signals to be sent outside the image sensor 1000 and send the image data to an external device. The active pixel sensor array 1500 can sense an external image. The active pixel sensor array 1500 can include a plurality of pixels (e.g., Figure 2 the pixel P shown, Figure 8 the shared pixel 2SP shown, or Figure 11 the shared pixel 4SP shown). The row driver 1600 can selectively activate the rows of the active pixel sensor array 1500. The correlated double sampler 1700 can sample and output the analog signals generated from the active pixel sensor array 1500. The comparator 1800 can generate various reference signals by comparing the data sent from the correlated double sampler 1700 and the slope of the ramp signal fed back according to the analog reference voltage. The analog-to-digital converter 1900 can convert the analog image data into digital image data.

[0033] The active pixel sensor array 1500 can be located within or on the pixel array region PXA of the first substrate 110 of the first structure 100 (e.g., pixel wafer) shown in Figure 4 . Additionally, each of the control register block 1100, the timing generator 1200, the ramp generator 1300, the buffer unit 1400, the row driver 1600, the correlated double sampler 1700, the comparator 1800, and the analog-to-digital converter 1900 can be located on the peripheral region PR of the first substrate 110 of the first structure 100 shown in Figure 4 or on the second substrate 210 of the second structure 200 (e.g., logic wafer).

[0034] Figure 2 is a circuit diagram of the pixel circuit P included in the image sensor according to an exemplary embodiment of the inventive concept.

[0035] Referring to Figure 2 , each pixel circuit P can include a photoelectric conversion unit PD (e.g., a photodiode), a floating diffusion region FD, and a plurality of transistors (such as a transfer transistor TX, a driving transistor DX, a selection transistor SX, and a reset transistor RX).

[0036] The photoelectric conversion unit PD can absorb light to generate and accumulate charges corresponding to the amount or intensity of the light. The transfer transistor TX can include a transfer gate TG. The transfer gate TG can transfer the charges accumulated in the photoelectric conversion unit PD to the floating diffusion region FD. The floating diffusion region FD can incrementally accumulate the charges received from the photoelectric conversion unit PD. The driving transistor DX can be controlled according to the amount of charges accumulated in the floating diffusion region FD. In some embodiments, the pixel circuit P does not include the transfer gate TG. That is, the photoelectric conversion unit PD of the pixel circuit P can be directly connected to the floating diffusion region FD.

[0037] The source of the driving transistor DX can be connected to the power supply voltage VDD, and the drain of the driving transistor DX can be connected to the source of the selection transistor SX. The driving transistor DX can be used as a source follower buffer amplifier, which generates a source-drain current proportional to the charges input to the gate. The driving transistor DX can amplify the potential change in the floating diffusion region FD and transmit the amplified signal to the selection transistor SX.

[0038] The selection transistor SX can include a selection gate SG and can be controlled by a row selection signal input from a row driver (e.g., Figure 1 the row driver 1600 shown). Specifically, the selection transistor SX can output the signal output to the drain of the driving transistor DX to the output line Vout according to the row selection signal.

[0039] The reset transistor RX can reset the charges accumulated in the floating diffusion region FD. For example, the reset transistor RX can include a reset gate RG, the drain of the reset transistor RX can be connected to the floating diffusion region FD, and the source of the reset transistor RX can be connected to the power supply voltage VDD. The reset transistor RX can be controlled by a reset signal. Specifically, the reset transistor RX can transfer the power supply voltage VDD connected to the source of the reset transistor RX to the floating diffusion region FD according to the reset signal. Therefore, the charges accumulated in the floating diffusion region FD can be released by the reset transistor RX, and thus, the floating diffusion region FD can be reset.

[0040] Figure 3 is a plan view of a first structure 100 included in an image sensor 1000 according to an exemplary embodiment of the inventive concept. Figure 4 is along Figure 3 a cross-sectional view of an image sensor 1000 according to an exemplary embodiment of the inventive concept taken along line BB'.

[0041] Refer to Figure 3 and Figure 4, the image sensor 1000 includes a first structure 100 and a second structure 200. The first structure 100 includes a first substrate 110, a plurality of photoelectric conversion units PD in the first substrate 110, a first connection layer 150 disposed on the first substrate 110, and a plurality of first pixel pads 130 disposed on the first connection layer 150. The second structure 200 includes a second substrate 210, devices 220 disposed on the second substrate 210, a second connection layer 250 disposed on the second substrate 210 and the devices 220, and a plurality of second pixel pads 230 disposed on the second connection layer 250. In an exemplary embodiment, since the plurality of first pixel pads 130 are respectively in contact with the plurality of second pixel pads 230, the first structure 100 is in contact with the second structure 200 (e.g., in direct contact). The first structure 100 and the second structure 200 can be bonded by directly bonding between the first pixel pads 130 and the second pixel pads 230.

[0042] In an exemplary embodiment, the first structure 100 further includes a plurality of first peripheral pads 140 disposed on the first connection layer 150, and the second structure 200 further includes a plurality of second peripheral pads 240 disposed on the second connection layer 250. In an exemplary embodiment, the plurality of first peripheral pads 140 are respectively in contact with (e.g., in direct contact with) the plurality of second peripheral pads 240. The first structure 100 and the second structure 200 can be bonded by direct bonding between the first pixel pads 130 and the second pixel pads 230 and between the first peripheral pads 140 and the second peripheral pads 240.

[0043] That is to say, the image sensor 1000 may include a first substrate 110, a plurality of photoelectric conversion units PD in the first substrate 110, a first connection layer 150 disposed on the first substrate 110, a plurality of first pixel pads 130 and a plurality of first peripheral pads 140 disposed on the first connection layer 150, a plurality of second pixel pads 230 respectively located on the plurality of first pixel pads 130, a plurality of second peripheral pads 240 respectively located on the plurality of first peripheral pads 140, a second connection layer 250 disposed on the plurality of second pixel pads 230 and the plurality of second peripheral pads 240, devices 220 disposed on the second connection layer 250, and a second substrate 210 disposed on the second connection layer 250 and the devices 220.

[0044] The first substrate 110 includes a pixel array region PXA, and the pixel array region PXA includes a plurality of pixel regions PX. The plurality of pixel regions PX may be arranged at a constant pitch in the X direction and the Y direction. For example, the pixel regions PX may be equally spaced from each other throughout the pixel array region PXA. In an exemplary embodiment, the pitch DX3 of the plurality of pixel regions PX in the X direction is the same as the length of each pixel region PX in the X direction, and the pitch DY3 of the plurality of pixel regions PX in the Y direction is the same as the length of each pixel region PX in the Y direction. In an exemplary embodiment, the pitch DX3 of the plurality of pixel regions PX in the X direction is the same as the pitch DY3 of the plurality of pixel regions PX. In an exemplary embodiment, the pitch DX3 of the plurality of pixel regions PX in the X direction and the pitch DY3 of the plurality of pixel regions PX in the Y direction are from about 0.5 μm to about 5 μm. In some embodiments, the first substrate 110 further includes a peripheral region PR around the pixel array region PXA. In an exemplary embodiment, the peripheral region PR of the first substrate 110 surrounds the pixel array region PXA of the first substrate 110. The second substrate 210 may be spaced apart from the first substrate 110 in the Z direction. The upper surface of the second substrate 210 faces the lower surface of the first substrate 110.

[0045] The first substrate 110 and the second substrate 210 may include, for example, group-IV semiconductor materials, group-III-V semiconductor materials, group-II-VI semiconductor materials, or combinations thereof. Group-IV semiconductor materials may include, for example, silicon (Si), germanium (Ge), or combinations thereof. Group-III-V semiconductor materials may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), or combinations thereof. Group-II-VI semiconductor materials may include, for example, zinc telluride (ZnTe), cadmium sulfide (CdS), or combinations thereof.

[0046] In an exemplary embodiment, a plurality of photoelectric conversion units PD are respectively located in the plurality of pixel regions PX of the first substrate 110. The photoelectric conversion units PD may include, for example, photodiodes, phototransistors, photogates, or combinations thereof. In an embodiment, the photodiode includes two impurity regions having different conductivity types.

[0047] The photoelectric conversion unit PD may be included in the pixel circuit P. The transmission gate TG and the floating diffusion region FD included in the pixel circuit P may be located on the pixel region PX of the first substrate 110. In some embodiments, different from Figure 4, the transfer gate TG is omitted. In some embodiments, the floating diffusion region FD may be separated from the photoelectric conversion unit PD by an isolation pattern (not shown). In an exemplary embodiment, the floating diffusion region FD includes impurities of a conductivity type different from that of the first substrate 110. The driving transistor DX (see Figure 2 ), the selection transistor SX (see Figure 2 ), and the reset transistor RX (see Figure 2 ) included in the pixel circuit P may be located in the pixel region PX of the first substrate 110. The pixel circuit P may further include a portion of the first conductive pattern 152 of the first connection layer 150 connected to at least one of the photoelectric conversion unit PD, the transfer gate TG, the floating diffusion region FD, the driving transistor DX (see Figure 2 ), the selection transistor SX (see Figure 2 ), and the reset transistor (RX (see Figure 2 )).

[0048] In an exemplary embodiment, the first structure 100 further includes a pixel isolation pattern 160 disposed between the plurality of photoelectric conversion units PD. The pixel isolation pattern 160 may be located at the boundary between the plurality of pixel regions PX of the first substrate 110. The pixel isolation pattern 160 may surround each photoelectric conversion unit PD. The pixel isolation pattern 160 may include an insulating material, which may include, for example, silicon oxide, silicon nitride, or a combination thereof.

[0049] In an exemplary embodiment, the first structure 100 further includes peripheral devices 120 disposed on the peripheral region PR of the first substrate 110. The peripheral devices 120 may include, for example, transistors, capacitors, resistors, or a combination thereof. The peripheral devices 120 and the portion of the first conductive pattern 152 of the first connection layer 150 connected to the peripheral devices 120 may constitute a peripheral circuit. The peripheral circuit may include a logic circuit, a storage circuit, or a combination thereof. The peripheral circuit may include, for example, Figure 1 at least one of the control register block 1100, the timing generator 1200, the ramp generator 1300, the buffer unit 1400, the row driver 1600, the correlated double sampler 1700, the comparator 1800, and the analog-to-digital converter 1900 shown in

[0050] The device 220 disposed on the second substrate 210 may overlap with the pixel array region PXA of the first substrate 110 in the Z direction, overlap with the peripheral region PR of the first substrate 110 in the Z direction, or overlap with both the pixel array region PXA and the peripheral region PR of the first substrate 110 in the Z direction. The device 220 may include, for example, a transistor, a capacitor, a resistor, or a combination thereof. The device 220 and a portion of the second conductive pattern 252 of the second connection layer 250 connected to the device 220 may constitute a circuit. The circuit may include a logic circuit, a storage circuit, or a combination thereof. The circuit may include, for example Figure 1 at least one of the control register block 1100, the timing generator 1200, the ramp generator 1300, the buffer unit 1400, the line driver 1600, the correlated double sampler 1700, the comparator 1800, and the analog-to-digital converter 1900 as shown. For example, the circuit may include a part or all of the circuit for controlling a pixel circuit (e.g., P, 2SP, 4SP) or a photoelectric conversion unit (e.g., PD, Pda, Pdb, Pdc, or Pdd).

[0051] The first connection layer 150 may be located on the lower surface of the first substrate 110, and the second connection layer 250 may be located on the upper surface of the second substrate 210. In an exemplary embodiment, the first connection layer 150 includes a first insulating layer 151 disposed on the lower surface of the first substrate 110 and a first conductive pattern 152 disposed in the first insulating layer 151. In an exemplary embodiment, the second connection layer 250 includes a second insulating layer 251 disposed on the upper surface of the second substrate 210 and a second conductive pattern 252 disposed in the second insulating layer 251. Each of the first insulating layer 151 and the second insulating layer 251 may include a plurality of insulating layers. Each of the first conductive pattern 152 and the second conductive pattern 252 may include a plurality of conductive lines (e.g., wires) and a plurality of conductive vias.

[0052] The first insulating layer 151 and the second insulating layer 251 may include an insulating material, which may include, for example, silicon oxide, silicon nitride, a low-k material, or a combination thereof. The low-k material may be a material having a dielectric constant lower than that of silicon oxide, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), organosilicate glass (OSG), spin-on glass (SOG), spin-on polymer, or a combination thereof. The first conductive pattern 152 and the second conductive pattern 252 may include a conductive material, which may include, for example, tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), or a combination thereof.

[0053] In an exemplary embodiment, the materials forming the first insulating layer 151 and the second insulating layer 251 have a higher transmittance with respect to light in the operating wavelength range (such as visible spectrum, IR spectrum, or UV spectrum) compared to the materials forming the first conductive pattern 152 and the second conductive pattern 252. In an exemplary embodiment, the materials forming the first conductive pattern 152 and the second conductive pattern 252 have a higher reflectance with respect to light in the operating wavelength range compared to the materials forming the first insulating layer 151 and the second insulating layer 251.

[0054] The first connection layer 150 may electrically connect a plurality of pixel circuits P, a peripheral device 120, and a plurality of first peripheral pads 140. That is, the first conductive pattern 152 of the first connection layer 150 may contact the plurality of pixel circuits P, the peripheral device 120, and the plurality of first peripheral pads 140. The first conductive pattern 152 of the first connection layer 150 may include a portion (e.g., a first line) connecting the plurality of pixels P to the peripheral device 120 and a portion (e.g., a second line) connecting the peripheral device 120 to the plurality of first peripheral pads 140. In an exemplary embodiment, the first conductive pattern 152 of the first connection layer 150 does not contact at least one of the plurality of first pixel pads 130. In another exemplary embodiment, the first conductive pattern 152 of the first connection layer 150 does not contact all of the plurality of first pixel pads 130. That is, the first connection layer 150 does not electrically connect the plurality of pixel circuits P to the plurality of first pixel pads 130. In other words, the plurality of first pixel pads 130 may be dummy pads that do not provide electrical connection.

[0055] The second connection layer 250 may electrically connect the device 220 to the plurality of second peripheral pads 240. That is, the second conductive pattern 252 of the second connection layer 250 may contact the device 220 and the plurality of second peripheral pads 240. In an exemplary embodiment, the second conductive pattern 252 of the second connection layer 250 does not contact at least one of the plurality of second pixel pads 230. In another exemplary embodiment, the second conductive pattern 252 of the second connection layer 250 does not contact all of the plurality of second pixel pads 230. That is, the second connection layer 250 does not electrically connect the device 220 to the plurality of second pixel pads 230. In other words, the plurality of second pixel pads 230 may be dummy pads that do not provide electrical connection.

[0056] A plurality of first pixel pads 130 may be located on a portion of a first connection layer 150 on a pixel array region PXA of a first substrate 110. That is, the plurality of first pixel pads 130 may overlap the pixel array region PXA of the first substrate 110 in the Z direction. In an exemplary embodiment, the first pixel pads 130 are positioned such that they do not overlap the photoelectric conversion units PD in the Z direction. A plurality of second pixel pads 230 may be respectively located on the plurality of first pixel pads 130 to be in contact with the plurality of first pixel pads 130 respectively. The plurality of first pixel pads 130 and the plurality of second pixel pads 230 may be used to directly bond a first structure 100 and a second structure 200.

[0057] In an exemplary embodiment, each first pixel pad 130 includes a filling layer 131 and a barrier layer 132 between the filling layer 131 and the first connection layer 150. In an exemplary embodiment, each second pixel pad 230 includes a filling layer 231 and a barrier layer 232 between the filling layer 231 and the second connection layer 250. The filling layer 131 of the first pixel pad 130 and the filling layer 231 of the second pixel pad 230 may be used for direct bonding. In an exemplary embodiment, the filling layers 131 and 231 include materials having a high reflectivity. For example, the filling layers 131 and 231 corresponding to a pixel region PX may reflect light toward the photoelectric conversion units PD within the same pixel region PX. For example, the filling layer 131 of the first pixel pad 130 and the filling layer 231 of the second pixel pad 230 may include copper (Cu), aluminum (Al), or a combination thereof. The barrier layer 132 of the first pixel pad 130 and the barrier layer 232 of the second pixel pad 230 may prevent the materials of the filling layer 131 of the first pixel pad 130 and the filling layer 231 of the second pixel pad 230 from diffusing into a first insulating layer 151 of the first connection layer 150 and a second insulating layer 251 of the second connection layer 250, respectively. In an exemplary embodiment, the barrier layers 132 and 232 include materials having a high reflectivity. For example, the barrier layers 132 and 232 corresponding to a pixel region PX may reflect light toward the photoelectric conversion units PD within the same pixel region PX. For example, the barrier layer 132 of the first pixel pad 130 and the barrier layer 232 of the second pixel pad 230 may include titanium (Ti), tantalum (Ta), tin (Sn), and copper (Cu), aluminum (Al), gold (Au), silver (Ag), or a combination thereof.

[0058] In an exemplary embodiment, a plurality of first pixel pads 130 are provided to relieve bonding stress that may occur when bonding the first structure 100 to the second structure 200 due to differences in the coefficients of thermal expansion between various materials. In an exemplary embodiment, the centers C130 of the plurality of first pixel pads 130 do not overlap the pixel isolation pattern 160 in the Z direction. Positioning the centers C130 to not overlap the pixel isolation pattern 160 can relieve the bonding stress. In an exemplary embodiment, the plurality of first pixel pads 130 do not overlap the pixel isolation pattern 160 in the Z direction. Positioning the first pixel pads 130 to not overlap the pixel isolation pattern 160 can relieve the bonding stress. In another exemplary embodiment, the plurality of first pixel pads 130 do not overlap the boundaries between the plurality of pixel regions PX of the first substrate 110 in the Z direction. That is, no first pixel pad 130 may be distributed across two or more adjacent pixel regions PX of the first substrate 110. In an exemplary embodiment, none of the first pixel pads 130 extends to overlap a pair of adjacent pixel regions PX.

[0059] In an exemplary embodiment, the plurality of first pixel pads 130 are arranged in the X direction at a pitch DX1 that is substantially the same as the pitch DX3 of the plurality of pixel regions PX in the X direction. In an exemplary embodiment, the plurality of first pixel pads 130 are arranged in the Y direction at a pitch DY1 that is substantially the same as the pitch DY3 of the plurality of pixel regions PX in the Y direction. Accordingly, the plurality of first pixel pads 130 may overlap the plurality of pixel regions PX of the first substrate 110 in the vertical direction, respectively. By arranging the plurality of first pixel pads 130 as described above, when planarizing the first structure 100 using chemical mechanical polishing (CMP), not only can the bonding stress be relieved, but a planar surface can also be obtained.

[0060] In an exemplary embodiment in which the pitch DX1 of the plurality of first pixel pads 130 in the X direction is substantially the same as the pitch DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction, the width DX7 of each of the first pixel pads 130 and the second pixel pads 230 in the X direction is greater than 0 and less than or equal to half of the pitch DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction. Similarly, in an exemplary embodiment in which the pitch DY1 of the plurality of first pixel pads 130 in the Y direction is substantially the same as the pitch DY3 of the plurality of pixel regions PX of the first substrate 110 in the Y direction, the width DY7 of each of the first pixel pads 130 and the second pixel pads 230 in the Y direction is greater than 0 and less than or equal to half of the pitch DY3 of the plurality of pixel regions PX of the first substrate 110 in the Y direction. As a result, when the first structure 100 and the second structure 200 are combined, even when the first structure 100 and the second structure 200 are not aligned, it is possible to prevent one first pixel pad 130 from contacting two second pixel pads 230 or to prevent one second pixel pad 230 from contacting two first pixel pads 130. For example, the width DX7 in the X direction and the width DY7 in the Y direction of the first pixel pad 130 and the second pixel pad 230 may be from about 0.1 μm to about 2.5 μm. In the case where the width DX7 in the X direction and the width DY7 in the Y direction of the first pixel pad 130 and the second pixel pad 230 are too small, it may be difficult to align the plurality of first pixel pads 130 with the plurality of second pixel pads 230 respectively when the first structure 100 and the second structure 200 are combined.

[0061] In an exemplary embodiment, the plurality of first pixel pads 130 are arranged to reflect light that is not absorbed by the plurality of photoelectric conversion units PD and is emitted from the plurality of photoelectric conversion units PD through the first connection layer 150. For example, the first pixel pads 130 may reflect the unabsorbed light back at the photoelectric conversion units PD so that they absorb more light. To this end, the plurality of first pixel pads 130 may be arranged on a portion of the first connection layer 150 having a high transmittance. For example, a portion of the first connection layer 150 on the pixel region PX of the first substrate 110 includes an overlapping portion 150a that overlaps the first pixel pads 130 in the Z direction and a non-overlapping portion 150b that does not overlap the first pixel pads 130 in the Z direction. In an exemplary embodiment, the transmittance of the overlapping portion 150a of the first connection layer 150 is higher than the transmittance of the non-overlapping portion 150b of the first connection layer 150.

[0062] In other words, in view of the fact that the first insulating layer 151 of the first connection layer 150 includes a material having a high transmittance and the first conductive pattern 152 includes a material having a high reflectivity, the plurality of first pixel pads 130 may be disposed on a portion of the first conductive pattern 152 of the first connection layer 150 where the volume ratio of the first conductive pattern 152 to the first insulating layer 151 is relatively small. For example, the ratio of the total volume of the portion of the first conductive pattern 152 in the overlapping portion 150a of the first connection layer 150 to the total volume of the portion of the first insulating layer 151 in the overlapping portion 150a of the first connection layer 150 may be less than the ratio of the total volume of the portion of the first conductive pattern 152 in the non-overlapping portion 150b of the first connection layer 150 to the total volume of the portion of the first insulating layer 151 in the non-overlapping portion 150b of the first connection layer 150.

[0063] Here, the total volume of the portion of the first insulating layer 151 in the overlapping portion 150a of the first connection layer 150 may be, for example, the sum of the volume of the portion of the first insulating layer 151 in the overlapping portion 150a of the portion of the first connection layer 150 located on one pixel region and the volume of the portion of the first insulating layer 151 in the overlapping portion 150a of the other portion of the first connection layer 150 located on another pixel region when the pixel array region PXA includes two pixel regions PX. That is, the volume ratio of the first conductive pattern 152 to the first insulating layer 151 in any one overlapping portion 150a may be the same as the volume ratio of the first conductive pattern 152 to the first insulating layer 151 in any one non-overlapping portion 150b, but the volume ratio of the first conductive pattern 152 to the first insulating layer 151 distributed on all the overlapping portions 150a in the first connection layer 150 may be less than the volume ratio of the first conductive pattern 152 to the first insulating layer 151 on all the non-overlapping portions 150b in the first connection layer 150. By arranging the plurality of first pixel pads 130 as described above, the amount of light leaking through the relatively low-density region (e.g., the overlapping portion 150a) of the first conductive pattern 152 can be reduced, and thus, the sensitivity of the image sensor 1000 can be improved and crosstalk can be reduced.

[0064] As a result of arranging a plurality of first pixel pads 130 to reduce light leakage, according to an exemplary embodiment, the center C130 of the first pixel pad 130 extends beyond the center CPX of the pixel region PX of the first substrate 110 in the horizontal direction. That is, the center C130 of the first pixel pad 130 does not overlap with the center CPX of the pixel region PX of the first substrate 110 in the Z direction. Further, in embodiments where the pitch DX1 of the plurality of first pixel pads 130 in the X direction is substantially the same as the pitch DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction and / or the pitch DY1 of the plurality of first pixel pads 130 in the Y direction is substantially the same as the pitch DY3 of the plurality of pixel regions PX of the first substrate 110 in the Y direction, the center C130 of each first pixel pad 130 is located at a certain distance (e.g., DX6) away from the center CPX of each pixel region PX of the first substrate 110 in the horizontal direction (e.g., in the X direction). In Figure 3 and Figure 4 , the center C130 of the first pixel pad 130 and the center CPX of the pixel region PX are separated in the X direction, but the center C130 of the first pixel pad 130 and the center CPX of the pixel region PX can be separated in any horizontal direction (including the Y direction).

[0065] A plurality of first peripheral pads 140 may be arranged on a portion of the first connection layer 150 on the peripheral region PR of the first substrate 110. That is, the plurality of first peripheral pads 140 may overlap with the peripheral region PR of the first substrate 110 in the Z direction. A plurality of second peripheral pads 240 may be respectively located on the plurality of first peripheral pads 140 and may respectively contact the plurality of first peripheral pads 140. The plurality of first peripheral pads 140 and the plurality of second peripheral pads 240 may be used for the direct bonding of the first structure 100 and the second structure 200 and may be electrically connected between the first connection layer 150 and the second connection layer 250 (i.e., between the first structure 100 and the second structure 200).

[0066] In an exemplary embodiment, each first peripheral pad 140 includes a filling layer 141 and a barrier layer 142 between the filling layer 141 and the first connection layer 150. In an exemplary embodiment, each second peripheral pad 240 includes a filling layer 241 and a barrier layer 242 between the filling layer 241 and the second connection layer 250. The filling layer 141 of the first peripheral pad 140 and the filling layer 241 of the second peripheral pad 240 can be used for direct bonding. In an exemplary embodiment, the filling layers 141 and 241 include a conductive material. For example, the filling layer 141 of the first peripheral pad 140 and the filling layer 241 of the second peripheral pad 240 can include copper (Cu), aluminum (Al), or a combination thereof. The barrier layer 142 of the first peripheral pad 140 and the barrier layer 242 of the second peripheral pad 240 can include materials that can prevent the filling layer 141 of the first peripheral pad 140 and the filling layer 241 of the second peripheral pad 240 from diffusing into the first insulating layer 151 of the first connection layer 150 and the second insulating layer 251 of the second connection layer 250, respectively. For example, the barrier layer 142 of the first peripheral pad 140 and the barrier layer 242 of the second peripheral pad 240 can include titanium (Ti), tantalum (Ta), tin (Sn), copper (Cu), aluminum (Al), gold (Au), silver (Ag), or a combination thereof.

[0067] In an exemplary embodiment, a plurality of first peripheral pads 140 are arranged to relieve bonding stress. For example, the pitch DX2 of the plurality of first peripheral pads 140 in the X direction can be substantially the same as the pitch DX1 of the plurality of first pixel pads 130 in the X direction. Similarly, the pitch DY2 of the plurality of first peripheral pads 140 in the Y direction can be substantially the same as the pitch DY1 of the plurality of first pixel pads 130 in the Y direction. Therefore, in an embodiment where the pitch DX1 of the plurality of first pixel pads 130 in the X direction is the same as the pitch DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction, the pitch DX2 of the plurality of first peripheral pads 140 in the X direction can be substantially the same as the pitch DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction. Similarly, in an embodiment where the pitch DY1 of the plurality of first pixel pads 130 in the Y direction is the same as the pitch DY3 of the plurality of pixel regions PX of the first substrate 110 in the Y direction, the pitch DY2 of the plurality of first peripheral pads 140 in the Y direction can be substantially the same as the pitch DY3 of the plurality of pixel regions PX of the first substrate 110 in the Y direction. By arranging the plurality of first peripheral pads 140 as described above, when planarizing the first structure 100 using CMP, not only can the bonding stress be relieved, but also a planar surface can be obtained.

[0068] In an exemplary embodiment of the inventive concept, the image sensor 1000 further includes a plurality of microlenses 380 disposed on an upper surface of the first substrate 110. The plurality of microlenses 380 may respectively overlap with the plurality of photoelectric conversion units PD in the Z direction. The microlenses 380 may collect or focus light into the photoelectric conversion units PD.

[0069] In an exemplary embodiment, the image sensor 1000 further includes a plurality of color filters 370 disposed on the upper surface of the first substrate 110. When the image sensor 1000 includes the plurality of microlenses 380, the plurality of color filters 370 may be respectively positioned between the first substrate 110 and the plurality of microlenses 380. The plurality of color filters 370 may be respectively disposed on the plurality of photoelectric conversion units PD. The color filters 370 may allow light having a specific wavelength to pass therethrough, such that the light having the specific wavelength reaches the photoelectric conversion units PD. The plurality of color filters 370 may form a color filter array including, for example, a red filter, a green filter, and a blue filter. However, the color filters 370 may further include a yellow filter, a magenta filter, a cyan filter, and / or a white filter.

[0070] The image sensor 1000 according to an exemplary embodiment of the inventive concept includes a plurality of first pixel pads 130 and a plurality of second pixel pads 230. The plurality of first pixel pads 130 and the plurality of second pixel pads 230 may be used for direct bonding of the first structure 100 and the second structure 200. By appropriately arranging the plurality of first pixel pads 130 and the plurality of second pixel pads 230, the bonding stress that may occur when bonding the first structure 100 to the second structure 200 due to differences in the coefficients of thermal expansion between various materials may be alleviated. Additionally or alternatively, by appropriately arranging the plurality of first pixel pads 130 and the plurality of second pixel pads 230, light that is not absorbed by the photoelectric conversion units PD and is emitted through the first connection layer 150 from the photoelectric conversion units PD may be reflected, and thus, light leakage may be reduced. Therefore, the sensitivity of the image sensor 1000 may be increased and crosstalk may be reduced.

[0071] Figure 5 is a cross-sectional view of the image sensor 1000b according to an exemplary embodiment of the inventive concept taken along line BB'. The differences between the image sensor 1000 shown below and the image sensor 1000b shown Figure 3 will be described below. Figure 4 in Figure 5 will be described.

[0072] Reference Figure 5, the first conductive pattern 152 of the first connection layer 150 contacts at least one of the plurality of first pixel pads 130. In another exemplary embodiment, the first conductive pattern 152 of the first connection layer 150 contacts all of the plurality of first pixel pads 130. In other words, the plurality of first pixel pads 130 are not dummy pads. In some embodiments, the first connection layer 150 may electrically connect the peripheral device 120 to the plurality of first pixel pads 130. That is, the first conductive pattern 152 of the first connection layer 150 may further include a portion that electrically connects the peripheral device 120 to the plurality of first pixel pads 130. In an exemplary embodiment, the first connection layer 150 electrically connects the plurality of pixel circuits P to the plurality of first pixel pads 130 respectively. That is, the first conductive pattern 152 of the first connection layer 150 may further include a portion that electrically connects the plurality of pixel circuits P to the plurality of first pixel pads 130 respectively.

[0073] In an exemplary embodiment, the second conductive pattern 252 of the second connection layer 250 contacts at least one of the plurality of second pixel pads 230. In another exemplary embodiment, the second connection layer 250 contacts all of the plurality of second pixel pads 230. In other words, the plurality of second pixel pads 230 are not dummy pads. In an exemplary embodiment, the second connection layer 250 electrically connects the device 220 to the plurality of second pixel pads 230. That is, the second conductive pattern 252 of the second connection layer 250 may further include a portion that electrically connects the device 220 to the plurality of second pixel pads 230.

[0074] In an exemplary embodiment, the second structure 200b further includes a plurality of pixel devices 260 disposed on the second substrate 210. The plurality of pixel devices 260 may include, for example, capacitors, resistors, transistors, or combinations thereof. The pixel devices 260 may overlap the pixel array region PXA of the first substrate 110 in the Z direction.

[0075] In an exemplary embodiment, the second connection layer 250 connects the plurality of pixel devices 260 to the device 220. That is, the second conductive pattern 252 of the second connection layer 250 may further include a portion that connects the plurality of pixel devices 260 to the device 220. In an exemplary embodiment, the second connection layer 250 electrically connects the plurality of pixel devices 260 to the plurality of second pixel pads 230 respectively. That is, the second conductive pattern 252 of the second connection layer 250 may further include a portion that electrically connects the plurality of pixel devices 260 to the plurality of second pixel pads 230 respectively.

[0076] Figure 6 is a plan view of the first structure 100c included in the image sensor 1000c according to an exemplary embodiment of the inventive concept. Figure 7 is along Figure 6Cross-sectional view of the image sensor 1000c according to an embodiment of the inventive concept taken along line BB'. Hereinafter, the differences between the image sensor 1000 shown in Figure 3 and Figure 4 and the image sensor 1000c shown in Figure 6 and Figure 7 will be described.

[0077] Referring to Figure 6 and Figure 7 , in an exemplary embodiment, the pitch DX1 of the plurality of first pixel pads 130 in the X direction is substantially equal to twice the pitch DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction. In an exemplary embodiment, the pitch DX1 of the plurality of first pixel pads 130 in the X direction is substantially the same as a value obtained by multiplying the pitch DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction by a natural number. The natural number can be any natural number of 1 or greater, such as 1, 2, 3, 4, etc. Similarly, in an exemplary embodiment, the pitch DY1 of the plurality of first pixel pads 130 in the Y direction is substantially the same as a value obtained by multiplying the pitch DY3 of the plurality of pixel regions PX of the first substrate 110 in the Y direction by an arbitrary natural number (e.g., 2). By arranging the plurality of first pixel pads 130 as described above, when planarizing the first structure 100c using CMP, not only can the bonding stress be reduced, but also a planar surface can be obtained.

[0078] In an exemplary embodiment, the pitch DX2 of the plurality of first peripheral pads 140 in the X direction is substantially the same as a value obtained by multiplying the pitch DX3 of the plurality of pixel regions PX of the first substrate 110 in the X direction by an arbitrary natural number (e.g., 2). In an exemplary embodiment, the pitch DY2 of the plurality of first peripheral pads 140 in the Y direction is substantially the same as a value obtained by multiplying the pitch DX3 of the plurality of pixel regions PX of the first substrate 110 in the Y direction by an arbitrary natural number (e.g., 2). By arranging the plurality of first peripheral pads 140 as described above, when planarizing the first structure 100c using CMP, not only can the bonding stress be reduced, but also a planar surface can be obtained.

[0079] Figure 8 is Figure 10 A circuit diagram of the shared pixel circuit 2SP included in the image sensor 1000d according to an exemplary embodiment of the inventive concept shown in Figure 2 Hereinafter, the differences between the pixel circuit P shown in Figure 8 and the shared pixel circuit 2SP shown in

[0080] Referring to Figure 8 , the shared pixel circuit 2SP includes a shared floating diffusion region FD (seeFigure 2 ) two pixel circuits P (see Figure 2 ). Specifically, the shared pixel circuit 2SP includes a first photoelectric conversion unit PDa, a second photoelectric conversion unit PDb, a first transfer transistor TXa, a second transfer transistor TXb, a shared floating diffusion region 2SFD, a driving transistor DX, a selection transistor SX, and a reset transistor RX. The first transfer transistor TXa may include a first transfer gate TGa, and the second transfer transistor TXb may include a second transfer gate TGb. The first transfer gate TGa may transfer the charge accumulated in the first photoelectric conversion unit PDa to the shared floating diffusion region 2SFD, and the second transfer gate TGb may transfer the charge accumulated in the second photoelectric conversion unit PDb to the shared floating diffusion region 2SFD. The driving transistor DX, the selection transistor SX, and the reset transistor RX may be connected to the shared floating diffusion region 2SFD.

[0081] Figure 9 is a plan view of a first structure 100d included in an image sensor 1000d according to an exemplary embodiment of the inventive concept. Figure 10 is along Figure 9 a cross-sectional view of an image sensor 1000d according to an exemplary embodiment of the inventive concept taken along line BB′ of Figure 3 and Figure 4 The differences between the image sensor 1000 shown in Figure 9 and Figure 10 the image sensor 1000d shown in

[0082] Referring to Figure 9 and Figure 10 , the pixel array region PXA of the first substrate 110 includes a plurality of shared pixel regions 2SPX. Each shared pixel region 2SPX includes a first pixel region PXa and a second pixel region PXb adjacent to each other. In an exemplary embodiment, the plurality of shared pixel regions 2SPX are arranged at a specific pitch in the X direction and the Y direction. In an exemplary embodiment, the pitch DX5 of the plurality of shared pixel regions 2SPX in the X direction is the same as the X-direction length of each shared pixel region 2SPX, and the pitch DY5 of the plurality of shared pixel regions 2SPX in the Y direction is the same as the Y-direction length of each shared pixel region 2SPX. In an exemplary embodiment, the pitch DX5 is twice the pitch DY5.

[0083] A plurality of first photoelectric conversion units PDa are respectively located in a plurality of first pixel regions PXa of the first substrate 110, and a plurality of second photoelectric conversion units PDb are respectively located in a plurality of second pixel regions PXb of the first substrate 110. In an exemplary embodiment, a pixel separation pattern 160 is located between the first photoelectric conversion unit PDa and the second photoelectric conversion unit PDb.

[0084] The first photoelectric conversion unit PDa and the second photoelectric conversion unit PDb are included in the shared pixel circuit 2SP. In an exemplary embodiment, the first transfer gate TGAa included in the shared pixel circuit 2SP is located on the first pixel region PXa of the first substrate 110, and the second transfer gate TGb included in the shared pixel circuit 2SP is located on the second pixel region PXb of the first substrate 110. The shared floating diffusion region 2SFD included in the shared pixel circuit 2SP may be distributed on the first pixel region PXa and the second pixel region PXb of the first substrate 110. For example, the shared floating diffusion region 2SFD may extend to overlap with the first pixel region PXa and the second pixel region PXb. The driving transistor DX (see Figure 8 ), the selection transistor SX (see Figure 8 ), or the reset transistor RX (see Figure 8 ) included in the shared pixel circuit 2SP may be located on the shared pixel region 2SPX of the first substrate 110.

[0085] A plurality of first pixel pads 130a and a plurality of second pixel pads 130b are located on the first connection layer 150, and a plurality of third pixel pads 230a and a plurality of fourth pixel pads 230b are located on the second connection layer 250. In an exemplary embodiment, a plurality of third pixel pads 230a are located on a plurality of first pixel pads 130a to respectively contact the plurality of first pixel pads 130a. In an exemplary embodiment, a plurality of fourth pixel pads 230b are located on a plurality of second pixel pads 130b to respectively contact the plurality of second pixel pads 130b. The plurality of first pixel pads 130a and the plurality of second pixel pads 130b may be located on a part of the first connection layer 150 in the pixel array region PXA of the first substrate 110. That is, the plurality of first pixel pads 130a and the plurality of second pixel pads 130b may overlap with the pixel array region PXA of the first substrate 110 in the Z direction.

[0086] In an exemplary embodiment, the distance DXFa between the first pixel pad 130a and the shared floating diffusion region 2SFD in the horizontal direction (e.g., the X direction) is substantially the same as the distance DXFb between the second pixel pad 130b and the shared floating diffusion region 2SFD in the horizontal direction (e.g., the X direction). Here, the distance DXFa between the first pixel pad 130a and the shared floating diffusion region 2SFD in the horizontal direction (e.g., the X direction) can be defined as the distance between the center C130a2 of the first pixel pad 130a and the center CFD of the shared floating diffusion region 2SFD in the horizontal direction (e.g., the X direction). Additionally, the distance DXFb between the second pixel pad 130b and the shared floating diffusion region 2SFD in the horizontal direction (e.g., the X direction) can be defined as the distance between the center C130b2 of the second pixel pad 130b and the center CFD of the shared floating diffusion region 2SFD in the horizontal direction (e.g., the X direction).

[0087] In an exemplary embodiment, the centers C130a2 of the plurality of first pixel pads 130a and the centers C130b2 of the plurality of second pixel pads 130b do not overlap with the pixel isolation pattern 160 in the Z direction. In another exemplary embodiment, the plurality of first pixel pads 130a and the plurality of second pixel pads 130b do not overlap with the pixel isolation pattern 160 in the Z direction. In another exemplary embodiment, each of the first pixel pad 130a and the second pixel pad 130b does not overlap with the boundary between the first pixel region PXa and the second pixel region PXb of the first substrate 110 in the Z direction. That is, any first pixel pad 130a may not be distributed on the first pixel region PXa and the second pixel region PXb, and any second pixel pad 130b may also not be distributed on the first pixel region PXa and the second pixel region PXb. In an exemplary embodiment, the first pixel pad 130a does not extend to overlap with the second pixel region PXb, and the second pixel pad 130b does not extend to overlap with the first pixel region PXa.

[0088] In an exemplary embodiment, the pitch DX1a of the plurality of first pixel pads 130a in the X direction and the pitch DX1b of the plurality of second pixel pads 130b in the X direction are substantially the same as a value obtained by multiplying the pitch DX5 of the plurality of shared pixel regions 2SPX in the X direction by a natural number. For example, the pitch DX1a of the plurality of first pixel pads 130a in the X direction and the pitch DX1b of the plurality of second pixel pads 130b in the X direction may be substantially the same as the pitch DX5 of the plurality of shared pixel regions 2SPX in the X direction. In an exemplary embodiment, the pitch DY1a of the plurality of first pixel pads 130a in the Y direction and the pitch DY1b of the plurality of second pixel pads 130b in the Y direction are substantially the same as a value obtained by multiplying the pitch DY5 of the plurality of shared pixel regions 2SPX in the Y direction by a natural number. For example, the pitch DY1a of the plurality of first pixel pads 130a in the Y direction and the pitch DY1b of the plurality of second pixel pads 130b in the Y direction may be substantially the same as the pitch DY5 of the plurality of shared pixel regions 2SPX in the Y direction. In an exemplary embodiment, the first pixel pad 130a overlaps with the first pixel region PXa of the first substrate 110 in the Z direction, and the second pixel pad 130b overlaps with the second pixel region PXb of the first substrate 110 in the Z direction. By arranging the plurality of first pixel pads 130a and the plurality of second pixel pads 130b as described above, when planarizing the first structure 100d using CMP, not only can the bonding stress be reduced, but also a planar surface can be obtained.

[0089] When a portion of the first connection layer 150 disposed on the shared pixel region 2SPX of the first substrate 110 includes an overlapping portion (the overlapping portion includes a first overlapping portion 150a1 overlapping with the first pixel pad 130a in the Z direction and a second overlapping portion 150a2 overlapping with the second pixel pad 130b in the Z direction) and a non-overlapping portion 150b that does not overlap with the first pixel pad 130a in the Z direction and does not overlap with the second pixel pad 130b in the Z direction, the transmittance of the overlapping portions 150a1 and 150a2 of the first connection layer 150 may be higher than the transmittance of the non-overlapping portion 150b of the first connection layer 150.

[0090] In an exemplary embodiment, the ratio of the total volume of the portions of the first conductive pattern 152 in the overlapping portions 150a1 and 150a2 of the first connection layer 150 to the total volume of the portions of the first insulating layer 151 in the overlapping portions 150a1 and 150a2 of the first connection layer 150 is less than the ratio of the total volume of the portions of the first conductive pattern 152 in the non - overlapping portion 150b of the first connection layer 150 to the total volume of the portions of the first insulating layer 151 in the non - overlapping portion 150b of the first connection layer 150. By arranging a plurality of first pixel pads 130 as described above, light leakage can be reduced. Therefore, the sensitivity of the image sensor 1000d can be improved, and crosstalk can be reduced.

[0091] As a result of arranging a plurality of first pixel pads 130a and a plurality of second pixel pads 130b to reduce light leakage, the in - shared - pixel - region distance DXab1 in the horizontal direction (e.g., the X - direction) between the first pixel pad 130a in the first shared pixel region and the second pixel pad 130b in the first shared pixel region can be substantially different from the inter - shared - pixel - region distance DXab2 in the horizontal direction (e.g., the X - direction) between the first pixel pad 130a in the first shared pixel region and the second pixel pad 130b in the second adjacent shared pixel region. Here, the in - shared - pixel - region distance DXab1 in the horizontal direction (e.g., the X - direction) between the first pixel pad 130a and the second pixel pad 130b can be defined as the distance in the horizontal direction (e.g., the X - direction) between the center C130a2 of the first pixel pad 130a and the center C130b2 of the second pixel pad 130b that overlap the same shared pixel region 2SPX in the Z - direction. Additionally, the distance DXab2 in the horizontal direction (e.g., the X - direction) between the first pixel pad 130a and the second pixel pad 130b can be defined as the distance in the horizontal direction (e.g., the X - direction) between the center C130a2 of the first pixel pad 130a and the center C130b1 of the second pixel pad 130b that overlap two adjacent shared pixel regions 2SPX in the Z - direction, respectively.

[0092] A plurality of first peripheral pads 140a and a plurality of second peripheral pads 140b can be located on a portion of the first connection layer 150 in the peripheral region PR of the first substrate 110. That is, a plurality of first peripheral pads 140a and a plurality of second peripheral pads 140b can overlap the peripheral region PR of the first substrate 110 in the Z - direction. In an exemplary embodiment, a plurality of third peripheral pads 240a are respectively located on a plurality of first peripheral pads 140a to respectively contact the plurality of first peripheral pads 140a. In an exemplary embodiment, a plurality of fourth peripheral pads 240b are respectively located on a plurality of second peripheral pads 140b to respectively contact the plurality of second peripheral pads 140b.

[0093] In an exemplary embodiment, the pitch DX2a of the plurality of first peripheral pads 140a in the X direction is substantially the same as the pitch DX1a of the plurality of first pixel pads 130a in the X direction, and the pitch DX2b of the plurality of second peripheral pads 140b in the X direction is substantially the same as the pitch DX1b of the plurality of second pixel pads 130b in the X direction. Similarly, in an exemplary embodiment, the pitch DY2a of the plurality of first peripheral pads 140a in the Y direction is substantially the same as the pitch DY1a of the plurality of first pixel pads 130a in the Y direction, and the pitch DY2b of the second peripheral pads 140b in the Y direction is substantially the same as the pitch DY1b of the plurality of second pixel pads 130b in the Y direction. Accordingly, the pitch DX2a of the plurality of first peripheral pads 140a in the X direction and the pitch DX2b of the plurality of second peripheral pads 140b in the X direction may be substantially the same as the pitch DX5 of the plurality of shared pixel regions 2SPX of the first substrate 110 in the X direction. The pitch DY2a of the plurality of first peripheral pads 140a in the Y direction and the pitch DY2b of the plurality of second peripheral pads 140b in the Y direction may be substantially the same as the pitch DY5 of the plurality of shared pixel regions 2SPX of the first substrate 110 in the Y direction. By arranging the plurality of first peripheral pads 140a and the plurality of second peripheral pads 140b as described above, when planarizing the first structure 100d using CMP, not only can the bonding stress be reduced, but also a flat surface can be obtained.

[0094] Figure 11 is a circuit diagram of a shared pixel circuit 4SP included in an image sensor according to an exemplary embodiment of the inventive concept. Hereinafter, Figure 2 the difference between the pixel circuit P shown in Figure 11 and the shared pixel circuit 4SP shown in

[0095] will be described with reference to Figure 11 , the shared pixel circuit 4SP includes four pixel circuits P (see Figure 2 ) sharing a floating diffusion region FD (see Figure 2) Specifically, the shared pixel circuit 4SP includes first to fourth photoelectric conversion units PDa, PDb, PDc, and PDd, first to fourth transfer transistors TXa, TXb, TXc, and TXd, a shared floating diffusion region 4SFD, a driving transistor DX, a selection transistor SX, and a reset transistor RX. The first to fourth transfer transistors TXa, TXb, TXc, and TXd may respectively include first to fourth transfer gates TGa, TGb, TGc, and TGd. The first to fourth transfer gates TGa, TGb, TGc, and TGd may transfer the charges accumulated in the first to fourth photoelectric conversion units PDa, PDb, PDc, and PDd to the shared floating diffusion region 4SFD, respectively. The driving transistor DX, the selection transistor SX, and the reset transistor RX may be connected to the shared floating diffusion region 4SFD.

[0096] Figure 12 is a plan view of a first structure 100e included in an image sensor according to an exemplary embodiment of the inventive concept. The following will describe Figure 9 the difference between the first structure 100d shown in Figure 12 and the first structure 100e shown in

[0097] Referring to Figure 12 , the pixel array region PXA of the first substrate 110 includes a plurality of shared pixel regions 4SPX. Each shared pixel region 4SPX includes adjacent first to fourth pixel regions PXa, PXb, PXc, and PXd. A plurality of third photoelectric conversion units PDc are respectively located in a plurality of third pixel regions PXc of the first substrate 110, and a plurality of fourth photoelectric conversion units PDd are located in a plurality of fourth pixel regions PXd of the first substrate 110. In the exemplary embodiment, the third transfer gate TGc is located on the third pixel region PXc of the first substrate 110, and the fourth transfer gate TGd is located on the fourth pixel region PXd of the first substrate 110. The shared floating diffusion region 4SFD may be distributed over the first pixel region PXa, the second pixel region PXb, the third pixel region PXc, and the fourth pixel region PXd of the first substrate 110. For example, the shared floating diffusion region 4SFD may extend to overlap with the first pixel region PXa, the second pixel region PXb, the third pixel region PXc, and the fourth pixel region PXd.

[0098] The first structure 100e further includes a plurality of fifth pixel pads 130c and a plurality of sixth pixel pads 130d. The plurality of fifth pixel pads 130c and the plurality of sixth pixel pads 130d may overlap the pixel array region PXA of the first substrate 110 in the Z direction.

[0099] In an exemplary embodiment, the distance DYFa between the first pixel pad 130a and the shared floating diffusion region 4SFD in the horizontal direction (e.g., the Y direction) and the distance DYFc between the fifth pixel pad 130c and the shared floating diffusion region 4SFD in the horizontal direction (e.g., the Y direction) are substantially the same. Here, the distance DYFa between the first pixel pad 130a and the shared floating diffusion region 4SFD in the horizontal direction (e.g., the Y direction) can be defined as the distance in the horizontal direction (e.g., the Y direction) between the center C130a2 of the first pixel pad 130a and the center C4FD of the shared floating diffusion region 4SFD. In addition, the distance DYFc between the fifth pixel pad 130c and the shared floating diffusion region 4SFD in the horizontal direction (e.g., the Y direction) can be defined as the distance in the horizontal direction (e.g., the Y direction) between the center C130c2 of the fifth pixel pad 130c and the center C4FD of the shared floating diffusion region 4SFD.

[0100] In an exemplary embodiment, the pitch DX1c of the plurality of fifth pixel pads 130c in the X direction and the pitch DX1d of the plurality of sixth pixel pads 130d in the X direction are substantially the same as the value obtained by multiplying the pitch DX5 of the plurality of shared pixel regions 4SPX in the X direction by a natural number. For example, the pitch DX1c of the plurality of fifth pixel pads 130c in the X direction and the pitch DX1d of the plurality of sixth pixel pads 130d in the X direction can be substantially the same as the pitch DX5 of the plurality of shared pixel regions 4SPX in the X direction. Additionally, the pitch DY1c of the plurality of fifth pixel pads 130c in the Y direction and the pitch DY1d of the plurality of sixth pixel pads 130d in the Y direction can be substantially the same as the value obtained by multiplying the pitch DY5 of the plurality of shared pixel regions 4SPX in the Y direction by a natural number. For example, the pitch DY1c of the plurality of fifth pixel pads 130c in the Y direction and the pitch DY1d of the plurality of sixth pixel pads 130d in the Y direction can be substantially the same as the pitch DY5 of the plurality of shared pixel regions 4SPX in the Y direction. In an exemplary embodiment, the fifth pixel pad 130c overlaps with the third pixel region PXc of the first substrate 110 in the Z direction, and the sixth pixel pad 130d overlaps with the fourth pixel region PXd of the first substrate 110 in the Z direction. By arranging the plurality of fifth pixel pads 130c and the plurality of sixth pixel pads 130d as described above, when the first structure 100e is planarized using CMP, not only can the bonding stress be reduced, but also a planar surface can be obtained.

[0101] As a result of arranging a plurality of fifth pixel pads 130c and a plurality of sixth pixel pads 130d to reduce light leakage, the distance DYac1 in the horizontal direction (e.g., Y direction) between the first pixel pad 130a of the first shared pixel region and the fifth pixel pad 130c in the first shared pixel region can be substantially different from the inter-shared pixel region distance DYac2 in the horizontal direction (e.g., Y direction) between the first pixel pad 130a of the second shared pixel region and the fifth pixel pad 130c in the first shared pixel region. Here, the distance DYac1 in the horizontal direction (e.g., Y direction) between the first pixel pad 130a and the fifth pixel pad 130c can be defined as the distance in the horizontal direction (e.g., Y direction) between the center C130a2 of the first pixel pad 130a overlapping with the same shared pixel region 4SPX in the Z direction and the center C130c2 of the fifth pixel pad 130c. In addition, the inter-shared pixel region distance DYac2 in the horizontal direction (e.g., Y direction) between the first pixel pad 130a and the fifth pixel pad 130c can be defined as the distance in the horizontal direction (e.g., Y direction) between the center C130a4 of the first pixel pad 130a overlapping with two adjacent shared pixel regions 4SPX in the Z direction and the center C130c2 of the fifth pixel pad 130c.

[0102] A plurality of fifth peripheral pads 140c and a plurality of sixth peripheral pads 140d may overlap with the peripheral region PR of the first substrate 110 in the Z direction. In an exemplary embodiment, the pitch DX2c of the plurality of fifth peripheral pads 140c in the X direction is substantially the same as the pitch DX1c of the plurality of fifth pixel pads 130c in the X direction, and the pitch DX2d of the plurality of sixth peripheral pads 140d in the X direction is substantially the same as the pitch DX1d of the plurality of sixth pixel pads 130d in the X direction. Similarly, in an exemplary embodiment, the pitch DY2c of the plurality of fifth peripheral pads 140c in the Y direction is substantially the same as the pitch DY1c of the plurality of fifth pixel pads 130c in the Y direction, and the pitch DY2d of the plurality of sixth peripheral pads 140d in the Y direction is substantially the same as the pitch DY1d of the plurality of sixth pixel pads 130d in the Y direction. Accordingly, the pitch DX2c of the plurality of fifth peripheral pads 140c in the X direction and the pitch DX2d of the plurality of sixth peripheral pads 140d in the X direction may be substantially the same as the pitch DX5 of the plurality of shared pixel regions 4SPX of the first substrate 110 in the X direction. The pitch DY2c of the plurality of fifth peripheral pads 140c in the Y direction and the pitch DY2d of the plurality of sixth peripheral pads 140d in the Y direction may be substantially the same as the pitch DY5 of the plurality of shared pixel regions 4SPX of the first substrate 110 in the Y direction. By arranging the plurality of fifth peripheral pads 140c and the plurality of sixth peripheral pads 140d as described above, when planarizing the first structure 100e using CMP, not only can the bonding stress be alleviated, but also a planar surface can be obtained.

[0103] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it is to be understood that various changes in form and detail may be made without departing from the spirit and scope of the inventive concept.

Claims

1. An image sensor, comprising: The first structure includes a pixel array region and a peripheral region adjacent to the pixel array region, wherein, The pixel array region includes a plurality of pixel regions; A plurality of pixel circuits in the first structure; A first dummy pad in the pixel array region of the first structure; A second dummy pad in the pixel array region of the first structure; And A third dummy pad in the pixel array region of the first structure, wherein, the pitch between the first dummy pad and the second dummy pad in a first direction in a plan view is substantially the same as the pitch between the first dummy pad and the third dummy pad in a second direction perpendicular to the first direction in the plan view, and wherein, the first to third dummy pads are electrically disconnected from the plurality of pixel circuits.

2. The image sensor according to claim 1, wherein, The width of the first dummy pad in the first direction in the plan view is substantially the same as the width of the third dummy pad in the first direction in the plan view.

3. The image sensor according to claim 2, further comprising: A first peripheral pad in the peripheral region of the first structure; and A second peripheral pad in the peripheral region of the first structure, Among them, The pitch between the first dummy pad and the second dummy pad in the first direction in the plan view is substantially the same as the pitch between the first peripheral pad and the second peripheral pad in the first direction in the plan view.

4. The image sensor according to claim 3, wherein, The width of the first dummy pad in the first direction in the plan view is substantially the same as the width of the first peripheral pad in the first direction in the plan view.

5. The image sensor according to claim 4, wherein The first peripheral pad and the second peripheral pad are electrically connected to the plurality of pixel circuits.

6. The image sensor according to claim 3, further comprising: A third peripheral pad in the peripheral region of the first structure, Among them, The pitch between the first dummy pad and the third dummy pad in the second direction in the plan view is substantially the same as the pitch between the first peripheral pad and the third peripheral pad in the second direction in the plan view.

7. The image sensor according to claim 6, wherein, The pixel array region further includes: a plurality of pixel isolation patterns partially penetrating the first structure.

8. The image sensor according to claim 6, wherein, The width of the first dummy pad in the second direction in the plan view is substantially the same as the width of the third peripheral pad in the second direction in the plan view.

9. The image sensor according to claim 1, wherein, The plurality of pixel regions include: A first pixel region, wherein, the first pixel region has a first pitch in the first direction in the plan view, and wherein, the first pitch is different from the pitch between the first dummy pad and the second dummy pad in the first direction in the plan view.

10. The image sensor according to claim 9, wherein, The first pitch is less than half of the pitch between the first dummy pad and the second dummy pad in the first direction in the plan view.

11. An image sensor, comprising: A first structure, including a pixel array region, the pixel array region including a plurality of pixel regions and a peripheral region adjacent to the pixel array region; A plurality of pixel circuits in the first structure; A first dummy pad in the pixel array region of the first structure; A second dummy pad in the pixel array region of the first structure; A first peripheral pad in a peripheral region of the first structure; and a second peripheral pad in the peripheral region of the first structure, wherein a width of the first dummy pad in a first direction in a plan view is substantially the same as a width of the first peripheral pad in the first direction in the plan view, and wherein the first dummy pad and the second dummy pad are electrically disconnected from the plurality of pixel circuits.

12. The image sensor according to claim 11, wherein, A width of the first dummy pad in a second direction in the plan view is substantially the same as a width of the first peripheral pad in the second direction in the plan view, and wherein the second direction is perpendicular to the first direction.

13. The image sensor according to claim 11, wherein, A pitch between the first dummy pad and the second dummy pad in the first direction in the plan view is substantially the same as a pitch between the first peripheral pad and the second peripheral pad in the first direction in the plan view.

14. The image sensor according to claim 11, further comprising: a third dummy pad in a pixel array region of the first structure; and a third peripheral pad in a peripheral region of the first structure, Among them, wherein a pitch between the first dummy pad and the third dummy pad in the second direction in the plan view is substantially the same as a pitch between the first peripheral pad and the third peripheral pad in the second direction in the plan view.

15. The image sensor according to claim 11, wherein, The first peripheral pad and the second peripheral pad are electrically connected to the plurality of pixel circuits.

16. The image sensor according to claim 11, wherein, A width of the first dummy pad in the second direction in the plan view is substantially the same as a width of the second dummy pad in the second direction in the plan view.

17. The image sensor according to claim 13, wherein, The plurality of pixel regions include: a first pixel region, wherein the first pixel region has a first pitch in the first direction in the plan view, and wherein the first pitch is different from a pitch between the first dummy pad and the second dummy pad in the first direction in the plan view.

18. The image sensor according to claim 17, wherein, The first pitch is less than half of a pitch between the first dummy pad and the second dummy pad in the first direction in the plan view.

19. An image sensor, comprising: a first structure including a pixel array region, the pixel array region including a plurality of pixel regions and a peripheral region adjacent to the pixel array region; a plurality of pixel circuits in the first structure; a first dummy pad in the pixel array region of the first structure; a second dummy pad in the pixel array region of the first structure; a first peripheral pad in the peripheral region of the first structure; and a second peripheral pad in the peripheral region of the first structure, wherein a pitch between the first dummy pad and the second dummy pad in the first direction in the plan view is substantially the same as a pitch between the first peripheral pad and the second peripheral pad in the first direction in the plan view, and wherein the first dummy pad and the second dummy pad are electrically disconnected from the plurality of pixel circuits.

20. The image sensor according to claim 19, further comprising: a third dummy pad in the pixel array region of the first structure; and The third peripheral pad in the peripheral region of the first structure Among them, the pitch between the first dummy pad and the third dummy pad in the second direction in the plan view is substantially the same as the pitch between the first peripheral pad and the third peripheral pad in the second direction in the plan view, and wherein the second direction is perpendicular to the first direction.

Images