Image sensor

Abstract

An image sensor includes a substrate including a first surface and a second surface opposite to the first surface; a first photoelectric conversion region; a floating diffusion region; a transfer gate configured to move charges generated in the first photoelectric conversion region to the floating diffusion region; a first conductive layer electrically connected to the transfer gate and vertically overlapping the transfer gate; and a first vertical contact portion including a first surface and a second surface, where the first surface of the first vertical contact portion is connected to the first conductive layer, where the first vertical contact portion vertically overlaps the first conductive layer, where the first surface of the first vertical contact portion has a first width in the second direction, where the second surface of the first vertical contact portion has a second width in the second direction. The first conductive layer has a second width that is at least 1.5 times the first width.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0010356, filed on January 23, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical field

[0003] One or more example embodiments of the present disclosure relate to an image sensor. Background art

[0004] An image sensor is a semiconductor - based sensor that receives light and generates an electrical signal, and may include a pixel array having a plurality of pixels, a logic circuit that drives the pixel array and generates an image, etc. Each pixel may include a photodiode and a pixel circuit that converts the charge generated by the photodiode into an electrical signal. As the number of pixels included in the image sensor increases and the size of each pixel decreases, various methods have been proposed to effectively form the elements provided in each pixel to provide a pixel circuit. Summary of the invention

[0005] Example embodiments provide an image sensor in which, during the formation of a via contact portion, damage to the devices forming the pixel circuit can be significantly reduced, and performance can be improved by forming an extended pattern for the contact portion on the devices.

[0006] According to an aspect of one or more example embodiments, an image sensor includes: a substrate including a first surface and a second surface opposite the first surface; a first photoelectric conversion region for a first pixel in the substrate; a floating diffusion region in the substrate; a transfer gate configured to move the charge generated in the first photoelectric conversion region to the floating diffusion region; a first conductive layer configured to be electrically connected to the transfer gate and vertically overlapping the transfer gate in a first direction perpendicular to the first surface of the substrate; and a first vertical contact portion including a first surface and a second surface, wherein the first surface of the first vertical contact portion is configured to be connected to the first conductive layer, wherein the first vertical contact portion vertically overlaps the first conductive layer in the first direction, wherein the first surface of the first vertical contact portion has a first width in a second direction perpendicular to the first direction, wherein the first conductive layer has a second width in the second direction, and the second width is at least 1.5 times the first width, wherein the first conductive layer is spaced apart from the first surface of the substrate, and wherein the transfer gate is in contact with the first surface of the substrate.

[0007] According to one aspect of one or more example embodiments, an image sensor includes: a substrate including a first surface and a second surface opposite the first surface; a first photoelectric conversion region for a first pixel in the substrate; a second photoelectric conversion region for a second pixel in the substrate; a device isolation film between the first pixel and the second pixel; a floating diffusion region in the substrate; a transfer gate configured to move charges generated in the first photoelectric conversion region to the floating diffusion region; a first conductive layer configured to be electrically connected to the transfer gate; and a first vertical contact portion including a first surface that contacts the first conductive layer, wherein the transfer gate, the first conductive layer, and the first vertical contact portion vertically overlap each other in a first direction perpendicular to the first surface of the substrate, wherein the first surface of the first vertical contact portion has a first width in a second direction perpendicular to the first direction, wherein the first conductive layer has a second width in the second direction, and the second width is greater than the first width, wherein the first conductive layer is spaced apart from the first surface of the substrate, wherein the transfer gate contacts the first surface of the substrate, and wherein the first conductive layer is offset from the device isolation film in the second direction. Description of the Drawings

[0008] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description given in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a simplified block diagram of an image sensor according to one or more example embodiments;

[0010] Figure 2 is a circuit diagram schematically showing a pixel circuit according to one or more example embodiments;

[0011] Figure 3 is schematically showing Figure 2 a pixel of the image sensor;

[0012] Figure 4A and Figure 4B is showing Figure 3 a cross-section of one of the pixels;

[0013] Figure 5A and Figure 5B is Figure 4A an enlarged view of a part of;

[0014] Figure 6 and Figure 7 are enlarged views of pixels of an image sensor according to one or more example embodiments;

[0015] Figure 8 is a diagram schematically showing a pixel of an image sensor according to one or more example embodiments;

[0016] Figure 9 is a cross-sectional view showing a cross-section of a pixel of Figure 8 ;

[0017] Figure 10A is a circuit diagram schematically showing a pixel circuit of an image sensor according to one or more example embodiments, and Figure 10B is a diagram schematically showing Figure 10A the pixel circuit of; and

[0018] Figures 11A to 11H is a cross-sectional view showing a method of manufacturing a pixel of an image sensor of Figure 4A . DETAILED DESCRIPTION

[0019] Hereinafter, one or more example embodiments will be described with reference to the accompanying drawings.

[0020] Figure 1 is a simple block diagram of an image sensor according to one or more example embodiments.

[0021] Referring to Figure 1 , the image sensor 1 may include a pixel array 10, a logic circuit 20, etc.

[0022] The pixel array 10 may include a plurality of pixels PX arranged in an array in multiple rows and columns. Each of the plurality of pixels PX may include at least one photoelectric conversion element that generates charge in response to light, a pixel circuit that generates a pixel signal corresponding to the charge generated by the photoelectric conversion element, etc. The photoelectric conversion element may include a photodiode containing a semiconductor material and / or an organic photodiode containing an organic material.

[0023] For example, the pixel circuit may include a floating diffusion region, a transfer transistor, a reset transistor, a driving transistor, a selection transistor, etc. The configuration of the pixel PX may vary according to the example embodiments. For example, each pixel PX may include an organic photodiode containing an organic material, or may be implemented as a digital pixel. When the pixel PX is implemented as a digital pixel, each pixel PX may include an analog-to-digital converter for outputting a digital pixel signal.

[0024] The logic circuit 20 may include a circuit for controlling the pixel array 10. For example, the logic circuit 20 may include a row driver 21, a readout circuit 22, a column driver 23, a control logic 24, etc. The row driver 21 may drive the pixel array 10 in units of row lines. For example, the row driver 21 generates a transfer control signal for controlling the transfer transistor of the pixel circuit, a reset control signal for controlling the reset transistor, a selection control signal for controlling the selection transistor, etc., and may input the generated signals into the pixel array 10 based on the row lines.

[0025] The readout circuit 22 may include a correlated double sampler (CDS), an analog-to-digital converter (ADC), etc. The correlated double sampler may be connected to the pixel PX through column lines. The correlated double sampler may read pixel signals from the pixel PX connected to the row line selected by the row line selection signal of the row driver 21 through the column lines. The analog-to-digital converter may convert the pixel signals detected by the correlated double sampler into digital pixel signals and send the converted signals to the column driver 23.

[0026] The column driver 23 may include a latch or buffer circuit, an amplifier circuit, etc. capable of temporarily storing digital pixel signals, and may process the digital pixel signals received from the readout circuit 22. The row driver 21, the readout circuit 22, and the column driver 23 may be controlled by the control logic 24. The control logic 24 may include a timing controller for controlling the operation timings of the row driver 21, the readout circuit 22, the column driver 23, etc.

[0027] Among the pixels PX, the pixels PX set at the same position in the horizontal direction may share the same column line. For example, the pixels PX set at the same position in the vertical direction may be simultaneously selected by the row driver 21 and output pixel signals through the column lines. In an exemplary embodiment, the readout circuit 22 may simultaneously obtain pixel signals from the pixels PX selected by the row driver 21 through the column lines. The pixel signals may include a reset voltage and a pixel voltage, and the pixel voltage may be a voltage in which the charge generated in each pixel PX in response to light is reflected in the reset voltage.

[0028] Figure 2 An example of a pixel circuit of an image sensor according to one or more exemplary embodiments is shown.

[0029] Reference Figure 2 , each of a plurality of pixels ( Figure 1 PX in) may include a photoelectric conversion element PD and a pixel circuit, and the pixel circuit may include a transfer transistor TX, a reset transistor RX, a selection transistor SX, a driving transistor DX, etc. Additionally, the pixel circuit may further include a floating diffusion region FD for accumulating the charge generated in the photoelectric conversion element PD.

[0030] Hereinafter, the photoelectric conversion element PD will be described as a photodiode as an example of the photoelectric conversion element PD.

[0031] The photodiode PD may generate and accumulate charge in response to light incident from the outside. According to an exemplary embodiment, the photodiode PD may be replaced with a phototransistor, a photogate, a pinned photodiode, etc.

[0032] The transfer transistor TX can be turned on or off by a transfer control signal input to the transfer gate TG. The transfer transistor TX can move the charge generated in the photodiode PD to the floating diffusion region FD. The floating diffusion region FD can store the charge generated in the photodiode PD. The voltage output by the driving transistor DX can vary according to the amount of charge accumulated in the floating diffusion region FD.

[0033] The reset transistor RX can reset the voltage of the floating diffusion region FD by removing the charge accumulated in the floating diffusion region FD. The drain electrode of the reset transistor RX can be connected to the floating diffusion region FD, and the source electrode can be connected to the power supply voltage VDD. When the reset transistor RX is turned on, the power supply voltage VDD connected to the source electrode of the reset transistor RX is applied to the floating diffusion region FD, and the charge accumulated in the floating diffusion region FD can be removed.

[0034] The driving transistor DX can operate as a source follower buffer amplifier. The driving transistor DX can amplify the voltage change in the floating diffusion region FD and output it to the column lines COL1 and COL2.

[0035] The selection transistor SX can select the pixel PX to be read from among a plurality of pixels PX in units of rows. When the selection transistor SX is turned on, the voltage of the driving transistor DX can be output to the column lines COL1 and COL2. For example, when the selection transistor SX is turned on, the reset voltage or the pixel voltage can be output through the column lines COL1 and COL2.

[0036] Each pixel PX can also include a grounding region GND that can receive the ground voltage. Therefore, each pixel PX can include a grounding region GND, a photodiode PD, a transfer transistor TX, a reset transistor RX, a selection transistor SX, and a driving transistor DX.

[0037] On the other hand, as Figure 2 shown, two or more adjacent pixels PX can share at least some of the transistors included in the pixel circuit. For example, four adjacent pixels PX can share the reset transistor RX, the driving transistors DX1 and DX2, and the selection transistor SX.

[0038] Within the pixel regions PA1 to PA4, four adjacent pixels PX can respectively include transfer transistors TX1 to TX4 having photodiodes PD1 to PD4, a grounding region GND, and transfer gates TG1 to TG4, and floating diffusion regions FD1 to FD4.

[0039] In the example, the first pixel region PA1 in which the first pixel among the four pixels PX is placed may include a ground region GND, a first photodiode PD1, a first floating diffusion region FD1, and a first transfer transistor TX1 having a first transfer gate TG1. In the first pixel region PA1, the first photodiode PD1 may be connected to the first floating diffusion region FD1 through the first transfer transistor TX1. Similarly, second photodiodes PD2 to fourth photodiodes PD4 in second pixel regions PA2 to fourth pixel regions PA4 in which the second pixel to the fourth pixel among the four pixels PX are respectively arranged may be connected to second floating diffusion regions FD2 to fourth floating diffusion regions FD4 through second transfer transistors TX2 to fourth transfer transistors TX4, respectively, where the second transfer transistors TX2 to fourth transfer transistors TX4 respectively include second transfer gates TG2 to fourth transfer gates TG4.

[0040] Among four adjacent pixels PX, the first floating diffusion region FD1 to the fourth floating diffusion region FD4 may be connected to each other through an interconnection or the like to operate as one floating diffusion region FD, and the first transfer transistors TX1 to the fourth transfer transistors TX4 may be commonly connected to one floating diffusion region FD to which the first floating diffusion region FD1 to the fourth floating diffusion region FD4 are connected to each other.

[0041] The pixel circuit shared by four adjacent pixels PX may include a reset transistor RX, a first driving transistor DX1, a second driving transistor DX2, and a selection transistor SX. The reset transistor RX may be controlled by a reset control signal RG, and the selection transistor SX may be controlled by a selection control signal SEL.

[0042] For example, in addition to the transfer transistor TX, each of the four pixel regions PA1 to PA4 may further include an additional transistor. Among the four additional transistors included in the four pixel regions PA1 to PA4, two additional transistors may be connected in parallel to provide the first driving transistor DX1 and the second driving transistor DX2, and one of the remaining two additional transistors may be configured to serve as the selection transistor SX, and the other may be configured to provide the reset transistor RX.

[0043] Reference Figure 2The described pixel circuit is merely an example, and the present disclosure is not limited to this example. For example, one of the four additional transistors can be assigned as the driving transistor DX, one can be assigned as the selection transistor SX, another can be assigned as the reset transistor RX, and the remaining one can be assigned as the dual conversion gain transistor DCX connected in series with the reset transistor RX, thereby implementing an image sensor capable of adjusting the conversion gain of the pixel. Alternatively, the pixel circuit can vary according to the number of transistors included in each pixel PX.

[0044] Hereinafter, reference will be made to Figures 3 to 5B to describe Figure 2 the pixel.

[0045] Figure 3 is a diagram schematically showing Figure 2 the pixel of the image sensor 1, and Figure 4A and Figure 4B are cross-sectional views showing Figure 3 a cross-section of one of the pixels.

[0046] Figure 4A is a cross-sectional view taken along the line I-I' of Figure 3 and Figure 4B is a cross-sectional view taken along the line II-II' of Figure 3 the cross-section. Figure 5A is Figure 4A an enlarged view of the region "A" of Figure 5B and Figure 4A is an enlarged view of the region "B" of

[0047] Referring to Figure 3 According to one or more example embodiments, the pixel 100 of the image sensor 1 can be distinguished from other surrounding pixels by the pixel separator 103. One pixel 100 can include a pixel circuit region disposed within the pixel separator 103. For example, the pixel circuit region includes two pixel regions PX1 and PX2 or PX3 and PX4, and each pixel region PX1, PX2, PX3, PX4 can include a floating diffusion region 110, a transfer gate structure TG, at least one transistor 120, 130, etc. The respective pixel regions PX1 and PX2 or PX3 and PX4 within one pixel circuit region can be spaced apart from each other by the intermediate separation region 102, but the present disclosure is not limited thereto.

[0048] Elements of two pixel regions PX1 and PX2 or PX3 and PX4 provided in a pixel circuit region may be symmetrically arranged with respect to the intermediate separation region 102. The intermediate separation region 102 may include an intermediate separation region 102 extending upward from an intermediate position within a pixel circuit region and an intermediate separation region 102 extending downward from the intermediate position within a pixel circuit region, and the two intermediate separation regions 102 may be spaced apart from each other in a central region of a pixel circuit region. The ground region GND may be placed in the central region.

[0049] The floating diffusion regions 110 in the respective pixel regions PX1, PX2, PX3, and PX4 may be regions doped with impurities of a first conductivity type and may be regions for accumulating charges generated in the accumulation photodiodes 107. At least one contact structure 147 or 149 may be connected to the floating diffusion region 110, and the floating diffusion region 110 may be adjacent to the transfer gate structure TG. The transfer gate structure TG may be adjacent to the photodiode 107 formed within the pixel separator 103 in a first direction (e.g., the Z-axis direction). For example, the impurities of the first conductivity type may be N-type impurities.

[0050] When a first bias voltage is input to the transfer gate structure TG, the charges generated in the photodiode 107 may not move to the floating diffusion region 110. When the voltage of the transfer gate structure TG increases to a second bias voltage higher than the first bias voltage, the charges generated in the photodiode 107 may move to the floating diffusion region 110. For example, the first bias voltage may be a negative voltage, and the second bias voltage may be a positive voltage. The absolute value of the first bias voltage may be less than the absolute value of the second bias voltage.

[0051] In Figure 3 the illustrated exemplary embodiment, the floating diffusion region 110 may extend in a second direction (e.g., the X-axis direction), a third direction (e.g., the Y-axis direction), etc. However, the shape of the floating diffusion region 110 is not limited to Figure 3 the illustrated shape and may be modified in various ways according to the exemplary embodiment.

[0052] The transistors 120 and 130 may provide at least one of the reset transistor RX, the selection transistor SX, and the driving transistors DX1 and DX2 included in the pixel circuit. Refer to Figure 3, the first transistor 120 may include a first gate structure 125 and active regions disposed on both sides of the first gate structure 125, and the second transistor 130 may include a second gate structure 135 and active regions disposed on both sides of the second gate structure 135. The area of each of the active regions may be smaller than the area of the floating diffusion region 110. This may be because the area of the floating diffusion region 110 that accumulates charges generated by the photodiode needs to be ensured to be relatively large.

[0053] On the other hand, the pixel 100 may include a floating diffusion region 110 and at least one impurity region 140 separated from the transistors 120 and 130 in the central region of one pixel circuit area. The impurity region 140 may not contact the transfer gate structure TG and may be separated from the transfer gate structure TG by the device isolation film 105. In an exemplary embodiment, the impurity region 140 may be doped with impurities of a second conductivity type different from that of the floating diffusion region 110 and the active regions. The impurity region 140 may be a ground region GND that receives a ground voltage.

[0054] A contact structure CS may be disposed in the transfer gate structure TG, the floating diffusion region 110, the active regions, and the impurity region 140.

[0055] The contact structure CS may include: first-type contact structures 157, 159 disposed on the transfer gate structure TG; second-type contact structures 147, 149 disposed in the floating diffusion region 110 and the active regions of the transistors 120 and 130; and third-type contact structures 127, 129, 137, and 139 disposed on the gate structures 125 and 135 of the transistors 120 and 130.

[0056] The first-type contact structures (157, 159), the second-type contact structures (147, 149), and the third-type contact structures (137, 139, 127, 129) may respectively include: horizontal contact portions 157, 147, 137, and 127 configured to be in direct contact with the contact objects of the respective elements and conduct electricity on the contact objects of the respective elements; and vertical contact portions 159, 149, 139, and 129 disposed on the horizontal contact portions 157, 147, 137, and 127 and electrically connected to the upper interconnect 174.

[0057] The vertical contact portions 159, 149, 139, and 129 may be contact vias, and may include a conductive material filling the via hole VH penetrating the interlayer insulating layer 160, and may electrically connect the upper interconnect 174 and the lower object. The width of the upper surface of the vertical contact portions 159, 149, 139, and 129 may be greater than the width W3 of the lower surface of the vertical contact portions 159, 149, 139, and 129, and may include inclined side surfaces, the width of which becomes smaller as the inclined side surfaces advance downward. The lower surface of the vertical contact portions 159, 149, 139, and 129 may be circular, but is not limited thereto.

[0058] The area of the horizontal contact portions 157, 147, 137, and 127 may be greater than the area of the lower surface of the vertical contact portions 159, 149, 139, and 129, and for example, may have an area 1.5 times to 10 times the area of the lower surface of the vertical contact portions 159, 149, 139, and 129, and for example, may have an area 2 times to 5 times the area of the lower surface of the vertical contact portions 159, 149, 139, and 129.

[0059] Reference Figure 4A and Figure 4B ,the pixel circuit region may be defined by the pixel separator 103 formed in the substrate 101, and within one pixel circuit region, two pixel regions PX1 and PX2 or PX3 and PX4 may be set based on the intermediate separation region 102.

[0060] The substrate 101 may be a semiconductor substrate. For example, the substrate 101 may be a substrate formed of a semiconductor material, for example, a single crystal silicon substrate.

[0061] The photodiodes 107 may be formed in the substrate 101 within the two pixel regions PX1 and PX2 or PX3 and PX4, respectively. The photodiodes 107 may be adjacent to each transfer gate structure TG in the Z direction perpendicular to one surface of the substrate 101.

[0062] On the other hand, the optical unit 170 may be provided on the first surface of the substrate 101 adjacent to the photodiodes 107 in the Z direction (vertical direction). The optical unit 170 may include a color filter 171, a grid structure 173, a planarization layer 175, a microlens 177, etc. The color filter 171 may be separated from the color filters of other adjacent pixels through the grid structure 173, and may transmit light of a predetermined wavelength band. The microlens 177 may refract the light incident on the pixel 100 and focus the light on the photodiodes 107. The photodiodes 107 may generate charges in response to the light passing through the optical unit 170.

[0063] On the other hand, pixel regions PX1, PX2, PX3, and PX4 may be disposed on the second surface of the substrate 101, and the second surface of the substrate 101 faces the first surface adjacent to the photodiode 107 in the Z direction (vertical direction) relative to the ground. Thus, the optical unit 170 and the pixel regions PX1, PX2, PX3, and PX4 may be disposed on both sides of the photodiode 107 in the first direction (i.e., the Z direction). The pixel regions PX1, PX2, PX3, and PX4 may include a floating diffusion region 110, a transfer gate structure TG adjacent to the floating diffusion region 110, at least one transistor 120, 130, etc.

[0064] On the second surface of the substrate 101, an active region may be defined by a device isolation film 105 within the substrate 101. The source / drain regions 123 and 133 of each circuit element may be doped regions formed within the active region. In an exemplary embodiment, some regions partitioned by the device isolation film 105 may be dummy active regions, which are regions where transistors are not formed. For example, the dummy active region may include a ground region GND.

[0065] The circuit elements 120 and 130 may include elements such as transistors including gate electrodes 125 and 135 and source / drain regions 123 and 133. The gate electrodes 125 and 135 may include a semiconductor material, for example, silicon, germanium, or a combination thereof. The gate electrodes 125 and 135 may include an n-type or p-type doped layer, but may alternatively include an undoped layer. In an exemplary embodiment, the circuit elements 120 and 130 may be a driving transistor DX1 and DX2, a reset transistor RX, and a selection transistor SX. However, the types and arrangement relationships of the circuit elements 120 and 130 may vary differently.

[0066] According to the magnitude of the voltage input to the transfer gate structure TG, the charge generated in the photodiode 107 may be accumulated within the photodiode 107 or moved to the floating diffusion region 110. For example, when a first bias voltage is input to the transfer gate structure TG, the charge is accumulated within the photodiode 107, and when a second bias voltage greater than the first bias voltage is input to the transfer gate structure TG, the charge within the photodiode 107 may be moved to the floating diffusion region 110.

[0067] The floating diffusion region 110 may include a plurality of regions doped with impurities at different concentrations, but is not limited thereto. When the floating diffusion region 110 includes a plurality of regions, as the floating diffusion region 110 moves away from the transfer gate structure TG, the floating diffusion region 110 may be doped at a higher concentration.

[0068] The transfer gate structure TG may include a transfer gate electrode 117, a transfer gate insulating layer 118, a transfer gate spacer 119, etc. The transfer gate electrode 117 may include a conductive material such as polysilicon, metal, or metal silicide, and the first bias voltage and the second bias voltage may be applied to the transfer gate electrode 117. The transfer gate insulating layer 118 may be disposed between the transfer gate electrode 117 and the substrate 101.

[0069] The transfer gate electrode 117 may include a first electrode layer and a second electrode layer, and the first electrode layer and the second electrode layer may have different shapes. In an example, the second electrode layer may be disposed between the first electrode layer and the photodiode 107 in a first direction, and the width of the second electrode layer may become narrower as the second electrode layer approaches the photodiode 107. The second electrode layer may be disposed below the upper surface of the substrate 101 and buried in the substrate 101, and the first electrode layer may have a region disposed at a level higher than the upper surface of the substrate 101.

[0070] The transfer gate insulating layer 118 may be formed along the interface between the transfer gate electrode 117 and the substrate 101. The first electrode layer and the second electrode layer may be offset from each other in a second direction (Y direction) and disposed at different positions. Therefore, at least a part of the lower surface of the first electrode layer may not be in direct contact with the upper surface of the second electrode layer, and at least a part of the transfer gate insulating layer 118 may be disposed between the device isolation film 105 and the first electrode layer in the first direction.

[0071] The transfer gate spacer 119 may include silicon nitride, etc., and may be formed only around the first electrode layer. Specifically, in a direction parallel to the upper surface of the substrate 101, the second electrode layer may not be adjacent to the transfer gate spacer 119. As Figure 4A shown, at least a part of the transfer gate spacer 119 may be positioned below the upper surface of the substrate 101 and may thus be disposed within the substrate 101. At least a part of the transfer gate spacer 119 may be disposed at the same height as the floating diffusion region 110 in the first direction.

[0072] The transfer gate spacer 119 disposed between the floating diffusion region 110 and the first electrode layer may include a first region extending along one side of the transfer gate insulating layer 118 and a second region extending along one side of the floating diffusion region 110. The first region may be formed to be longer than the second region in the first direction. The upper part of the second region may be separated from the first region in a horizontal direction (e.g., X direction or Y direction), and as Figure 4A shown, the transfer gate spacer 119 may include a valley region between the floating diffusion region 110 and the gate electrode 117.

[0073] The gate structures of transistors 120 and 130 other than the transfer transistor TX may have a shape different from that of the transfer gate structure TG. Refer to Figure 4B , the gate structure of the first transistor 120 may be formed on the substrate 101 and may include a gate electrode 125, a gate insulating layer 128, and gate spacers (not shown). In the Z direction perpendicular to the upper surface of the substrate 101, the length of each gate electrode 125 may be shorter than the length of the transfer gate electrode 117.

[0074] An interconnect region may be provided on the substrate 101. The interconnect region may include a first upper interconnect pattern 174, an interconnect via, and a second upper interconnect pattern 181 connected to the transfer gate structure TG, the gate electrodes 125 and 135 of the circuit elements 120 and 130, and the active region. The interconnect region may be formed in the interlayer insulating layer 160 and the intermetallic insulating layers 172 and 180 formed on the substrate 101. Through the interconnect region, the floating diffusion region 110, the transfer gate structure TG, the transistors 120 and 130, etc. included in the pixel 100 may be electrically connected to each other.

[0075] In an exemplary embodiment, the pixel 100 may include an insulating liner 161 and a plurality of upper insulating layers 162 and 166.

[0076] The insulating liner 161 may be conformally formed on the second surface of the substrate 101. The insulating liner 161 may conformally cover the lower gate structures TG, 125, and 135 and the substrate 101 on the gate structures TG, 125, and 135. The insulating liner 161 may include silicon oxide or a low-k material. The insulating liner 161 may extend from the insulating liner forming the gate insulating layers 118 and 128 provided below the gate structures TG, 125, and 135, and may be formed of the same material as the insulating liner forming the gate insulating layers 118 and 128.

[0077] The first upper insulating layer 162 may be provided on the insulating liner 161.

[0078] The first upper insulating layer 162 may be provided to conformally cover the upper portions of the gate structures TG, 125, and 135 of the respective circuit elements on the exposed substrate 101 (e.g., the transfer gate structure TG, the reset gate electrode, the selection gate electrode, the drive gate electrodes 125 and 135), and the insulating liner 161. The first upper insulating layer 162 may be a protective film and may include silicon oxide or a low-k material to insulate the lower circuit elements from the outside and protect the lower circuit elements from external influences.

[0079] The second upper insulating layer 166 may be disposed on the first upper insulating layer 162. The second upper insulating layer 166 may include a material different from that of the first upper insulating layer 162, and may conformally cover the circuit elements on the exposed substrate 101 and the upper portion of the first upper insulating layer 162 to have a thickness greater than that of the first upper insulating layer 162. The second upper insulating layer 166 may include silicon nitride, silicon oxynitride, or a low dielectric material. Since the second upper insulating layer 166 includes a material different from that of the first upper insulating layer 162, the second upper insulating layer 166 may be used as an etch stop layer during the process.

[0080] The first upper insulating layer 162 and the second upper insulating layer 166 have separate functions and can protect the lower circuit elements and the semiconductor substrate 101 by including different materials. The total thickness of the first upper insulating layer 162 and the second upper insulating layer 166 may satisfy 30 nm to 50 nm, and specifically, may satisfy 30 nm to 40 nm. Additionally, the second upper insulating layer 166 may have the maximum thickness within the above thickness, and the thickness of the insulating liner 161 may also be included in the above total thickness. For example, the second upper insulating layer 166 may be the thickest, the insulating liner 161 may be the thinnest, and the first upper insulating layer 162 may satisfy the thickness between them.

[0081] The insulating liner 161 and the first upper insulating layer 162 may be collectively referred to as an oxide layer 165 containing the same material, and may be implemented as a silicon oxide layer formed by setting different deposition temperatures during the process. Therefore, the crystal sizes of the silicon oxide layers may be different, but the present disclosure is not limited thereto.

[0082] The interlayer insulating layer 160 may be disposed on the substrate 101. The interlayer insulating layer 160 may cover the transmission gate structure TG and the gate electrodes 125 and 135 of the select transistor SX, the reset transistor RX, and the drive transistors DX1 and DX2, and the exposed substrate 101 therebetween on the second upper insulating layer 166. The interlayer insulating layer 160 may include a single-layer or multi-layer structure of at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and a porous low-k dielectric layer.

[0083] The inter-metal insulating layers 172 and 180 may be disposed on the interlayer insulating layer 160. The inter-metal insulating layers 172 and 180 may include a single-layer or multi-layer structure of at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and a porous insulating film. The first upper interconnect 174 and the second upper interconnect 181 and the contact plugs may be disposed between the inter-metal insulating layers 172 and 180. The contact plugs may contain a metal (e.g., tungsten (W), aluminum (Al), or copper (Cu)), and specifically, tungsten may be used.

[0084] The contact plug has a column shape and may have an inclined side surface, the width of which decreases toward the substrate 101.

[0085] In an exemplary embodiment, the pixel 100 may include a contact structure CS for electrical connection between respective circuit elements. Each contact structure may include horizontal contact portions 157, 147, 137, and 127 and vertical contact portions 159, 149, 139, and 129.

[0086] The horizontal contact portions 157, 147, 137, and 127 may be disposed on the transfer gate structure TG, the floating diffusion region 110, and the gate electrodes 125 and 135 of the driving transistors TX1 and TX2, respectively.

[0087] The areas of the respective horizontal contact portions 157, 147, 137, and 127 may be different from each other, but are not limited thereto. Specifically, the areas of the horizontal contact portions 157, 127, and 137 disposed on the transfer gate structure TG and the gate electrodes 125 and 135 of the driving transistors may be larger than the area of the horizontal contact portion 147 disposed in the floating diffusion region 110, but are not limited thereto.

[0088] The horizontal contact portions 157, 147, 137, and 127 may penetrate the first upper insulating layer 162 and the second upper insulating layer 166, and the lower surfaces of the horizontal contact portions 157, 147, 137, and 127 may directly contact the lower circuit structure (e.g., the upper surfaces of the gate electrodes 117, 125, and 135 and the upper surface of the floating diffusion region 110). Accordingly, the horizontal contact portions 157, 147, 137, and 127 may also be disposed to penetrate the insulating liner 161 under the first upper insulating layer 162.

[0089] Accordingly, the insulating liner 161, the first upper insulating layer 162, and the second upper insulating layer 166 are removed to form a first opening 167 exposing the upper surfaces of the lower gate electrodes 117, 125, and 135 and the upper surface of the floating diffusion region 110, and the horizontal contact portions 157, 147, 137, and 127 may be formed by filling the first opening 167.

[0090] The horizontal contact portions 157, 147, 137, and 127 may have a multi-layer structure and may include at least a bilayer structure.

[0091] The horizontal contact portions 157, 147, 137, and 127 may also include an extension region S2 that fills the first opening 167 and extends to the upper surface of the adjacent second upper insulating layer 166. Accordingly, the horizontal contact portions 157, 147, 137, and 127 may include a contact region S1 that fills the first opening 167 penetrating from the insulating liner 161 to the second upper insulating layer 166, and an extension region S2 that extends from the contact region S1 and extends to the upper surface of the second upper insulating layer 166.

[0092] Accordingly, the areas and shapes of the horizontal contact portions 157, 147, 137, and 127 may be designed in various ways according to the size of the extension region S2, and thus, the process freedom of the upper contact plugs in the vertical contact portions 159, 149, 139, and 129 may be ensured.

[0093] Reference Figure 5A and Figure 5B each of the horizontal contact portions 157, 147, 137, and 127 may have two conductive layers 151 and 152.

[0094] The horizontal contact portions 157, 147, 137, and 127 are disposed in the lower part and may include a first conductive layer 151 as a lower conductive layer, which is formed along the side surface and the bottom surface of the first opening 167 and fills the first opening 167. Hereinafter, the description of the first conductive layer 151 may be understood as the description of the lower conductive layer. The first conductive layer 151 may include hafnium (Hf) or titanium (Ti), but is not limited thereto. The first conductive layer 151 includes a first portion of the contact region S1 that fills the first opening 167 and a second portion of the extension region S2 that extends above the second upper insulating layer 166, and the thickness h2 of the first portion may be different from the thickness of the second portion. The area of the first portion (e.g., the area of the contact region S1) may be larger than the area of the second portion (e.g., the area of the extension region S2), and the area of the first portion may be smaller than the area of the upper surfaces of the gate electrodes 117, 125, and 135. Since the first portion of the first conductive layer 151 is formed by filling the first opening 167, the thickness of the first conductive layer 151 may generally be defined as the thickness h2 of the first portion. Additionally, the thickness h2 of the first conductive layer 151 may be greater than the depth h1 of the first opening 167. Accordingly, the first conductive layer 151 may be formed to protrude above the first opening 167, but is not limited thereto.

[0095] The second conductive layer 152 may be further formed as a pad conductive layer on the first conductive layer 151. Hereinafter, the description of the second conductive layer 152 may be understood as the description of the pad conductive layer.

[0096] The second conductive layer 152 may be formed conformally along the first conductive layer 151 and may be formed on the first conductive layer 151, and thus, may have the same thickness in the contact region S1 and the extension region S2.

[0097] The second conductive layer 152 may partially include a recessed region in its surface, in which the level of the uppermost surface decreases toward the center of the first opening 167, but is not limited thereto.

[0098] The second conductive layer 152 may be a conductive barrier and may block the diffusion of the conductive material into the first conductive layer 151 in the lower part when forming a contact plug that may be placed in the upper part. The second conductive layer 152 may be a metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)), but is not limited thereto.

[0099] As an example, in the case where the upper contact plugs in the vertical contact portions 159, 149, 139, and 129 include tungsten (W), and when tungsten is deposited, the metal (e.g., titanium) forming the lower first conductive layer 151 and the tungsten gas (WF6) may react to oxidize the lower first conductive layer 151 of titanium. Since the first conductive layer 151 basically performs electrical contact between the lower circuit elements and the upper vertical contact portions 159, 149, 139, and 129, damage to the first conductive layer 151 may cause damage to the silicon material, which results in leakage current in the floating diffusion region 110.

[0100] Therefore, by further forming the second conductive layer 152 on the first conductive layer 151, device reliability can be ensured by using the second conductive layer 152 as a barrier against the chemical reaction between the upper vertical contact portions 159, 149, 139, and 129 and the first conductive layer 151.

[0101] The thickness h2 of the first conductive layer 151 in the contact region S1 may be greater than the thickness of the second conductive layer 152, and the thickness of the first conductive layer 151 in the extension region S2 may be equal to or less than the thickness of the second conductive layer 152.

[0102] Therefore, on the second upper insulating layer 166, the thickness of the second conductive layer 152 may be equal to or greater than the thickness of the first conductive layer 151. In this way, by forming the second conductive layer 152 thick enough, electrical connection is possible without damaging the first conductive layer 151, and thus, damage to the silicon material of the lower gate structures TG, 125, and 135 or the substrate 101 can be prevented.

[0103] Specifically, as Figure 5AAs shown, the contact structure CS on the transfer gate structure TG may include a horizontal contact portion 157 and a vertical contact portion 159. As described above, the horizontal contact portion 157 may include a first conductive layer 151 and a second conductive layer 152 on the first conductive layer 151. The first conductive layer 151 is formed to extend by filling a first opening 167 that exposes the upper surface of the gate electrode 117 of the transfer gate structure TG. The horizontal contact portion 157 may have a rectangular shape that is longer in one direction (e.g., the X direction) as shown in Figure 3 , but alternatively, may have a square shape, or may have any other shape such as a circular or oval shape. A contact plug may be provided as the vertical contact portion 159 on the horizontal contact portion 157, and may form a via structure for electrical connection while physically contacting the horizontal contact portion 157. The contact plug forming the vertical contact portion 159 may be formed in a column shape that extends vertically from the upper surface of the interlayer insulating layer 160 to the upper surface of the second conductive layer 152 of the horizontal contact portion 157, and may contain a conductive metal material such as tungsten (W), aluminum (Al), copper (Cu), etc.

[0104] The vertical contact portion 159 may be formed only of a filling metal material filling the via hole VH instead of a multi-layer structure, and may not include a separate conduction barrier on the side surface and the bottom surface of the vertical contact portion 159. Therefore, even if the area of the lower surface of the vertical contact portion 159 becomes very small, it is possible to prevent the area from being further reduced due to the deposition of the conduction barrier, and the vertical contact portion 159 can ensure a sufficient contact area and maintain a low resistance during contact by direct bonding without a conduction barrier.

[0105] The area of the lower surface of the vertical contact portion 159 may be smaller than the area of the upper surface of the vertical contact portion 159, and the area of the lower surface of the vertical contact portion 159 may be 1 / 10 to 2 / 3 of the area of the horizontal contact portion 157, but is not limited thereto.

[0106] The width W3 of the lower surface of the vertical contact portion 159 may be smaller than the width of the lower portion of the horizontal contact portion 157 (e.g., the width W1 of the first opening 167). The vertical contact portion 159 may be disposed to deviate from the center of the horizontal contact portion 157 toward one side. For example, when the horizontal contact portion 157 has a rectangular shape that is longer in the X direction, the vertical contact portion 159 may be disposed on one side, specifically, disposed close to the intermediate separation region 102, but the present disclosure is not limited thereto.

[0107] The lower surface of the vertical contact portion 159 can be set to be lower than the upper surface of the second conductive layer 152 of the horizontal contact portion 157. For example, the level of the lower surface of the vertical contact portion 159 can be lower than the level of the uppermost surface of the second conductive layer 152, but can be set at a level higher than the upper surface of the first conductive layer 151.

[0108] For example, even when the vertical contact portion 159 is formed to be recessed into a part of the second conductive layer 152, the vertical contact portion 159 can be set to ensure a first separation distance I1 from the upper surface of the first conductive layer 151. Therefore, the first conductive layer 151 and the vertical contact portion 159 can be spaced apart by the second conductive layer 152, thereby sufficiently preventing a chemical reaction between them.

[0109] The height h4 of the vertical contact portion 159 can satisfy 2 to 20 times the height h3 of the horizontal contact portion 157, and specifically, can be 5 to 15 times the height h3 of the horizontal contact portion 157. Each vertical contact portion 159 can have a different height according to the height of the lower circuit element, and the area and width of the lower surface of each vertical contact portion 159 can thus be different from each other.

[0110] Specifically, as Figure 5B shown, the height h4 of the contact plug of the vertical contact portion 149 forming the floating diffusion region 110 can be greater than the height of the contact plug of the vertical contact portion 159 forming the transfer gate structure TG.

[0111] Referring to Figure 3 、 Figure 4A 、 Figure 4B and Figure 5B , the horizontal contact portion 147 provided in the floating diffusion region 110 can include the first conductive layer 151 and the second conductive layer 152 on the first conductive layer 151, and the first conductive layer 151 extends by filling the first opening 167 that opens the substrate 101 provided with the floating diffusion region 110. As Figure 3 shown, the area of the horizontal contact portion 147 can be smaller than the area of the first conductive layer 151 on the gate structure TG, and can have a square shape, or alternatively, can have a rectangular shape, or can have any other shape such as a circular or oval shape. The contact plug can be provided as the vertical contact portion 149 on the horizontal contact portion 147, and can form a via structure for electrical connection while physically contacting the horizontal contact portion 147. The contact plug forming the vertical contact portion 149 can be formed in a column shape that extends vertically from the upper surface of the interlayer insulating layer 160 to the upper surface of the second conductive layer 152 of the horizontal contact portion 147, and can include tungsten (W), aluminum (Al), or copper (Cu).

[0112] The area of the lower surface of the vertical contact portion 149 may be smaller than the area of the upper surface of the vertical contact portion 149, and the area of the lower surface of the vertical contact portion 149 may satisfy 1 / 10 to 2 / 3 of the area of the horizontal contact portion 147, and specifically, may be 1 / 3 to 1 / 2 of the area of the horizontal contact portion 147, but is not limited thereto.

[0113] The width W3 of the lower surface of the vertical contact portion 149 may be smaller than the width of the lower part of the horizontal contact portion 147 (for example, the width W1 of the first opening 167). The vertical contact portion 149 may be provided at the center of the horizontal contact portion 147, but is not limited thereto.

[0114] The lower surface of the vertical contact portion 149 may be provided below the upper surface of the second conductive layer 152 of the horizontal contact portion 147. For example, the level of the lower surface of the vertical contact portion 149 may be lower than the level of the uppermost surface of the second conductive layer 152, but may be provided at a level higher than the upper surface of the first conductive layer 151.

[0115] For example, even when the vertical contact portion 149 is formed by recessing a part of the second conductive layer 152, the vertical contact portion 149 may be provided to ensure a first separation distance I1 from the upper surface of the first conductive layer 151. Therefore, a chemical reaction between the first conductive layer 151 and the vertical contact portion 149 can be sufficiently prevented.

[0116] Reference Figure 3 and Figure 4B , similar to the transfer gate structure TG, the horizontal contact portions 127 and 137 (collectively referred to as 127 hereinafter) provided on the gate electrodes 125 and 135 of the transistors 120 and 130 other than the transfer gate structure TG may include the first conductive layer 151 and the second conductive layer 152 on the first conductive layer 151, and the first conductive layer 151 extends by filling the first opening 167 that opens the upper surface of the gate electrode 125. As Figure 3 shown, the area of the horizontal contact portion 127 may be equal to or smaller than the area of the first conductive layer 151 on the transfer gate structure TG, and may have an area larger than the area of the first conductive layer 151 on the floating diffusion region 110. The second conductive layer 152 may have a rectangular shape that is longer in the first direction (for example, the X direction), but alternatively, may have a square shape, or may have a circular or elliptical shape. The contact plug may be provided as the vertical contact portion 129 on the horizontal contact portion 127. The layer structure and connection of the vertical contact portion 129 and the horizontal contact portion 127 may be the same as the layer structure and connection of the vertical contact portion 159 and the horizontal contact portion 157 on the transfer gate structure TG.

[0117] The width of the lower surface of the vertical contact portion 129 may be smaller than the width of the lower portion of the horizontal contact portion 127 (e.g., the width of the first opening 167). The vertical contact portion 129 may be provided at the center of the horizontal contact portion 127, but is not limited thereto.

[0118] The first upper interconnect 174 and the second upper interconnect 181 may be provided in multiple layers on the interlayer insulating layer 160 and between the intermetallic insulating layers 172 and 180, and the gate electrodes 117, 125, and 135 and the source / drain regions 123 and 133 of the respective transistors may be connected to the floating diffusion region 110 according to the pixel circuit design, thereby applying an electrical signal.

[0119] As Figure 4B shown, the gate electrodes 125 and 135 of the source follower transistors serving as the driving transistor DX and the floating diffusion region 110 may be electrically connected to each other. For this purpose, the vertical contact portions 149 and 129 may be connected by the first upper interconnect 174 on the interlayer insulating layer 160.

[0120] In Figure 3 and Figure 4B , the first upper interconnect 174 that connects the gate electrodes 125 and 135 of the source follower transistors serving as the driving transistor DX to the floating diffusion region 110 is shown as being provided across the pixel separator 103, but is not limited thereto, and may be implemented in various ways in the multilayer structure on the intermetallic insulating layers 172 and 180.

[0121] In the above, the contact structure including the horizontal contact portions 157, 147, 137, and 127 and the vertical contact portions 159, 149, 139, and 129 on the transfer gate structure TG, the floating diffusion region 110, and the driving gate electrodes 125 and 135 has been described, but in the exemplary embodiments of the present disclosure, the contact structure including the horizontal contact portions 157, 147, 137, and 127 and the vertical contact portions 159, 149, 139, and 129 may be applied to the contact portions of the respective circuit elements.

[0122] Specifically, the contact portions of the gate electrodes of the transistors other than the transfer gate structure TG may be implemented in the same manner as Figure 4B the contact structure of the driving gate electrodes 125 and 135, and the contact portions of the source / drain regions 123 and 133 of the respective transistors and the contact portions of the ground region 140 may be implemented in the same manner as the contact structure of the floating diffusion region 110.

[0123] In this way, in the region where the contact plugs forming the vertical contact portions 159, 149, 139, and 129 are provided, while the contact structure including the horizontal contact portions 157, 147, 137, and 127 is implemented as a landing pad for making electrical contact with a larger area of the lower circuit element, the contact structure including the horizontal contact portions 157, 147, 137, and 127 and the vertical contact portions 159, 149, 139, and 129 can be formed as a multilayer structure.

[0124] The upper surface of the multilayer structure of the horizontal contact portions 157, 147, 137, and 127 that is exposed to the outside can be formed of a conduction barrier, and thus, the vertical contact portions 159, 149, 139, and 129 can be implemented only using a filling conductive metal material without a separate conduction barrier, and thus, the vertical contact portions 159, 149, 139, and 129 can ensure a contact area and can be formed without damaging the first conductive layer 151 below.

[0125] Hereinafter, with reference to Figure 6 and Figure 7 modifications of the contact structure including the vertical contact portions 159, 149, 139, and 129 and the horizontal contact portions 157, 147, 137, and 127 according to one or more exemplary embodiments will be described.

[0126] Figure 6 and Figure 7 show the horizontal contact portion 157 and the vertical contact portion 159 on the transfer gate structure TG, but are not limited thereto, and can be equivalently applied to the horizontal contact portions 147 and 127 and the vertical contact portions 149 and 129 provided on the floating diffusion region 110 and the gate electrodes 125 and 135 of other transistors.

[0127] With reference to Figure 6 except for the shapes of the horizontal contact portion 157 and the vertical contact portion 159 as the contact structure, the pixel 100a can be the same as the pixel 100 of Figures 4A to 5B .

[0128] The horizontal contact portion 157 may include a first conductive layer 151 that is uniformly formed along the side surface and the bottom surface of the first opening 167 exposing the gate electrode 117 to a first thickness. A second conductive layer 152 may be uniformly formed on the first conductive layer 151 to a second thickness. The second thickness may be greater than the first thickness, but is not limited thereto.

[0129] Both the first conductive layer 151 and the second conductive layer 152 can be conformally formed along the first opening 167, and the depth h1 of the first opening 167 can be greater than the total thickness h5 of the horizontal contact portion 157. Accordingly, the horizontal contact portion 157 can be recessedly formed along the first opening 167 and have a flat upper surface on the bottom surface of the first opening 167. The vertical contact portion 159 can be disposed on the flat upper surface to enable physical and electrical connection between the two structures.

[0130] The area of the contact region S1 including the flat upper surface can be formed to be equal to or less than the area of the extension region S2. For example, the extension region S2 extends widely outside the first opening 167 in the upward direction of the second upper insulating layer 166, and thus, can have a width W2 greater than the width of the contact region S1. The width W2 of the extension region S2 includes a width corresponding to the difference between W2 and W1, for example, 2×W4.

[0131] The upper contact plug in the vertical contact portion 159 can be formed in a column shape that vertically extends from the upper surface of the interlayer insulating layer 160 to the upper surface of the second conductive layer 152 of the horizontal contact portion 157, and can have a length h6 greater than that of the horizontal contact portion 157 in Figure 4A .

[0132] The area of the lower surface of the vertical contact portion 159 can be smaller than the area of the upper surface of the vertical contact portion 159, and the area of the lower surface of the vertical contact portion 159 can satisfy 1 / 2 to 1 / 3 of the area of the contact region S1 of the horizontal contact portion 157, but is not limited thereto.

[0133] The width W3 of the lower surface of the vertical contact portion 159 can be smaller than the width of the lower portion of the horizontal contact portion 157 (for example, the width W1 of the first opening 167). The vertical contact portion 159 can be disposed to deviate to one side of the horizontal contact portion 157, but can alternatively be disposed in the center of the horizontal contact portion 157.

[0134] The lower surface of the vertical contact portion 159 can be disposed at a level lower than the uppermost surface level of the second conductive layer 152 within the first opening 167 of the horizontal contact portion 157. For example, the level of the lower surface of the vertical contact portion 159 can be lower than the upper surface level of the second conductive layer 152, but can be disposed at a level higher than the upper surface level of the first conductive layer 151.

[0135] For example, even when the vertical contact portion 159 is formed by partially recessing the second conductive layer 152, the vertical contact portion 159 can be disposed to ensure a separation distance I1 from the upper surface of the first conductive layer 151. Accordingly, a chemical reaction between the first conductive layer 151 and the vertical contact portion 159 can be sufficiently prevented.

[0136] Reference Figure 7 , except for the shapes of the horizontal contact portion 157 and the vertical contact portion 159, the pixel 100b may be the same as the pixel 100 of Figures 4A to 5B .

[0137] The shape and stacked structure of the horizontal contact portion 157 may be the same as the shape and stacked structure of the horizontal contact portion 157 in Figure 5A , and for example, may include a first conductive layer 151 and a second conductive layer 152 on the first conductive layer 151, and the first conductive layer 151 fills a first opening 167 exposing the gate electrode 117.

[0138] However, the horizontal contact portion 157 may further include the first conductive layer 151 and the second conductive layer 152 conformally formed along the side surface and the bottom surface of the first opening 167.

[0139] Figure 7 The vertical contact portion 159 of

[0140] may further include a conduction barrier 158 that covers the side surface and the bottom surface of a via hole VH formed in the interlayer insulating layer 160.

[0141] The conduction barrier 158 may be used as a diffusion prevention layer to prevent the filled conductive metal material from diffusing into the interlayer insulating layer 160, and may be formed of a conductive material, but is not limited thereto.

[0142] The conduction barrier 158 may include a metal nitride, and for example, may include titanium nitride (TiN), tantalum nitride (TaN), etc. The conduction barrier 158 may include the same material as the material of the second conductive layer 152, but is not limited thereto. For example, if the second conductive layer 152 includes titanium nitride, the conduction barrier 158 may include tantalum nitride. Figure 5A and Figure 6 when the conduction barrier 158 is formed, the thickness of the second conductive layer 152 may be less than the thickness of the second conductive layer 152 in

[0143] Therefore, when the conduction barrier 158 is formed, even if the separation distance I2 is relatively further reduced compared to the first separation distance I1, the barrier of the conduction barrier 158 can prevent the filling gas (WF6) from reacting with the lower first conductive layer 151 when tungsten, which is a filling metal material, is filled.

[0144] Therefore, the via hole VH can be formed without considering the remaining separation distance I2 of the second conductive layer 152, thereby further ensuring the prevention of process errors.

[0145] Hereinafter, reference will be made to Figures 8 to 10BTo describe a pixel according to one or more example embodiments.

[0146] Figure 8 is a diagram schematically showing a pixel of an image sensor according to one or more example embodiments, and Figure 9 shows a cross-sectional view of a cross-section taken along line III-III' of Figure 8 .

[0147] Except that Figure 8 and Figure 9 the pixel 100c of the image sensor 1 in also includes a connection pattern 190, Figure 8 and Figure 9 the pixel 100c of the image sensor 1 in can be the same as the pixel in Figures 3 to 7 .

[0148] Figure 8 and Figure 9 the pixel 100c of the image sensor 1 in can also include a connection pattern 190 with respect to the above-mentioned pixels 100, 100a, and 100b.

[0149] The connection pattern 190 can connect the gate electrodes 125 and 135 of the driving transistors DX1 and DX2 to the plurality of floating diffusion regions FD1 to FD4 and 110. Specifically, the connection pattern 190 can fill the first opening 167 that opens from the insulating layer 161 to the second upper insulating layer 166 on the objects to be electrically connected. The first conductive layer 151 can be formed as a lower pattern conductive layer, and the second conductive layer 152 can be formed as a pattern conductive layer (or upper pattern conductive layer) on the first conductive layer 151, thereby providing a structure of the horizontal contact portion 157.

[0150] The connection pattern 190 can be understood as a structure in which the extended region S2 extends from the horizontal contact portion 157 for a long distance, and according to the region through which the connection pattern 190 passes, this region can be defined as the first connection region 191 within the first opening 167, the second connection region 192 passing through the pixel regions PX1 to PX4, and the other third connection region 193. The first connection region 191 and the second connection region 192 can overlap each other and be connected in the vertical Z direction, and the second connection region 192 and the third connection region 193 can be connected in the horizontal direction in the X-Y plane.

[0151] As Figure 8As shown, the connection pattern 190 may include a first connection region 191, a second connection region 192 that connects the first connection regions 191 to each other on a plurality of floating diffusion regions FD1 to FD4, 110, and a third connection region 193 that extends from the second connection region 192 and is disposed on the device isolation film 105. The third connection region 193 may extend to a position where the gate electrodes 125 and 135 of the driving transistors DX1 and DX2 are provided, and may be connected to the second connection region 192 on the gate electrodes 125 and 135 of the driving transistors DX1 and DX2, and the second connection region 192 may be connected to the lower first connection region 191, thereby forming a connection pattern 190. The connection pattern 190 may be understood to include: a plurality of contact portions that cover a first opening that opens from the insulating layer 161 to the second upper insulating layer 166 and contact the driving gate electrodes 125, 135 and the floating diffusion region 110; and an extension portion that connects the plurality of contact portions along the upper surface of the upper insulating layer 166. The extension portion may simultaneously connect the contact portions of the floating diffusion regions of two or more adjacent pixels to each other.

[0152] The connection pattern 190 may be set in various ways according to the circuit design, and since the connection pattern 190 is disposed on the second upper insulating layer 166, electrical connection of spaced-apart elements is possible by extending the horizontal contact portion 157 without forming the vertical contact portion 159 on the horizontal contact portion 157.

[0153] In this way, the number of vertical contact portions 159 that are vias penetrating the interlayer insulating layer 160 can be significantly reduced, thereby increasing the layout freedom, and the interconnections 174 and 181 on the upper metal interlayer insulating layers 172 and 180 can be simplified.

[0154] Figure 10A is a circuit diagram schematically showing a pixel circuit of an image sensor according to one or more example embodiments, and Figure 10B is schematically showing Figure 10A of the pixel circuit.

[0155] Figure 10A The pixel circuit of the image sensor 1 in may be a circuit diagram schematically showing a pixel circuit including the following: eight photodiodes PD1 to PD8, eight transfer gate structures TG1 to TG8, eight floating diffusion regions FD1 to FD8, and five transistors RX, DCX, DX1, DX2, and SX.

[0156] Reference Figure 10A, the first photodiode PD1 and the first transfer transistor TX1 of the first pixel PX1 can be connected to the first floating diffusion node FD1. Similarly, the second photodiodes PD2 to the eighth photodiodes PD8 of the second pixel PX2 to the eighth pixel PX8 can be connected to the second floating diffusion node FD2 to the eighth floating diffusion node FD8 through the second transfer transistor TX2 to the eighth transfer transistor TX8, respectively. The integrated floating diffusion node FD can be implemented by connecting the floating diffusion nodes FD1 to FD8 included in the first pixel PX1 to the eighth pixel PX8 to each other using an interconnect pattern or the like. The first transfer transistor TX1 to the eighth transfer transistor TX8 can be implemented by transfer gate structures TG1 to TG8, respectively.

[0157] The pixel circuit may include a reset transistor RX, a dual conversion gain transistor DCX, a first driving transistor DX1, a second driving transistor DX2, and a selection transistor SX. The reset transistor RX and the dual conversion gain transistor DCX are connected in series with each other, and the integrated floating diffusion node FD can be defined therebetween. The reset transistor RX and the dual conversion gain transistor DCX can be controlled by a reset control signal RG and a dual conversion gain signal DG, respectively.

[0158] For example, among the eight transistors included in the four pixel circuit regions, two transistors can be connected in parallel to provide the first driving transistor DX1 and the second driving transistor DX2, and two transistors can be connected in series with each other to provide the reset transistor RX and the dual conversion gain transistor DCX. On the other hand, among the eight transistors, one transistor can be used as the selection transistor SX, and the remaining three transistors can be dummy transistors, but it is not limited thereto. By connecting and disconnecting the respective floating diffusion nodes FD1 to FD8 and the integrated floating diffusion node FD, the conversion gain of the image sensor can be changed.

[0159] Figure 10B The circuit arrangement of Figure 10A is an example arrangement of the pixel circuit of

[0160] Reference Figure 10B , in the pixel 100d of the image sensor 1, four pixel circuit regions are arranged in a 2×2 shape in the horizontal direction (X-axis direction) and the vertical direction (Y-axis direction), and two pixel regions are provided in each of the four pixel circuit regions. Therefore, it will be understood that the first pixel PX1 to the eighth pixel PX8 can be respectively assigned to eight pixel regions in a 4×2 form.

[0161] The structure of each pixel circuit region is as described above, and for example, each of the first pixel region to the eighth pixel region may have the same as previously in Figures 3 to 7The structures described therein. Accordingly, each of the first pixel PX1 to the eighth pixel PX8 may include a floating diffusion region 110, a transfer gate structure TG, and transistors 120, 130, etc.

[0162] In Figure 10B In the exemplary embodiment shown, the first pixel PX1 to the fourth pixel PX4 and the fifth pixel PX5 to the eighth pixel PX8 may be set to the same shape. The first pixel PX1 to the fourth pixel PX4 may be set such that the floating diffusion regions FD1 to FD4 included in the first pixel PX1 to the fourth pixel PX4 are adjacent to each other. Additionally, the fifth pixel PX5 to the eighth pixel PX8 may be set such that the floating diffusion regions FD5 to FD8 included in the fifth pixel PX5 to the eighth pixel PX8 are adjacent to each other. Furthermore, the floating diffusion regions FD5 to FD8 included in the fifth pixel PX5 to the eighth pixel PX8 may be symmetrically arranged with respect to the axis of the pixel separator 103 with the floating diffusion regions FD1 to FD4 included in the first pixel PX1 to the fourth pixel PX4 to face each other.

[0163] By aggregating the eight floating diffusion regions FD1 to FD8 as described above, the connection pattern 190 can be effectively set.

[0164] Figure 10B The pixel 100d of Figure 3 and Figure 8 may be substantially the same as the pixel 100c of

[0165] and may differ only in the configuration of the connection patterns 190, 195, and 196. Each of the first pixel PX1 to the eighth pixel PX8 may include only one transistor 120, 130, and the eight transistors may be arranged in four pixel circuit regions forming a pixel group. In the exemplary embodiment, with respect to the eight floating diffusion regions FD1 to FD8 included in the first pixel PX1 to the eighth pixel PX8, the eight transistors included in one pixel group may be implemented with the following: a first driving transistor DX1 and a second driving transistor DX2 connected in parallel, a reset transistor RX and a dual conversion gain transistor DCX connected in series, a selection transistor SX, and three dummy transistors. The dummy transistors may be applied as additional driving transistors and reset transistors and may be designed in various ways according to the circuit design.

[0166] The connection patterns 190, 195, and 196 may be filled in the first opening 167 that opens from the insulating layer 161 to the second upper insulating layer 166 on the object to be electrically connected, and may form a first conductive layer 151, which may be Figures 3 to 5B with the horizontal contact portion 157 where the second conductive layer 152 of Figure 8 andFigure 9 is the same as the structure of the connection pattern 190.

[0167] The connection patterns 190, 195, and 196 can be understood as structures in which the extended regions extend and elongate from the horizontal contact portion 157, and the regions of the connection patterns 190, 195, and 196 can be defined as a first connection region 191 within the first opening 167, a second connection region 192 passing through the pixel circuit region, and a third connection region 193 according to the regions through which the connection patterns 190, 195, and 196 pass. The first connection region 191 and the second connection region 192 can overlap and be connected to each other in the vertical Z direction, and the second connection region 192 and the third connection region 193 can be connected in the horizontal direction in the X-Y plane.

[0168] The connection patterns 190, 195, and 196 can include a first connection pattern 190 that connects eight floating diffusion regions FD1 to FD8 and two driving gate electrodes 125 and 135.

[0169] Additionally, a second connection pattern 195 can connect the drains 123 and 133 of two driving transistors DX1 and DX2 and the source 133 of a selection transistor SX. Additionally, a third connection pattern 196 can connect the source / drain regions 123 and 133 for series connection of a reset transistor RX and a dual conversion gain transistor DCX. The third connection pattern 196 can extend to a part of a dummy transistor, but is not limited thereto.

[0170] In this way, by applying the connection patterns 190, 195, and 196 in which the horizontal contact portion 157 is extended, an electrical connection between a plurality of circuit elements connected to each other through the interconnections 174 and 181 in the interlayer insulating layers 172 and 180 on the interlayer insulating layer 160 can be obtained. Therefore, the need to form via holes VH and fill vias in the interlayer insulating layer 160 can be significantly reduced, and unnecessary capacitance can be reduced, thereby improving signal transmission efficiency.

[0171] In this way, the number of vertical contact portions 159, which are through holes penetrating the interlayer insulating layer 160, can be significantly reduced, thereby increasing the degree of freedom in layout and simplifying the interconnections on the upper interlayer insulating layer.

[0172] Figures 11A to 11H is a cross-sectional view schematically showing a method of manufacturing an image sensor according to one or more example embodiments. Figures 11A to 11H shows the region corresponding to Figure 4A the corresponding region.

[0173] Refer to Figure 11A, A method of manufacturing an image sensor according to one or more example embodiments may include: preparing a substrate 101, forming a photodiode 107 within the substrate 101, then forming a device isolation film 103 on the surface to define an active region, and forming circuit elements 120 and 130 on the substrate 101 and a first upper insulating layer 162 covering the circuit elements 120 and 130.

[0174] The photodiode 107 may be formed as a photoelectric conversion element PD in the substrate 101, and the device isolation film 103 may be formed to define the active region of the substrate 101. And by forming an insulating liner 161 on the substrate 101, depositing a semiconductor material layer, and performing a patterning process, the circuit elements 120 and 130 may be formed. The transfer gate structure TG and other transistor gate electrodes 125 and 135 may have different patterns according to their shapes. The transfer gate structure TG may extend below the upper surface of the substrate 101 to have a longer depth so as to reach a region adjacent to the photodiode 107 within the substrate 101. At this time, the heights of the transistor gate electrodes 117, 125, and 135 to the upper surface of the substrate 101 may be the same. The insulating liner 161 may be formed to cover each of the gate electrodes 117, 125, and 135 and the exposed upper surface of the substrate 101, and the first upper insulating layer 162 may be formed continuously.

[0175] The insulating liner 161 and the first upper insulating layer 162 may be formed by depositing the same material, and the deposition temperatures may be set to be different from each other. The insulating liner 161 may be deposited at a low temperature, and the first upper insulating layer 162 may be deposited at a temperature higher than that of the insulating liner 161 to form a silicon oxide or a low dielectric layer. The first upper insulating layer 162 may be deposited to have a thickness greater than that of the insulating liner 161.

[0176] Reference Figure 11B , A second upper insulating layer 166 may be formed on the first upper insulating layer 162.

[0177] The second upper insulating layer 166 may conformally cover the entire first upper insulating layer 162, and the second upper insulating layer 166 may be formed by depositing a material different from that of the first upper insulating layer 162. For example, the atomic layer deposition (ALD) method or the chemical vapor deposition (CVD) method may be used to form the second upper insulating layer 166. The thickness of the second upper insulating layer 166 may be greater than that of the first upper insulating layer 162, and for example, may be 3 to 4 times the thickness of the first upper insulating layer 162, but is not limited thereto. The second upper insulating layer 166 may be formed of a material different from that of the first upper insulating layer 162 and having an etching selectivity (for example, silicon nitride (SiN) or silicon oxynitride (SiON)).

[0178] ReferenceFigure 11C , a first opening 167 can be formed to expose the regions of respective contact portions of the circuit elements.

[0179] The first opening 167 can be an opening that exposes the upper surface of the gate electrode 117 of the transfer gate structure TG, the upper surfaces of the gate electrodes 125 and 135 of the other transistors 120 and 130, or the upper surface of the floating diffusion region 110, or can be an opening that exposes the source / drain regions 123 and 133 or the grounding region 140, which are regions of the respective transistor elements serving as other contact portions.

[0180] The first opening 167 can be formed by removing from the second upper insulating layer 166 to the insulating substrate 161 to expose the upper surface of the circuit elements, and can be formed in various shapes (e.g., circular, elliptical, rectangular, or square) having a first width W1 on one side. The first opening 167 can be formed by a photomask and etching process, but is not limited thereto.

[0181] Reference Figure 11D , a first conductive layer 151 can be formed to cover the first opening 167, and a second conductive layer 152 can be formed to continuously cover the first conductive layer 151.

[0182] The first conductive layer 151 and the second conductive layer 152 can be formed by a chemical vapor deposition process of a conductive material layer, and the first conductive layer 151 can be deposited to fill the first opening 167, and the first conductive layer 151 protrudes from the upper surface of the first opening 167 to cover the entire pixel region. The first conductive layer 151 can be formed to have a first thickness h2 above the first opening 167, and a highly conductive metal (e.g., titanium (Ti) or hafnium (Hf)) can be used as the first conductive layer 151, but is not limited thereto.

[0183] Next, the second conductive layer 152 can be conformally deposited on the first conductive layer 151, and the second conductive layer 152 can be formed to have a second thickness that is equal to or greater than the protruding thickness of the first conductive layer 151 on the second upper insulating layer 166. At this time, according to the area of the first opening 167, when depositing the first conductive layer 151, an upper surface including a concave region toward the center of the first opening 167 can be provided, and the second conductive layer 152 can be conformally formed along the upper surface including the concave region. However, when the area of the first opening 167 is relatively large, a flat region can be formed in the central region of the first opening 167 except for the edge region.

[0184] Next, reference Figure 11E , the first conductive layer 151 and the second conductive layer 152 can be etched to form a horizontal contact portion 157 of the contact structure.

[0185] In the case of the horizontal contact portion 157, a mask layer is formed on the first conductive layer 151 and the second conductive layer 152 above each first opening 167 to have a second width W2 greater than the first width W1, and then the mask layer is etched to form the horizontal contact portion 157. In this way, even if dry etching and wet etching are sequentially performed on the patterning of the horizontal contact portion 157, the second upper insulating layer 166 can be used as an etch stop layer to prevent damage to the lower first upper insulating layer 162.

[0186] Accordingly, the first opening 167 can be filled, and the horizontal contact portion 157 can be formed to have an extended area S2 around the first opening 167. Figure 4A and Figure 4B of the first opening 167, and the horizontal contact portion 157 can be formed to have an extended area S2 around the first opening 167.

[0187] At this time, the first conductive layer 151 can remain in the extended area S2, and the size and area of the horizontal contact portion 157 can vary according to the length of the extended area S2. If the extended area S2 is formed to be long and extends to the extended area S2 of another horizontal contact portion, a connection pattern 190 of Figure 8 or Figure 10B can be formed.

[0188] As shown in Figure 11F , an interlayer insulating layer 160 can be formed on the substrate 101. For example, the interlayer insulating layer 160 can be formed by chemical vapor deposition. The interlayer insulating layer 160 can be formed thick enough to uniformly cover the substrate 101, as well as the gate structures TG, 125, and 135, on the second upper insulating layer 166 and the horizontal contact portion 157. The interlayer insulating layer 160 can be formed of a single layer of at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and a porous low-k dielectric layer, or a multi-layer of at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and a porous low-k dielectric layer, but the present disclosure is not limited thereto.

[0189] Referring to Figure 11G , via holes VH exposing the horizontal contact portion 157 can be formed in the interlayer insulating layer 160.

[0190] After the interlayer insulating layer 160 is formed to be flat, a mask can be deposited on the interlayer insulating layer 160 and etched to form via holes VH exposing the upper surface of the horizontal contact portion 157, respectively. The mask can be removed after the via holes VH are formed.

[0191] When forming the vias VH, a part of the surface of the second conductive layer 152 can be recessed, but it can only be recessed to a predetermined depth of the second conductive layer 152 to ensure a first separation distance I1 or greater, so that a part of the second conductive layer 152 remains on the first conductive layer 151. The width of the upper part of the opening of each via VH is greater than that of the lower part, and the width W3 of the lower surface of the opening can be smaller than the first width W1, which is the width of the first opening 167 of the horizontal conductive layer 157.

[0192] Reference Figure 11H , the vertical contact part 159 can be formed by filling the via VH with a conductive metal material.

[0193] Specifically, a conductive metal material is deposited to form an upper part while filling the via VH, and this deposition can continue to cover the interlayer insulating layer 160.

[0194] After that, the vertical contact part 159 can be formed by etching using chemical and physical polishing to expose the interlayer insulating layer 160. In the case of applying tungsten (W) as the conductive metal material for the vertical contact part 159, when applying WF6 gas as the deposition gas to react with the first conductive layer 151 (such as titanium (Ti)) of the horizontal contact part 157, the titanium in the first conductive layer 151 can react actively with the WF6 gas and be oxidized. This chemical reaction may cause corrosion of the first conductive layer 151 and damage to the silicon of the substrate 101 or the lower gate electrodes 117, 125, and 135. In the case of the transmission gate structure TG, leakage current may flow into the floating diffusion region 110. In the present disclosure, the second conductive layer 152 can be applied as a conduction barrier on the first conductive layer 151, and the second conductive layer 152 is formed on the first conductive layer 151 with a sufficient thickness to prevent contact between the first conductive layer 151 and the vertical contact part 159 with the deposition gas. Therefore, tungsten deposition in the vertical contact part 159 can be performed without damaging the lower first conductive layer 151.

[0195] In addition, when depositing tungsten in the vertical contact part 159, a separate conduction barrier is deposited on the side surface and the bottom surface of the via VH, and then tungsten can be directly deposited instead of filling with tungsten, so that the narrow area of the bottom surface of the via VH can be sufficiently filled with tungsten, thereby significantly reducing the contact resistance.

[0196] After forming the first upper interconnect 174 on the vertical contact part 159, the interconnect process of repeatedly forming the intermetal insulating layer 172 and forming the second upper interconnect 181 on the intermetal insulating layer 172 can be repeated in various ways according to the circuit design, and then, an optical unit 170 can be formed on one surface of the substrate 101, thereby forming Figure 4A andFigure 4B pixel 100.

[0197] As described above, according to one or more example embodiments, by forming an extended pattern for electrically connecting devices in a pixel circuit, damage to lower devices during via contact can be significantly reduced. Further, by forming the pad as the extended pattern into a multi-layer structure, it can be achieved only by filling a conductive metal material without a via resistance blocking layer, thereby ensuring contact stability even when the via size is minimized and significantly reducing the contact resistance. Further, by providing the extended pattern not only on the transfer gate structure but also on the contact portion of the floating diffusion region and the contact portion of the driving gate structure, damage to lower devices can be prevented.

[0198] Further, by performing electrical connection between various elements via a connection pattern extending from the extended pattern instead of via an interconnection on the interlayer insulating layer, the interconnection structure on the interlayer insulating layer can be simplified.

[0199] Although example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes can be made without departing from the scope of the present disclosure defined by the appended claims.

Claims

1. An image sensor, comprising: A substrate, comprising a first surface and a second surface opposite to the first surface; A first photoelectric conversion region for a first pixel, in the substrate; A floating diffusion region, in the substrate; A transfer gate, configured to move charges generated in the first photoelectric conversion region to the floating diffusion region; A first conductive layer, configured to be electrically connected to the transfer gate and vertically overlap with the transfer gate in a first direction perpendicular to the first surface of the substrate; And A first vertical contact portion, comprising a first surface and a second surface, wherein the first surface of the first vertical contact portion is configured to be connected to the first conductive layer, Wherein, the first vertical contact portion vertically overlaps with the first conductive layer in the first direction, Wherein, the first surface of the first vertical contact portion has a first width in a second direction perpendicular to the first direction, Wherein, the first conductive layer has a second width in the second direction, and the second width is at least 1.5 times the first width, Wherein, the first conductive layer is spaced apart from the first surface of the substrate, and Wherein, the transfer gate contacts the first surface of the substrate.

2. The image sensor according to claim 1, wherein, The second surface of the first vertical contact portion has a third width in the second direction, and Wherein, the second width is greater than the third width.

3. The image sensor according to claim 2, wherein, A part of the transfer gate extends into the first surface of the substrate.

4. The image sensor according to claim 3, further comprising: A second photoelectric conversion region for a second pixel, in the substrate; A third photoelectric conversion region for a third pixel, in the substrate; And A fourth photoelectric conversion region for a fourth pixel, in the substrate, Wherein, the floating diffusion region is shared by the first photoelectric conversion region, the second photoelectric conversion region, the third photoelectric conversion region and the fourth photoelectric conversion region.

5. The image sensor according to claim 4, wherein, The first vertical contact portion comprises a first material, and the first conductive layer has a second material different from the first material.

6. The image sensor according to claim 4, wherein, A part of the first vertical contact portion extends into the first conductive layer.

7. The image sensor according to claim 5, wherein, The first conductive layer comprises a metal material.

8. The image sensor according to claim 4, further comprising: A second vertical contact portion, comprising a first surface; and A second conductive layer, comprising a first surface connected to the first surface of the second vertical contact portion, Wherein, the first surface of the second vertical contact portion has a fourth width in the second direction, and the first surface of the second conductive layer has a fifth width in the second direction, Wherein, the fifth width is at least 1.5 times the fourth width, and Wherein, the floating diffusion region, the second conductive layer and the second vertical contact portion vertically overlap with each other in the first direction.

9. The image sensor according to claim 8, wherein, The distance from the first surface of the substrate to the first conductive layer is closer than the distance from the first surface of the substrate to the second conductive layer.

10. The image sensor according to claim 9, wherein, The second width is different from the fifth width.

11. The image sensor according to claim 9, wherein, The first vertical contact portion has a first height in the first direction, and the second vertical contact portion has a second height different from the first height in the first direction.

12. The image sensor according to claim 9, wherein, The first conductive layer has a third height in the first direction, and the second conductive layer has a fourth height in the first direction, and wherein the third height is the same as the fourth height.

13. The image sensor according to claim 9, further comprising: A dual conversion gain transistor; And A reset transistor, wherein the first pixel, the second pixel, the third pixel, and the fourth pixel are configured to be connected to the reset transistor and the dual conversion gain transistor.

14. An image sensor, comprising: A substrate including a first surface and a second surface opposite to the first surface; A first photoelectric conversion region for a first pixel in the substrate; A second photoelectric conversion region for a second pixel in the substrate; A device isolation film between the first pixel and the second pixel; A floating diffusion region in the substrate; A transfer gate configured to move charges generated in the first photoelectric conversion region to the floating diffusion region; A first conductive layer configured to be electrically connected to the transfer gate; And A first vertical contact portion including a first surface that contacts the first conductive layer, wherein the transfer gate, the first conductive layer, and the first vertical contact portion vertically overlap each other in a first direction perpendicular to the first surface of the substrate, wherein the first surface of the first vertical contact portion has a first width in a second direction perpendicular to the first direction, wherein the first conductive layer has a second width in the second direction, and the second width is greater than the first width, wherein the first conductive layer is spaced apart from the first surface of the substrate, wherein the transfer gate contacts the first surface of the substrate, and wherein the first conductive layer is offset from the device isolation film in the second direction.

15. The image sensor according to claim 14, further comprising: A second vertical contact portion including a first surface; and A second conductive layer including a first surface connected to the first surface of the second vertical contact portion, wherein the first surface of the second vertical contact portion has a fourth width in the second direction, and the first surface of the second conductive layer has a fifth width in the second direction, wherein the fifth width is greater than the fourth width, and wherein the second conductive layer is offset from the device isolation film in the second direction.

16. The image sensor according to claim 15, wherein, The second conductive layer contacts the first surface of the substrate.

17. The image sensor according to claim 15, wherein, The second conductive layer vertically overlaps the floating diffusion region in the first direction.

18. The image sensor according to claim 17, wherein, The first conductive layer has a first height in the first direction, and the second conductive layer has a second height in the first direction, and wherein the first height is the same as the second height.

19. The image sensor according to claim 17, wherein, The first conductive layer includes a metal material.

20. The image sensor according to claim 17, further comprising: A third photoelectric conversion region for a third pixel, in the substrate; and a fourth photoelectric conversion region for a fourth pixel, in the substrate, wherein the floating diffusion region is shared by the first photoelectric conversion region, the second photoelectric conversion region, the third photoelectric conversion region, and the fourth photoelectric conversion region.

Images