Devices, systems, and methods for out-of-band delivery of error reports

Abstract

An example computing device includes an in-band processor and an out-of-band controller. The example computing device also includes a machine inspection architecture including a pipeline and a plurality of error detectors. The error detector is configured to detect errors occurring in the plurality of circuits and report the errors to the in-band processor and the out-of-band controller via the pipeline. Various other devices, systems, and methods are also disclosed.

Description

BACKGROUND

[0001] Machine check architectures are often used to report errors to an operating system running on a processor. In some examples, the operating system running on the processor logs the error and forwards a copy of the error to an out-of-band controller (e.g., a baseboard management controller). This forwarding of the copy of the error constitutes out-of-band work of the operating system and / or the processor, which may cause degradation in the performance of substantial in-band workloads (e.g., user applications). Accordingly, the present disclosure identifies and addresses the need for additional and improved devices, systems, and methods for out-of-band delivery of error reports generated by machine check architectures. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The drawings illustrate multiple exemplary embodiments and are a part of the specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.

[0003] Figure 1 is a block diagram of a portion of an exemplary computing device that facilitates out-of-band delivery of error reports according to one or more embodiments of the present disclosure.

[0004] Figure 2 is a block diagram of an exemplary machine check architecture that facilitates out-of-band delivery of error reports according to one or more embodiments of the present disclosure.

[0005] Figure 3 is a block diagram of an exemplary computing device that facilitates out-of-band delivery of error reports according to one or more embodiments of the present disclosure.

[0006] Figure 4 is an illustration of an exemplary computing device that facilitates out-of-band delivery of error reports according to one or more embodiments of the present disclosure.

[0007] Figure 5 is a block diagram of an exemplary embodiment of a computing system that facilitates out-of-band delivery of error reports according to one or more variations of the present disclosure.

[0008] Figure 6 is a flowchart of an exemplary method for out-of-band delivery of error reports according to one or more embodiments of the present disclosure.

[0009] Figure 7 is a block diagram of a portion of an exemplary in-band processor that implements a library of machine check architectures according to one or more embodiments of the present disclosure.

[0010] In all the figures, the same reference numerals and descriptions indicate like but not necessarily identical elements. While the exemplary specific embodiments described herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the figures and will be described in detail herein. However, the exemplary specific embodiments described herein are not intended to be limited to the particular forms disclosed. Rather, the disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims. Detailed Description

[0011] The present disclosure describes various devices, systems, and methods for out-of-band delivery of error reports. In some examples, traditional delivery of error reports to an out-of-band controller (e.g., a baseboard management controller) may impair and / or degrade the performance of the processor that forwards the error report. In addition to forwarding the error report to the out-of-band controller, such a processor often elevates the reporting privilege above that of typical user applications, thereby driving the processor to operate in system management mode. Unfortunately, system management mode creates security vulnerabilities that can enable malware to gain control of the processor.

[0012] Furthermore, machine check architectures often involve shadow registers that are accessible to both the operating system and the out-of-band controller for changing the state of error reports. These shadow registers can create race conditions between the operating system and the out-of-band controller, potentially resulting in undesired outcomes and / or orderings. As will be described in more detail below, the devices, systems, and methods described herein can enhance and / or augment the machine check architecture such that reporting entities (e.g., memory controllers, central processing units, etc.) can send error reports to both the processor and the out-of-band controller simultaneously.

[0013] For example, the enhanced block and / or circuitry of the machine check architecture can constitute and / or represent a single unified interface that includes a fork creating two independent and / or parallel channels for reporting errors to the processor and the out-of-band controller simultaneously. By doing so, the enhanced block and / or circuitry of the machine check architecture facilitates error reporting to both the processor and the out-of-band controller without requiring the operating system running on the processor to expend in-band workload potential for out-of-band error reporting, thereby improving the performance of user applications running on the processor. Additionally, the enhanced block and / or circuitry of the machine check architecture facilitates error reporting to both the processor and the out-of-band controller without elevating the processor to system management mode or creating race conditions between the operating system and the out-of-band controller, thereby improving the security of the processor and / or alleviating disjoint or mismatched states between the operating system and the out-of-band controller due to race conditions.

[0014] In some examples, a computing device includes an in-band processor and an out-of-band controller. In such examples, the computing device also includes a machine check architecture that includes a pipeline and a plurality of error detectors. In one example, the error detectors are configured to detect errors occurring in a plurality of circuits and report the errors to the in-band processor and the out-of-band controller via the pipeline.

[0015] In some examples, the pipeline includes a unified channel configured to carry error reports toward the in-band processor and the out-of-band controller. In such examples, the pipeline also includes a fork configured to divide the unified channel into a first channel and a second channel. In one example, the first channel carries a first copy of the error report toward the in-band processor, and the second channel carries a second copy of the error report toward the out-of-band controller.

[0016] In some examples, the machine check architecture includes at least one in-band register configured to receive a first copy of the error report via the first channel and store the first copy of the error report for access by the in-band processor. In such examples, the machine check architecture also includes at least one out-of-band register configured to receive a second copy of the error report via the second channel and store the second copy of the error report for access by the out-of-band controller.

[0017] In some examples, the in-band processor is configured to access the first copy of the error report via the in-band register and is restricted from accessing the second copy of the error report via the out-of-band register. Additionally or alternatively, the in-band processor includes an operating system configured to obtain the first copy of the error report from the in-band register.

[0018] In some examples, the out-of-band controller is configured to access the second copy of the error report via the out-of-band register and is restricted from accessing the first copy of the error report via the in-band register. Additionally or alternatively, the out-of-band controller includes a baseboard management controller and / or a system management unit communicatively coupled to the baseboard management controller.

[0019] In some examples, the system management unit is configured to access the second copy of the error report via the out-of-band register and provide the second copy of the error report to the baseboard management controller. In one example, the computing device also includes a first integrated circuit and a second integrated circuit, the first integrated circuit including the in-band processor, the machine check architecture, and the system management unit, and the second integrated circuit being external to the first integrated circuit and including the baseboard management controller.

[0020] In some examples, the in-band processor and the out-of-band controller are configured to make error logging decisions independently of each other. Additionally or alternatively, the out-of-band controller is configured to instruct the machine check architecture to perform a specific action in response to a specific error detected in one of the circuits. For example, the specific action may include and / or represent triggering an interrupt that notifies the out-of-band controller of the specific error.

[0021] In some examples, a system includes: a first integrated circuit and a second integrated circuit, the first integrated circuit including an out-of-band controller, and the second integrated circuit communicatively coupled to the first integrated circuit. In such an example, the second integrated circuit includes an in-band processor and a machine check architecture, and the machine check architecture includes a pipeline and a plurality of error detectors. In one example, the error detectors are configured to detect errors occurring in the plurality of circuits and report the errors to the in-band processor and the out-of-band controller via the pipeline.

[0022] In some examples, a method includes creating an in-band processor and a machine check architecture. In such an example, the machine check architecture includes a pipeline and a plurality of error detectors. In one example, the error detectors are configured to detect errors occurring in the plurality of circuits and report the errors to the in-band processor and the out-of-band controller via the pipeline. Additionally or alternatively, the method further includes communicatively coupling the out-of-band controller to the machine check architecture.

[0023] Reference will be made below Figures 1 to 5 and Figure 7 to provide a detailed description of exemplary devices, systems, and / or corresponding embodiments for out-of-band delivery for error reporting. The description will be provided in conjunction with Figure 6 to provide a detailed description of an exemplary method for out-of-band delivery for error reporting.

[0024] Figure 1 Exemplary computing device 100 that facilitates and / or supports out-of-band delivery of error reporting is illustrated. As Figure 1 illustrated, exemplary computing device 100 includes and / or represents machine check architecture 102, in-band processor 104, and / or out-of-band controller 106. In some examples, in-band processor 104 and / or out-of-band controller 106 are electrically and / or communicatively coupled to machine check architecture 102. In one example, machine check architecture 102 includes and / or represents pipeline 112 and / or a plurality of circuits 108(1)-(N). In this example, circuits 108(1)-(N) respectively include and / or represent error detectors 110(1)-(N). In certain embodiments, error detectors 110(1)-(N) respectively detect errors occurring in circuits 108(1)-(N) and / or report the errors to in-band processor 104 and out-of-band controller 106 via pipeline 112.

[0025] In some examples, the machine check architecture 102 may include and / or represent circuitry, devices, and / or mechanisms that detect errors and / or report errors to another circuit, device, and / or mechanism. For example, a system-on-chip (SoC) may include and / or implement the machine check architecture 102 as well as various processors and / or central processing unit (CPU) cores. In this example, the machine check architecture 102 is configured and / or programmed to monitor for hardware errors that occur in the circuits 108(1)-(N), the processors or CPU cores implemented on the SoC, and / or other features or components of the SoC.

[0026] In some examples, the circuits 108(1)-(N) include and / or represent hardware blocks and / or libraries of the machine check architecture 102. In one example, the hardware blocks and / or libraries include and / or represent a memory controller and / or a CPU core. Additionally or alternatively, the hardware blocks and / or libraries include and / or represent control registers and / or model-specific registers for checking, detecting, and / or logging various hardware and / or machine errors. Examples of such errors include but are not limited to memory or cache errors, buffer errors, translation errors, parity errors, system bus errors, error-correcting code (ECC) failures, error detection and correction (EDAC) failures, communication errors, input / output (I / O) errors, portions of one or more of the above, combinations or variations of one or more of the above, and / or any other detectable error.

[0027] In some examples, the machine check architecture 102 may be instantiated and / or implemented as multiple libraries across sub-blocks of one or more CPUs. For example, as Figure 7 illustrated, the in-band processor 104 may include and / or represent the CPU 702. In Figure 7 the illustrated example, the CPU 702 may include and / or represent at least CPU sub-blocks 704(1), 704(2), 704(3), and / or 704(4). In one example, the CPU sub-blocks 704(1)-(4) may each include and / or implement machine check architecture libraries 706(1), 706(2), 706(3), and / or 706(4). Thus, the machine check architecture 102 may be distributed across the CPU sub-blocks 704(1)-(4), and / or the machine check architecture libraries 706(1)-(4) may log a specific set of errors for each CPU sub-block. In certain implementations, each CPU may include and / or represent 3 to 10 machine check architecture instances distributed across the corresponding CPU sub-blocks.

[0028] In some examples, the in-band processor 104 may include and / or represent a hardware-implemented device and / or circuit capable of executing firmware, an operating system, and / or user applications. For example, the in-band processor 104 may include and / or represent a graphics processing unit (GPU), a GPU core, a CPU, and / or a CPU core. In this example, the in-band processor 104 may include and / or represent one of several processors (e.g., several x86 processors) implemented and / or disposed on the SoC. Additional examples of the in-band processor 104 include, but are not limited to, parallel acceleration processors, tensor cores, microprocessors, microcontrollers, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), integrated circuits, chiplets, portions of one or more of the foregoing, variations or combinations of one or more of the foregoing, and / or any other suitable in-band processor.

[0029] The in-band processor 104 may implement and / or be configured with any of a variety of different architectures and / or microarchitectures. For example, the in-band processor 104 may implement and / or be configured as a reduced instruction set computer (RISC) architecture. In another example, the in-band processor 104 may implement and / or be configured as a complex instruction set computer (CISC) architecture. Additional examples of such architectures and / or microarchitectures include, but are not limited to, 16-bit computer architectures, 32-bit computer architectures, 64-bit computer architectures, x86 computer architectures, advanced RISC machines (ARM) architectures, microprocessors without interlocked pipeline stages (MIPS) architectures, scalable processor architectures (SPARC), load-store architectures, portions of one or more of the foregoing, combinations or variations of one or more of the foregoing, and / or any other suitable architecture or microarchitecture.

[0030] In some examples, the out-of-band controller 106 may include and / or represent a hardware-implemented device and / or circuit capable of controlling and / or modifying certain hardware features and / or components on an integrated circuit (e.g., an SoC implementing various CPU cores). In one example, the out-of-band controller 106 may include and / or represent a device and / or circuit on-board (e.g., on-chip) and / or internal to the SoC implementing the in-band processor 104. For example, the out-of-band controller 106 may include and / or represent a system management unit implemented on-board and / or internal to the SoC. In another example, the out-of-band controller 106 may include and / or represent a baseboard management controller implemented external (e.g., off-chip) and / or outside of the SoC implementing the in-band processor 104. Additional examples of the out-of-band controller 106 include, but are not limited to, microprocessors, microcontrollers, FPGAs, ASICs, integrated circuits, chiplets, portions of one or more of the foregoing, variations or combinations of one or more of the foregoing, and / or any other suitable out-of-band controller.

[0031] In some examples, the term "out-of-band" may refer to any component, circuit, and / or process dedicated to and / or supporting the control plane (e.g., control data and / or firmware), management plane, and / or data regarding an underlying device (e.g., SoC). In contrast, the term "in-band" may refer to any component, circuit, and / or process dedicated to and / or supporting the user plane (e.g., user data and / or user applications) running on and / or implemented by a processor (e.g., a CPU core of an SoC). In one example, the in-band workload of an SoC may include and / or represent computational tasks performed for and / or in conjunction with user applications running on the processor, and the out-of-band workload of the SoC may include and / or represent computational tasks performed for any other purpose other than being utilized and / or consumed by such user applications.

[0032] Figure 2 Illustrated is an exemplary implementation of a machine check architecture 102 that facilitates and / or supports out-of-band delivery of error reports. In some examples, the machine check architecture 102 may include and / or represent certain components and / or features that perform and / or provide functions similar and / or identical to those described above in connection with Figure 1 the functions described. In one example, the pipeline 112 of the machine check architecture 102 includes and / or represents a unified channel 212, a fork 214, a single channel 222, and / or a single channel 224. In this example, the unified channel 212 carries and / or transmits an error report 220 towards both the in-band processor 104 and the out-of-band controller 106.

[0033] In some examples, the unified channel 212 is electrically and / or communicatively coupled to the fork 214. In such an example, the unified channel 212 feeds and / or delivers the error report 220 to the fork 214, which duplicates and / or copies the error report 220. For example, the fork 214 splits and / or divides the unified channel 212 into a single channel 222 and a single channel 224. In this example, the single channel 222 carries and / or transmits one copy of the error report 220 towards the in-band processor 104, and the single channel 224 carries and / or transmits another copy of the error report 220 towards the out-of-band controller 106.

[0034] In some examples, the machine check architecture 102 also includes and / or represents one or more in-band registers 216 and / or out-of-band registers 218. In one example, the single channel 222 may electrically and / or communicatively couple the fork 214 to the in-band register 216. Additionally or alternatively, the single channel 224 may electrically and / or communicatively couple the fork 214 to the out-of-band register 218.

[0035] In some examples, error detectors 110(1)-(N) respectively monitor and / or detect certain errors in and / or via circuits 108(1)-(N). In such examples, one or more of error detectors 110(1)-(N) generate and / or issue error reports 220 in response to detecting such errors. In one example, error detectors 110(1)-(N) may send and / or transmit error reports 220 via pipeline 112 towards both in-band processor 104 and out-of-band controller 106. For example, error report 220 may traverse and / or travel from one or more of circuits 108(1)-(N) via unified channel 212 to fork 214. In this example, fork 214 may duplicate and / or copy error report 220 for transmission to both in-band register 216 and out-of-band register 218. Thus, one copy of error report 220 may traverse and / or travel from fork 214 to in-band register 216 via a single channel 222, and another copy of error report 220 may traverse and / or travel from fork 214 to out-of-band register 218 via a single channel 224.

[0036] In some examples, in-band register 216 receives one copy of error report 220 and stores this copy of error report 220 for access by in-band processor 104. Additionally or alternatively, out-of-band register 218 receives another copy of error report 220 and stores this copy of error report 220 for access by out-of-band controller 106. By delivering copies of error report 220 to both in-band register 216 and out-of-band register 218 via pipeline 112, machine check architecture 102 may enable out-of-band controller 106 to access and / or obtain a copy of error report 220 without in-band processor 104 forwarding a copy of error report 220 to out-of-band controller 106, thereby alleviating and / or reducing out-of-band work performed by in-band processor 104, improving its performance or efficiency, and / or avoiding race conditions between in-band processor 104 and out-of-band controller 106. Further, by bypassing in-band processor 104 when delivering a copy of error report 220 to out-of-band controller 106, machine check architecture 102 may prevent and / or avoid the need to push in-band processor 104 into system management mode, thereby alleviating and / or reducing corresponding security vulnerabilities.

[0037] Figure 3 Illustrates an exemplary embodiment of computing device 100 that facilitates and / or supports out-of-band delivery of error reports. In some examples, computing device 100 may include and / or represent performing and / or providing in connection with the above Figure 1 and Figure 2Certain components and / or features that perform functions similar to and / or the same as those described for either. In one example, computing device 100 includes and / or represents integrated circuit 302 and / or integrated circuit 304 communicatively coupled to each other. In this example, integrated circuit 302 includes and / or represents machine check architecture 102 and / or in-band processor 104, and integrated circuit 304 includes and / or represents out-of-band controller 106. Thus, integrated circuit 304 is off-chip and / or external to integrated circuit 302. However, integrated circuits 302 and 304 may be mounted and / or applied to the same circuit board.

[0038] In some examples, integrated circuit 302 includes and / or represents a SoC having a number of CPU cores and machine check architecture 102. In one example, in-band processor 104 is on-chip and / or internal to the SoC, and out-of-band controller 106 is off-chip and / or external to the SoC. In this example, in-band processor 104 is able to access a copy of error report 220 stored in in-band register 216, but is restricted from accessing a copy of error report 220 stored in out-of-band register 218. For example, in-band processor 104 may implement and / or execute operating system 306, which obtains, receives, and / or retrieves a copy of error report 220 from in-band register 216. Additionally or alternatively, out-of-band controller 106 is able to access a copy of error report 220 stored in out-of-band register 218, but is restricted from accessing a copy of error report 220 stored in in-band register 216.

[0039] In some examples, in-band processor 104 and out-of-band controller 106 may make error logging decisions independently of each other. For example, in-band processor 104 may clear a specific flag (e.g., a status flag) in in-band register 216, which remains set in out-of-band register 218. Alternatively, out-of-band controller 106 may clear a specific flag (e.g., a status flag) in out-of-band register 218, which remains set in in-band register 216. Either way, this flag mismatch across in-band register 216 and out-of-band register 218 may cause in-band register 216 and out-of-band register 218 to log and / or ignore different errors from the same error report. Thus, in-band processor 104 and out-of-band controller 106 may have independent control and / or programmability over their respective registers in machine check architecture 102.

[0040] Figure 4 Illustrates another exemplary implementation of computing device 100 that facilitates and / or supports out-of-band delivery of error reports. In some examples, computing device 100 may include and / or represent certain components and / or features that perform functions similar to and / or the same as those described for any of the above in Figures 1 to 3 and perform functions similar to and / or the same as those described for any of the above. AsFigure 4 As illustrated, the exemplary computing device 100 includes and / or represents integrated circuit 302 and / or integrated circuit 304 communicatively coupled to each other. In one example, integrated circuit 302 includes and / or represents machine check architecture 102, in-band processor 104, and / or out-of-band interface 404. In this example, integrated circuit 304 includes and / or represents out-of-band controller 106 communicatively coupled to out-of-band interface 404, which facilitates access by out-of-band controller 106 to a copy of error report 220 stored in out-of-band register 218.

[0041] In some examples, out-of-band interface 404 may include and / or represent a system management unit that obtains, receives, and / or retrieves a copy of error report 220 from out-of-band register 218. Additionally or alternatively, out-of-band controller 106 may include and / or represent a baseboard management controller that interfaces with and / or communicates with the system management unit. In one example, the baseboard management controller obtains, receives, and / or retrieves a copy of error report 220 from the system management unit.

[0042] In some examples, out-of-band controller 106 and / or out-of-band interface 404 may instruct and / or direct machine check architecture 102 to perform one or more specific actions in response to a specific error identified and / or included in error report 220. For example, out-of-band controller 106 and / or out-of-band interface 404 may be programmed and / or configured to initiate and / or trigger a specific action in response to a specific error by programming out-of-band register 218. In one example, the specific action may include and / or represent triggering an interruption to notify out-of-band controller 106 of the specific error. For example, out-of-band interface 404 may be programmed and / or configured to generate an interruption to notify out-of-band controller 106 of the specific error.

[0043] Figure 5 Exemplary implementation 500 involving computing system 502 is illustrated. In some examples, computing system 502 may include and / or represent certain components and / or features that perform and / or provide functions similar and / or identical to those described above in connection with Figures 1 to 4 any of the foregoing. As illustrated in exemplary implementation 500 of Figure 5 the foregoing, computing system 502 includes and / or represents an SoC 506 equipped with machine check architecture 102 and / or system management unit 508.

[0044] In some examples, computing system 502 also includes and / or represents a baseboard management controller 510 that is electrically and / or communicatively coupled to system management unit 508. In one example, system management unit 508 obtains, receives, and / or retrieves a copy of an error report from out-of-band registers in machine check architecture 102. In this example, baseboard management controller 510 then obtains, receives, and / or retrieves a copy of the error report from system management unit 508 for processing and / or facilitating decision-making.

[0045] In some examples, in combination with Figures 1 to 5 and Figure 7 the various devices and / or systems described may include and / or represent one or more additional circuits, components, and / or features that are not necessarily illustrated and / or labeled in Figures 1 to 5 and Figure 7 For example, computing device 100 may also include and / or represent additional analog and / or digital circuits, on-board logic components, transistors, resistors, capacitors, diodes, inductors, switches, registers, flip-flops, connections, traces, buses, semiconductor (e.g., silicon) devices and / or structures, processing devices, storage devices, circuit boards, packages, substrates, enclosures, combinations or variations of one or more of the foregoing, and / or any other suitable components that facilitate and / or support out-of-band delivery of error reports. In certain implementations, one or more of these additional circuits, components, devices, and / or features may be inserted and / or applied between any existing circuits, components, and / or devices illustrated in Figures 1 to 5 and Figure 7 that are consistent with the purposes and / or objectives provided herein. Thus, the electrical and / or communicative couplings described with reference to Figures 1 to 5 and Figure 7 may be direct connections without intermediate components, devices, and / or nodes, or indirect connections with one or more intermediate components, devices, and / or nodes.

[0046] In some examples, as used herein, the phrase "configured to couple" and / or the term "coupled" may refer to a direct connection and / or an indirect connection. For example, a direct coupling between two components may constitute and / or represent a coupling in which the two components are directly connected to each other through a single node that provides electrical continuity from one of the two components to the other. In other words, a direct coupling may exclude and / or omit any additional components between the two components.

[0047] Additionally or alternatively, an indirect coupling between two components may constitute and / or represent a coupling in which the two components are indirectly connected to each other through multiple nodes that do not provide electrical continuity from one of the two components to the other. In other words, an indirect coupling may include and / or incorporate at least one additional component between the two components.

[0048] Figure 6 is a flowchart of an exemplary method 600 for out-of-band delivery for error reporting. In one example, Figure 6 the steps shown in may be performed and / or implemented during the manufacturing and / or assembly of a computing device and / or system. Additionally or alternatively, Figure 6 the steps shown in may also incorporate and / or involve various sub-steps and / or variations consistent with the description provided above in conjunction with Figures 1 to 5 the provided description.

[0049] As Figure 6 illustrated, the exemplary method 600 includes and / or involves a step (610) of creating an in-band processor. Step 610 may be performed in various ways, including any of the ways described above in conjunction with Figures 1 to 5 the provided description. For example, a computing equipment manufacturer and / or subcontractor may create, manufacture, and / or produce an in-band processor.

[0050] The exemplary method 600 also includes a step (620) of creating a machine check architecture that includes a pipeline and a plurality of error detectors configured to detect errors occurring in a plurality of circuits and report the errors to the in-band processor and an out-of-band controller via the pipeline. Step 620 may be performed in various ways, including any of the ways described above in conjunction with Figures 1 to 5 the provided description. For example, a computing equipment manufacturer and / or subcontractor may create, manufacture, and / or produce a machine check architecture that includes a pipeline and a plurality of error detectors configured to detect errors occurring in a plurality of circuits and report the errors to the in-band processor and an out-of-band controller via the pipeline.

[0051] The exemplary method 600 also includes a step (630) of communicatively coupling an out-of-band controller to the machine check architecture. Step 630 may be performed in various ways, including any of the ways described above in conjunction with Figures 1 to 5 the provided description. For example, a computing equipment manufacturer and / or subcontractor may communicatively couple and / or connect an out-of-band controller to the machine check architecture.

[0052] While the foregoing disclosure has set forth various specific implementations using specific block diagrams, flowcharts, and examples, each block diagram component, flowchart step, operation, and / or component described and / or illustrated herein can be implemented individually and / or jointly using a variety of hardware, software, or firmware (or any combination thereof) configurations. Additionally, any disclosure of components contained within other components should be considered exemplary in nature, as many other architectures can be implemented to achieve the same functionality. Furthermore, the various steps, events, and / or features performed by such components should be considered exemplary in nature, as many alternative ways and / or variations can be implemented within the scope of the present disclosure to achieve the same functionality.

[0053] The order of process parameters and steps described and / or illustrated herein is given by way of example only and can vary as needed. For example, while the steps illustrated and / or described herein are shown or discussed in a particular order, these steps do not necessarily need to be performed in the order illustrated or discussed. The various exemplary methods described and / or illustrated herein can also omit one or more steps described or illustrated herein, or include additional steps other than those disclosed.

[0054] The foregoing description has been provided to enable other technicians in the art to best utilize the various aspects of the exemplary specific implementations disclosed herein. This exemplary description is not intended to be exhaustive or limited to any precise form. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The specific implementations disclosed herein should be considered illustrative rather than restrictive in all respects. When determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0055] Unless otherwise indicated, the terms "connected to" and "coupled to" (and their derivatives) as used in the specification and claims will be regarded as allowing both direct and indirect (i.e., via other elements or components) connections. Additionally, the term "a" or "an" as used in the specification and claims will be regarded as meaning "at least one". Finally, for ease of use, the terms "comprising" and "having" (and their derivatives) as used in the specification and claims may be interchanged with the word "including" and have the same meaning.

Claims

1. A computing device, the computing device comprising: an in-band processor; an out-of-band controller; and a machine check architecture, the machine check architecture comprising: a pipeline; and a plurality of error detectors, the plurality of error detectors being configured to: detect errors occurring in a plurality of circuits; and report the errors to the in-band processor and the out-of-band controller via the pipeline.

2. The computing device according to claim 1, wherein the pipeline comprises: a unified channel configured to carry error reports towards the in-band processor and the out-of-band controller; and a fork configured to divide the unified channel into: a first channel configured to carry a first copy of the error report towards the in-band processor; and a second channel configured to carry a second copy of the error report towards the out-of-band controller.

3. The computing device according to claim 2, wherein the machine check architecture comprises: at least one in-band register configured to: receive the first copy of the error report via the first channel; and store the first copy of the error report for access by the in-band processor; and at least one out-of-band register configured to: receive the second copy of the error report via the second channel; and store the second copy of the error report for access by the out-of-band controller.

4. The computing device according to claim 3, wherein the in-band processor: is configured to access the first copy of the error report via the in-band register; and is restricted from accessing the second copy of the error report via the out-of-band register.

5. The computing device according to claim 4, wherein the in-band processor includes an operating system configured to obtain the first copy of the error report from the in-band register.

6. The computing device according to claim 3, wherein the out-of-band controller: is configured to access the second copy of the error report via the out-of-band register; and is restricted from accessing the first copy of the error report via the in-band register.

7. The computing device according to claim 3, wherein the out-of-band controller includes at least one of the following: a baseboard management controller; or a system management unit communicatively coupled to the baseboard management controller.

8. The computing device according to claim 7, wherein the system management unit is configured to: access the second copy of the error report via the out-of-band register; and provide the second copy of the error report to the baseboard management controller.

9. The computing device according to claim 7, the computing device further comprising: a first integrated circuit including the in-band processor, the machine check architecture, and the system management unit; and a second integrated circuit external to the first integrated circuit and including the baseboard management controller.

10. The computing device according to claim 1, wherein the in-band processor and the out-of-band controller are configured to make error logging decisions independently of each other.

11. The computing device according to claim 1, wherein the out-of-band controller is configured to instruct the machine check architecture to perform a specific action in response to a specific error detected in one of the circuits.

12. The computing device according to claim 11, wherein the specific action includes triggering an interruption to notify the out-of-band controller of the specific error.

13. A system, the system comprising: A first integrated circuit, the first integrated circuit including an out-of-band controller; And A second integrated circuit, the second integrated circuit communicatively coupled to the first integrated circuit, the second integrated circuit including: An in-band processor; and A machine check architecture, the machine check architecture including: A pipeline; and A plurality of error detectors, the plurality of error detectors being configured to: Detect errors occurring in a plurality of circuits; and Report the errors to the in-band processor and the out-of-band controller via the pipeline.

14. The system according to claim 13, wherein the pipeline includes: A unified channel, the unified channel being configured to carry error reports towards the in-band processor and the out-of-band controller; And A fork, the fork being configured to divide the unified channel into: A first channel, the first channel carrying a first copy of the error report towards the in-band processor; And A second channel, the second channel carrying a second copy of the error report towards the out-of-band controller.

15. The system according to claim 14, wherein the machine check architecture includes: At least one in-band register, the at least one in-band register being configured to: Receive the first copy of the error report via the first channel; And Store the first copy of the error report for access by the in-band processor; And At least one out-of-band register, the at least one out-of-band register being configured to: Receive the first copy of the error report via the first channel; And Store the second copy of the error report for access by the out-of-band controller.

16. The system according to claim 14, wherein the in-band processor: Is configured to access the first copy of the error report via the in-band register; and Is restricted from accessing the second copy of the error report via the out-of-band register.

17. The system according to claim 16, wherein the in-band processor includes an operating system, the operating system being configured to obtain the first copy of the error report from the in-band register.

18. The system according to claim 15, wherein the out-of-band controller: Is configured to access the second copy of the error report via the out-of-band register; and Is restricted from accessing the first copy of the error report via the in-band register.

19. The system according to claim 15, wherein the out-of-band controller includes at least one of the following: A baseboard management controller; or A system management unit communicatively coupled to a baseboard management controller.

20. A method, the method comprising: Creating an in-band processor; Creating a machine check architecture, the machine check architecture comprising: A pipeline; and A plurality of error detectors configured to: Detect errors occurring in a plurality of circuits; and Report the errors to the in-band processor and an out-of-band controller via the pipeline; and Communicatively coupling the out-of-band controller to the machine check architecture.

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