Interface circuit, data transmission method, display panel and display device

Abstract

The invention discloses an interface circuit, a data transmission method, a display panel and a display device, belongs to the technical field of interfaces, and solves the problem of data asynchronization when data transmission is carried out on existing multiple port physical layers (PHY). The data transmission method comprises the following steps: each port physical layer (PHY) in a data transmission module (10) analyzes a received first input signal to obtain input data (Data), a clock signal (PHYCLK) and a lock signal (Lock) corresponding to the port physical layer (PHY); the control module (20) generates a control signal according to a second input signal, wherein the second input signal is related to a plurality of lock signals (Lock) of a plurality of port physical layers (PHYs); when lock signals (Lock) corresponding to all port physical layers (PHY) are working levels, a plurality of data synchronization units (FIFO) in the data synchronization module (30) synchronously send respective corresponding input data (Data) based on control signals; data synchronization is realized when data is transmitted by a plurality of port physical layers (PHY).

Description

Interface circuit, data transmission method, display panel and display device Technical Field

[0001] The present disclosure belongs to the field of interface technology, and particularly relates to an interface circuit, a data transmission method, a display panel, and a display device. Background Art

[0002] Existing point-to-point (P2P) high-speed communication receiving interfaces typically use two lanes for signal transmission. However, the data volume of a two-lane interface cannot meet the requirements of some ultra-high-definition display driver chips. Therefore, the development of a multi-lane P2P high-speed interface is needed. Currently, multi-lane or two-lane interfaces are implemented using the same port physical layer (PHY). Since each PHY corresponds to one clock signal and one lock signal, multiple lanes or two lanes share a single clock signal and only need to be locked once, ensuring that synchronization between lanes is not required. However, due to the high cost of PHY design and improvement, integrating too many lanes into a single PHY module is inflexible and hinders scalability. Existing technologies use a single PHY IP with only one lane, combining multiple PHYs to form a multi-lane interface IP. Since each PHY corresponds to one clock signal and one lock signal, this can lead to data asynchrony and lane lock asynchrony due to different clock signals corresponding to the lanes of different PHYs.

[0003] Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a data synchronization interface circuit, a data transmission method, a display panel and a display device.

[0005] In a first aspect, the technical solution adopted to solve the technical problem of the present invention is an interface circuit, characterized in that it is applied to an integrated circuit, and the interface circuit includes:

[0006] A data transmission module comprising a plurality of port physical layers; for each port physical layer, the port physical layer parses a first input signal at a first input terminal to obtain input data at a data output terminal and a clock signal at a clock signal terminal; each port physical layer further comprises a lock signal terminal for outputting a lock signal; when a lock signal at the lock signal terminal of the port physical layer detects that the clock signal is in a locked state, the lock signal at the lock signal terminal changes from a non-operating level to an operating level;

[0007] a control module, configured to obtain a control signal at a second output terminal of the control module according to a second input signal inputted at a second input terminal of the control module, wherein the second input signal is correlated with a plurality of lock signals at a plurality of lock signal terminals of the plurality of port physical layers;

[0008] A data synchronization module includes multiple data synchronization units corresponding one-to-one to the multiple port physical layers, and one data synchronization unit corresponds to one control signal terminal; for each data synchronization unit, a third input terminal of the data synchronization unit receives the input data of the port physical layer corresponding to the data synchronization unit, an eighth input terminal of the data synchronization unit receives the lock signal, a control signal terminal of the data synchronization unit receives the control signal, and a fourth input terminal of the data synchronization unit receives the clock signal or reset signal of the port physical layer corresponding to the data synchronization unit based on the control signal; when the lock signals corresponding to all port physical layers are at working levels, the multiple data synchronization units synchronously send the input data corresponding to each of them based on the control signal.

[0009] In some embodiments, the second input signal is a plurality of lock signals of the physical layers of the plurality of ports, the control signal is the reset signal, and when the control module responds that the plurality of lock signals are all at a working level, the reset signal outputted from the second output end is at a working level.

[0010] In some embodiments, the control module is an AND gate.

[0011] In some embodiments, the control module includes a judgment unit and a plurality of first control units corresponding one-to-one to the physical layer of the port, the control signal includes a plurality of first control signals corresponding one-to-one to the first control units, the first control signal is a write clock signal of the data synchronization unit; for each first control unit, it includes a fifth input terminal and a sixth input terminal, the fifth input terminal is used to receive an external clock signal; the sixth input terminal is used to receive the clock signal output by the physical layer of the corresponding port; wherein,

[0012] The judging unit is configured to judge whether the multiple clock signals corresponding to the physical layers of the multiple ports are in an unlocked state according to the second input signal;

[0013] The first control unit is configured to select the external clock from the external clock signal received at the fifth input terminal and the clock signal received at the sixth input terminal as the write clock signal when any one of all the clock signals is in an unlocked state.

[0014] In some embodiments, the control module further includes a plurality of second control units corresponding one-to-one to the physical layers of the ports, the control signal further includes a plurality of second control signals corresponding one-to-one to the second control units, and the second control signal is a read clock signal; each second control unit includes a ninth input terminal and a tenth input terminal, the ninth input terminal is used to receive an external read clock signal; the tenth input terminal is used to receive any one of the plurality of read clock signals corresponding to the physical layers of the plurality of ports;

[0015] The second control unit is used to select the external read clock signal received from the ninth input terminal and the any one of the clock signals received from the tenth input terminal as the read clock signal when any one of all the clock signals is in an unlocked state.

[0016] In some embodiments, the first control unit and the second control unit are both selectors.

[0017] In some embodiments, one of the port physical layers further includes a reset signal terminal, the interface circuit further includes a reset module, the seventh input terminal of the reset module is connected to the second output terminal of the control module, and the third output terminal of the reset module is connected to the reset signal terminals of all port physical layers.

[0018] In some embodiments, when multiple integrated circuits are cascaded, each integrated circuit corresponds to a control signal, and the interface circuit also includes a lock control module, the first end of the lock control module is connected to the multiple integrated circuits, and is used to receive the control signals corresponding to each integrated circuit, the second end of the lock control signal is connected to the seventh input end of the reset module, and is used to send the control signals corresponding to each integrated circuit to the reset module; the third output end of the reset module is connected to the third end of the lock control module, and is used to receive the reset signal output by the reset module, and send it to each integrated circuit through the first end of the lock control module.

[0019] In some embodiments, the first input signal received by the first input end of the physical layer of the port is one input signal.

[0020] In some embodiments, the first input signal received by the first input end of the one port physical layer is a multi-path input signal.

[0021] In some embodiments, the interface module also includes a parsing module, which is connected to the data synchronization module and includes multiple parsing units corresponding one to one with the port physical layer, one data synchronization unit corresponding to one parsing unit, for receiving and parsing the input data sent by the data synchronization unit.

[0022] In a second aspect, an embodiment of the present disclosure further provides a method for data transmission, the method being applied to the interface circuit according to any one of claims 1 to 11, the method comprising:

[0023] The physical layer of each port in the data transmission module parses the received first input signal to obtain input data, a clock signal, and a lock signal corresponding to the physical layer of the port;

[0024] The control module generates a control signal according to a second input signal, wherein the second input signal is related to a plurality of lock signals of a physical layer of a plurality of ports;

[0025] When the lock signals corresponding to the physical layers of all ports are at the working level, the multiple data synchronization units in the data synchronization module synchronously send the input data corresponding to each of them based on the control signal.

[0026] In some embodiments, the control module is an AND gate, and the control module generates a control signal according to the second input signal, including:

[0027] A plurality of lock signals corresponding to the plurality of physical layers are received, and the control signal is generated through an AND gate.

[0028] In some embodiments, when the lock signals corresponding to the physical layers of all ports are at a working level, the multiple data synchronization units in the data synchronization module synchronously send the input data corresponding to each of them based on the control signal, including:

[0029] Using the control signal as a reset signal for multiple data synchronization units of the data synchronization module;

[0030] Based on the reset signal, the multiple data synchronization units synchronously send the input data corresponding to each of them when the lock signals corresponding to the physical layers of all ports are at the working level.

[0031] In some embodiments, the method further comprises:

[0032] The physical layers of the multiple ports are reset based on the control signal.

[0033] In some embodiments, the control signal includes a write clock signal, and the control module generates the control signal according to the second input signal, including:

[0034] The control module determines whether the multiple clock signals corresponding to the physical layers of the multiple ports are in an unlocked state according to the second input signal;

[0035] When any one of all the clock signals is in an unlocked state, the control module selects the external clock from the external clock signal and the clock signal as the write clock signal.

[0036] In some embodiments, the control module further includes a read clock signal, and the control module generates a control signal according to the second input signal, further including:

[0037] When any one of all the clock signals is in an unlocked state, the external read clock is selected from the external read clock signal and any one of the clock signals as the read clock signal.

[0038] In a third aspect, an embodiment of the present disclosure further provides a display panel, comprising the interface circuit described in any embodiment of the first aspect.

[0039] In a fourth aspect, an embodiment of the present disclosure further provides a display device, comprising the display panel provided in the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic diagram of an interface circuit in the prior art;

[0041] FIG2 is another interface circuit provided in the prior art;

[0042] FIG3 is a schematic diagram of an interface circuit provided in an embodiment of the present disclosure;

[0043] FIG4 is a partial schematic diagram of an interface circuit provided by an embodiment of the present disclosure;

[0044] FIG5 is a schematic diagram of a control module according to an embodiment of the present disclosure;

[0045] FIG6 is a partial schematic diagram of an interface circuit provided by an embodiment of the present disclosure;

[0046] FIG7 is another interface circuit provided by an embodiment of the present disclosure;

[0047] FIG8 is another interface circuit provided in an embodiment of the present disclosure;

[0048] FIG9a-FIG9b are an interface circuit of a dual-lock architecture provided by an embodiment of the present disclosure;

[0049] FIG10 is another interface circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0051] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0052] Figure 1 is a schematic diagram of an interface circuit in the prior art. This interface circuit is illustrated using a PHY transmitting a 2-lane signal as an example. As shown in Figure 1 , the interface circuit includes two input terminals, one receiving Lane 1 and the other receiving Lane 2 from the data transmitter. The PHY parses the two input signals into corresponding Data 1 [19:0], Data 2 [19:0], and a PHY_CLK signal, while also generating a Lock signal. When the PHY transmits data, both Data 1 [19:0] and Data 2 [19:0] are transmitted according to the PHY_CLK signal when the Lock signal is at the operating level. Because Data 1 [19:0] and Data 2 [19:0] both respond to the same PHY_CLK and Lock signals, Data 1 [19:0] and Data 2 [19:0] are transmitted simultaneously, preventing any asynchrony. However, in order to meet the requirements of some ultra-high-definition display driver chips, it is necessary to develop more lane interface circuits, which means that a PHY needs to integrate more lane signals. However, when a PHY integrates too many lane signals, it will cause PHY transmission to be inflexible and not conducive to expansion.

[0053] To address the above issues, another interface circuit has been proposed in the prior art. Figure 2 shows another interface circuit provided in the prior art. For better integration and flexibility, the interface circuit adopts an architecture where 1 PHY corresponds to 1 Lane signal. A multi-Lane circuit architecture can be spliced ​​together according to the data volume requirements. As shown in Figure 2, this architecture includes n PHYs, namely PHY_1, PHY_2, ..., PHY_n. Each PHY corresponds to 1 Lane signal, namely Lane_1, Lane_2, ..., Lane_n, with a total of n input signals. Each PHY receives a PHY_CLK (not shown in the figure), a Lock, and input data corresponding to the input signal. Each PHY transmits its own Data according to its own PHY_CLK signal and its own Lock signal. Since the PHY_CLK recovery time of each PHY is not fixed (i.e., the time when the clock is locked is not fixed), the time when the PHY transmits data is different. At the same time, each PHY also corresponds to a Link circuit, which is used to parse the received input data for subsequent use. Although each PHY corresponds to a PHY_CLK signal, all link circuits use the same clock signal. Figure 2 illustrates this by assuming each link circuit uses clk1 (PHY_CLK corresponding to PHY1). Because each link circuit corresponding to each lane signal uses Lane_1's PHY_CLK (clk1), clock domain crossover occurs. These two factors lead to data asynchrony, resulting in display anomalies.

[0054] In response to the problems existing in the prior art, an interface circuit is proposed in an embodiment of the present disclosure. FIG3 is a schematic diagram of an interface circuit provided in an embodiment of the present disclosure. As shown in FIG3 , the interface circuit is applied to an integrated circuit, and the interface circuit includes: a data transmission module 10, a control module 20, and a data synchronization module 30. Among them, the data transmission module 10 includes a plurality of port physical layers PHY (PHY_1....PHY_n); for each port physical layer PHY, the port physical layer PHY parses the first input signal of the first input end to obtain the input data Data of the data output end and the clock signal PHY_CLK of the clock signal end; each port physical layer PHY also includes a lock signal end for outputting a lock signal Lock; when the lock signal Lock of the lock signal end of the port physical layer PHY detects that the clock signal PHY_CLK of the clock signal end is in a locked state, the lock signal Lock of the lock signal end changes from a non-working level to a working level.

[0055] The control module 20 is used to obtain a control signal at a second output end of the control module 20 according to a second input signal inputted at a second input end of the control module 20 , where the second input signal is related to multiple lock signals Lock at multiple lock signal ends of multiple port physical layer PHYs.

[0056] The data synchronization module 30 includes multiple data synchronization units FIFO (FIFO_1...FIFO_n) corresponding one-to-one to multiple port physical layer PHYs, and one data synchronization unit FIFO corresponds to one control signal terminal; for each data synchronization unit FIFO, the third input terminal of the data synchronization unit FIFO receives the input data Data of the port physical layer PHY corresponding to the data synchronization unit FIFO, the eighth input terminal of the data synchronization unit FIFO receives the lock signal Lock, the control signal terminal of the data synchronization unit FIFO receives the control signal, and the fourth input terminal of the data synchronization unit FIFO receives the clock signal PHY_CLK of the port physical layer PHY corresponding to the data synchronization unit FIFO or the reset signal reset of the FIFO based on the control signal; when the lock signals Lock corresponding to all port physical layer PHYs are at the working level, multiple data synchronization units FIFO (FIFO_1....FIFO_n) synchronously send the input data Data corresponding to each of them based on the control signal.

[0057] Specifically, the data transmission module 10 is used to receive input data from the data transmitter and transmit it to the data receiver. The port physical layer (PHY) is a common abbreviation for the physical layer of the OSI model and is a type of chip. From a hardware perspective, a typical PHY chip is a hybrid analog-digital circuit responsible for receiving analog signals such as electrical and optical signals. After demodulation and A / D conversion, the signal is passed to the MAC chip for processing via the MII interface. Each PHY parses the received first input signal to obtain the corresponding input data (Data) and a clock signal (PHY_CLK), and simultaneously generates a lock signal (Lock). That is, there is a one-to-one correspondence between the PHY, PHY_CLK, and Lock. As shown in Figure 3, the data transmission module 10 includes PHY_1 and its corresponding PHY_1_CLK, Lock_1, and Data_1; ... PHY_n and its corresponding PHY_n_CLK, Lock_n, and Data_n. PHY_CLK is the clock signal of PHY, which changes periodically. The circuit only collects signals or data when the rising edge of the clock signal triggers it. Lock is a status signal that characterizes the status of the PHY_CLK signal. When Lock is in the working state, it means that the corresponding PHY_CLK is in the locked state, and normal data transmission can be performed at this time. On the contrary, when Lock is in the non-working state, it means that the corresponding PHY_CLK is in the unlocked state, and data transmission cannot be performed at this time. Generally, before PHY transmits input data, the transmitting end sends a clk traning signal to PHY, and starts to lock the PHY_CLK signal after receiving the clk traning signal. Generally, after about 15 microseconds, PHY_CLK is in the locked state, that is, Lock changes from the non-working level to the working level. The working level of Lock can be high or low, and the present disclosure does not limit this. In some embodiments, the first input signal is a differential signal.

[0058] The data synchronization module 30 is used to synchronize the input data of each PHY based on the control signal. Specifically, the data synchronization module 30 receives the input data Data, the clock signal PHY_CLK and the lock signal Lock sent by the data transmission module 10, and sends the input data Data according to the clock signal PHY_CLK and the lock signal Lock. The data synchronization module 30 includes multiple data synchronization units FIFO, and the PHY and FIFO also have a one-to-one correspondence. FIFO_1 receives Data_1, PHY_1_CLK and Lock_1 transmitted by PHY_1; ... FIFO_n receives Data_n, PHY_n_CLK and Lock_n transmitted by PHY_n. In addition, each data synchronization unit FIFO also receives a reset signal reset. Only when reset is in working state, the data synchronization unit FIFO starts to work. Generally, the reset signal reset is in working state by default after power-on. In the prior art, the reset signal reset of each FIFO is in a working state by default after power-on, and each PHY directly sends its own PHY_CLK and Lock to the data synchronization module 30. Since there is a one-to-one correspondence between PHY and PHY_CLK and Lock, when the PHY transmits data according to their own PHY_CLK and Lock, there is no interference between the PHYs. The problem of asynchronous data transmission may exist between the PHYs, further resulting in abnormal display of the display panel.

[0059] The inventors discovered that, in fact, the signals used by FIFO to control the transmission of input data Data include the reset signal reset and the FIFO clock. Among them, for the reset signal reset, the FIFO starts working only when the reset signal reset is in working state, and the transmission of input data by the FIFO can be controlled by controlling the reset signal reset; for the FIFO clock, the circuit only collects the action of the signal or data when the rising edge of the clock is triggered, that is, the input data Data is transmitted according to the frequency of the FIFO clock, so the transmission of input data by the FIFO can be controlled by controlling the FIFO clock. Furthermore, the clock of the FIFO is generally related to the clock signal PHY_CLK of the PHY, and the write clock of the FIFO is generally the clock signal PHY_CLK of the PHY. In summary, the time for each PHY to transmit data can be controlled by controlling the PHY_CLK of each PHY or the reset of the FIFO, so as to achieve synchronous data transmission between each PHY.

[0060] Since Lock is a status signal that indicates whether PHY_CLK is locked, PHY_CLK can only perform normal data transmission when Lock is in operation. Therefore, the disclosed embodiments can determine the operating status of each PHY based on a second input signal associated with multiple lock signals "Lock" at multiple lock signal terminals of multiple-port physical layer PHYs. Simultaneously, a control signal is generated based on the second signal associated with multiple lock signals "Lock" at multiple lock signal terminals of multiple-port physical layer PHYs. This control signal is used to control data transmission in each FIFO, thereby ensuring synchronous data transmission across each PHY.

[0061] In the embodiment of the present disclosure, the control module 20 first processes the second input signal related to the multiple lock signals Lock of the multiple lock signal terminals of the multiple port physical layer PHY to obtain a control signal, and then transmits the control signal to the multiple data synchronization unit FIFOs corresponding to the data synchronization module 30. Among them, the second input signal related to the multiple lock signals Lock of the multiple lock signal terminals of the multiple port physical layer PHY can be the Lock signal itself, or it can be a signal that controls the Lock signal or other signals related to the Lock signal, such as the clock signal PHY_CLK, etc., which is not limited by the present disclosure. The control signal can be used as the clock signal of the FIFO to control the transmission of input data by each FIFO, and can also be used as a reset signal reset to control the time when each FIFO starts working, thereby controlling the time when each FIFO transmits input data. And the control signal only becomes the working state when each data synchronization unit FIFO is in a state where it can transmit data (Lock is the working level). According to the control signal, each data synchronization unit FIFO can control all PHYs to synchronously transmit input data. At the same time, the other signal (PHY_CLK or reset) not sent as a control signal to the data synchronization unit FIFO is directly received by the fourth input terminal of the data synchronization unit FIFO and serves as the clock signal or reset signal for the data synchronization unit FIFO. In this way, each data synchronization unit FIFO can maintain synchronized data transmission through reset or clock. When the lock signal corresponding to the physical layer PHY of all ports is at an operating level, multiple data synchronization unit FIFOs synchronously transmit their corresponding input data.

[0062] It should be noted that one data synchronization unit FIFO corresponds to one data control terminal, and each data control terminal must receive a data control signal.

[0063] In the embodiment of the present disclosure, based on a second input signal related to multiple lock signals Lock at multiple lock signal terminals of multiple port physical layers PHY, the second input signal can reflect the current state of input data transmitted by each port physical layer, for example, whether each PHY is currently capable of transmitting data; the control module 30 generates a control signal based on the second input signal, and sends the control signal to multiple data synchronization units FIFO of the data synchronization module 30, so that the control signal can control each FIFO to send the corresponding input data based on the current state of data transmitted by each PHY, so that each FIFO can synchronously send the corresponding input data. Specifically, the control signal only becomes a working state to control each FIFO to transmit data when each data synchronization unit FIFO is in a state capable of transmitting data. In this way, when each data synchronization unit FIFO transmits input data Data according to the received control signal, it can ensure that each data synchronization unit FIFO corresponding to each PHY synchronously sends its own input data.

[0064] In some embodiments, the second input signal is multiple lock signals Lock of multiple port physical layers PHY, the control signal is a reset signal reset, and when the control module 20 responds to multiple lock signals Lock being at working levels, the reset signal reset outputted from the second output end is at a working level.

[0065] Specifically, in the embodiment of the present disclosure, a reset signal reset is generated based on all the Locks corresponding to all the PHYs. The reset signal reset is in working state only when the Locks of all the PHYs are in working state. That is to say, only when all the FIFOs are in a state where they can transmit data, the reset signal rest is in working state, controlling each FIFO to start working. At this time, the clocks of the FIFOs are also the same, and there will be no problem of different clocks, which can ensure that each FIFO can transmit data synchronously. At this time, the fourth input terminal of each data synchronization unit FIFO respectively receives the clock signal PHY_CLK of the port physical layer PHY corresponding to the data synchronization unit FIFO.

[0066] It should be noted that the control signal terminal corresponding to each FIFO receives the reset signal reset respectively, so as to ensure that each FIFO is reset at the same time and starts working at the same time.

[0067] In the embodiment of the present disclosure, the start time of each FIFO is controlled by controlling the reset signal reset of the FIFO, thereby ensuring that each FIFO can transmit data when starting to work, and realizing synchronous transmission of input data by each PHY.

[0068] In some embodiments, the control module 10 is an AND gate.

[0069] Specifically, the lock corresponding to each PHY serves as the input of an AND gate, and the output control signal serves as the output of the AND gate. This ensures that the output control signal is active only when all the locks corresponding to the PHY are active. If one of the locks corresponding to the PHY is inactive, the output control signal is inactive. The control signal output by all the PHY locks after passing through the AND gate serves as the reset signal for each FIFO, controlling the reset function of each FIFO. This ensures that the FIFO will not start operating until all the PHY locks are active, ensuring synchronized data transmission.

[0070] Of course, the control module 10 may also be a judgment unit for judging the Lock status corresponding to each PHY. The control module 10 may also be in other forms, which is not limited in the present disclosure.

[0071] FIG4 is a partial schematic diagram of an interface circuit provided by an embodiment of the present disclosure. FIG4 only shows a schematic diagram of a FIFO in the interface circuit receiving a control signal through the control module 20, and the control signal controls the transmission of input data in the PHY corresponding to the FIFO. As shown in FIG4 , the PHY_n in the data transmission module 10 transmits the parsed input data Data_n, PHY_n_CLK and Lock_n (Lock is not shown in the figure) to the FIFO_n in the data synchronization module 30. At the same time, the control module 20 is an AND gate, and the input of the AND gate is Lock_1...Lock_n corresponding to all PHYs. The control signal is output through the AND gate, and the control signal serves as the reset signal reset of the FIFO_n in the data synchronization module 30. When the Locks corresponding to all PHYs are at the working level, the output control signal is at the working level, that is, the reset signal reset of the FIFO is at the working level, and the FIFO starts working. The Lock signals output by all PHYs pass through an AND gate and serve as reset signals to control the reset functions of all FIFOs. From a functional perspective, the FIFOs only start working after all PHYs are successfully locked. At this time, there will be no clock difference problems and no data synchronization problems.

[0072] For interface circuits with multiple lanes corresponding to multiple PHYs, there can be a problem of inter-lane asynchrony, that is, the lock states of the various PHYs are out of sync. The lock process is the process by which the PHY recovers the clock. When the external signal sends the training signal, the PHY performs clock recovery. Once the clock recovery is successful, the lock signal becomes active. However, the lock process duration varies for each PHY, resulting in asynchrony between the lock signals of different lanes. For a PHY operating normally, the difference in the lock process between different lanes is not noticeable. However, if a lane signal problem occurs, this difference can cause prolonged display anomalies.

[0073] For example, when static electricity occurs externally, it interferes with PHY_CLK. When the normal signal cannot be recognized, the PHY will re-lock and re-recover the clock; or when the interface is plugged in and unplugged, there will be a signal loss, which will also trigger re-locking; or other unexpected situations will cause a Lane (Lane_x) signal to be abnormal, and the PHY corresponding to this Lane will lose lock and need to be retrained: when the Lock signal (Lock_x) of Lane_x is at a non-working level, the signal transmitter detects the abnormality and starts sending the Training signal. When the time is between 10ms and 20ms, other lanes will re-lock because they have not received normal data. However, the start time of re-locking of each Lane is different, and the locking process time is also different. In this way, some lanes are locked, but some are not locked. After the unlocked lanes are locked, the previously locked lanes will re-lock because they have not received normal data for a long time (mutual waiting process). This may cause all lanes to not be locked at the same time for a long time, resulting in display abnormalities.

[0074] To address the above issues, an embodiment of the present disclosure provides a circuit interface. FIG8 shows another interface circuit provided in an embodiment of the present disclosure.

[0075] In some embodiments, a port physical layer PHY further includes a reset signal terminal, and the interface circuit further includes a reset module (Lane en Ctrl) 40, the seventh input terminal of the reset module (Lane en Ctrl) 40 is connected to the second output terminal of the control module 20, and the third output terminal of the reset module (Lane en Ctrl) 40 is connected to the reset signal terminals of all port physical layer PHYs.

[0076] Specifically, as shown in Figure 8, the reset module 40 uses the control signal output from the second output terminal of the control module 20 as the input signal Lock_all of the seventh input terminal. When any Lock_x is at a non-working level, Lock_all is also at a non-working level. A Lane_en non-working level pulse is generated through Lane en Ctrl40. This pulse resets all PHYs, and all PHYs re-lock at the same time. In this way, there is no situation where the re-lock start time of different PHYs is different, and there is no waiting process. The re-lock process of all Lanes can be completed quickly without display abnormalities.

[0077] In the embodiment of the present disclosure, all PHYs are reset according to the control signal output by the control module 20 through the reset module 40, so that all PHYs are re-locked at the same time. This ensures that the start time of re-locking all PHYs is the same, saves the locking time of all PHYs, and ensures normal display.

[0078] In some embodiments, when multiple integrated circuits IC are cascaded, each integrated circuit IC corresponds to a control signal, and the interface circuit further includes a lock control module (I / O Ctrl) 50. The first end of the lock control module 50 is connected to the multiple integrated circuits IC for receiving control signals corresponding to each integrated circuit IC. The second end of the lock control module is connected to the seventh input end of the reset module (Lane en Ctrl) 40 for sending control signals corresponding to each integrated circuit IC to the reset module 40; the third output end of the reset module 40 is connected to the third end of the lock control module 50 for receiving the reset signal output by the reset module 40 and sending it to each integrated circuit IC through the first end of the lock control module 50.

[0079] Specifically, when multiple ICs are in use simultaneously, the multiple locks corresponding to multiple PHYs in the second input signal refer to the locks corresponding to all PHYs of all ICs. In this case, not only do the locks corresponding to multiple PHYs within an IC need to wait for each other, but the locks between ICs also need to wait for each other. Only when all the locks corresponding to all PHYs of all ICs are in an active state will the control signal output by control module 20 reach an active level. This makes the waiting time between locks longer. Because more ICs mean more lanes, the re-locking start time becomes more chaotic, making it more difficult to restore normal operation.

[0080] Based on this problem, the embodiment of the present disclosure provides a dual-Lock circuit architecture. Figures 9a and 9b are interface circuits of a dual-Lock architecture provided by the embodiment of the present disclosure, and the control module 20 is taken as an AND gate for illustration. Among them, Figure 9a is a schematic diagram of a cascade connection method of multiple ICs provided by the embodiment of the present disclosure. As shown in Figure 9a, Lock1_1 and Lock2_1 refer to the lock signal Lock that is used as a feedback signal to the data sending end (TCON or FPGA, etc.) such as the subsequent circuit; and Lock1_2 and Lock_2_2 refer to the reset signal output by the reset module 40 received by the lock control module 50, and all ICs are connected to each other using the INOUT port.

[0081] The seventh input of the reset module 40 receives control signals from each IC. Each IC's control signal reflects the lock status of all PHYs within that IC. The third output of the reset module 40 outputs a reset signal to reset all ICs. If any IC requires retraining, all other ICs undergo a retraining process, first returning their lanes to an inactive level and then to an active level. This allows all lanes of all ICs to retrain simultaneously, ensuring that ICs do not wait for each other during retraining.

[0082] In the disclosed embodiment, when multiple ICs are cascaded, a dual-lock architecture is implemented through a lock control module 50. This sends control signals from each IC to the reset module 40, which then resets the PHYs corresponding to all ICs based on the lock signals from all ICs. This ensures that ICs do not wait for each other during retraining, improving data transmission efficiency.

[0083] As described above, the disclosed embodiments can achieve inter-PHY data synchronization by controlling the FIFO reset or the FIFO clock. However, the FIFO reset signal is typically consistent with the subsequent Link circuit reset signal, making it difficult to control independently. Therefore, inter-PHY data asynchrony can also be addressed by controlling the FIFO clock.

[0084] The FIFO clock includes a write clock signal W_CLK and a read clock signal R_CLK. The write clock signal W_CLK of each FIFO comes from two signals: one is an external clock signal OSC_CLK provided by the external, and the other comes from the PHY_CLK output by the PHY corresponding to each FIFO.

[0085] When PHY_CLK is unstable, OSC_CLK is used as the FIFO's W_CLK. A stable PHY_CLK means the corresponding lock for PHY_CLK is in operation, while an unstable PHY_CLK means the corresponding lock for PHY_CLK is inoperative. For example, upon power-up, the PHY_CLK is not locked before the lock receives the clk traning signal, and thus the PHY_CLK is unstable. Alternatively, if data transmission is interrupted for some reason, an error or no PHY_CLK may occur. A normal PHY_CLK must be restored based on the clk traning signal, and during this period, the PHY_CLK is unstable. Once the PHY_CLK of each FIFO's corresponding PHY is stable, the respective PHY_CLK is used as the W_CLK for each FIFO. However, because each PHY's signal is controlled independently, the PHY_CLKs corresponding to each PHY may stabilize at different times after power-up. Alternatively, if a PHY experiences an unexpected data interruption or other issues, the PHY_CLKs of the various PHYs may stabilize at different times. Furthermore, the write clock signals W_CLKs used by the various FIFOs to transmit input data may be out of sync, leading to data transmission asynchrony between the FIFOs.

[0086] To address the aforementioned problem of different data transmission caused by the asynchrony of the W_CLKs of the FIFOs due to the asynchrony of the PHY_CLKs of the PHYs corresponding to the FIFOs, the embodiments of the present disclosure provide another control module of an interface circuit.

[0087] FIG5 is a schematic diagram of a control module in an embodiment of the present disclosure.

[0088] In some embodiments, the control module 20 includes a judgment unit 201 and multiple first control units 202 corresponding one-to-one to the port physical layer PYH. The control signal includes multiple first control signals corresponding one-to-one to the first control unit 202, where the first control signal is a write clock signal W_CLK of the data synchronization unit FIFO. Each first control unit 202 includes a fifth input terminal and a sixth input terminal. The fifth input terminal is used to receive an external clock signal OSC_CLK; the sixth input terminal is used to receive a clock signal PHY_CLK output by the corresponding port physical layer PHY. The judgment unit 201 is used to determine whether the multiple clock signals PHY_CLK corresponding to the multiple port physical layers PHY are in an out-of-lock state based on the second input signal. The first control unit 202 is used to select the external clock OSC_CLK from the external clock signal OSC_CLK received at the fifth input terminal and the clock signal PHY_CLK received at the sixth input terminal as the write clock signal W_CLK when any one of the clock signals PHY_CLK is in an out-of-lock state.

[0089] Specifically, the control signal terminals of each FIFO include a first control signal terminal for receiving a write clock signal W_CLK and a second control signal terminal for receiving a read clock signal R_CLK. The control module 20 includes a first control unit 202 corresponding to each FIFO. The first control unit 202 is configured to generate a first control signal and input the first control signal to the corresponding FIFO via the first control signal terminal of the FIFO as the FIFO's W_CLK. Each first control unit 202 includes a fifth input terminal for receiving an external clock signal OSC_CLK and a sixth input terminal for receiving PHY_CLK. One of the first control signals is selected and output as the first control signal, which is then sent to the first control signal terminal of the corresponding FIFO. In some embodiments, OSC_CLK can be a crystal oscillator signal provided by a crystal oscillator.

[0090] To ensure the synchronization of the W_CLKs of the various FIFOs, in the embodiment of the present disclosure, when the integrated circuit (IC) is just powered on, the write clocks W_CLK of all FIFOs use OSC_CLK, and after the PHY_CLKs of all PHYs are stable, the PHY_CLKs of each PHY are used. This ensures that when the PHY_CLK is unstable in the early stage or when an accident causes the PHY_CLK to be unstable, the OSC_CLK ensures that all FIFOs are in the same stable state (similar to a reset state). After all PHYs are stable, they switch back to the normal working state to ensure data synchronization.

[0091] The judgment unit 201 judges whether the multiple clock signals PHY_CLK corresponding to the physical layer PHY of all ports are in an unlocked state based on the second input signal. Only when all PHY_CLKs are in a locked state, it means that all PHY_CLKs are in a working state, all PHYs reach a stable state, and can transmit data normally. When PHY_CLK is used as W_CLK, all FIFOs can transmit data according to their corresponding PHY_CLKs; when there is a PHY_CLK in an unlocked state, it means that there is a PHY_CLK in a non-working state, the corresponding PHY is still unstable, and cannot transmit data normally. When PHY_CLK is used as W_CLK, there is a FIFO that cannot transmit data under the corresponding W_CLK. In order to ensure that all FIFOs can transmit data, all FIFOs use OSC_CLK as W_CLK at this time.

[0092] Among them, whether the PHY_CLK is in an unlocked state can be determined by the state of the Lock corresponding to the PHY_CLK. When the Lock is in the working state, it indicates that the PHY_CLK is in the locked state, that is, the PHY is stable. When the Lock is in the non-working state, it indicates that the PHY_CLK is in the unlocked state, that is, the PHY is unstable at this time. The second input signal is the state of the Lock corresponding to all PHY_CLKs. Specifically, in some embodiments, the second input signal can be a signal output by passing all PHY_CLK signals through an AND gate. The signal output through the AND gate will only output the working level when all PHY_CLKs are in the working state. The first control unit 202 selects the corresponding signal as W_CLK based on the result of the AND gate. In some embodiments, the state of the Lock corresponding to all PHY_CLKs can also be determined by a detection signal input by an external device to determine the working state of the Lock. The second input signal can be a detection signal of an external device. When the detection signal detects an abnormality, it indicates that the corresponding Lock is in the non-working state, and the corresponding PHY is unstable at this time. The judgment unit 201 determines whether each PHY is stable based on the detection signal, and the first control unit 202 selects the corresponding signal as W_CLK based on the detection signal. Of course, the second input signal can also be in other forms. This disclosure does not limit the second input signal, as long as it can determine the working status of PHY_CLK.

[0093] In some embodiments, the first control unit 202 is a selector, the external clock signal and the PHY clock signal are used as inputs of the selector, and the output of the selector is controlled according to the determination result of the determination unit 201 .

[0094] Of course, the first controller 202 may also have other structures, which is not limited in this disclosure.

[0095] In the disclosed embodiment, W_CLK comes from two signals, one is the PHY_CLK corresponding to the PHY, and the other is the externally provided OSC_CLK. When the IC is just powered on or when the PHY_CLK is unstable, the write clock W_CLK of all FIFOs uses OSC_CLK. After all PHY_CLKs are stable, their respective PPHY_CLKs are used. In this way, when the PHY_CLK is unstable, the OSC_CLK ensures that all FIFOs are in the same stable state (similar to a reset state). After all PHYs are stable, they switch back to the normal working state to ensure data synchronization.

[0096] FIG6 is a partial schematic diagram of an interface circuit provided by an embodiment of the present disclosure. FIG6 illustrates an example in which the first control unit 202 is a selector MUX. The inputs of the MUX are the PHY_CLK output by the PHY and the external input OSC_CLK. The determination unit 201 (not shown) outputs one of the two as the FIFO's W_CLK.

[0097] In some embodiments, the control module 20 includes not only a first control unit 202, but also includes multiple second control units corresponding one-to-one to the port physical layers, and the control signal also includes multiple second control signals corresponding one-to-one to the multiple second control units, and the second control signal is a read clock signal R_CLK; for each second control unit, it includes a ninth input terminal and a tenth input terminal, the ninth input terminal is used to receive an external clock signal OSC_CLK; the tenth input terminal is used to receive any one of the multiple read clock signals PHY_CLK corresponding to the multiple port physical layers.

[0098] The second control unit is configured to select the external clock OSC_CLK as the read clock signal R_CLK from the external clock signal OSC_CLK received at the ninth input terminal and any one of the clock signals PHY_CLK received at the tenth input terminal when any one of all the clock signals PHY_CLK is in an unlocked state.

[0099] In some embodiments, the second control unit is a selector.

[0100] Specifically, the clock signal of the FIFO includes a write clock signal W_CLK and a read clock signal R_CLK. R_CLK is similar to W_CLK. R_CLK also comes from two signals, one is the PHY_CLK corresponding to the PHY, and the other is the externally provided OSC_CLK. In the prior art, when the PHY is unstable, for example, when the IC is just powered on, the R_CLK of the FIFO is OSC_CLK; when the PHY is stable, the R_CLK of the FIFO is PHY_CLK. This R_CLK is used to control other modules to read the data in the FIFO. Unlike W_CLK, the R_CLK of all FIFOs is the same signal. Even after the PHY_CLK is stable, the R_CLK of all FIFOs is the same PHY_CLK. Since the time it takes for each PHY_CLK to stabilize is different, the time it takes to read the input data in each FIFO is different, resulting in asynchronous data reading. To ensure synchronization of the W_CLKs of all FIFOs, the disclosed embodiment uses PHY_CLK only when all PHYs are stable. Otherwise, OSC_CLK is used. This ensures that when the PHYs are unstable, OCK_CLK maintains the same stable state for all FIFOs (similar to a reset state). Once all PHYs are stable, the system switches back to normal operation, ensuring data synchronization.

[0101] In some embodiments, after all PHY_CLKs are stable, the R_CLKs of all FIFOs may be any one of the multiple PHY_CLKs corresponding to the multiple PHYs, which is not limited in the present disclosure.

[0102] In some embodiments, the second control unit is a selector.

[0103] Other details corresponding to R_CLK are similar to those of W_CLK and will not be repeated here.

[0104] FIG7 is another interface circuit provided by an embodiment of the present disclosure. As shown in FIG7 , the first control unit and the second control unit are both selector MUXs for illustration. The input end of the MUX corresponding to the first control unit is the PHY_CLK output by the PHY and the external input OSC_CLK. According to the judgment unit 201 (not shown in the figure), one of them is output as the W_CLK of the FIFO. The input end of the MUX corresponding to the second control unit is the Lane1_PHY_CLK output by the PHY_1 and the external input OSC_CLK. According to the judgment unit 201 (not shown in the figure), one of them is output as the R_CLK of the FIFO.

[0105] In some embodiments, the first input signal received by the first input end of a port physical layer is one input signal.

[0106] Specifically, the physical layer of the port parses the input signal to obtain one channel of input data. One PHY corresponds to one channel of input signal, and multiple PHYs can be combined to achieve the transmission of multiple channels of data, making the PHY more flexible.

[0107] In some embodiments, the first input signal received by the first input end of a port physical layer is a multi-path input signal.

[0108] Specifically, in any of the above-mentioned embodiments, a free splicing design can be performed based on a small IP in which 1PHY corresponds to one lane of the first input signal, or a larger IP in which 1PHY corresponds to 2 lanes or 1PHY corresponds to 3Lane, 4Lane or even more first input signals. If a combination design is performed based on an IP such as 1PHY corresponding to 2Lane, an IC with multiples of 2 lanes such as 4Lane, 6Lane, 8Lane can be spliced ​​out; an IC with an odd number of lanes such as 3Lane, 5Lane, 7Lane can also be spliced ​​out based on 1PHY corresponding to 1Lane and 1PHY corresponding to 2Lane, and the present disclosure does not impose any restrictions on this. It should be noted that when 1PHY corresponds to multiple lanes, the multiple lanes corresponding to one PHY share the same Lock, PHY_CLK, Lane_en, reset and other signals mentioned in the above embodiments.

[0109] In some embodiments, the interface circuit may not only include a data transmission module 10, a control module 20, a data synchronization module 30, a reset module 40 and a lock control module 50, but may also include a parsing module 60, which is connected to the data synchronization module 30 and includes multiple parsing units Link corresponding one to one with the port physical layer PHY, and one data synchronization unit FIFO corresponds to one parsing unit Link, which is used to receive and parse the input data sent by the data synchronization unit FIFO.

[0110] Specifically, Figure 10 is another interface circuit provided by an embodiment of the present disclosure. As shown in Figure 10, the Link and the FIFO have a one-to-one correspondence, and are used to receive the input data Data, Lock and the clock required by the Link transmitted by the corresponding FIFO. It should be noted that all Links receive the same PHY_CLK as the clock of the Link. Figure 10 takes the clock PHY_1_CLK as an example for explanation. Of course, the clock can be any one of the PHY_CLKs corresponding to all PHYs, as long as all Links use the same PHY_CLK, and the input data is parsed according to the Link's clock and Lock for subsequent use.

[0111] The interface circuit provided in the embodiment of the present disclosure generates a control signal based on the second input control signal related to the Lock corresponding to all PHYs in the integrated circuit to control the reset of the FIFO or the read and write clocks (R_CLK, W_CLK) of the FIFO, thereby ensuring the synchronous transmission of the input data corresponding to each PHY.

[0112] On the one hand, the Lock signal output by all PHYs passes through an AND gate and serves as the FIFO reset signal, controlling the Reset function of all FIFOs. From a functional perspective, the FIFO only begins to operate after all PHYs have successfully locked. At this time, both the read and write clocks are the same, eliminating clock differences and data synchronization issues. Furthermore, to ensure the synchronization of the locks corresponding to each PHY, a reset module is designed. When Lock_x is at a non-operating level, the control signal is also at a non-operating level. In this way, the reset module generates a pulse with Lane_en at a non-operating level. This pulse resets all PHYs, and all PHYs re-lock simultaneously. This eliminates the situation where different PHYs re-lock at different start times, eliminates the need for mutual waiting, and quickly completes the re-lock process for all Lanes without display anomalies. Furthermore, for the integration of multiple integrated circuits, a dual-lock architecture is proposed. A lock control module is set up to connect all ICs to each other. Once any IC needs to be retrained, the lane en of all other ICs is converted from a non-working level to a working level. All lanes of all ICs are retrained simultaneously, ensuring that there is no waiting between ICs during retraining.

[0113] Secondly, FIFO includes a write clock signal W_CLK and a read clock signal R_CLK. W_CLK comes from two signals, one is the PHY's own clock signal PHY_CLK, and the other is the externally provided OSC_CLK. When the IC is just powered on, the read clocks of all FIFOs use OSC_CLK, and after all PHY clocks are stable, they use their own PHY_CLK; R_CLK also comes from two signals, one is Lane1_PHY_CLK recovered by PHY_1, and the other is the externally provided OSC_CLK. When the IC is just powered on, it is OSC_CLK, and after all PHY clocks are stable, Lane1_PHY_CLK is used. In this way, when the PHY is unstable, OSC_CLK ensures that all FIFOs are in the same stable state (similar to a reset state). After all PHYs are stable, they switch back to normal working state to ensure data synchronization.

[0114] The interface circuit provided by the embodiment of the present disclosure realizes data synchronization and re-lock synchronization, thereby ensuring the normal display of the image on the display panel.

[0115] An embodiment of the present disclosure also provides a method for data transmission, which is applied to any of the above-mentioned interface circuit embodiments, and the method includes: each port physical layer in the data transmission module parses the received first input signal to obtain input data, clock signal and lock signal corresponding to the port physical layer; the control module generates a control signal according to the second input signal, wherein the second input signal is related to multiple lock signals of multiple port physical layers; when the lock signals corresponding to all port physical layers are at working levels, the multiple data synchronization units in the data synchronization module synchronously send the input data corresponding to each of them.

[0116] In some embodiments, the control module is an AND gate, and the step of the control module generating the control signal according to the second input signal includes: receiving multiple lock signals corresponding to multiple physical layers, and generating the control signal through the AND gate.

[0117] In some embodiments, when the lock signals corresponding to the physical layers of all ports are at the working level, multiple data synchronization units in the data synchronization module synchronously send the input data corresponding to each of them based on the control signal, including: using the control signal as the reset signal of the multiple data synchronization units of the data synchronization module; multiple data synchronization units synchronously send the input data corresponding to each of them based on the reset signal when the lock signals corresponding to the physical layers of all ports are at the working level.

[0118] In some embodiments, the method further includes resetting physical layers of the plurality of ports based on the control signal.

[0119] In some embodiments, the control signal includes a write clock signal, and the control module generates a control signal based on a second input signal, including: the control module determines whether multiple clock signals corresponding to multiple port physical layers are in an unlocked state based on the second input signal; when any clock signal among all clock signals is in an unlocked state, the control module selects an external clock from the external clock signal and the clock signal as the write clock signal.

[0120] In some embodiments, the control module also includes a read clock signal, and the control module generates a control signal based on the second input signal, and also includes: when any clock signal among all clock signals is in an unlocked state, selecting the external read clock from the external read clock signal and any one clock signal as the read clock signal.

[0121] The specific details of the data transmission method provided by the present disclosure refer to any of the embodiments of the above-mentioned interface circuits and will not be repeated here.

[0122] An embodiment of the present disclosure further provides a display panel, comprising any one of the interface circuits in the above-mentioned interface circuit embodiments.

[0123] An embodiment of the present disclosure further provides a display device, comprising any one of the display panels in the above-mentioned display panel embodiments.

[0124] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. An interface circuit, characterized in that: Applied in an integrated circuit, the interface circuit comprises: A data transmission module, comprising a plurality of port physical layers; for each port physical layer, the port physical layer parses a first input signal at a first input terminal to obtain input data at a data output terminal and a clock signal at a clock signal terminal; each port physical layer further comprises a lock signal terminal for outputting a lock signal; when a lock signal at the lock signal terminal of the port physical layer detects that the clock signal is in a locked state, the lock signal at the lock signal terminal changes from a non-working level to a working level; a control module, configured to obtain a control signal at a second output terminal of the control module according to a second input signal inputted at a second input terminal of the control module, wherein the second input signal is related to a plurality of lock signals at a plurality of lock signal terminals of the plurality of port physical layers; A data synchronization module comprises a plurality of data synchronization units corresponding one-to-one to the plurality of port physical layers, one data synchronization unit corresponding to one control signal terminal; for each data synchronization unit, a third input terminal of the data synchronization unit receives the input data of the port physical layer corresponding to the data synchronization unit, an eighth input terminal of the data synchronization unit receives the lock signal, a control signal terminal of the data synchronization unit receives the control signal, and a fourth input terminal of the data synchronization unit receives the clock signal or reset signal of the port physical layer corresponding to the data synchronization unit based on the control signal; when the lock signals corresponding to all port physical layers are at working levels, the plurality of data synchronization units synchronously send the input data corresponding to each of them based on the control signal.

2. The interface circuit according to claim 1, characterized in that: The second input signal is a plurality of lock signals of the physical layers of the plurality of ports, the control signal is the reset signal, and when the control module responds that the plurality of lock signals are all at working levels, the reset signal outputted by the second output end is at a working level.

3. The interface circuit according to claim 2, characterized in that: The control module is an AND gate.

4. The interface circuit according to claim 1, characterized in that: The control module includes a judgment unit and a plurality of first control units corresponding to the port physical layer one by one, the control signal includes a plurality of first control signals corresponding to the first control units one by one, the first control signal is a write clock signal of the data synchronization unit; for each first control unit, a fifth input terminal and a sixth input terminal are included, the fifth input terminal is used to receive an external clock signal; the sixth input terminal is used to receive the clock signal output by the corresponding port physical layer; wherein, The judging unit is used to judge whether the multiple clock signals corresponding to the physical layers of the multiple ports are in an unlocked state according to the second input signal; The first control unit is used to select the external clock from the external clock signal received at the fifth input terminal and the clock signal received at the sixth input terminal as the write clock signal when any one of all the clock signals is in an unlocked state.

5. The interface circuit according to claim 4, characterized in that: The control module further includes a plurality of second control units corresponding to the physical layers of the ports one by one, the control signal further includes a plurality of second control signals corresponding to the second control units one by one, and the second control signal is a read clock signal; Each second control unit comprises a ninth input terminal and a tenth input terminal, wherein the ninth input terminal is used to receive an external read clock signal; The tenth input terminal is used to receive any one clock signal among a plurality of read clock signals corresponding to the physical layers of the plurality of ports; The second control unit is used to select the external read clock as the read clock signal from the external read clock signal received at the ninth input terminal and the any clock signal received at the tenth input terminal when any one of all the clock signals is in an unlocked state.

6. The interface circuit according to claim 5, characterized in that: The first control unit and the second control unit are both selectors.

7. The interface circuit according to claim 2, characterized in that: One of the port physical layers also includes a reset signal terminal, the interface circuit also includes a reset module, the seventh input terminal of the reset module is connected to the second output terminal of the control module, and the third output terminal of the reset module is connected to the reset signal terminals of all port physical layers.

8. The interface circuit according to claim 7, characterized in that: When multiple integrated circuits are cascaded, each integrated circuit corresponds to a control signal, and the interface circuit also includes a lock control module, a first end of the lock control module is connected to the multiple integrated circuits, and is used to receive control signals corresponding to each integrated circuit, and a second end of the lock control signal is connected to the seventh input end of the reset module, and is used to send the control signal corresponding to each integrated circuit to the reset module; the third output end of the reset module is connected to the third end of the lock control module, and is used to receive the reset signal output by the reset module, and send it to each integrated circuit through the first end of the lock control module.

9. The interface circuit according to any one of claims 1 to 8, characterized in that: The first input signal received by the first input end of the physical layer of the port is one input signal.

10. The interface circuit according to any one of claims 1 to 8, characterized in that: The first input signal received by the first input end of the one-port physical layer is a multi-path input signal.

11. The interface circuit according to claim 1, characterized in that: The interface module also includes a parsing module, which is connected to the data synchronization module and includes a plurality of parsing units corresponding to the port physical layers one by one, one data synchronization unit corresponding to one parsing unit, and is used to receive and parse the input data sent by the data synchronization unit.

12. A method for data transmission, the method being applied to the interface circuit according to any one of claims 1 to 11, the method comprising: The physical layer of each port in the data transmission module analyzes the received first input signal to obtain input data, a clock signal and a lock signal corresponding to the physical layer of the port; The control module generates a control signal according to a second input signal, wherein the second input signal is related to a plurality of lock signals of a plurality of port physical layers; When the lock signals corresponding to the physical layers of all ports are at working levels, the multiple data synchronization units in the data synchronization module synchronously send the input data corresponding to each of them based on the control signal.

13. The method according to claim 12, characterized in that The control module is an AND gate, and the control module generates a control signal according to the second input signal, including: A plurality of lock signals corresponding to the plurality of physical layers are received, and the control signal is generated through an AND gate.

14. The method according to claim 13, characterized in that When the lock signals corresponding to the physical layers of all ports are at working levels, the multiple data synchronization units in the data synchronization module synchronously send the input data corresponding to each of them based on the control signal, including: Using the control signal as a reset signal for multiple data synchronization units of the data synchronization module; Based on the reset signal, the multiple data synchronization units synchronously send the input data corresponding to each of them when the lock signals corresponding to the physical layers of all ports are at the working level.

15. The method according to claim 14, characterized in that The method further comprises: The physical layers of the multiple ports are reset based on the control signal.

16. The method according to claim 12, characterized in that The control signal includes a write clock signal, and the control module generates the control signal according to the second input signal, including: The control module determines whether the multiple clock signals corresponding to the physical layers of the multiple ports are in an unlocked state according to the second input signal; When any one of all the clock signals is in an unlocked state, the control module selects the external clock from the external clock signal and the clock signal as the write clock signal.

17. The method according to claim 16, characterized in that The control module further includes a read clock signal, the control module generates a control signal according to the second input signal, and further includes: When any one of all the clock signals is in an unlocked state, the external read clock is selected from the external read clock signal and any one of the clock signals as the read clock signal.

18. A display panel, characterized in that: Comprising the interface circuit as claimed in any one of claims 1-11.

19. A display device, characterized in that: Comprising the display panel as claimed in claim 18.

Images