Thermal expansion matching chip module with integrated liquid cooling

Abstract

A chip and chiller assembly includes an active or passive interposer (114) having a front side and a back side. An integrated circuit chip (102, 112) is mounted on the rear side of the interposer (114). Each of the chips (102, 112) has a front side attached to the interposer (114) and a rear side facing away from the interposer (114). A gap (108) separates the chips (102, 112). The assembly also includes a frame (300) that is fitted into the gap (108) between the chips (102, 112). The frame (300) is CTE matched to the chips (102, 112). The frame (300) and the chip (102, 112) define a back side surface. A cooler module (200) is attached to the rear side surface. The cooler module (200) is in CTE match with the chips (102, 112). The chiller module (200) includes a microchannel chiller (202) disposed directly against a rear side of the chip and a manifold (204, 206) attached to the microchannel chiller (202) opposite the chip (102, 112). The manifolds (204, 206) are matched to the microchannel cooler (202) CTE.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention relates to the fields of electrical, electronic, and computer technologies, and more particularly, to the thermal management of integrated circuit components.

[0002] Integrated circuits generate waste heat during their operation. If this heat is not removed, it can degrade the performance of the circuit. In the worst case, the retained heat can lead to thermal runaway. Therefore, it is desirable to remove waste heat from integrated circuit chips. Typically, this is accomplished using a cooling plate attached to the chip. In a multi-chip module, discrete cooling plates can be attached to each individual chip. Alternatively, a suitable thermal interface material can be used as an intermediate layer between multiple chips and a single shared cooling plate. Sometimes, the cooling plate will be made flexible to accommodate multiple chips that may have different thicknesses or heights. Typically, the cooling plate is made of metal to achieve high thermal conductivity.

[0003] Electronic modules or packages generally need to provide power, input / output (I / O) connections, cooling, and mechanical protection to the active semiconductor devices they contain. In the packaging of semiconductor chips, an organic substrate is typically used, which fans out the controlled collapse chip connector (C4) solder bumps on the silicon die from a fine pitch (usually 0.15 to 0.2 mm) to a larger pitch (usually 1.0 to 1.2 mm) to form ball grid array (BGA) or land grid array (LGA) connections. With BGA, the chip package is attached to a printed circuit board (PCB) by reflow soldering balls to form a permanent connection, while the LGA type interposer provides a connection where the chip package can be easily removed and replaced on the printed circuit board.

[0004] For LGA interposers or connectors / sockets, a mechanical load is required to compress springs or other contact elements to form individual electrical connections. Typically, with an organic package substrate, a lid made of a thermally conductive material (such as copper) is attached to the chip and the organic substrate to protect the chip during handling and increase the mechanical strength of the organic substrate. A thermal interface material (TIM) is dispensed between the back of the chip and the lid to provide a thermal path. If needed, a second TIM layer is then used to attach a heat sink to the outer surface of the lid. The chip is mounted face-down or device-side-down on the package substrate and connected via C4.

[0005] A typical organic laminate for encapsulating chips has a coefficient of thermal expansion (CTE) of approximately 13 - 18 ppm / °C, which is greater than the silicon CTE (approximately 3 ppm / °C). This difference limits the size of chips that can be reliably attached to the laminate with C4 solder balls, as well as the minimum pitch of the solder balls due to the stress generated during thermal cycling. The CTE mismatch between the silicon chip and the copper lid (CTE of ~17 ppm / °C) means that for reliable operation of large chips, a compliant and thicker TIM layer is required, which has lower performance than a rigid TIM layer, such as silver-filled epoxy, solder, or a metal such as indium.

[0006] Contemporary multi-chip high-performance computing modules contain stacked chips as well as high-bandwidth memory chip stacks (HBM). The lower chips in each stack contain through-silicon vias (TSVs). The chip stacks are mounted on a silicon carrier, which has multiple wiring layers and TSVs for interconnecting the chips mounted thereon. A midplane is then attached to the organic laminate. The significant advantage of silicon carriers (also known as midplanes) is that they can be fabricated with finer-pitch wiring than organic laminates, and because they match the chip CTE, large chips can be mounted on them with finer-pitch solder balls, both of which enable a greater data bandwidth between the chips. The disadvantage of silicon midplanes is that due to the etching process used to form the TSVs, they are typically thin, with a thickness of approximately 0.05 to 0.2 mm, which means they are fragile and may be prone to cracking when they span a large area. Glass that matches the silicon CTE can also be used to fabricate carriers or midplanes with multiple fine-pitch wiring layers and vias, which are functionally equivalent to silicon carriers in many respects. Both silicon and glass are brittle materials and are strong under compression but will fracture when the tensile stress exceeds the critical load. The failure strength of silicon and glass depends on the location of the largest existing crack nucleation sites. TSVs are crack nucleation sites. Stacked chips are increasingly being joined by "hybrid bonding", in which the oxide layer and copper connections are bonded directly to each other and do not require solder bumps. For some higher power density modules, integrating liquid cooling directly into the lid of the module is considered to provide improved cooling. Such multi-chip modules as described above typically use LGA connections instead of BGA to be mounted on a PCB, making them replaceable. For the current state-of-the-art high-performance multi-chip modules, due to the use of materials with different CTEs, very careful engineering, design, and assembly methods are required to ensure long-term reliable operation. Any bending of large-area silicon or glass carriers is to be avoided, as such bending may potentially fracture the carrier. Summary of the Invention

[0007] The principles of the present invention provide techniques for a thermal expansion matching chip module with integrated liquid cooling.

[0008] In one aspect, an exemplary chip and cooler assembly includes an interposer having a front side and a back side, and a plurality of integrated circuit chips mounted to the back side of the interposer. Each of the chips has a front side attached to the interposer and a back side facing away from the interposer. The chips are separated by gaps. The chip and cooler assembly further includes a frame fitted into the gaps between the chips. The frame has a CTE that matches that of the chips. The frame and the chips define a back side surface. A cooler module is attached to the back side surface. The cooler module has a CTE that matches that of the chips. The cooler module includes a microchannel cooler disposed directly against the back sides of the chips and a manifold attached to the microchannel cooler opposite the chips. The manifold has a CTE that matches that of the microchannel cooler.

[0009] In another aspect, an exemplary method includes assembling a plurality of chips onto the back side of an interposer. The chips have a CTE that matches that of the interposer. The method further includes assembling a frame into the gaps between the chips; depositing an adhesive onto the back sides of the chips; and loading a chip cooler module onto the adhesive. The microchannel cooler has a CTE that matches that of the chips and the interposer.

[0010] In view of the foregoing, the technology of the present invention can provide substantially beneficial technical effects.

[0011] For example, one or more embodiments provide one or more of the following:

[0012] A rigid monolithic thermally matched multi-chip module with enhanced integration, cooling, and reliability.

[0013] A thick thermally matched manifold that provides stiffness for the module and fluid distribution.

[0014] A glass or silicon carrier with a redistributed wiring layer that enables fine pitch interconnects and high wiring density for improved chip-to-chip bandwidth.

[0015] A thermally matched microchannel cooler with a rigid thermal interface (silver epoxy, solder, or metal) that reduces chip operating temperature, improves reliability, and reduces leakage current.

[0016] Fine pitch vias are not required in a carrier with a 1 mm pitch land grid array.

[0017] An elastomeric seal in a load block on the side of the module opposite the LGA can be used to provide a coolant fluid connection, and additional elastomeric seals can be used to evenly distribute mechanical loads without additional fluid connections.

[0018] A rigid monolithic structure is formed by using an underfill or other filler material to bond together a midplane, one or more frame components, a microchannel cooler, and chips, and to fill any major voids or gaps that exist between the midplane and the microchannel cooler.

[0019] Some embodiments may not have these potential advantages, and these potential advantages are not required for all embodiments. These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments of the invention read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A side view of an integrated circuit chip assembly according to an exemplary embodiment is depicted in schematic form, the integrated circuit chip assembly including a plurality of chips on a midplane.

[0021] Figure 2 A thermal expansion matching chip cooler module is depicted in exploded component schematic form according to an exemplary embodiment.

[0022] Figure 3 Depicted in exploded component schematic form is a Figure 2 thermal expansion matching chip cooler module as shown in Figure 1 the integrated circuit chip assembly as shown in

[0023] Figure 4 Depicted in schematic form is a Figure 1 planar (top - down) view of the integrated circuit chip assembly with thermal epoxy as shown in

[0024] Figure 5 Depicted in schematic form is a Figure 1 side view of the integrated circuit chip assembly with a frame and thermal epoxy as shown in

[0025] Figure 6 Depicted in schematic form is a Figure 3 side view of the assembly of components as shown in

[0026] Figure 7 Depicted in schematic form is a Figure 3 LGA load block for the assembled components as shown in

[0027] Figure 8 Depicted in schematic form is a multi - piece thermal expansion matching frame according to an exemplary embodiment.

[0028] Figure 9 An exemplary embodiment of a thermal expansion matching framework is depicted in schematic form, the thermal expansion matching framework including recessed channels to facilitate the flow of underfill.

[0029] Figure 10 An exemplary method in accordance with one aspect of the present invention is depicted in flowchart form.

[0030] Figure 11 A chip and cooler assembly having reinforcements at each edge of the components is depicted in schematic form in accordance with an exemplary embodiment. Detailed Description

[0031] Figure 1 A side view of a processor module 100 including a plurality of chips 102, 112 on an interposer 114 is depicted in schematic form in accordance with an exemplary embodiment. Each of the chips 102, 112 has a front side 104 and a back side 106. In one or more embodiments, chip 102 is a processor or computing unit, while chip 112 is a memory, e.g., high bandwidth memory (HBM). A gap 108 separates adjacent chips. In some of the gaps, there are silicon capacitors 110. In one or more embodiments, chip 102 is attached to interposer 114 by controlled collapse chip connection (C4), i.e., fine pitch solder bumps, or by hybrid copper / oxide bonding. Interposer 114 also includes redistribution wiring layers (RDL) 120 and 122, where through-silicon vias (TSV) 124 connect the RDL. On the front side surface, interposer 114 has land grid array (LGA) pads 126. In one or more embodiments, the TSV has a pitch of 1 to 1.5 mm or less. RDL 120 is configured to provide signal connections between the chips on the top surface of the interposer and to distribute power through C4. The TSVs connected to the chips through RDL 120 and C4 provide off-module signaling and power. For the LGA connected to the power supply, multiple TSVs can be used in parallel to reduce the resistance. Depending on the detailed design, there may or may not be an RDL layer 122 on the LGA side of the interposer, in which case the LGA pads will be directly connected to the TSV. In one or more embodiments, during the manufacture of processor module 100, the LGA side of interposer 114 can be mounted to a processing wafer 128 using a removable adhesive layer during the manufacture of RDL120 and chip attachment.

[0032] In one or more embodiments, the processor module 100 may include a chip stack such as an HBM (High Bandwidth Memory Module) or a thin capacitor (e.g., a silicon capacitor). In alternative embodiments, the active silicon interposer may include additional elements such as integrated decoupling capacitors, active devices for power conversion, or other active devices for routing I / O signals or other purposes. If such devices are added to the silicon interposer, they may be formed on the top surface, the bottom surface, or both surfaces. In one embodiment, the active silicon interposer may be equivalent to a chip or chip array having TSVs and LGA pads formed on the back side and having an HBM memory stack or additional active chips bonded to the front side, as Figure 1 shown.

[0033] Figure 2 A thermal expansion matching chip cooler module 200 according to an exemplary embodiment is depicted in the form of an exploded component schematic. Module 200 includes a microchannel cooler 202, a lower manifold 204, and an upper manifold 206, all of which are bonded together using a rigid material such as glass frit.

[0034] Figure 2 A perspective view of the silicon microchannel cooler 202 is shown, where an interleaved fin 208 pattern extending from left to right has been formed by patterning the silicon to a depth of approximately 300 microns using a deep reactive etching process. The specific geometry of the fins will depend on the details of the application and may be optimized as is well known to those skilled in the art. The etched microchannels 210 are surrounded on all sides by a frame region 211, which may be, for example, 3.5 mm wide, to allow the glass manifold layer above to be sealed to the microchannel layer. The nominal dimensions of the microchannel layer are 77 x 87 x 0.775 mm.

[0035] In one or more embodiments, each glass manifold layer 204, 206 has dimensions of approximately 77 x 87 x 5 mm and is made of Schott 33 Glass (a registered trademark of SCHOTT AG MAINZ FED REP GERMANY) or other glass materials that match the silicon CTE are used to fabricate. The lower glass manifold layer 204 has been processed to form three recessed slots or grooves 214, 216 on the bottom surface and three through-hole arrays or vertical channels 212 that are aligned with these grooves. In one or more embodiments, the grooves 214, 216 are approximately 2.4 mm wide and are used to confine the water flow in the microchannels. The fluid path through the glass uses hole arrays to avoid over-weakening the glass layer. The upper glass manifold layer 206 has been processed to form tapered manifold channels 218, 220 that extend from the central holes 222, 224 such that the tapered channels 218, 220 overlap the holes 212 in the lower manifold layer after the assembly of the chip cooler module 200 and supply fluid to and / or from them. In an exemplary non-limiting embodiment, the glass layer and the microchannel layer are permanently and rigidly joined by using a glass powder material (such as Ferro 11-036 (manufactured by Ferro Corporation of Mayfield Heights, Ohio)) between them.

[0036] In operation, the cooling fluid is supplied from the LGA load block 700 ( Figure 7 as shown) through a compliant seal such as an O-ring to the central inlet 224 on the top surface of the glass microchannel cooler. The coolant then flows along the tapered channel 220 in the upper glass manifold layer until it flows downward through the hole 212 into the recessed channel 216 on the bottom of the lower glass manifold layer. The coolant flows from the channel or groove 216 through the microchannel layer 202 to the outlet recessed channel 214 on the bottom of the lower glass manifold layer. Then, the coolant flows upward through the hole 212 from the groove or channel 214 to the tapered outlet manifold 218 on the bottom surface of the upper glass manifold layer and then to the outlet opening 222. The outlet opening 222 is sealed to the fluid channel in the LGA load block 700 by a compliant member. Alternative configurations are also possible.

[0037] In one or more embodiments, the fins 208 and channels 210 of the silicon microchannel cooler 202 are formed by deep reactive ion etching (DRIE), which is a highly anisotropic etching process for creating deep-penetrating, steep-sided holes and slots in a silicon wafer / substrate, and typically has a high aspect ratio. In one or more embodiments, the manifold layers 204, 206 are formed by processing polished plates of borosilicate glass. In one or more embodiments, the microchannel cooler and the manifold layers are assembled and attached by screen printing frit, drying, glazing, aligning / stacking, clamping, and firing on a pattern across the surface.

[0038] In one or more embodiments, the lower manifold 204 includes a plurality of vertical channels 212 leading to two outward exit slots 214 and a central inlet slot 216. The grooves 214, 216 correspond to the exit cavities 218 and the inlet cavity 220 in the upper manifold 206. Each exit cavity 218 has an exit nozzle 222, and the inlet cavity 220 has an inlet nozzle 224. The length direction of the staggered fins in the microchannel cooler 202 is perpendicular to the inlet and exit slots. Note that in other embodiments, additional manifold layers may be used depending on the specific application, so the use of only two layers in these illustrations should not be considered restrictive.

[0039] Figure 3 Depicted in exploded component schematic form is the Figure 2 thermal expansion matched chip cooler module 200 shown in Figure 1 the processor module 100 shown in, and the thermal expansion matched frame 300. The frame 300 includes edges 302, 304, 306, 308 and crossbars 310, 312. In one or more embodiments, the portions of the crossbars 310, 312 that cover the capacitors 110 are thinner than the edges 302, 304, 306, 308. Thus, the frame 300 fits into the gap 108 between the chips 102 on the processor module 100 to provide a uniform surface to which the module 200 can be attached. The frame 300 additionally extends beyond the chips 102, 112 to the edges of the interposer 114 and also to the edges of the microchannel cooler 202. In other words, the frame 300 occupies the space around the chips 102 and between the interposer 114 and the microchannel cooler 202. In one or more embodiments, the frame 300 or individual components of the frame are made of CTE-matched glass (i.e., glass having the same coefficient of thermal expansion as silicon) or silicon. Generally, the frame 300 is intended to occupy the void space between the filled silicon or glass carrier 114 and the flat base of the chip cooler module 200, except for a small gap of approximately 25 to 200 microns high, which will subsequently be filled with underfill or other filling materials. This is used to increase the strength and stiffness of the final structure and to minimize the volume fraction of modules that are not fully CTE-matched to silicon. In a preferred embodiment, the spacer frame is constructed of a material (such as silicon or 33 glass) that is CTE-matched to silicon and need not be a single component, but can be multiple components or even multi-layer components (see alternative configurations 800, 900 of the frame 300 in Figure 8 and Figure 9 ).

[0040] In one or more embodiments, chip 102 is attached to a carrier or interposer with C4 solder balls at a 150-micron pitch, HBM module 112 is attached to the carrier with micro-bumps at a 55-micron pitch, and capacitor 110 and optional EEPROM chip(s) are also attached using solder. In a specific embodiment, the interposer 114 has dimensions of 77 x 87 x 0.5 mm, and each chip 102 has dimensions of 30 x 25 mm. The silicon or glass carrier can be thicker than typical because the via pitch requirement is relaxed to only 1 mm. Interposers made of glass with a via pitch of 0.25 mm and a thickness of 0.5 mm, which match the silicon CTE, are commercially available. An exemplary CTE-matching glass is 33 glass, which can be obtained from SCHOTT North America, Inc., Rye Brook, New York. Generally, in the context of the present disclosure, "CTE matching" means matching within 5% of the respective average values for 20°C and 300°C. In an exemplary embodiment without limiting the scope of the invention, the thickness of the processing device 128 is approximately 0.775 mm, and the same is true for the processor chip 102; the thickness of the HBM stack is approximately 0.72 mm; and commercially available silicon capacitors are used, and their thickness can be as thin as 0.1 mm.

[0041] In one or more embodiments, chip 102 is attached to a carrier or interposer using copper-oxide hybrid bonding, copper-copper bonding, or any other solid-state bonding, fusion bonding, or other permanent bonding. The bonding can occur at the chip or wafer scale. Then, the frame 300 can be bonded to the carrier using an adhesive, epoxy resin, solder, copper-oxide hybrid bonding, copper-copper bonding, or any other suitable bonding. Depending on the heat treatment requirements of the gap-filling material and the required mechanical properties, the frame bonding material can be appropriately selected to withstand the required downstream processing. The gaps between die and between die and the frame can be substantially equal to enable a direct gap-filling process. Gap filling can be performed using organic or inorganic materials. Organic materials as described in alternative embodiments can include underfills. Inorganic gap-filling materials can include silicon-based materials or other dielectric or semiconductor materials. Silicon-based materials or other semiconductor or dielectric materials can make the gap-filling material CTE-match with adjacent die and the frame. Exemplary materials include silicon nitride, silicon oxide, SiCOH, SiCN. For example, silicon dioxide has a CTE of approximately 0.6 x 10 -6 / K, while germanium has a CTE of approximately 5.8 x 10 -6CTE of / K. The silicon-based gap-fill material can be applied or deposited at the die or wafer level. The silicon-based gap-fill material can be deposited by various chemical vapor deposition techniques, such as plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). Additionally, silicon inks and pastes can be deposited at low temperatures. Silicon can also be sputtered at low temperatures. Depending on the thermal limitations of the chip interconnect component, the deposition temperature can be maintained below 400°C or 450°C. Alternatively, the gap-fill material can be deposited at a low temperature (e.g., 200°C) and annealed at a moderate temperature (e.g., 400°C) without negatively affecting the copper features in the chip and carrier. The encapsulation of the chip and carrier can be achieved first with a thin inorganic material and subsequently with other hard dielectric or semiconductor layers. Deposition techniques typically deposit materials on the back side of the die and the frame, thereby degrading the thermal performance of the cooling scheme. Grinding, polishing, or etching of the film can be performed to planarize and remove the film on the back side of the die and expose the chip and the frame. All of the above processes can be performed using a processing apparatus with a high-temperature compatible temporary bonding film, or if the carrier or the interposer is thick enough, they can be performed without using a processing apparatus.

[0042] Figure 4 A plan (top-down) view of the processor module 100 shown in Figure 1 in accordance with an exemplary embodiment is depicted in schematic form, where a thermal epoxy or other thermally filled rigid adhesive 400 is applied to the chips 102 and 112. The thermal epoxy 400 can be, for example, a silver-filled epoxy material such as Ablestik 965-1L (manufactured by Henkel Corporation of Rocky Hill, Connecticut), which can be dispensed on the top or back side surfaces of the processor chip, the HBM memory module, and other components that require cooling.

[0043] Figure 5 A side view of the integrated circuit chip assembly shown in Figure 1 in accordance with an exemplary embodiment is depicted in schematic form after the frame 300 has been placed and the thermal epoxy 400 has been deposited.

[0044] Figure 6 A depiction in schematic form of Figure 3Side view of the components 600 of the assembly shown in order to form a thermal expansion matching chip module with integrated liquid cooling. Thus, in order to assemble the components 600: A thermal (e.g., silver) epoxy or other thermally filled rigid adhesive 400 is dispensed on the back sides of the chips 102 and 112; the frame 300 and the cooler module 200 are stacked onto the chip assembly 100; the components are aligned and clamped together in a fixture (not shown); and then the silver epoxy is cured in a load fixture. After removing the assembly from the load fixture, the next step is to apply underfill. Capillary underfill materials are typically epoxies or similar polymers loaded with silica particles or other fillers and are used to fill the gaps between the carrier, components, spacer frames, and microchannel coolers. Typically, heat is used to reduce the viscosity of the underfill and to accelerate the flow of the underfill. In one or more embodiments, after removing the module from the fixture, a vacuum underfill step is used to ensure that all gaps are filled. In this process, the module and an open container with an underfill pool are placed in a chamber, and then the chamber is evacuated. The bottom of the module, i.e., a portion of the processing device, filled carrier, spacer frame, and glass microchannel cooler, is immersed in the underfill pool, and then the chamber is vented so that atmospheric pressure forces the underfill material 602 into all of the gaps between the filled carrier and the silicon microchannels. It can be noted that no underfill material enters the glass microchannel cooler through ports on the top surface. After removing the module from the chamber and wiping away any excess underfill from the sides and bottom of the processing device, the underfill material is cured. Figure 6 Depicts the underfilled assembly after the disposal device 128 and the adhesive have been removed and the LGA pads are exposed.

[0045] Figure 7 Depicts in schematic form a loading block 700 for clamping the assembled module onto an LGA. The loading block 700 has a body 702 in which three holes 704, 706, 708 (corresponding to the inlet and outlet nozzles of the module 200) are formed. A circular groove 710 for receiving an O-ring (not shown) is also formed on the surface 712 of the body 702. When using the loading block, an O-ring is inserted into all of the grooves 710, and the loading block 700 holding the O-rings is pressed down onto the module 600 in order to seal the fluid inlets / outlets and to actuate the LGA. Only the O-rings contact the top glass manifold layer. In addition to the three O-rings surrounding the nozzle holes 704, 706, 708, an array of evenly distributed O-rings allows the assembly to be pressed against the LGA socket without cracking the module due to the application of uneven forces.

[0046] In one or more embodiments, underfill may be dispensed after curing the silver epoxy resin or cured simultaneously with the silver epoxy resin. The underfill secures the frame to the interposer and the cooler module to form a rigid monolithic structure.

[0047] If the handling device 128 is used during assembly, the handling device is removed to expose the LGA pads on the interposer. The carrier can be removed by a laser release process in which a laser guided through the handling device is used to ablate or decompose the adhesive material, or the carrier can be removed using a solvent that dissolves the adhesive material. In the case of the solvent, if the handling device is provided with holes to allow the solvent to act more quickly, a tape can be applied to the bottom surface prior to the vacuum underfill step to prevent these holes from being inadvertently filled with underfill.

[0048] If a solder or other metallic thermal interface is to be provided between the chips 102 and 112 and the microchannel cooler 202, a modified assembly process can be used. Solder or other metallic thermal bonding material can be used to reduce the thermal resistance between the heat dissipating component and the microchannel cooler. In this process, the back sides of the heat dissipating chips and the memory stack on the filled carrier can be metallized by evaporation via a metal mask, and likewise, all or part of the bottom of the glass microchannel cooler can be metallized such that the solder wets the surface. In the process described above, solder paste or preforms can be placed in the desired locations and the components joined together using a reflow process instead of dispensing the silver epoxy resin filler prior to performing the remaining steps of vacuum underfilling and handling device removal. An alternative assembly method is to use Cu-to-Cu and oxide-to-oxide hybrid bonding instead of solder balls for joining the chips, HBM memory stacks, etc. to the carrier.

[0049] For large LGA sockets, a relatively large load is required for actuation. For example, for a 77x87 mm module and an LGA with a 75x85 array at a pitch of 1 mm, where the typical actuation load is 44 gm / contact, the total required load is 280.5 kg. As mentioned previously, for brittle materials such as glass or silicon, it is important to avoid tensile loads that can cause fracture. For example, the bending force on the described module will result in tensile loads on one surface and compressive loads on the opposite surface. By applying the load as uniformly as possible on the module surface while uniformly supporting the opposite face to avoid any bending force, such tensile loads can be avoided. In a preferred embodiment, an additional mechanical-only O-ring or other compliant device is used between the LGA loading block and the module to distribute the load more evenly. In a preferred embodiment, the LGA loading block 700 has a smooth surface facing the module and an annular recess for receiving the O-ring, where three of the O-rings in the O-ring also provide fluid inlets or outlets to / from the module. The LGA loading block provides a controlled force to clamp the module, LGA, and PCB together through a clamping mechanism. In one or more embodiments, the PCB has a reinforcement plate behind it, and the clamping mechanism is connected to the reinforcement plate.

[0050] Figure 7 is a schematic diagram showing a possible distribution of O-rings on the module to distribute the LGA load more evenly, where ten of the O-rings are for mechanical purposes only, and three provide fluid connections. Figure 7 Shows the LGA loading block 700 having a groove 710 for receiving the O-ring, which is appropriately recessed such that in one or more embodiments, only the compressed O-ring contacts the glass manifold surface and not the loading block. A related advantage of this module structure (in addition to complete CTE matching) is that it has a greater thickness than prior art modules, since the stiffness of the plate is proportional to the cube of the thickness. For a given example, it is approximately 12 mm thick compared to a typical chip package that is approximately 4 mm thick. If desired, the stiffness can be further increased by using a thicker or additional glass layer in the manifold. This greater stiffness allows a slightly non-uniform load to be applied by using thirteen O-rings, as Figure 7 shown. The LGA provides a more uniform load through 1 mm pitch compressible contacts against the bottom surface of the module.

[0051] Figure 8A multi-piece thermal expansion matching frame 800 including a central crossbar 802 having arms 804, 806, 808, 810 is depicted in schematic form. Corner pieces 812, 814, 816, 818 are assembled with the central crossbar 802 to define fill vents 820, 822, 824, 826 and bottom fill nozzles 828, 830, 832, 834; during assembly, if conventional atmospheric bottom fill is used, the bottom fill is introduced through nozzles 828, 830, 832, 834 and air is exhausted through vents 820, 822, 824, 826.

[0052] Figure 9 A thermal expansion matching frame 900 is depicted in schematic form having a central crossbar 902 connected to edge pieces 904 which include recessed channels 906, 908, 910, 912 for exhausting air and channels 914, 916, 918, 920 which allow bottom fill to flow if conventional atmospheric bottom fill is used.

[0053] Figure 11 A chip and cooler assembly 1100 according to an exemplary embodiment is depicted in schematic form having stiffeners 1102 at each edge of the assembly. Assembly 1100 includes an interposer 1104, a first chip 1106, a second chip 1108, bottom fill 1110, a microchannel cooler 1112, and a fluid manifold plate 1114. In one or more embodiments, fluid manifold plate 1114 is similar to load block 700 and has an O-ring in direct interfacial connection with the upper surface of microchannel cooler 1112. In one or more embodiments, fluid manifold plate 1114 is made of stainless steel. In one or more embodiments, microchannel cooler 1112 is similar to the combination of cooler manifold upper 206 and microchannel cooler 202 as shown in cooler module 200( Figure 2 ). In one or more embodiments, microchannel cooler 1112 is made of silicon for thermal conductivity. In one or more embodiments, stiffeners 1102 are made of multiple silicon layers 1116, 1118, 1120, 1122 joined together; for example, by adhesive 1124. In one or more embodiments, top layer 1122 is present at one edge of the assembly but not at the opposite edge; advantageously, this can provide microchannel cooler 1112 with the ability to expand or contract laterally due to temperature changes. Additionally, adhesive is a non-limiting example of a joining technique for multiple silicon layers 1116, 1118, 1120, 1122; other examples include any suitable joining material / method such as hybrid bonding, direct bonding, soldering, etc.

[0054] In view of the discussion so far, it will be understood that, generally speaking, the exemplary chip and cooler assembly 600 includes an interposer 114 having a front side 118 and a back side 116, and a plurality of integrated circuit chips 102, 112 mounted to the back side of the interposer. Each of the chips has a front side 104 attached to the interposer and a back side 106 facing away from the interposer. The chips are separated by gaps. The chip and cooler assembly 600 also includes a frame 300 fitted into the gaps between the chips. The frame extends beyond the chips to the edge of the interposer. The frame matches the CTE of the chips. The frame and the chips define a back side surface. A chip cooler module 200 is attached to the back side surface. The chip cooler module matches the CTE of the chips. The chip cooler module includes a microchannel cooler 202 attached to the back side of the chips and manifolds 204, 206 attached to the microchannel cooler opposite the chips. The manifolds match the CTE of the microchannel cooler.

[0055] In one or more embodiments, the chip and cooler assembly 600 also includes a plurality of thinner chips embedded in portions of the gaps between the plurality of chips, and the frame is thinner above the thinner chips and thicker where there are no thinner chips.

[0056] In one or more embodiments, the chips have electrical contacts on their front sides, and the interposer includes a land grid array pad disposed on the front side of the interposer and including through-silicon vias that connect the electrical contacts of the chips to the land grid array pad.

[0057] In one or more embodiments, the interposer matches the CTE of the chips and includes a redistribution wiring layer 120 adjacent to the chips.

[0058] In one or more embodiments, the material of the manifolds is glass. In one or more embodiments, the material of the bottom portion 204 of the manifolds is silicon. In one or more embodiments, the material of the microchannel cooler is silicon.

[0059] In one or more embodiments, the chip and cooler assembly 600 also includes a filled thermal epoxy 400, such as silver-filled epoxy, that attaches the microchannel cooler to the chips. In other embodiments, a metallic substance, material, or compound (e.g., indium foil, silver-tin solder) attaches the microchannel cooler to the chips.

[0060] In one or more embodiments, the thickness of the module is between 2 mm and 25 mm. In some embodiments, the thickness of the module is between 4 mm and 12 mm.

[0061] In one or more embodiments, the chip and cooler assembly also includes an underfill that bonds the interposer, chips, frame, and cooler together and fills the gaps therebetween.

[0062] In one or more embodiments, the frame has a plurality of components. In one or more embodiments, the plurality of components includes a plurality of layers; for example, a plurality of silicon layers joined together as discussed elsewhere herein - see Figure 11 layers 1116, 1118, 1120, 1122 of Figure 11 In one or more embodiments, the plurality of layers includes a first layer extending along all edges of the component and a second layer on top of the first layer; the second layer (e.g.,

[0063] In one or more embodiments, the chip and cooler assembly 600 further includes a load block 700 on top of the manifold, where the load block has holes matching the holes of the manifold, has a compliant member (e.g., an O-ring) around the matching holes, and has additional compliant members (e.g., O-rings) distributed in a uniform array across the interface of the load block and the manifold.

[0064] In one or more embodiments, the manifold includes a top member 206 and a bottom member 204, where there is a central inlet hole 224 and two peripheral outlet holes 222 that extend from the top of the manifold through the top member to grooves 220, 218 across the bottom of the top member, and the bottom member includes a plurality of holes 212 that pass from each groove through the bottom member to the microchannel cooler.

[0065] In one or more embodiments, the chip and cooler assembly further includes a glass frit that joins the top member of the manifold to the bottom member of the manifold and joins the bottom member of the manifold to the microchannel cooler.

[0066] According to another aspect, referring to Figure 10 , exemplary method 1000 includes: at 1002, assembling a plurality of chips onto the back side of the interposer. The chips are CTE-matched to the interposer. The method further includes: at 1004, assembling a frame into the gaps between the chips; at 1006, depositing a thermal epoxy 400 onto the back side of the chips; and at 1010, loading a chip cooler module 200 onto the thermal epoxy. The microchannel cooler is CTE-matched to the chips and the interposer.

[0067] In one or more embodiments, method 1000 further includes: at 1008, forming a chip cooler module 200 by attaching the manifolds 204, 206 to the microchannel cooler 202; and at 1012, filling a bottom fill 602 into the gaps between the chips, the frame, the microchannels, and the interposer.

[0068] In one or more embodiments, method 1000 further includes, at 1014, combining a thermally expansion-matched chip and cooler assembly 600 with a load block 700, wherein a first plurality of O-rings connect holes of the load block 700 to holes of the upper manifold 206, and wherein a second plurality of O-rings distribute mechanical loads across the interface of the load block and the manifold.

[0069] In one or more embodiments, method 1000 further includes, at 1016, loading the chip and cooler assembly into a pin grid array socket using pressure on the load block.

[0070] In one or more embodiments, method 1000 further includes, at 1018, flowing coolant from the load block through the manifold.

[0071] The description of the various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to a person of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein were chosen to best explain the principles of the embodiments, the practical application, or technical improvements to the technology found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A chip and cooler assembly, comprising: An interposer having a front side and a back side interposer; A plurality of integrated circuit chips mounted on the back side of the interposer, wherein each of the chips has a front side attached to the front side of the interposer and a back side facing away from the interposer, and wherein a gap separates the chips; A frame assembled around the chips, wherein the frame has a CTE match with the chips, and wherein the frame and the chips define a back side surface; And A cooler module attached to the back side surface, wherein the cooler module has a CTE match with the chips, and wherein the cooler module includes a microchannel cooler disposed against the back side of the chips and a manifold attached to the microchannel cooler opposite the chips, and wherein the manifold has a CTE match with the microchannel cooler.

2. The chip and cooler assembly according to claim 1, further comprising: A plurality of thinner chips embedded in a portion of the gap between the plurality of chips, wherein the frame is thinner above the thinner chips and thicker where there are no thinner chips.

3. The chip and cooler assembly according to claim 1, wherein the chips have electrical contacts at their front sides, and wherein the interposer includes a land grid array pad disposed on the front side of the interposer and includes through-silicon vias connecting the electrical contacts of the chips to the land grid array pads.

4. The chip and cooler assembly according to claim 1, wherein the interposer has a CTE match with the chips and includes a redistribution wiring layer adjacent to the chips.

5. The chip and cooler assembly according to claim 1, wherein the material of the manifold includes glass.

6. The chip and cooler assembly according to claim 1, wherein at least one of the chips is mounted to the interposer by hybrid bonding.

7. The chip and cooler assembly according to claim 1, wherein the frame includes a plurality of components.

8. The chip and cooler assembly according to claim 7, wherein the plurality of components include a plurality of silicon layers bonded together.

9. The chip and cooler assembly according to claim 8, wherein the plurality of layers include a first layer present around the entire edge of the assembly and a second layer on top of the first layer, and wherein the second layer is present at a first side of the assembly but not at a side of the assembly opposite the first side.

10. The chip and cooler assembly according to claim 1, further comprising a filled thermally rigid adhesive attaching the microchannel cooler to the chips.

11. The chip and cooler assembly according to claim 1, further comprising a metallic substance attaching the microchannel cooler to the chips.

12. The chip and cooler assembly according to claim 1, wherein the thickness of the module is between 2 mm and 25 mm.

13. The chip and cooler assembly according to claim 1, wherein the thickness of the module is between 4 mm and 12 mm.

14. The chip and cooler assembly according to claim 1 further includes a filler material that bonds the interposer, the frame, the chip, and the cooler together and fills the gaps therebetween.

15. The chip and cooler assembly according to claim 14, wherein the filler material has a CTE between approximately 0.6×10 -6 / K and approximately 5.8×10 -6 / K.

16. The chip and cooler assembly according to claim 1 further includes a load block on top of the manifold, wherein the load block has holes that match the holes of the manifold, has an O-ring around the matching holes, and has additional O-rings distributed in a uniform array across the interface of the load block and the manifold.

17. The chip and cooler assembly according to claim 16, wherein the manifold includes a top member and a bottom member, wherein one or more inlet holes and one or more outlet holes extend from the top of the manifold through the top member to a groove across the bottom of the top member, and wherein the bottom member includes a plurality of holes that pass through the bottom member from each groove to the microchannel cooler.

18. The chip and cooler assembly according to claim 1, wherein the interposer is an active interposer.

19. A method includes: assembling a plurality of chips onto the rear side of an interposer, wherein the chips are CTE-matched with the interposer; assembling a frame into the gaps between the chips; depositing an adhesive onto the rear sides of the chips; and loading a chip cooler module against the adhesive, wherein the chip cooler module is CTE-matched with the chips and the interposer.

20. The method according to claim 19 further includes: forming the chip cooler module by attaching a manifold to a microchannel cooler; and filling a bottom filler into the gaps between the chips, the frame, the microchannels, and the interposer.

21. The method according to claim 20 further includes: forming a chip and cooler assembly by assembling a load block to the manifold, wherein a first plurality of O-rings connect the holes of the load block to the holes of the manifold, and wherein a second plurality of O-rings distribute mechanical loads across the interface of the load block and the manifold.

22. The method according to claim 21 further includes: loading the chip and cooler assembly into a land grid array socket while applying pressure to the load block.

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