Package architecture including memory chips with different process regions

Abstract

An embodiment of a microelectronic assembly includes a first integrated circuit (IC) die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and packaging the substrate. The first IC die includes: a first portion including a first active region and a first back end region in contact with the first active region; and a second portion including a second active region and a second rear end region in contact with the second active region. In plan view, the second portion is surrounded by the first portion, the first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region includes a transistor larger than a transistor in the second active region, and the first back end region includes a conductive trace, the conductive traces have a pitch greater than a pitch of the conductive traces in the second back end region.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of the priority date of U.S. Application No. 18 / 148543, filed on December 30, 2022. Technical field

[0003] This disclosure relates to techniques, methods, and apparatuses for packaging architectures for memory chips that include different process regions. Background art

[0004] Electronic circuits that are typically fabricated on wafers of semiconductor materials such as silicon are referred to as integrated circuits (ICs). Wafers having such ICs are typically cut into a plurality of individual die. The die can be packaged into an IC package that includes one or more die and other electronic components such as resistors, capacitors, and inductors. The IC package can be integrated into an electronic system (such as a consumer electronics system) or a server (such as a host). Brief description of the drawings

[0005] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. For ease of description, the same reference numerals denote the same structural elements. Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings.

[0006] Figure 1A is a simplified cross - sectional view of an example IC die according to some embodiments of the present disclosure.

[0007] Figure 1B is according to some embodiments Figure 1A simplified plan view of an example IC die.

[0008] Figure 1C is according to some embodiments Figure 1A simplified plan view of an example IC die.

[0009] Figure 2 is a simplified cross - sectional view of an example IC die according to some embodiments of the present disclosure.

[0010] Figure 3 is a simplified cross - sectional view of an example IC die according to some embodiments of the present disclosure.

[0011] Figure 4 is a simplified cross - sectional view of an example IC die according to some embodiments of the present disclosure.

[0012] Figure 5 is a simplified cross - sectional view of an example microelectronic component according to some embodiments of the present disclosure.

[0013] Figure 6is a simplified cross-sectional view of an example microelectronic component in accordance with some embodiments of the present disclosure.

[0014] Figure 7A is a simplified cross-sectional view of an example microelectronic component in accordance with some embodiments of the present disclosure.

[0015] Figure 7B is a simplified cross-sectional view of an example microelectronic component in accordance with some embodiments of the present disclosure.

[0016] Figure 8 is a simplified cross-sectional view of an example microelectronic component in accordance with some embodiments of the present disclosure.

[0017] Figure 9 is a simplified cross-sectional view of an example microelectronic component in accordance with some embodiments of the present disclosure.

[0018] Figure 10 is a simplified cross-sectional view of an example microelectronic component in accordance with some embodiments of the present disclosure.

[0019] Figure 11 is a simplified cross-sectional view of an example microelectronic component in accordance with some embodiments of the present disclosure.

[0020] Figure 12 is a simplified cross-sectional view of an example microelectronic component in accordance with some embodiments of the present disclosure.

[0021] Figure 13 is a simplified cross-sectional view of an example microelectronic component in accordance with some embodiments of the present disclosure.

[0022] Figure 14 is a flowchart of an example operation that may be associated with fabricating an IC die in accordance with some embodiments of the present disclosure.

[0023] Figure 15 is a cross-sectional view of a device package including one or more microelectronic components in accordance with any of the embodiments disclosed herein.

[0024] Figure 16 is a cross-sectional side view of a device assembly including one or more microelectronic components in accordance with any of the embodiments disclosed herein.

[0025] Figure 17 is a block diagram of an example computing device including one or more microelectronic components in accordance with any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0026] Overview

[0027] For purposes of showing the IC packages described herein, it is important to understand the phenomena that may come into play during the assembly and packaging of an IC. The following fundamental information can be considered as the basis upon which the present disclosure can be properly interpreted. Such information is provided for purposes of explanation only and should not, therefore, be construed in any way as limiting the broad scope of the present disclosure and its potential applications.

[0028] In the semiconductor industry, the demand for miniaturization of form factors and increased integration for high performance is driving complex packaging methods. Advancements in semiconductor processing and logic design allow for an increase in the amount of logic circuitry that can be included in a processor and other IC devices. As a result, many processors now have multiple cores monolithically integrated on a single die. Generally, these types of monolithic ICs are also described as planar because they take the form of a flat surface and are typically built on a single silicon wafer made from a single-crystalline silicon ingot. A typical manufacturing process for such monolithic ICs is called the planar process, which allows lithography, etching, thermal diffusion, oxidation, and other such processes to occur on the surface of the wafer such that active circuit elements (e.g., transistors and diodes) are formed on the flat surface of the silicon wafer.

[0029] Current technology allows for the formation of hundreds or thousands of such active circuit elements on a single die, enabling many logic circuits to be implemented thereon. In such a monolithic die, the manufacturing process must be optimized equally for all circuits, resulting in trade-offs between different circuits. Additionally, due to the limitation of having to place circuits on a flat surface, some circuits are further away from some other circuits, leading to performance degradation such as longer delays. The manufacturing yield can also be severely affected because if even one circuit fails, the entire die may have to be discarded.

[0030] One solution to overcome such negative impacts of a monolithic die is to break the circuit into smaller dies (e.g., dielets, tiles) that are electrically coupled via interconnect bridges. The smaller dies are part of the components of the interconnected dies that together form a complete IC in terms of application and / or function, such as a memory chip, a microprocessor, a microcontroller, a commodity IC (e.g., a chip for repetitive processing routines, simple tasks, an application-specific IC, etc.), and a system-on-chip (SOC). In other words, the individual dies are connected to establish the functionality of a monolithic IC. By using separate dies, each individual die can be optimally designed and manufactured for a specific function. For example, a processor core containing logic circuitry may be targeted for performance and may thus require a layout that is highly optimized for speed; this has different manufacturing requirements compared to a USB controller that is built to meet certain USB standards rather than being targeted for processing speed; by separating different parts of the overall design into different dies, each die can be optimized in terms of design and manufacturing, improving the overall yield and cost of the combined die solution.

[0031] The connections between these die can be achieved in a variety of ways. For example, in a 2.5D packaging solution, a silicon interposer and through-silicon vias (TSVs) connect the die at silicon interconnect speeds with minimal footprint. In another example, a silicon bridge embedded under the edges of two interconnected die, known as an Embedded Multi-Die Interconnect Bridge (EMIB TM ), facilitates electrical coupling between them. The bridge die can be embedded in the package substrate, promoting Omni-Directional Interconnect (ODI TM ), which allows the top-packaged chips to communicate with other chips using the bridge die in the horizontal direction and through-molded vias (TMVs) in the package substrate in the vertical direction. This die partitioning enables miniaturization and high performance in a small form factor without the problems seen with other methods, but requires fine die-to-die interconnects. EMIB can facilitate such high-density interconnects by inserting bridge die only where needed. Standard flip-chip assemblies are used for robust power delivery and to connect high-speed signals directly from the chip to the package substrate.

[0032] Even with this advanced packaging technology, future trends pose increasing challenges to various memory devices. For example, Static Random Access Memory (SRAM) is a memory circuit where data is stored in transistors and requires a constant power flow. Due to the continuous power, SRAM circuits do not need to be refreshed to remember the data being stored. In Dynamic Random Access Memory (DRAM), data is stored in capacitors. The capacitors storing data in DRAM gradually release energy, so periodic refresh power is required to operate. In a general sense, SRAM circuits consist of transistor memory cells, while DRAM circuits consist of transistors and capacitors. Since SRAM circuits use a larger number of transistors than DRAM circuits, the manufacturing of SRAM circuits is more complex than that of DRAM circuits. SRAM circuits are faster than DRAM circuits, but store less data and are also more expensive to manufacture. For example, RAM circuits operate at speeds in the range between 20 nanoseconds and 50 nanoseconds, while DRAM circuits operate at speeds in the range between 60 nanoseconds and 100 nanoseconds, making DRAM circuits less suitable for high-bandwidth applications. On the other hand, DRAM circuits can store more data than SRAM circuits, making DRAM circuits more suitable for high-capacity applications. In current memory applications, SRAM circuits are used in cache memories, positioned close to the computing circuits for faster access, while DRAM circuits are used in main memories and can be located further away from the computing circuits. In future memory applications, it may be beneficial to combine the efficacy of SRAM circuits with the cost-effectiveness and storage capacity of DRAM circuits in a single IC to achieve faster, cheaper, and higher-capacity memory devices.

[0033] Accordingly, embodiments of a microelectronic component include: a first IC die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and a package substrate. The first IC die is located between the second IC die and the package substrate, and the first IC die includes: a first portion including a first active region and a first back-end region in contact with the first active region; and a second portion including a second active region and a second back-end region in contact with the second active region. The first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region includes transistors that are larger than the transistors in the second active region, and the first back-end region includes conductive traces having a pitch that is larger than the pitch of the conductive traces in the second back-end region.

[0034] Some other embodiments disclose an IC structure that includes: a substrate including a semiconductor material; a first portion including a first active region and a first back-end region; and a second portion including a second active region and a second back-end region. The first portion is in contact with the second portion along an interface, the first active region and the second active region are in the substrate, the first active region includes transistors that are larger than the transistors in the second active region, and the first back-end region includes conductive traces having a pitch that is larger than the pitch of the conductive traces in the second back-end region.

[0035] Some other embodiments disclose an IC structure that includes: a substrate having a first side and a second side; a first portion including a first active region and a first back-end region; and a second portion including a second active region and a second back-end region. The first portion is on the first side of the substrate, the second portion is on the second side of the substrate, the first active region includes transistors that are larger than the transistors in the second active region, and the first back-end region includes conductive traces having a pitch that is larger than the pitch of the conductive traces in the second back-end region.

[0036] Each of the structures, components, packages, methods, devices, and systems of the present disclosure may have several innovative aspects, none of which alone is responsible for all of the desired attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the following description and the drawings.

[0037] In the following detailed description, the various aspects of the illustrative embodiments may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.

[0038] The terms "circuit" and "circuitry" refer to one or more passive and / or active electrical and / or electronic components arranged to cooperate with each other to provide a desired function. The terms also relate to analog circuitry, digital circuitry, hardwired circuitry, programmable circuitry, microcontroller circuitry, and / or any other type of physical hardware electrical and / or electronic components.

[0039] The term "integrated circuit" refers to a circuit that is integrated into a single piece of semiconductor or similar material.

[0040] In some embodiments, the IC die disclosed herein may include a substantially single-crystalline semiconductor, such as silicon or germanium, as a substrate material (e.g., a substrate, a body) on which integrated circuits are fabricated using conventional semiconductor processing methods. The semiconductor substrate material may include, for example, N-type or P-type material. The die may include, for example, a crystalline substrate material formed using bulk silicon (or other bulk semiconductor material) or a silicon-on-insulator (SOI) structure. In some other embodiments, the substrate material of one or more of the IC dies may include alternative materials that may or may not be combined with silicon, the alternative materials including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV group materials. In other embodiments, the substrate material may include a compound semiconductor, e.g., having a first sublattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). In other embodiments, the substrate material may include an intrinsic IV or III-V semiconductor material or alloy that is not intentionally doped with any electrically active impurities; in alternative embodiments, a nominal impurity dopant level may be present. In other embodiments, the die may include an amorphous material, such as a polymer; for example, the substrate material may include silica-filled epoxy resin. In other embodiments, the substrate material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Generally, the substrate material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, cupric peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, among others. Although several examples of materials for the die are described herein, any material or structure that can be used as a basis (e.g., a substrate material) on which the IC circuits and structures described herein can be built falls within the spirit and scope of the present disclosure.

[0041] Unless otherwise described, the IC die described herein includes one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) certain functions. In one such instance, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuitry (e.g., an IC that implements one or more of a memory device, a memory array, control logic configured to control the memory device and array, etc.). In another such example, the term "compute die" may be used to describe a die that includes one or more ICs that implement logic / compute circuitry (e.g., an IC that implements one or more of I / O functions, arithmetic operations, data pipelining, etc.).

[0042] In another example, the terms "package" and "IC package" are synonymous, as are the terms "die" and "IC die". Note that the terms "chip", "die", and "IC die" may be used interchangeably herein.

[0043] The term "optical structure" includes various forms of arrangements fabricated in an IC to receive, transform, and / or transmit optical signals as described herein. It may include optical conductors such as waveguides, sources of electromagnetic radiation such as lasers and light-emitting diodes (LEDs), and electro-optic devices such as photodetectors.

[0044] In various embodiments, any photonics IC (PIC) described herein may include a semiconductor material, which may include, for example, N-type or P-type material. The PIC may include, for example, a crystalline substrate material formed using bulk silicon (or other bulk semiconductor material) or a SOI structure (or generally, a semiconductor-on-insulator structure). In some embodiments, the PIC may be formed using alternative materials that may or may not be combined with silicon, the alternative materials including but not limited to lithium niobate, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, aluminum indium arsenide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride, or gallium antimonide, or other combinations of III-N or IV group materials. In some embodiments, the PIC may include amorphous materials such as polymers. In some embodiments, the PIC may be formed on a printed circuit board (PCB). In some embodiments, the PIC may be heterogeneous, including a carrier material (such as glass or silicon carbide) as the substrate material, with a thin semiconductor layer on its active side that includes transistors and like components. Although several examples of materials for PICs are described herein, any material or structure that can be used as a basis on which a PIC can be built falls within the spirit and scope of this disclosure.

[0045] Unless otherwise specified, the term "insulated" means "electrically insulated", and the term "conductive" means "electrically conductive". With reference to optical signals and / or devices, components, and elements that operate on or use optical signals, the term "conductive" can also mean "optically conductive".

[0046] The terms "oxide", "carbide", "nitride", etc. refer to compounds containing oxygen, carbon, nitrogen, etc., respectively.

[0047] The term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide.

[0048] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refers to a solid material (and / or a liquid material that cures after processing as described herein) that is substantially non-conductive. By way of example and not limitation, they can include organic polymers and plastics, as well as inorganic materials such as ionic crystals, porcelain, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and aluminum oxide or combinations thereof. They can include dielectric materials, high polarizability materials, and / or piezoelectric materials. Without departing from the scope of the present disclosure, they can be transparent or opaque. Other examples of insulating materials are underfills and molding or molding-like materials used in encapsulation applications, including, for example, materials used in organic interposers, encapsulation supports, and other such components.

[0049] In various embodiments, the elements associated with an IC can include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, the elements associated with an IC can include elements monolithically integrated within the IC, elements mounted on the IC, or elements connected to the IC. Depending on the components associated with the IC, the ICs described herein can be analog or digital and can be used in a plurality of applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc. The ICs described herein can be used in a single IC die or as part of a chipset for performing one or more related functions in a computer.

[0050] In various embodiments of the present disclosure, the transistors described herein can be field effect transistors (FETs), such as MOSFETs. In many embodiments, the FET is a four-terminal device. In silicon-on-insulator or nanoribbon or gate-all-around (GAA) FETs, the FET is a three-terminal device including source, drain, and gate terminals, and uses an electric field to control the current flowing through the device. The FET generally includes a channel material, source and drain regions disposed in and / or on the channel material, and a gate stack including gate electrode material disposed over a portion of the channel material ("channel portion") that is between the source and drain regions, which is alternatively referred to as "work function" material, and optionally, the gate stack further includes a gate dielectric material between the gate electrode material and the channel material.

[0051] In a general sense, an "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components, facilitating the communication of electrical signals therebetween; an optical interconnect provides an optical connection between two optical components, facilitating the communication of optical signals therebetween. As used herein, both electrical and optical interconnects are included in the term "interconnect". The nature of the described interconnects will be understood with reference to the signal medium associated therewith. Thus, when referring to an electronic device such as an IC that operates using electrical signals, the term "interconnect" describes any element formed of a conductive material for providing an electrical connection to and / or between one or more elements associated with the IC. In such cases, the term "interconnect" can refer to both electrical traces (sometimes also referred to as "lines", "wires", "metal lines", or "trenches") and conductive vias (sometimes also referred to as "vias" or "metal vias"). Sometimes, the conductive traces and vias can be referred to as "conductive traces" and "conductive vias" respectively, to highlight the fact that these elements include a conductive material such as metal. Similarly, when referring to a device that also operates on optical signals (such as a photonic IC (PIC)), "interconnect" can also describe any element formed of an optically conductive material for providing an optical connection to one or more elements associated with the PIC. In such cases, the term "interconnect" can refer to optical waveguides, including optical fibers, splitters, combiners, couplers, and optical vias.

[0052] The term "waveguide" refers to any structure used to guide light from one location to another, typically through a substrate material such as silicon or glass. In various examples, waveguides can be formed from silicon, doped silicon, silicon nitride, glass (such as silica (e.g., silicon dioxide or SiO2)), borosilicate (e.g., 70 - 80 wt% SiO2, 7 - 13 wt% B2O3, 4 - 8 wt% Na2O or K2O, and 2 - 8 wt% Al2O3), etc. Waveguides can be formed using various techniques, including but not limited to in-situ waveguide formation. For example, in some embodiments, waveguides can be formed in-situ in glass using low-temperature glass-to-glass bonding or by direct laser writing. In-situ formed waveguides can have the characteristic of lower loss.

[0053] The term "conductive trace" can be used to describe a conductive element isolated by an insulating material. Within an IC die, such insulating material includes interlayer low-k dielectrics disposed within the IC die. Within a package substrate and a PCB, such insulating material includes organic materials such as Ajinomoto Build-up Film (ABF), polyimide, or epoxy resin. Such conductive traces are typically arranged in several levels or layers of a metallization stack.

[0054] The term "conductive via" can be used to describe a conductive element that interconnects two or more conductive traces of different levels of a metallization stack. For this purpose, vias can be arranged to be substantially perpendicular to the plane of the IC die / chip or the plane of a support structure on which the IC structure is provided, and can interconnect two conductive traces in adjacent levels or two conductive traces in non-adjacent levels.

[0055] The term "package substrate" can be used to describe any substrate material that facilitates the encapsulation of any collection of semiconductor dies and / or other electrical components (e.g., passive electrical components). As used herein, a package substrate can be formed from any material, including but not limited to insulating materials such as resin-impregnated fiberglass (e.g., PCB or Printed Wiring Board (PWB)), glass, ceramic, silicon, silicon carbide, etc. Additionally, as used herein, a package substrate can refer to a substrate that includes build-up layers (e.g., ABF layers).

[0056] The term "metallization stack" can be used to refer to one or more stacked interconnects used to provide connections to different circuit components of an IC die / chip and / or a package substrate.

[0057] As used herein, the "pitch" of an interconnect refers to the center-to-center distance between adjacent interconnects.

[0058] In the context of a stack of die that are coupled to each other or in the context of a die that is coupled to a package substrate, the term "interconnect" can also refer to die-to-die (DTD) interconnects and die-to-package-substrate (DTPS) interconnects, respectively. DTD interconnects can also be referred to as first-level interconnects (FLI). DTPS interconnects can also be referred to as second-level interconnects (SLI).

[0059] Although not specifically shown in all of the presented figures so as not to clutter the drawings, when describing DTD or DTPS interconnects, the surface of the first die can include a first set of conductive contacts, and the surface of the second die or package substrate can include a second set of conductive contacts. Then, one or more conductive contacts of the first set can be electrically and mechanically coupled to some of the conductive contacts of the second set via the DTD or DTPS interconnect.

[0060] In some embodiments, the pitch of the DTD interconnects can be different from the pitch of the DTPS interconnects, but in other embodiments, these pitches can be substantially the same.

[0061] The DTPS interconnects disclosed herein can take any suitable form. In some embodiments, a set of DTPS interconnects can include solder (e.g., solder bumps or balls that are subjected to thermal reflow to form the DTPS interconnect). The DTPS interconnects that include solder can include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, a set of DTPS interconnects can include anisotropic conductive materials, such as anisotropic conductive films or anisotropic conductive pastes. An anisotropic conductive material can include conductive materials dispersed in a non-conductive material. In some embodiments, an anisotropic conductive material can include microscopic conductive particles embedded in a binder or a thermosetting adhesive film (e.g., a thermosetting biphenyl-type epoxy resin or an acrylic-based material). In some embodiments, the conductive particles can include polymers and / or one or more metals (e.g., nickel or gold). For example, the conductive particles can include gold coated with nickel or copper coated with silver, which in turn is coated with a polymer. In another example, the conductive particles can include nickel. When the anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other side. However, when the anisotropic conductive material is sufficiently compressed (e.g., by conductive contacts on either side of the anisotropic conductive material), the conductive materials near the compressed region can contact each other to form a conductive path from one side of the film to the other side in the compressed region.

[0062] The DTD interconnects disclosed herein can take any suitable form. In some embodiments, some or all of the DTD interconnects in a microelectronic component or IC package as described herein can be metal-to-metal interconnects (e.g., copper-to-copper interconnects or plated interconnects). In such embodiments, the conductive contacts on either side of the DTD interconnect can be joined together (e.g., under elevated pressure and / or temperature) without using an intermediate solder or anisotropic conductive material. In some metal-to-metal interconnects, a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide) can be present between the joined metals (e.g., between copper pads or pillars providing the associated conductive contacts). In some embodiments, one side of the DTD interconnect can include metal pillars (e.g., copper pillars), and the other side of the DTD interconnect can include metal contacts (e.g., copper contacts) recessed in a dielectric. In some embodiments, the metal-to-metal interconnect (e.g., copper-to-copper interconnect) can include a noble metal (e.g., gold) or a metal (e.g., silver) whose oxide is conductive. In some embodiments, the metal-to-metal interconnect can include metal nanostructures (e.g., nanorods) that can have a reduced melting point. Metal-to-metal interconnects may be able to reliably conduct higher currents than other types of interconnects; for example, when current flows, some solder interconnects can form brittle intermetallic compounds, and the maximum current provided through such interconnects can be constrained to mitigate mechanical failures.

[0063] In some embodiments, the die on either side of a set of DTD interconnects can be a bare (e.g., unpackaged) die.

[0064] In some embodiments, the DTD interconnect can include solder. For example, the DTD interconnect can include conductive bumps or pillars (e.g., copper bumps or pillars) attached to corresponding conductive contacts by solder. In some embodiments, a thin cap of solder can be used in a metal-to-metal interconnect to accommodate planarization, and the solder can turn into an intermetallic compound during processing. In some embodiments, the solder used in some or all of the DTD interconnects can have a higher melting point than the solder included in some or all of the DTPS interconnects. For example, when forming the DTD interconnects in an IC package before forming the DTPS interconnects, the solder-based DTD interconnects can use a higher temperature solder (e.g., having a melting point above 200 degrees Celsius), while the DTPS interconnects can use a lower temperature solder (e.g., having a melting point below 200 degrees Celsius). In some embodiments, the high temperature solder can include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the low temperature solder can include tin and bismuth (e.g., eutectic tin bismuth), tin, silver, bismuth, indium, indium and tin, or gallium.

[0065] In some embodiments, a set of DTD interconnects can include anisotropic conductive materials, such as any of the materials discussed above for DTPS interconnects. In some embodiments, DTD interconnects can be used as data transmission channels, while DTPS interconnects can be used for power and ground lines, etc.

[0066] In a microelectronic component or IC package as described herein, some or all of the DTD interconnects can have a finer pitch than the DTPS interconnects. In some embodiments, the DTPS interconnects disclosed herein can have a pitch between about 80 microns and 300 microns, while the DTD interconnects disclosed herein can have a pitch between about 0.5 microns and 100 microns, depending on the type of DTD interconnect. Examples of silicon-level interconnect density are provided by the density of some DTD interconnects. In some embodiments, the pitch of the DTD interconnects may be too fine to be directly coupled to the package substrate (e.g., too fine to be used as a DTPS interconnect). Since the materials in different dies on either side of a set of DTD interconnects are more similar than the materials between the die and the package substrate on either side of a set of DTPS interconnects, the DTD interconnects can have a smaller pitch than the DTD interconnects. In particular, due to the heat generated during operation (and the heat applied during various manufacturing operations), the difference in the material compositions of the die and the package substrate can cause differential expansion and contraction of the die and the package substrate. To mitigate damage (e.g., cracking, solder bridging, etc.) caused by such differential expansion and contraction, the DTPS interconnects in any of the microelectronic components or IC packages as described herein can be formed to be larger and farther apart than the DTD interconnects, which may experience less thermal stress due to the greater material similarity of a pair of dies on either side of the DTD interconnects.

[0067] It will be appreciated that one or more levels of underfill (e.g., an organic polymer material such as benzotriazole, imidazole, polyimide, or epoxy resin) can be provided in the IC packages described herein and the one or more levels of underfill can be unlabeled to avoid obscuring the drawings. In various embodiments, the levels of underfill can include the same or different insulating materials. In some embodiments, the levels of underfill can include a thermosetting epoxy resin with silica particles; in some embodiments, the levels of underfill can include any suitable material that can perform an underfill function such as supporting the die and reducing thermal stress on the interconnects. In some embodiments, the selection of the underfill material can be based on design considerations such as form factor, size, stress, operating conditions, etc.; in other embodiments, the selection of the underfill material can be based on material properties and processing conditions such as cure temperature, glass transition temperature, viscosity, and chemical resistance, as well as other factors; in some embodiments, the selection of the underfill material can be based on both design and processing considerations.

[0068] In some embodiments, one or more levels of solder mask (e.g., epoxy liquid, liquid photoimageable polymer, dry film photoimageable polymer, acrylic, solvent) may be provided in the IC packages described herein, and the one or more levels of solder mask may not be labeled or shown to avoid making the drawings difficult to understand. The solder mask may be a liquid or dry film material including a photoimageable polymer. In some embodiments, the solder mask may be non-photoimageable.

[0069] The terms “substantially,” “close to,” “approximately,” “approximate,” and “about” generally refer to within + / - 20% of a target value (e.g., within + / - 5% or 10% of the target value) based on the context of a particular value as described herein or known in the art.

[0070] The terms indicating the orientation of various elements, such as “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between elements generally refer to within + / - 5%-20% of a target value based on the context of a particular value as described herein or known in the art.

[0071] The term “connected” refers to a direct connection (which may be one or more of a mechanical connection, an electrical connection, and / or a thermal connection) between the things being connected without any intervening device, while the term “coupled” refers to a direct connection between the things being connected or an indirect connection through one or more passive or active intervening devices.

[0072] The description uses the phrase “in an embodiment,” which may refer to one or more of the same or different embodiments.

[0073] Furthermore, the terms “comprising,” “including,” “having,” etc., used with respect to embodiments of the present disclosure are synonymous.

[0074] The present disclosure may use perspective-based descriptions, such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are for ease of discussion and are not intended to limit the application of the disclosed embodiments.

[0075] As used herein, the terms "above", "below", "between", and "on" refer to the relative position of one layer or component of a material with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intermediate layers. Additionally, a layer disposed between two layers may be in direct contact with one or both of the two layers or may have one or more intermediate layers. In contrast, a first layer described as "on" a second layer refers to a layer in direct contact with the second layer. Similarly, unless otherwise expressly stated, a feature disposed between two features may be in direct contact with an adjacent feature or may have one or more intermediate layers.

[0076] As used herein, the term "disposed" refers to positioning, being located, placing, and / or arranging, and does not refer to any particular method of formation.

[0077] When used in reference to a measurement range, the term "between" includes the endpoints of the measurement range.

[0078] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0079] Although certain elements are referred to herein in the singular, such elements may include multiple sub-elements. For example, "conductive material" may include one or more conductive materials. In another example, "dielectric material" may include one or more dielectric materials.

[0080] Unless otherwise specified, the use of ordinal adjectives such as "first", "second", and "third" to describe common objects merely indicates that different instances of similar objects are being referred to and is not intended to imply that the objects so described must be in a given sequence in time, space, order, or in any other way.

[0081] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description should not be taken in a limiting sense.

[0082] The drawings are not necessarily to scale.

[0083] In the drawings, like reference numerals refer to the same or similar elements / materials shown, such that, unless otherwise specified, the explanation of an element / material with a given reference numeral provided in the context of one drawing in the drawings applies to other drawings in which an element / material with the same reference numeral may be shown. In addition, singular and plural forms of the markers may be used with reference numerals to denote a single or multiple elements, respectively, of the same or similar type, kind, or category of elements.

[0084] In addition, in the drawings, some schematic illustrations of example structures of the various devices and components described herein may be shown with exact right angles and straight lines, but it should be understood that such schematic illustrations may not reflect real process limitations that may result in features not looking so "ideal" when using images of, for example, suitable characterization tools (such as scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, or non-contact profilometers) to examine any of the structures described herein. In images of such real structures, possible processing and / or surface defects may also be visible, such as surface roughness, curvature or profile deviation, pits or scratches, imperfect straight edges of materials, tapered vias or other openings, unintentional rounding of corners, or variations in the thickness of different material layers, accidental screw dislocations, edge dislocations, or combined dislocations within a (multiple) crystal region, and / or accidental dislocation defects of individual atoms or clusters of atoms. There may be other defects not listed herein but common in the field of device fabrication and / or packaging.

[0085] Note that in the drawings, various components (e.g., interconnects) are shown as aligned (e.g., at corresponding interfaces) only for ease of illustration; in reality, some or all of them may be misaligned. In addition, there may be other components in the assemblies, such as bond pads, landing pads, metallizations, etc., which are not shown in the drawings to prevent confusion. In addition, the drawings are intended to show the relative arrangement of the components within them, and generally speaking, such assemblies may include other components not shown (e.g., various interface layers or various other components related to optical functions, electrical connections, or thermal mitigation). For example, in some additional embodiments, an assembly as shown in the figures may include more die and other electrical components. Additionally, although some components of the assemblies are illustrated as planar rectangles or formed by solid rectangles in the drawings, this is merely for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregular in shape, which is determined by and sometimes inevitable due to the manufacturing processes used to fabricate the various components.

[0086] In the drawings, a specific number and arrangement of structures and components are presented for illustrative purposes, and any desired number or arrangement of such structures and components may exist in various embodiments.

[0087] In addition, unless otherwise specified, the structures shown in the drawings may take any suitable form or shape depending on the material properties, manufacturing processes, and operating conditions.

[0088] For convenience, if there are sets of drawings designated by different letters (e.g., Figure 10 A- Figure 10 C), then such sets may be referred to herein without the letters (e.g., as “ Figure 10 ”). Similarly, if there are sets of reference numerals designated by different letters (e.g., 112a-112e), then such sets may be referred to herein without the letters (e.g., as “112”).

[0089] The various operations may be described sequentially in multiple discrete actions or operations in the manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations necessarily depend on the order. In particular, these operations may not be performed in the order presented. The described operations may be performed in a different order than the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0090] Example Embodiment

[0091] Figure 1A is a schematic cross-sectional view of an example IC die 100 in accordance with some embodiments of the present disclosure. As shown, a portion of the IC structure in IC die 100 includes a substrate 102 of semiconductor material listed in the previous section. Substrate 102 includes a portion 104 and a portion 106 that contacts portion 104 along interface 107. Portion 104 includes an active region 108 and a back-end region 110 having conductive traces 112 in an inorganic dielectric material. Portion 106 includes an active region 114 and a back-end region 116 having conductive traces 118 in an inorganic dielectric material. In various embodiments, the inorganic dielectric material in the respective back-end regions 110 and 116 may include the same interlayer dielectric (ILD) material; in other embodiments, the inorganic dielectric material may include different ILD materials. Examples of high-k ILD materials include silicon dioxide (SiO2), hafnium silicate (HfSiO4), zirconium silicate (ZrSiO4), and barium titanate (BaTiO3). Examples of low-k ILD materials include carbon- or fluorine-doped silicon dioxide, organosilicate glass (OSG), and various silsesquioxanes.

[0092] As used herein, terms such as "backend region" (or "back-end region" or "back end region" or "BEOL (backend of the line)") like backend regions 110 and 116 refer to regions in a semiconductor device that include conductive traces and vias capable of enabling conductive coupling of active elements in a front-end region. The backend region includes contacts (e.g., pads that contact active elements), insulating layers (e.g., dielectric layers), metal levels (e.g., conductive traces and vias), and bonding sites such as bonding pads for chip-to-package and chip-to-chip connections. In some semiconductor devices, there may be more than 10 dielectric layers between the active region and the bonding site. In some embodiments, backend regions 110 and 116 do not include semiconductor materials or active devices fabricated in semiconductor materials.

[0093] In various embodiments, the fabrication of backend regions 110 and 116 includes forming contacts and dielectric structures. For example, the process typically begins with deposition of a conductive metal layer such as copper or aluminum on top of active regions 108 and / or 114. A layer of UV-sensitive photoresist is added on top of the metal. Then, the UV light source is exposed to the photoresist through a mask that describes the desired layout of the metal wires; then the unactivated segments of the photoresist are removed in a subsequent chemical etching step. The etching process removes the unprotected metal to obtain a wire pattern that connects different active elements in active region 108 (or 114) as described by the mask. ILD material can be deposited on the conductive wiring, and the process is repeated until the desired stack of conductive traces 112 is obtained. The individual layers of conductive traces 112 are interconnected by conductive vias in the dielectric material.

[0094] In some embodiments, the active regions 108 and 114 are formed by performing an ion implantation process and other processes (including lithography, doping, etching, masking, etc.) in the substrate 102. The active region 108 includes transistors larger than those in the active region 114. The back-end region 110 includes conductive traces 112 having a pitch 126 greater than the pitch 128 of the conductive traces 118 in the back-end region 116. In various embodiments, the TSV 120 is located in the portion 106, and the TSV 120 extends through the active region 114. In some embodiments, the active region 108 may not include any TSV 120 passing through the active region 108, and in some other embodiments, the active region 108 may include TSV 120 passing through the active region 108. In some embodiments, the portion 104 may include an SRAM circuit, and the portion 106 may include a DRAM circuit. In some other embodiments, the portion 104 may include a DRAM circuit, and the portion 106 may include an SRAM circuit. In some embodiments, both the portion 104 and the portion 106 may include a DRAM circuit. In some embodiments, both the portion 104 and the portion 106 may include an SRAM circuit. In various embodiments, the portion 106 may include various types of capacitors, for example, metal-insulator-metal (MIM) capacitors 122 in the back-end region 116 and / or trench capacitors 124 in the active region 114.

[0095] In various embodiments, a different semiconductor process may be used to fabricate portion 104 compared to portion 106. For example, portion 104 may be fabricated using an older semiconductor process or a semiconductor process customized for DRAM circuits rather than SRAM circuits, and vice versa. Accordingly, the size of the transistors in active region 108 may be different from the size of the transistors in active region 114. In some embodiments, the transistors in active region 108 may be larger than the transistors in active region 114. In other embodiments, the transistors in active region 108 may be smaller than the transistors in active region 114. Additionally, the size of conductive traces 112 in back-end region 110 may be different from the size of conductive traces 118 in back-end region 116. In some embodiments, conductive traces 112 in back-end region 110 may be larger than conductive traces 118 in back-end region 116. In other embodiments, conductive traces 112 in back-end region 110 may be smaller than conductive traces 118 in back-end region 116. In various embodiments, conductive traces 112 may be disposed in a number of layers, numbered from one to five. In other embodiments, conductive traces 118 may be disposed in a greater number of layers than conductive traces 112. In various embodiments, the pitch 126 between conductive traces 112 in portion 104 may be different from the pitch 128 between conductive traces 118 in portion 106. In some embodiments, pitch 126 may be greater than pitch 128. In other embodiments, pitch 126 may be the same as or less than pitch 128. In some embodiments, back-end region 116 may extend over back-end region 110, as shown in the figure.

[0096] In various embodiments, interconnects 130 may be formed on the surface of IC die 100, for example, by a bumping operation, where interconnects 130 include flip-chip bumps. In other embodiments, interconnects 130 may include copper pillars or other types as described in the previous subsection with reference to DTD interconnects and DTPS interconnects. In various embodiments, interconnects 130 may include DTD interconnects; in other embodiments, interconnects 130 may include DTPS interconnects. A redistribution layer 132 including an organic dielectric material, such as a solder mask or polyimide, may be disposed around interconnects 130. In some embodiments, redistribution layer 132 may include a number of layers of organic dielectric material and conductive traces. In other embodiments, redistribution layer 132 may include one or more layers of solder mask.

[0097] Figure 1B is shown Figure 1APlanar view of an IC structure. In various embodiments, the IC die 100 can be fabricated on a pre - existing wafer including portion 104 on a substrate 102. Portion 104 can include one, two, or three metal layers of conductive traces 112. Trenches can be formed in, on, or around portion 104 in certain areas until the substrate 102 is exposed in the trenches. Portion 106 can be fabricated in the trenches. In some embodiments, additional segments of portion 106 can be fabricated on portion 104 to produce a composite memory die having two different types (e.g., variations) of memory circuits. For example, as Figure 1B shown, the IC die 100 can include more than one portion 104 surrounded by portion 106, e.g., 104(1) and 104(2).

[0098] Figure 1C is a planar view of another embodiment (or location) in the IC die 100 where portion 106 is surrounded by portion 104. In some such embodiments, portion 106 can include a DRAM circuit similar to SRAM. In other words, portion 104 can include a DRAM circuit fabricated using an older process, and portion 106 can include another DRAM circuit fabricated using a newer process, which can achieve a faster speed, closer to an SRAM circuit. The combination of the two processes on the same IC die 100 can simultaneously achieve higher bandwidth and higher capacity while keeping the manufacturing cost reduced. In some embodiments, a bank of such IC dies 100 having a medium - bandwidth DRAM circuit and a high - bandwidth (e.g., SRAM - like DRAM) DRAM circuit can be provided in a stack of IC dies 100. In some embodiments, such a customized DRAM stack can replace the L2 / L3 cache in a compute die or a microelectronic component. Note that for ease of illustration, the shapes of portions 104 and 106 are shown as rectangles. Any suitable shape as determined by circuit design and / or manufacturing considerations outside the scope of this disclosure can be used within a wide range of embodiments.

[0099] Figure 2Is a simplified cross-sectional view of the structure in IC die 100 according to some embodiments of the present disclosure. The embodiment shown in the figure is substantially similar to the embodiment of FIG. 1, except that portion 106 does not extend over portion 104. Instead, portions 104 and 106 are adjacent to each other and contact along interface 107. In some embodiments, although portions 104 and 106 may have the same total thickness, the individual metal layers may have different thicknesses such that portion 104 may have conductive traces 112 disposed in a different number of layers than conductive traces 118 in portion 106. In the example shown, there are 3 metal layers in portion 104 and 4 metal layers in portion 106 because the conductive traces 118 in portion 106 are thinner than the conductive traces 112 in portion 104. Other numbers of metal layers are envisioned within a broad range of embodiments. Such an arrangement may be present in embodiments described with reference to other figures herein.

[0100] Figure 3 Is a simplified cross-sectional view of the structure in IC die 100 according to some embodiments of the present disclosure. The embodiment shown in the figure is substantially similar to the embodiment of FIG. 1, except that portion 106 is only over portion 104. In such an embodiment, there is no active region 114 of portion 106, for example, or no other structural features that may be found near the active region 114, such as trench capacitor 124, etc. In some such embodiments, there may also be no TSV 120, but in other embodiments, there may be a TSV 120.

[0101] Figure 4 Is a simplified cross-sectional view of the structure in IC die 100 according to some embodiments of the present disclosure. The embodiment shown in the figure is similar to the embodiment of FIG. 1, except that the substrate 102 has two opposite sides 402 and 404, where portion 104 is on side 402 of the substrate 102 and portion 106 is on the opposite side 404 of the substrate 102. In some such embodiments, the TSV 120 may extend between the active region 108 in portion 104 and the active region 114 in portion 406.

[0102] Figure 5 Is a simplified cross-sectional view of a microelectronic component 500 according to some embodiments of the present disclosure. The microelectronic component 500 includes an IC die 100 directly attached to another IC die 502. The IC die 100 may include as in FIG. 1- Figure 4The structures described in any one or more of them. The IC die 100 can be directly attached to the IC die 502 through an interconnect (not shown for simplicity). In some embodiments, the interconnect can include an FLI as described in the previous subsection. In some embodiments, multiple IC dies 100 can be attached to the IC die 502. The IC die 100 can be embedded in the interposer 504, which includes an organic dielectric material 506 having through-dielectric vias (TDVs) 508 therein. The TDV 508 can include copper. Examples of the organic dielectric material 506 include molding compounds and epoxy-based materials with fillers. The IC die 510 can be directly attached to the side of the IC die 502 opposite to the IC die 100. In some embodiments, the interposer 504 can be directly attached to the package substrate 512 through SLI or mid-level interconnect (MLI). MLI can be substantially similar to SLI except that MLI is smaller in size than SLI. In other embodiments, the interposer 504 can be directly attached to the motherboard. Note that various other structural details (e.g., redistribution layers, interconnects, etc.) are not shown for simplicity only and not by way of limitation.

[0103] In various embodiments, the IC die 502 can include network circuits (e.g., fabric, memory controller, L2 cache, etc.). In some embodiments, the TDV 508 can be conductively coupled to SOC circuits and peripheral interconnect (PHY) circuits disposed along the periphery of the IC die 502. In various embodiments, the IC die 510 can include computing circuits (e.g., graphics processing unit (GPU), central processing unit (CPU), etc.). In various embodiments, the IC die 100 can include a high-capacity tightly-coupled high-speed cache DRAM (TCCD) circuit having more DRAM circuits than SRAM circuits; in other embodiments, the IC die 100 can include a high-bandwidth TCCD circuit having more SRAM circuits than DRAM circuits.

[0104] Figure 6 is a simplified cross-sectional view of a microelectronic component 500 according to some embodiments of the present disclosure. Note that the package substrate 512 is not shown for simplicity. The microelectronic component 500 includes one or more IC dies 100 directly attached to other IC dies 602, 604, 606, etc. through suitable interconnects (not shown). In the figure, the IC die 100 is shown as being attached only to the IC dies 604 and 606, which is only for indicating that some IC dies (e.g., 602) may not have an IC die 100 attached thereto. The IC die 100 can be included in the interposer 504, which includes an organic dielectric material 506 having TDVs 508 passing therethrough. Each of the IC dies 100 can include, as referred to in FIGS. 1 - Figure 4The described structure. In various embodiments, IC die 602 may include some type of circuitry, such as a CPU, IC die 604 may include other types of circuitry, such as a SOC, and IC die 606 may include still other types of circuitry, such as a GPU. In some embodiments, IC die 100 may include a high-capacity TCCD circuit.

[0105] Figure 7A is a simplified cross-sectional view of a microelectronic component 500 in accordance with some embodiments of the present disclosure. Note that for ease of illustration, the package substrate 512 is not shown. The microelectronic component 500 includes one or more IC dies 100 directly attached to another IC die 702 via suitable interconnects (not shown). Other IC dies 704 and 706 may also be attached to IC die 702. The IC dies 100, 704, and 706 may be disposed in an interposer 504 that includes an organic dielectric material 506 having a TDV 508 therethrough. Each of the IC dies 100 may include the structure as described in any one or more of FIGS. 1- Figure 4 any one or more of those described. In various embodiments, IC die 702 may include some type of circuitry, such as a GPU, IC die 704 may include other types of circuitry, such as PHY circuitry, and IC die 706 may include still other types of circuitry, such as a SOC. In some embodiments, IC die 100 may include a high-capacity TCCD circuit.

[0106] Figure 7B is a simplified cross-sectional view of a microelectronic component 500 in accordance with some embodiments of the present disclosure. Note that for ease of illustration only, the package substrate 512 is not shown. The microelectronic component 500 is substantially similar to Figure 7A the embodiment, except that the IC die 100 includes (or is replaced with) a stack of similar IC dies 100 that are arranged one on top of the other. In some embodiments, IC die 100 may include a high-capacity TCCD circuit. Each of the IC dies 100 may include the structure as described in any one or more of FIGS. 1- Figure 4 any one or more of those described. The stack of IC dies 100 may be assembled together in the interposer 504 to replace a single IC die among the IC dies 100. The stack of IC dies 100 may provide increased capacity in those applications where more capacity is desired. Over a wide range of embodiments, any number of IC dies 100 may be included in the stack according to specific needs.

[0107] Figure 8is a simplified cross-sectional view of a microelectronic component 500 in accordance with some embodiments of the present disclosure. Note that for ease of illustration only, the package substrate 512 is not shown. The microelectronic component 500 includes an IC die 802 having an IC die 100 and another IC die 804 coupled on one side and yet another IC die 806 coupled on the opposite side. Each of the IC dies 100, 804, and / or 806 may include a stack of IC dies having similar functions. In some embodiments, the IC die 802 may include a textured (e.g., network) circuit, the IC die 804 may include a PHY circuit or a SOC circuit, and the IC die 806 may include a computing circuit (e.g., CPU, GPU). The IC die 100 and the IC die 804 may be embedded in an organic dielectric material 506 in an interposer 504. Each of the IC dies 100 may include a structure as described in any one or more of FIGS. 1- Figure 4 Any of the structures described in one or more of the foregoing. Structures 808 and 810 may be disposed on opposite sides (e.g., bottom and top, respectively) of the component to facilitate providing power to the IC dies 804 and 806 substantially independently. For example, power may be delivered from the bottom structure 808 to the IC die 804 through the TDV 508 and the IC die 802, while power may be delivered independently to the IC die 806 through the top structure 810. The structures 808 and 810 may include printed circuit boards having power delivery networks associated therewith, including inductors, voltage regulators, and power supplies, as appropriate. In some embodiments, providing power to the computing circuit in the IC die 806 through the structure 810 proximate thereto may be more efficient than providing power through a TSV or other conductive structures in the IC die 802.

[0108] Figure 9 is a simplified cross-sectional view of a microelectronic component 500 in accordance with some embodiments of the present disclosure. The microelectronic component 500 includes an IC die 902 coupled to a package substrate 512. An IC die 904 may be coupled to the IC die 902 on a side opposite the package substrate 512. The IC die 100 may be coupled to the IC die 904 to form a stack of IC dies. In various embodiments, the IC die 904 may include a graphics or computing circuit and a memory controller circuit. The IC die 902 may include a textured circuit that facilitates communication coupling between different stacks of IC dies. Each of the IC dies 100 may include a structure as described in any one or more of FIGS. 1- Figure 4 Any of the structures described in one or more of the foregoing. Such embodiments differ from the embodiments shown in reference Figures 5 - 8 because the IC dies 904 and 100 are coupled to only one side rather than both sides of the IC die 902. Thus, in such embodiments, the IC die 100 may not be disposed in an interposer but may be directly attached to other IC dies, such as the IC die 904.

[0109] Figure 10 is a simplified cross-sectional view of a microelectronic component 500 in accordance with some embodiments of the present disclosure. Note that the package substrate 512 is not shown for ease of illustration only. The microelectronic component 500 is substantially similar to Figure 9 the embodiments of, except that the IC die 100 (and / or its stack) is directly attached to the IC die 1002 including the textured circuitry. In some embodiments, the IC die 100 may include high-bandwidth TCCD circuitry. Each of the IC dies 100 may include the structures as described in any one or more of FIGS. 1 - Figure 4 Any one of which. The IC die 1004 including, for example, graphics or computing circuitry and memory controller circuitry may be disposed adjacent to the IC die 100. Such a configuration may provide heat transfer advantages, for example, by directly attaching a heat sink to the IC die 1004 on the respective side opposite to the IC die 1002.

[0110] Figure 11 is a simplified cross-sectional view of a microelectronic component 500 in accordance with some embodiments of the present disclosure. Note that the package substrate 512 is not shown for ease of illustration only. The microelectronic component 500 is substantially similar to Figure 10 the embodiments of, except that the IC die 100 (and / or its stack) is placed towards the middle region of the IC die 1102, away from the peripheral region. The IC die 1104 may be coupled to the peripheral region. In some embodiments, the IC die 100 may include high-bandwidth TCCD circuitry. Each of the IC dies 100 may include the structures as described in any one or more of FIGS. 1 - Figure 4 Any one of which. By positioning the IC die 100 in the middle region, the IC die 1104 accessing the memory circuitry in the IC die 100 may be equidistant from the IC die 100, which may be advantageous in certain applications.

[0111] Figure 12 is a simplified cross-sectional view of a microelectronic component 500 in accordance with some embodiments of the present disclosure. Note that the package substrate 512 is not shown for ease of illustration only. The microelectronic component 500 is substantially similar to Figure 11 the embodiments of, except that the graphics, memory controller, PHY, SOC, or other such circuitry provided in the IC die 1104 may be moved to the IC die 1204, for example, as circuitry 1206 along the peripheral region of the IC die 1204. The IC die 100 (and / or its stack) may be attached to the IC die 1204 and may be conductively coupled to the circuitry 1206 through suitable conductive paths in the IC die 1204. In some embodiments, the IC die 100 may include high-capacity TCCD circuitry. Each of the IC dies 100 may include the structures as described in any one or more of FIGS. 1 - Figure 4any one or more of the structures described above.

[0112] Figure 13 is a simplified cross-sectional view of a microelectronic component 500 according to some embodiments of the present disclosure. Note that for ease of illustration only, the package substrate 512 is not shown. The microelectronic component 500 may include an interposer 504 to which various IC dies 1302, 1304, 1306, etc. are attached. The IC die 100 may be coupled to one or more of the IC dies 1302 - 1306 on the respective sides of the IC dies 1302 - 1306 opposite the interposer 504. Some of the IC dies 1302 - 1306 (such as the IC die 1302 shown in the figure) may not have any IC die 100 coupled thereto. The interposer 504 may be attached to a package substrate 512 (not shown) on the side of the interposer 504 opposite the IC dies 1302 - 1306. The IC die 100 may include a high-capacity TCCD circuit. Each of the IC dies 100 may include the structures described in reference to FIGS. 1 - Figure 4 any one or more of the structures described above. In various embodiments, one or more of the IC dies 1302 - 1306 may include various circuits, such as computing circuits, graphics circuits, and SOC circuits.

[0113] In various embodiments, any of the features discussed with reference to any one of FIGS. 1 - 13 herein may be combined with any other feature to form a package having one or more IC dies as described herein. For example, some microelectronic components on a circuit board may conform to the structures shown and described in reference to Figures 9 - 13 and some other microelectronic components on the circuit board may conform to the structures shown and described in reference to Figures 5 - 8 as shown. The above describes some such combinations, but in various embodiments, further combinations and modifications are possible. Within the broad scope of the embodiments, the various different embodiments described in different figures may be appropriately combined based on specific requirements.

[0114] Example Method

[0115] Figure 14 is a schematic flow chart showing various operations 1400 that may be associated with manufacturing the IC die 100 according to some embodiments of the present disclosure. At 1402, one or more memory circuits may be provided to the wafer. In various embodiments, the memory circuits and the structures on the wafer may correspond to FIGS. 1 - Figure 4portion 104. At 1404, at least one of the active region 114, the back-end region 116, and / or the TSV 120 can be formed adjacent to, surrounding, or near portion 104. Such a structure formed in operation 1404 can correspond to FIG. 1- Figure 4 portion 106. Thus, a composite wafer can be produced having two different regions corresponding to portions 104 and 106. At 1406, the composite wafer can be diced into custom memory chips, each of the custom memory chips corresponding to an IC die 100 as described in one or more of FIGS. 1- Figure 4 In 1408, the custom memory chips (i.e., IC dies 100) can be assembled into the microelectronic component 500 together with logic and texture layers as described in any one or more of the references Figures 5 - 13 The assembly can include forming appropriate interconnections (e.g., FLI, SLI, etc.) between the various components of the microelectronic component 500. Compared to creating high-bandwidth and / or high-capacity memory circuits individually and / or separately in different IC dies, some such embodiments can facilitate the creation of custom memory chips assembled in a microelectronic component and provide various functional advantages, including high-bandwidth memory circuits, high-capacity memory circuits, etc., in a single IC die at a lower or more efficient manufacturing cost.

[0116] Although Figure 14 the various operations are shown performed in a particular order, this is merely illustrative, and the operations discussed herein can be reordered and / or repeated as appropriate. Additionally, additional processes not shown can be performed without departing from the scope of the present disclosure. Further, the various operations discussed herein Figure 14 can be modified in accordance with the present disclosure to manufacture other ones of the IC die 100 and / or the microelectronic component 500 disclosed herein. Although each of the various operations is shown Figure 14 once in

[0117] Additionally, Figure 14The operations shown may be combined or may include more details than described. For example, suitable modifications to the operations may be made without departing from the scope of the present disclosure for IC dies that do not have a semiconductor substrate but are fabricated on other materials such as glass or ceramic materials. Additionally, the various operations shown and described may also include other manufacturing operations related to other components of the microelectronic assemblies described herein, or may include any device fabricated with the IC die and / or microelectronic assembly as described herein. For example, operations not shown in the figures may include various cleaning operations, additional surface planarization operations, operations for surface roughening, operations for including barrier and / or adhesion layers as needed, and / or operations for incorporating the microelectronic assembly described herein into an IC component, computing device, or any desired structure or device, or for combining the microelectronic assembly described herein with an IC component, computing device, or any desired structure or device.

[0118] Example Devices and Components

[0119] The packages disclosed herein (e.g., any of the embodiments shown in FIGS. 1 - Figure 14 any of the embodiments shown or any other embodiments described herein) may be included in any suitable electronic component. Figures 15 - 17 Various examples of packages, components, and devices are shown that may be used with or include any of the IC packages disclosed herein.

[0120] Figure 15 FIG. is a side cross - sectional view of an example IC package 2200 that may include an IC package according to any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a SIP.

[0121] As shown, the package substrate 2252 may be formed of an insulator (e.g., ceramic, stacked film, epoxy film with filler particles, etc.) and may have conductive vias extending through the insulator between a first face 2272 and a second face 2274, or between different locations on the first face 2272 and / or between different locations on the second face 2274. These conductive vias may take the form of any interconnect structure including lines and / or vias.

[0122] The package substrate 2252 may include conductive contacts 2263 that are coupled to the conductive vias 2262 through the package substrate 2252 to allow the circuitry within the die 2256 and / or the interposer 2257 to be electrically coupled to each of the conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).

[0123] The IC package 2200 may include an interposer 2257, which is coupled to a package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 shown in the figure are solder bumps, but any suitable first-level interconnects 2265 may be used, such as solder bumps, solder pillars, or bond wires.

[0124] The IC package 2200 may include one or more dies 2256 that are coupled to the interposer 2257 via conductive contacts 2254 of the die 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive paths (not shown) through the interposer 2257, thereby allowing the circuitry within the die 2256 to be electrically coupled to each of the conductive contacts 2261 (or to other devices, not shown, included in the interposer 2257). The first-level interconnects 2258 shown in the figure are solder bumps, but any suitable first-level interconnects 2258 may be used, such as solder bumps, solder pillars, or bond wires. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., metal) that serves as an interface between different components; the conductive contact may be recessed in the surface of the component, flush with the surface of the component, or extend away from the surface of the component, and may take any suitable form (e.g., a conductive pad or socket).

[0125] In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257, surrounding the first-level interconnects 2265, and a molding 2268 may be disposed to surround the die 2256 and the interposer 2257 and contact the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the molding 2268. Example materials that may be used for the underfill material 2266 and the molding 2268 are epoxy resins, as appropriate. A second-level interconnect 2270 may be coupled to the conductive contact 2264. The second-level interconnect 2270 shown in the figure is a solder ball (e.g., for a ball grid array (BGA) arrangement), but any suitable second-level interconnect 2270 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnect 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and as discussed below with reference to Figure 16 discussed.

[0126] In various embodiments, any of the die 2256 can be the IC die 100 or the microelectronic component 500 as described herein. In embodiments where the IC package 2200 includes multiple die 2256, the IC package 2200 can be referred to as a multi-chip package (MCP). The die 2256 can include circuitry for performing any desired function. For example, in addition to one or more of the die 2256 being the IC die 100 or the microelectronic component 500 as described herein, one or more of the die 2256 can be a logic die (e.g., a silicon-based die), one or more of the die 2256 can be a memory die (e.g., HBM), etc. In some embodiments, any of the die 2256 can be implemented as discussed with reference to any of the previous figures. In some embodiments, at least some of the die 2256 may not include the implementation as described herein.

[0127] Although the IC package 2200 shown in the figures is a flip-chip package, other packaging architectures can be used. For example, the IC package 2200 can be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 can be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two die 2256 are shown in the IC package 2200, the IC package 2200 can include any desired number of die 2256. The IC package 2200 can include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252, or on either side of the interposer 2257. More generally, the IC package 2200 can include any other active or passive components known in the art.

[0128] In some embodiments, the IC package 2200 does not include an interposer 2257; instead, the die 2256 can be directly coupled to the conductive contacts 2263 at the first side 2272 through first-level interconnects 2265.

[0129] Figure 16is a cross-sectional side view of an IC device assembly 2300 that can include components having one or more IC dies 100 or microelectronic components 500, according to any embodiment disclosed herein. The IC device assembly 2300 includes a number of components disposed on a circuit board 2302, which can be, for example, a motherboard. The IC device assembly 2300 includes components disposed on a first side 2340 of the circuit board 2302 and on an opposite second side 2342 of the circuit board 2302; generally, components can be disposed on one or both sides 2340 and 2342. In particular, any suitable component among the components of the IC device assembly 2300 can include any IC die 100 or microelectronic component 500 of one or more IC dies 100 or microelectronic components 500 according to any embodiment of the embodiments disclosed herein; for example, any IC package in the IC packages discussed below with reference to the IC device assembly 2300 can take the form of any embodiment of the IC package 2200 discussed above with reference to Figure 15 and described in any embodiment of the embodiments of the IC package 2200 discussed above.

[0130] In some embodiments, the circuit board 2302 can be a PCB that includes a plurality of metal layers separated from each other by insulator layers and interconnected by conductive vias. Any one or more of the metal layers can be formed in a desired circuit pattern to route electrical signals (optionally in combination with other metal layers) between components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 can be a non-PCB package substrate.

[0131] As shown, in some embodiments, the IC device assembly 2300 can include an on-interposer package structure 2336 coupled to the first side 2340 of the circuit board 2302 by a coupling component 2316. The coupling component 2316 can electrically and mechanically couple the on-interposer package structure 2336 to the circuit board 2302 and can include solder balls (as shown), male and female parts of a socket, an adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0132] The on-interposer package structure 2336 can include an IC package 2320 coupled to an interposer 2304 by a coupling component 2318. Depending on the desired function, the coupling component 2318 can take any suitable form, such as the forms discussed above with reference to the coupling component 2316. In some embodiments, the IC package 2320 can be or include the IC package 2200, for example, as described above with reference to Figure 15 and described. In some embodiments, the IC package 2320 can include at least one microelectronic component 500 as described herein. The IC die 100 or microelectronic component 500 is not specifically shown in the figure so as not to obscure the drawings.

[0133] Although a single IC package 2320 is shown in the figure, multiple IC packages can be coupled to the interposer 2304; in fact, additional interposers can be coupled to the interposer 2304. The interposer 2304 can provide an intermediate package substrate for bridging the circuit board 2302 and the IC package 2320. Generally, the interposer 2304 can redistribute connections to a wider pitch or reroute connections to different connections. For example, the interposer 2304 can couple the IC package 2320 to the BGA of the coupling component 2316 to couple to the circuit board 2302.

[0134] In the embodiment shown in the figure, the IC package 2320 and the circuit board 2302 are attached to opposite sides of the interposer 2304. In other embodiments, the IC package 2320 and the circuit board 2302 can be attached to the same side of the interposer 2304. In some embodiments, three or more components can be interconnected through the interposer 2304.

[0135] The interposer 2304 can be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or a polymeric material such as polyimide. In some implementations, the interposer 2304 can be formed of alternative rigid or flexible materials, which can include the same materials used in semiconductor substrates described above, such as silicon, germanium, and other group III-V materials, as well as group IV materials. The interposer 2304 can include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. The interposer 2304 can also include embedded devices 2314, including passive devices and active devices. Such devices can include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and storage devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, can also be formed on the interposer 2304. The on-interposer package structure 2336 can take the form of any on-interposer package structure known in the art.

[0136] In some embodiments, the IC device assembly 2300 can include an IC package 2324 coupled to the first surface 2340 of the circuit board 2302 through a coupling component 2322. The coupling component 2322 can take the form of any of the embodiments discussed above with reference to the coupling component 2316, and the IC package 2324 can take the form of any of the embodiments discussed above with reference to the IC package 2320.

[0137] In some embodiments, the IC device assembly 2300 can include a package - on - package structure 2334 coupled to the second side 2342 of the circuit board 2302 via a coupling component 2328. The package - on - package structure 2334 can include an IC package 2326 and an IC package 2332 coupled together via a coupling component 2330 such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 can take the form of any of the embodiments of the coupling component 2316 discussed above, and the IC package 2326 and / or 2332 can take the form of any of the embodiments of the IC package 2320 discussed above. The package - on - package structure 2334 can be configured according to any package - on - package structure known in the art.

[0138] Figure 17 is a block diagram of an example computing device 2400 that can include one or more components having one or more IC packages according to any of the embodiments disclosed herein. For example, any suitable component among the components of the computing device 2400 can include a microelectronic component (e.g., 100) according to any of the embodiments disclosed herein. In another example, any one or more components of the computing device 2400 can include any embodiment of the IC package 2200 (e.g., as Figure 15 shown). In yet another example, any one or more components of the computing device 2400 can include the IC device assembly 2300 (e.g., as Figure 16 shown).

[0139] Several components are shown in the figure as being included in the computing device 2400, but any one or more of these components can be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the computing device 2400 can be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single SOC die.

[0140] Additionally, in various embodiments, the computing device 2400 can exclude one or more components shown in the figure, but the computing device 2400 can include interface circuitry for coupling to one or more components. For example, the computing device 2400 can exclude the display device 2406, but can include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 2406 can be coupled. In another set of examples, the computing device 2400 can exclude the audio input device 2418 or the audio output device 2408, but can include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 2418 or the audio output device 2408 can be coupled.

[0141] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory. The processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing device. The computing device 2400 may include a memory 2404, which may itself include one or more memory devices, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard disk drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. The memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0142] In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured to manage wireless communications for transmitting data to and from the computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may transmit data by using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0143] The communication chip 2412 can implement any wireless standard or protocol among a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), LTE project, and any modifications, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16 compliant broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, which is an acronym representing Worldwide Interoperability for Microwave Access, and is a certification mark for products that have passed the IEEE 802.16 standard's conformance and interoperability tests. The communication chip 2412 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 2412 can operate according to GSM Enhanced Data rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher. In other embodiments, the communication chip 2412 can operate according to other wireless protocols. The computing device 2400 can include an antenna 2422 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0144] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 can include multiple communication chips. For example, a first communication chip 2412 can be dedicated to short-range wireless communication, such as Wi-Fi or Bluetooth, and a second communication chip 2412 can be dedicated to long-range wireless communication, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 2412 can be dedicated to wireless communication, and the second communication chip 2412 can be dedicated to wired communication.

[0145] The computing device 2400 may include a battery / power circuitry 2414. The battery / power circuitry 2414 may include one or more energy storage devices (e.g., a battery or a capacitor) and / or circuitry for coupling components of the computing device 2400 to an energy source (e.g., AC line power) separate from the computing device 2400.

[0146] The computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as described above). The display device 2406 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0147] The computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry, as described above). The audio output device 2408 may include any device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0148] The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as described above). The audio input device 2418 may include any device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., an instrument having a Musical Instrument Digital Interface (MIDI) output).

[0149] The computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as described above). The GPS device 2416 may communicate with a satellite-based system and may receive the location of the computing device 2400, as is known in the art.

[0150] The computing device 2400 may include other output devices 2410 (or corresponding interface circuitry, as described above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0151] The computing device 2400 may include other input devices 2420 (or corresponding interface circuitry, as described above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0152] The computing device 2400 can have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, smartphone, mobile Internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 can be any other electronic device that processes data.

[0153] Selected Examples

[0154] Example 1 provides a microelectronic component (e.g., 500, Figure 9 ), comprising: a first IC die (e.g., 100, FIG. 1) having a first memory circuit and a second memory circuit; a second IC die (e.g., 902); a third IC die (e.g., 904); and a package substrate (e.g., 512), wherein: the second IC die is between the first IC die and the package substrate, the first IC die includes: a first portion (e.g., 104) including a first active region (e.g., 108) and a first back-end region (e.g., 110) in contact with the first active region; and a second portion (e.g., 106) including a second active region (e.g., 114) and a second back-end region (e.g., 116) in contact with the second active region, the second portion being surrounded by the first portion in a plan view, the first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region includes transistors that are larger than the transistors in the second active region, and the first back-end region includes conductive traces (e.g., 112) having a pitch (e.g., 126) that is larger than the pitch of the conductive traces (e.g., 118) in the second back-end region.

[0155] Example 2 provides the microelectronic component according to Example 1, wherein: the first portion is configured to operate at a speed in a range between 60 nanoseconds and 100 nanoseconds, and the second portion is configured to operate at a speed in a range between 20 nanoseconds and 50 nanoseconds.

[0156] Example 3 provides the microelectronic component according to Example 1, wherein the first memory circuit and the second memory circuit are DRAM circuits.

[0157] Example 4 provides the microelectronic component according to any one of Examples 1-3, wherein: the third IC die is between the first IC die and the second IC die.

[0158] Example 5 provides a microelectronic component according to any one of Examples 1-4, wherein: the first IC die comprises a plurality of stacked first IC dies, and each of the first IC dies in the plurality of stacked IC dies has the first memory circuit and the second memory circuit.

[0159] Example 6 provides a microelectronic component according to Example 5, wherein the number of stacked first IC dies is between 2 and 8.

[0160] Example 7 provides a microelectronic component according to any one of Examples 1-6, wherein: the second IC die comprises a network circuit, and the third IC die comprises one or more computing circuits.

[0161] Example 8 provides a microelectronic component according to any one of Examples 1-7, wherein (for example, Figure 13 ): an organic dielectric material (e.g., 506) is between the second IC die and the package substrate, and a TDV (e.g., 120) through the organic dielectric material conductively couples the second IC die (e.g., 1304) and the package substrate.

[0162] Example 9 provides a microelectronic component according to any one of Examples 1-7, wherein (for example, Figure 10 、 Figure 11 ): the first IC die is coupled to the second IC die (e.g., 1002), the third IC die (e.g., 1004) is adjacent to the first IC die, and the third IC die is coupled to the second IC die.

[0163] Example 10 provides a microelectronic component according to any one of Examples 1-7, wherein (for example, Figure 12 ): the third IC die comprises another one of the first memory circuits and another one of the second memory circuits in a structure substantially similar to the first IC die, and the third IC die is between the first IC die and the second IC die.

[0164] Example 11 provides a microelectronic component according to Example 10, wherein: the second IC die comprises a network circuit (e.g., 1202), a system-on-chip circuit (e.g., 1204), and a peripheral interface circuit (e.g., 1206).

[0165] Example 12 provides an IC structure (e.g., 100, Figure 1A), comprising: a substrate (e.g., 102) comprising a semiconductor material; a first portion (e.g., 104) comprising a first active region (e.g., 108) and a first back-end region (e.g., 110); and a second portion (e.g., 106) comprising a second active region (e.g., 114) and a second back-end region (e.g., 116), wherein: the first portion contacts the second portion along an interface (e.g., 107), the first active region and the second active region are in the substrate, the first active region comprises transistors that are larger than the transistors in the second active region, and the first back-end region comprises conductive traces (e.g., 112) having a pitch (e.g., 126) that is greater than the pitch of the conductive traces (e.g., 118) in the second back-end region, and the first portion and the second portion comprise DRAM circuits.

[0166] Example 13 provides the IC structure according to Example 12, wherein the transistors in the first active region and the conductive traces in the first back-end region are part of one or more memory circuits.

[0167] Example 14 provides the IC structure according to any one of Examples 12-13, wherein: the first back-end region comprises a first number of metal layers, the second back-end region comprises a second number of metal layers, and the first number is less than the second number.

[0168] Example 15 provides the IC structure according to any one of Examples 12-14, wherein: the first active region does not contain any TSVs (e.g., 120) passing through it, and the second active region comprises one or more TSVs passing through it.

[0169] Example 16 provides the IC structure according to Example 15, wherein the TSV extends through the thickness of the substrate.

[0170] Example 17 provides the IC structure according to any one of Examples 12-16, wherein: the first back-end region does not contain MIM capacitors (e.g., 122), and the second back-end region comprises MIM capacitors.

[0171] Example 18 provides the IC structure according to any one of Examples 12-17, wherein: the first active region does not contain trench capacitors (e.g., 124), and the second active region comprises trench capacitors.

[0172] Example 19 provides the IC structure according to any one of Examples 12-18, further comprising an interconnect (e.g., 130) configured to couple to at least one of the following: (1) another IC structure, (2) an interposer, or (3) a package substrate.

[0173] Example 20 provides an IC structure according to Example 19, further including a layer (e.g., 132) that includes an organic dielectric material and is adjacent to the interconnect.

[0174] Example 21 provides an IC structure according to any one of Examples 12 - 20, wherein: the first back - end region includes a first inorganic dielectric material, the second back - end region includes a second inorganic dielectric material, and the first inorganic dielectric material is different from the second inorganic dielectric material.

[0175] Example 22 provides an IC structure according to any one of Examples 12 - 21, wherein the second back - end region also extends over the first back - end region.

[0176] Example 23 provides an IC structure according to any one of Examples 12 - 21, wherein (e.g., Figure 1B ) in a plan view, a first part is surrounded by a second part.

[0177] Example 24 provides an IC structure according to any one of Examples 12 - 21, wherein (e.g., Figure 1C ) in a plan view, a second part is surrounded by a first part.

[0178] Example 25 provides an IC structure (e.g., 100, Figure 3 ) including: a substrate (e.g., 102) that includes a semiconductor material; a first part (e.g., 104) that includes an active region (e.g., 108) and a first back - end region (e.g., 110); and a second part (e.g., 106) that includes a second back - end region (e.g., 116), wherein: the second back - end region has a first side and an opposite second side, the first back - end region contacts the first side of the second back - end region, the interconnect is on the second side of the second back - end region, the first back - end region includes conductive traces (e.g., 112) having a pitch (e.g., 126) greater than the pitch of the conductive traces (e.g., 118) in the second back - end region, and the first part and the second part include DRAM circuits.

[0179] Example 26 provides an IC structure according to Example 25, wherein: the first back - end region has a first number of metal layers, the second back - end region has a second number of metal layers, and the first number satisfies at least one of the following: (1) greater than the second number, (2) equal to the second number, or (3) less than the second number.

[0180] Example 27 provides an IC structure according to any one of Examples 25 - 26, wherein: the conductive traces in the first back - end region are thicker than the conductive traces in the second back - end region.

[0181] Example 28 provides an IC structure according to any one of Examples 25 - 27, wherein: the first back - end region has a first dielectric material, the second back - end region has a second dielectric material, and the first dielectric material is different from the second dielectric material.

[0182] Example 29 provides an IC structure according to any one of Examples 25 - 28, wherein: the interconnect is in a redistribution layer, and the redistribution layer contacts the second side of the second back - end region.

[0183] Example 30 provides an IC structure according to any one of Examples 25 - 29, wherein (for example, Figure 1B ) in a plan view, the first portion is surrounded by the second portion.

[0184] Example 31 provides an IC structure according to any one of Examples 25 - 29, wherein (for example, Figure 1C ) in a plan view, the second portion is surrounded by the first portion.

[0185] Example 32 provides an IC structure (for example, 100, Figure 4 ) including: a substrate (for example, 102) including a semiconductor material, the substrate having a first side (for example, 402) and an opposite second side (for example, 404); a first portion (for example, 104) including a first active region (for example, 108) and a first back - end region (for example, 110); and a second portion (for example, 106) including a second active region and a second back - end region (for example, 116), wherein: the first portion is on the first side of the substrate, the second portion is on the second side of the substrate, the first active region includes transistors, the transistors being larger than the transistors in the second active region, and the first back - end region includes conductive traces (for example, 112), the conductive traces having a pitch (for example, 126) larger than the pitch of the conductive traces (for example, 118) in the second back - end region, and the first portion and the second portion include DRAM circuits.

[0186] Example 33 provides an IC structure according to Example 32, further including: a TSV passing through the substrate, the TSV conductively coupling the first portion and the second portion.

[0187] Example 34 provides an IC structure according to any one of Examples 32 - 33, further including: a first interconnect coupled to the first portion and a second interconnect coupled to the second portion, wherein the first interconnect has a larger pitch than the second interconnect.

[0188] Example 35 provides an IC structure according to Example 34, further comprising: a first redistribution layer in contact with the first portion and a second redistribution layer in contact with the second portion, wherein: the first interconnect is located in the first redistribution layer, and the second interconnect is located in the second redistribution layer.

[0189] Example 36 provides an IC structure according to any one of Examples 32 - 35, wherein: the first back-end region has a first number of metal layers, the second back-end region has a second number of metal layers, and the first number satisfies at least one of the following: (1) greater than the second number, (2) equal to the second number, or (3) less than the second number.

[0190] Example 37 provides an IC structure according to any one of Examples 32 - 36, wherein (for example, Figure 1B ) in a plan view, the first portion is surrounded by the second portion.

[0191] Example 38 provides an IC structure according to any one of Examples 32 - 36, wherein (for example, Figure 1C ) in a plan view, the second portion is surrounded by the first portion.

[0192] The above description of the embodiments of the present disclosure (including what is described in the abstract) is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. While specific embodiments and examples of the present disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure as will be recognized by those skilled in the relevant art.

Claims

1. A microelectronic component, comprising: A first integrated circuit (IC) die having a first memory circuit and a second memory circuit; A second IC die; A third IC die; And A package substrate, Wherein: The second IC die is between the first IC die and the package substrate, The first IC die includes: A first portion including a first active region and a first back-end region in contact with the first active region; and A second portion including a second active region and a second back-end region in contact with the second active region, The second portion is surrounded by the first portion, The first memory circuit is in the first portion, The second memory circuit is in the second portion, The first active region includes transistors that are larger than the transistors in the second active region, and The first back-end region includes conductive traces having a pitch greater than the pitch of the conductive traces in the second back-end region.

2. The microelectronic component according to claim 1, wherein: The first portion is configured to operate at a speed in the range between 60 nanoseconds and 100 nanoseconds, and The second portion is configured to operate at a speed in the range between 20 nanoseconds and 50 nanoseconds.

3. The microelectronic component according to claim 2, wherein, The first memory circuit and the second memory circuit are dynamic random access memory (DRAM) circuits.

4. The microelectronic component according to any one of claims 1-3, wherein: The third IC die is between the first IC die and the second IC die.

5. The microelectronic component according to any one of claims 1-4, wherein: The first IC die includes a plurality of stacked first IC dies, and each first IC die in the plurality of stacked IC dies has the first memory circuit and the second memory circuit.

6. The microelectronic component according to any one of claims 1-5, wherein: An organic dielectric material is between the second IC die and the package substrate, and A through-dielectric via (TDV) passing through the organic dielectric material conductively couples the second IC die and the package substrate.

7. The microelectronic component according to any one of claims 1-5, wherein: The first IC die is coupled to the second IC die, The third IC die is adjacent to the first IC die, and The third IC die is coupled to the second IC die.

8. The microelectronic component according to any one of claims 1-5, wherein: The third IC die includes another one of the first memory circuit and another one of the second memory circuit in a structure substantially similar to the first IC die, and The third IC die is between the first IC die and the second IC die.

9. The microelectronic component according to claim 8, wherein: The second IC die includes a network circuit, a system-on-chip circuit, and a peripheral interface circuit.

10. An IC structure, comprising: A substrate including a semiconductor material; A first portion including a first active region and a first back-end region; And A second portion including a second active region and a second back-end region, Wherein: The first part contacts the second part along an interface, The first active region and the second active region are in the substrate, The first active region includes transistors, and the transistors are larger than the transistors in the second active region, The first back-end region includes conductive traces, and the pitch of the conductive traces is greater than the pitch of the conductive traces in the second back-end region, and The first part and the second part include DRAM circuits.

11. The IC structure according to claim 10, wherein, The transistors in the first active region and the conductive traces in the first back-end region are part of one or more memory circuits.

12. The IC structure according to any one of claims 10-11, wherein: The first back-end region includes a first number of metal layers, The second back-end region includes a second number of metal layers, The first number is less than the second number.

13. The IC structure according to any one of claims 10-12, wherein: The first active region does not contain any through-substrate vias (TSVs) passing through it, and The second active region includes one or more TSVs passing through it.

14. The IC structure according to any one of claims 10-13, wherein: The first back-end region does not contain metal-insulator-metal (MIM) capacitors, and The second back-end region includes MIM capacitors.

15. The IC structure according to any one of claims 10-14, wherein: The first active region does not contain trench capacitors, and The second active region includes trench capacitors.

16. The IC structure according to any one of claims 10-15, further comprising interconnects configured to couple to at least one of the following: (1) another IC structure, (2) an interposer, or (3) a package substrate.

17. The IC structure according to claim 16, further comprising a layer including an organic dielectric material adjacent to the interconnects.

18. The IC structure according to any one of claims 10-17, wherein: The first back-end region includes a first inorganic dielectric material, The second back-end region includes a second inorganic dielectric material, and The first inorganic dielectric material is different from the second inorganic dielectric material.

19. The IC structure according to any one of claims 10-18, wherein, The second back-end region also extends over the first back-end region.

20. The IC structure according to any one of claims 10-18, wherein, The first part is surrounded by the second part.

21. The IC structure according to any one of claims 10-18, wherein, The second part is surrounded by the first part.

22. An IC structure, comprising: A substrate including semiconductor material, the substrate having a first side and an opposite second side; A first part including a first active region and a first back-end region; And A second part including a second active region and a second back-end region, Wherein: The first part is on the first side of the substrate, The second part is on the second side of the substrate, The first active region includes transistors, and the transistors are larger than the transistors in the second active region, The first back-end region includes conductive traces having a pitch greater than the pitch of the conductive traces in the second back-end region, and the first portion and the second portion include DRAM circuits.

23. The IC structure according to claim 22 further comprises: Through-silicon vias (TSVs) passing through the substrate, the TSVs electrically coupling the first portion and the second portion.

24. The IC structure according to any one of claims 22-23 further includes a first interconnect coupled to the first portion and a second interconnect coupled to the second portion, wherein, The first interconnect has a pitch greater than the pitch of the second interconnect.

25. The IC structure according to claim 24, further comprising a first redistribution layer in contact with the first portion and a second redistribution layer in contact with the second portion, wherein: the first interconnect is in the first redistribution layer, and the second interconnect is in the second redistribution layer.

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