Mask layout design, mask preparation method and semiconductor structure forming method

Abstract

The invention discloses a mask layout design and mask preparation method and a semiconductor structure forming method, and the mask layout design method comprises the steps: generating a first light-transmitting layout according to an initial layout, the first light-transmitting layout comprises a plurality of plug patterns, and the positions of the plug patterns in the first light-transmitting layout are the same as the positions of initial plug patterns in the initial layout; a second light-transmitting layout is generated, the second light-transmitting layout comprises a pattern area, the shape of the pattern area and the position of the pattern area in the second light-transmitting layout are the same as the shape of the second area and the position of the second area in the initial layout, and a plurality of liner layer patterns are arranged in the pattern area; the first light-transmitting layout and the second light-transmitting layout are combined to form a mask layout, the mask layout comprises a plurality of plug patterns and a plurality of liner layer patterns surrounding the plug patterns, the plug patterns and the liner layer patterns have preset pattern density, and the plug patterns and the liner layer patterns respectively form different light-transmitting areas of the mask, the process complexity is reduced, and the production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a mask layout design and mask preparation method, and a semiconductor structure formation method. Background Art

[0002] In a state where the development of very large scale integrated circuits is increasingly approaching the physical limit, three-dimensional integrated circuits, which have advantages in both physical size and cost, are an effective way to extend Moore's Law and solve advanced packaging problems. And the wafer bonding technology is one of the key technologies for three-dimensional circuit integration. In particular, the hybrid bonding technology can achieve internal interconnection of thousands of chips while bonding two wafers, which can greatly improve chip performance and save costs.

[0003] However, the existing hybrid bonding technology still needs to be further improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a mask layout design and mask preparation method, and a semiconductor structure formation method to simplify the hybrid bonding process and save production costs.

[0005] To solve the above technical problem, the technical solution of the present invention provides a mask layout design method, including: obtaining an initial layout, the initial layout including a first region and a second region surrounding the first region, the first region having a plurality of initial plug patterns, the first region and the second region having a plurality of initial liner layer patterns, one of the initial plug patterns and one of the initial liner layer patterns overlapping each other, and each of the initial plug patterns being located within the contour range of the corresponding initial liner layer pattern; generating a first light-transmitting layout according to the initial layout, the first light-transmitting layout including a plurality of plug patterns, the positions of the plug patterns in the first light-transmitting layout being the same as the positions of the initial plug patterns in the initial layout, and the shapes of the plug patterns being the same as the shapes of the initial liner layer patterns; generating a second light-transmitting layout, the second light-transmitting layout including a pattern region, the shape of the pattern region and the position of the pattern region in the second light-transmitting layout being the same as the shape of the second region and the position of the second region in the initial layout, and the pattern region having a plurality of liner layer patterns; merging the first light-transmitting layout and the second light-transmitting layout to form a mask layout, the mask layout including a plurality of plug patterns and a plurality of liner layer patterns surrounding the plug patterns, the plug patterns and the liner layer patterns having a preset pattern density.

[0006] Optionally, the method for generating the first light-transmitting layout includes: within the initial layout, identifying the initial plug patterns according to the pattern sizes; extracting a plurality of the initial plug patterns from the initial layout to obtain a first transitional layout, the first transitional layout including a plurality of the initial plug patterns, and the positions of the initial plug patterns within the first transitional layout being the same as their positions within the initial layout; enlarging the sizes of the respective initial plug patterns within the first transitional layout to form the plug patterns, and using the first transitional layout to form the first light-transmitting layout.

[0007] Optionally, the method for generating the second light-transmitting layout includes: after removing a plurality of the initial plug patterns, using the initial layout to form a second transitional layout, the second transitional layout including a plurality of the initial liner layer patterns; according to the relative positions of the plurality of the initial plug patterns and the plurality of the initial liner layer patterns within the initial layout, superposing the first light-transmitting layout and the second transitional layout, and removing the patterns that overlap with the plurality of the plug patterns from the plurality of the initial liner layer patterns, and using the plurality of the initial liner layer patterns to form a plurality of the liner layer patterns, and using the second transitional layout to form the second light-transmitting layout.

[0008] Optionally, the method for generating the second light-transmitting layout includes: according to the distribution of the plurality of the plug patterns within the first light-transmitting layout, filling a plurality of the liner layer patterns around the plurality of the plug patterns within the first light-transmitting layout, so that the plug patterns and the liner layer patterns have the preset pattern density within the first light-transmitting layout; after obtaining the plurality of the liner layer patterns, removing the plurality of the plug patterns within the first light-transmitting layout, and using the first light-transmitting layout to generate the second light-transmitting layout.

[0009] Optionally, the method for generating the first light-transmitting layout includes: within the initial layout, identifying a plurality of the initial plug patterns according to the pattern sizes; within the initial layout, identifying and using the initial liner layer patterns that have an overlapping relationship with the initial plug patterns as the plug patterns according to the pattern overlapping relationship; extracting a plurality of the plug patterns from the initial layout to obtain the first light-transmitting layout, the first light-transmitting layout including a plurality of the plug patterns, and the positions of the plurality of the plug patterns within the first light-transmitting layout being the same as the positions of the plug patterns within the initial layout.

[0010] Optionally, the method for generating the second light-transmitting layout includes: within the initial layout, identifying, according to the graphic overlapping relationship, the initial liner layer graphics that have no overlapping relationship with the initial plug graphics as the liner layer graphics; and obtaining the second light-transmitting layout according to a plurality of the liner layer graphics, where the second light-transmitting layout includes a plurality of the liner layer graphics, and the positions of the plurality of the liner layer graphics in the second light-transmitting layout are the same as the positions of the plurality of the liner layer graphics in the initial layout.

[0011] Optionally, the plurality of the initial liner layer graphics include a plurality of functional metal graphics and a plurality of dummy metal graphics, and each of the functional metal graphics overlaps with the initial plug graphics; the plurality of the dummy metal graphics include a plurality of first dummy graphics surrounding the plurality of the functional metal graphics and a plurality of second dummy graphics surrounding the plurality of the first dummy graphics.

[0012] Correspondingly, the technical solution of the present invention further provides a method for manufacturing a mask plate, including: providing a mask layout, where the mask layout includes a plurality of plug graphics and a plurality of liner layer graphics surrounding the plurality of plug graphics, and the plug graphics and the liner layer graphics have a preset graphic density; forming a mask plate by using the mask layout, where the mask plate includes a first light-transmitting area formed by using the plug graphics and a second light-transmitting area formed by using the liner layer graphics, and the light transmittance of the first light-transmitting area and the second light-transmitting area is different.

[0013] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a mask layout, where the mask layout includes a plurality of plug graphics and a plurality of liner layer graphics surrounding the plurality of plug graphics, and the plug graphics and the liner layer graphics have a preset graphic density; forming a mask plate by using the mask layout, where the mask plate includes a first light-transmitting area formed by using the plug graphics and a second light-transmitting area formed by using the liner layer graphics, and the light transmittance of the first light-transmitting area and the second light-transmitting area is different; providing a substrate; forming a device layer on the substrate, where the device layer has an electrical interconnection structure; forming a first opening and a second opening in the device layer by using the mask plate, where the first opening is patterned by using the first light-transmitting area, the second opening is patterned by using the second light-transmitting area, the depth of the first opening is greater than the depth of the second opening, and the first opening exposes a part of the electrical interconnection structure; and forming a bonding interconnection structure in the first opening and the second opening.

[0014] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0015] In the mask layout design method provided by the technical solution of the present invention, a first light-transmitting layout and a second light-transmitting layout are respectively generated according to the initial layout. The first light-transmitting layout includes a plurality of plug patterns, and the second light-transmitting layout includes a plurality of liner layer patterns. The first light-transmitting layout and the second light-transmitting layout are combined to form a mask layout. When preparing a mask according to the mask layout, the plug patterns and the liner layer patterns respectively form different light-transmitting regions. Furthermore, when performing photolithography using the mask, grooves with different depths are generated in the material to be etched. Compared with the existing single photolithography process that can only obtain grooves with the same depth, it is beneficial to reduce the process complexity and lower the production cost.

[0016] In the mask preparation method provided by the technical solution of the present invention, the formed mask includes a first light-transmitting region formed by plug patterns and a second light-transmitting region formed by liner layer patterns. The light transmittance of the first light-transmitting region and the second light-transmitting region is different. Furthermore, when performing photolithography using the mask, grooves with different depths are generated in the material to be etched. Compared with the existing single photolithography process that can only obtain grooves with the same depth ratio, it is beneficial to reduce the process complexity and lower the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of a wafer hybrid bonding structure;

[0018] Figures 2 to 4 is a schematic diagram of the structures of the steps of another wafer hybrid bonding method;

[0019] Figures 5 to 7 is a schematic flowchart of the mask layout design method according to an embodiment of the present invention;

[0020] Figures 8 to 13 is a schematic diagram of the structures of the steps of the mask layout design method according to an embodiment of the present invention;

[0021] Figures 14 to 15 is a schematic diagram of the structure of the mask according to an embodiment of the present invention;

[0022] Figures 16 to 17 is a schematic diagram of the structures of the steps of the method for forming a semiconductor structure according to an embodiment of the present invention;

[0023] Figure 18 is a schematic flowchart of the mask layout design method according to another embodiment of the present invention;

[0024] Figures 19 to 21 is a schematic diagram of the structures of the steps of the mask layout design method according to another embodiment of the present invention;

[0025] Figures 22 to 23 is a schematic flowchart of the mask layout design method according to still another embodiment of the present invention;

[0026] Figures 24 to 29 It is a schematic structural diagram of each step of a mask layout design method according to another embodiment of the present invention. Detailed implementation manners

[0027] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0028] As described in the background art, the performance of the hybrid bonding structure formed by the existing hybrid bonding technology needs to be improved urgently. Now, a wafer hybrid bonding structure is combined for illustration and analysis.

[0029] Figure 1 It is a schematic diagram of a wafer hybrid bonding structure.

[0030] Please refer to Figure 1 , a first wafer structure 100, the first wafer structure 100 includes a first substrate 101 and a first dielectric layer 102 located on the surface of the first substrate 101. A first functional metal layer 103 and a first dummy metal layer 104 are provided in the first dielectric layer 102. The first wafer structure 100 exposes the surfaces of the first functional metal layer 103 and the first dummy metal layer 104; a second wafer structure 110 bonded to the first wafer structure 100, the second wafer structure 110 includes a second substrate 111 and a second dielectric layer 112 located on the surface of the second substrate 111. A second functional metal layer 113 and a second dummy metal layer 114 are provided in the second dielectric layer 112. The second wafer structure 110 exposes the second functional metal layer 113 and the second dummy metal layer 114. The first dielectric layer 102 and the second dielectric layer 112 are bonded to each other, the first functional metal layer 103 and the second functional metal layer 113 are bonded to each other, and the first dummy metal layer 104 and the second dummy metal layer 114 are bonded to each other.

[0031] In the above structure, several first electrical interconnect layers 106 are provided in the first dielectric layer 102. The first functional metal layer 103 is electrically connected to the first interconnect layer 106 through a first conductive plug 105. Several second electrical interconnect layers 116 are provided in the second dielectric layer 112. The second functional metal layer 113 is electrically connected to the second interconnect layer 116 through a second conductive plug 115, while the first dummy metal layer 104 and the second dummy metal layer 114 do not play a substantial connection role. The first dummy metal layer 104 and the second dummy metal layer 114 are used to make the metal density on the bonding surface uniform and improve the bonding stability.

[0032] The above structure is formed by separately forming a first wafer structure 100 and a second wafer structure 200, and then bonding them using a wafer hybrid bonding process. The first functional metal layer 103, the second functional metal layer 113, and the first conductive plug 105 have different depths. The grooves where the first functional metal layer 103 and the second functional metal layer 113 are located are formed using the same lithography process, while the contact holes where the first conductive plug 105 is located require another lithography process to be formed. The two lithography processes increase the process complexity and the process cost is relatively high.

[0033] Therefore, in another embodiment, a novel mask and a method of performing lithography using the novel mask are provided. In this method, the grooves where the first functional metal layer, the second functional metal layer, and the first conductive plug are located are formed in the same lithography process. Here, the formation method of the first wafer structure is taken as an example for illustration. For details, please refer to Figures 2 to 4 .

[0034] Figures 2 to 4 is a schematic structural diagram of each step of another wafer hybrid bonding method.

[0035] Please refer to Figure 2 , a novel mask is provided. The novel mask includes a non-transmissive region I, a semi-transmissive region II, and a transmissive region III. A first wafer is provided, which includes a first substrate 131 and a first dielectric layer 132 on the surface of the first substrate 131. There are several first interconnect layers 133 in the first dielectric layer 132. A photoresist layer 134 is formed on the surface of the first dielectric layer 132. The photoresist layer 134 is exposed and developed using the novel mask to form first grooves 135 and second grooves 136 with different depths in the photoresist layer 134. The depth of the first grooves 135 is less than the depth of the second grooves 136.

[0036] Please refer to Figure 3 , using the photoresist layer 134 as a mask, etch the photoresist layer 134 at the bottom of the first grooves 135 and etch the first dielectric layer 132 at the bottoms of the first grooves 135 and the second grooves 136 until the first interconnect layers 133 are exposed, so as to form first through-holes 137 and second through-holes 138 in the first dielectric layer 132. The depth of the second through-holes 138 is greater than that of the first through-holes 137, and the bottoms of the second through-holes 138 expose the first interconnect layers 133.

[0037] Please refer to Figure 4 , remove the photoresist layer 134. A first dummy metal layer 139 is formed in the first through-holes 137. A first functional metal layer 140 is formed in the second through-holes 138.

[0038] Subsequently, the second wafer structure is formed by the same method, and the first wafer structure and the second wafer structure are bonded. In this embodiment, the grooves where the first functional metal layer, the second functional metal layer, and the first conductive plug are located are formed in the same lithography process, which simplifies the process steps and is conducive to reducing production costs.

[0039] However, as a new mask structure, there is no relevant layout design method for the novel mask.

[0040] To solve the above problems, in a mask layout design method and a mask preparation method provided by the present invention, a first light-transmitting layout and a second light-transmitting layout are respectively generated according to the initial layout. The first light-transmitting layout includes a plurality of plug patterns, and the second light-transmitting layout includes a plurality of liner layer patterns. The first light-transmitting layout and the second light-transmitting layout are combined to form a mask layout. When preparing a mask according to the mask layout, the plug patterns and the liner layer patterns respectively form different light-transmitting regions. Furthermore, when lithography is performed using the mask, grooves with different depths are generated in the material to be etched. Compared with the existing single lithography process that can only obtain grooves with the same depth, it is conducive to reducing process complexity and production costs.

[0041] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0042] Figures 5 to 7 It is a schematic flow chart of a mask layout design method according to an embodiment of the present invention.

[0043] Please refer to Figure 5 , the mask layout design method includes the following steps:

[0044] Step S201, obtain an initial layout, the initial layout includes a first region and a second region surrounding the first region. The first region has a plurality of initial plug patterns, and the first region and the second region have a plurality of initial liner layer patterns. One initial plug pattern and one initial liner layer pattern overlap each other, and each initial plug pattern is located within the contour range of the corresponding initial liner layer pattern;

[0045] Step S202, generate a first light-transmitting layout according to the initial layout. The first light-transmitting layout includes a plurality of plug patterns. The positions of the plug patterns in the first light-transmitting layout are the same as the positions of the initial plug patterns in the initial layout, and the shapes of the plug patterns are the same as the shapes of the initial liner layer patterns;

[0046] Step S203: Generate a second light-transmissive layout. The second light-transmissive layout includes a graphic area. The shape of the graphic area and the position of the graphic area in the second light-transmissive layout are the same as the shape of the second area and the position of the second area in the initial layout. There are several underlayer patterns in the graphic area.

[0047] Step S204: Merge the first light-transmissive layout and the second light-transmissive layout to form a mask layout. The mask layout includes several plug patterns and several underlayer patterns surrounding the plug patterns. The plug patterns and the underlayer patterns have a preset pattern density.

[0048] The following will be described in detail with reference to the accompanying drawings.

[0049] Figures 8 to 13 It is a schematic structural diagram of each step of a mask layout design method according to an embodiment of the present invention.

[0050] Please refer to Figure 8 and continue to refer to Figure 5 to obtain an initial layout 30. The initial layout 30 includes a first area I and a second area II surrounding the first area I. There are several initial plug patterns 300 in the first area I. There are several initial underlayer patterns 400 in the first area I and the second area II. One of the initial plug patterns 300 and one of the initial underlayer patterns 400 overlap with each other, and each of the initial plug patterns 300 is located within the contour range of the corresponding initial underlayer pattern 400.

[0051] It should be noted that the initial layout 30 can be obtained by merging an existing metal layer layout (not shown in the figure) and a plug layout (not shown in the figure). The metal layer layout includes several of the initial underlayer patterns 400. The plug layout includes several of the initial plug patterns 300. In the prior art, the metal layer layout is used to make a metal mask, and the plug layout is used to make a plug mask. The metal mask and the plug mask are respectively used to form a metal layer and a conductive plug.

[0052] In this embodiment, several of the initial liner layer patterns 400 include several functional metal patterns 401 and several dummy metal patterns 402. Each of the functional metal patterns 401 overlaps with the initial plug pattern 300. In the prior art, several of the functional metal patterns 401 are used to form a functional metal layer, and the initial plug pattern 300 is used to form a conductive plug. The conductive plug is located at the bottom of the functional metal layer and is electrically connected to the functional metal layer, serving as an actual electrical lead-out function. And several dummy metal patterns are used to form several dummy metal layers, and the several dummy metal layers do not serve as electrical lead-out functions, but are only used to make the metal density at the bonding interface in the wafer bonding process reach a preset value, improving the wafer bonding performance.

[0053] In another embodiment, several of the dummy metal patterns further include several first dummy patterns surrounding several of the functional metal patterns, and several second dummy patterns surrounding several of the first dummy patterns. In the prior art, several of the first dummy patterns are used to form a first dummy metal layer, and the first dummy metal layer is located around the functional metal layer, improving the process window for forming the functional metal layer. Several of the second dummy patterns are used to form a second dummy metal layer, and the second dummy metal layer is used to make the metal density at the bonding interface in the wafer bonding process reach a preset value, improving the wafer bonding performance.

[0054] Please continue to refer to Figure 5 , generate a first light-transmitting layout according to the initial layout 30. The first light-transmitting layout includes several plug patterns. The positions of the plug patterns in the first light-transmitting layout are the same as the positions of the initial plug pattern 300 in the initial layout 30, and the shapes of the plug patterns are the same as the shapes of the initial liner layer patterns 400.

[0055] In this embodiment, for the method of generating a first light-transmitting layout according to the initial layout 30, please refer to Figure 6 , which includes the following steps:

[0056] Step S2021, within the initial layout, identify the initial plug pattern according to the graphic size.

[0057] Step S2022, extract several of the initial plug patterns from the initial layout to obtain a first transitional layout. The first transitional layout includes several of the initial plug patterns, and the positions of the initial plug patterns in the first transitional layout are the same as the positions of the initial plug patterns in the initial layout.

[0058] Step S2023, perform an enlargement process on the sizes of the initial plug patterns in the first transitional layout to form the plug patterns, and form the first light-transmitting layout with the first transitional layout.

[0059] The method for generating the first light-transmitting layout will be described in detail below with reference to the accompanying drawings.

[0060] Please continue to refer to Figure 8 and refer to Figure 9 In the initial layout 30, according to the size of the pattern, identify the initial plug pattern 300; extract a plurality of the initial plug patterns 300 from the initial layout 30 to obtain a first transitional layout 50. The first transitional layout 50 includes a plurality of the initial plug patterns 300, and the positions of the initial plug patterns 300 in the first transitional layout 50 are the same as the positions of the initial plug patterns 300 in the initial layout 30.

[0061] Please refer to Figure 9 Enlarge the sizes of the respective initial plug patterns 300 in the first transitional layout 50 to form the plug patterns 500, and form the first light-transmitting layout 51 with the first transitional layout 50.

[0062] After the enlargement process, the size of the plug pattern 500 is greater than or equal to the size of the functional metal pattern 401 that overlaps the initial plug pattern 300 in the initial layout 30. The size of the plug pattern 500 can be adjusted according to actual needs.

[0063] In this embodiment, after the enlargement process, the size of the plug pattern 500 is equal to the size of the functional metal pattern 401 that overlaps the initial plug pattern 300 in the initial layout 30.

[0064] Please continue to refer to Figure 5 Generate a second light-transmitting layout. The second light-transmitting layout includes a graphic area. The shape of the graphic area and the position of the graphic area in the second light-transmitting layout are the same as the shape of the second area and the position of the second area in the initial layout 30, and there are a plurality of liner layer patterns in the graphic area.

[0065] In this embodiment, the method for generating the second light-transmitting layout includes the following steps:

[0066] Step S2031, after removing a plurality of the initial plug patterns, form a second transitional layout with the initial layout. The second transitional layout includes a plurality of the initial liner layer patterns;

[0067] Step S2032: According to the relative positions of a plurality of the initial plug patterns and a plurality of the initial interlayer dielectric patterns in the initial layout, superpose the first light-transmissive layout and the second transition layout on each other, and remove, from the plurality of the initial interlayer dielectric patterns, the patterns that are superposed on the plurality of the plug patterns, so as to form a plurality of the interlayer dielectric patterns from the plurality of the initial interlayer dielectric patterns, and form a second light-transmissive layout with the second transition layout.

[0068] The method for generating the second light-transmissive layout will be described in detail below with reference to the accompanying drawings.

[0069] Please refer to Figure 8 and on the basis of Figure 11 , after removing a plurality of the initial plug patterns 300, form a second transition layout 52 with the initial layout 30, and the second transition layout 52 includes a plurality of the initial interlayer dielectric patterns 400.

[0070] Please refer to Figure 12 , and continue to refer to Figure 8 , according to the relative positions of a plurality of the initial plug patterns 300 and a plurality of the initial interlayer dielectric patterns 400 in the initial layout 30, superpose the first light-transmissive layout 51 (as shown in Figure 10 ) and the second transition layout 52 (as shown in Figure 11 ), and remove, from the plurality of the initial interlayer dielectric patterns 400, the patterns that are superposed on the plurality of the plug patterns 500, so as to form a plurality of the interlayer dielectric patterns 501 from the plurality of the initial interlayer dielectric patterns 400, and form a second light-transmissive layout 53 with the second transition layout 52.

[0071] The second light-transmissive layout 53 includes a graphic area ii, and the shape of the graphic area ii and the position of the graphic area ii in the second light-transmissive layout 53 are the same as the shape of the second area II and the position of the second area II in the initial layout 30, and a plurality of the interlayer dielectric patterns 501 are provided in the graphic area ii.

[0072] Please refer to Figure 13 , combine the first light-transmissive layout 51 (as shown in Figure 10 ) and the second light-transmissive layout 53 (as shown in Figure 12 ) to form a mask layout 54, and the mask layout 54 includes a plurality of plug patterns 300 and a plurality of the interlayer dielectric patterns 501 surrounding the plug patterns 300, and the plug patterns 300 and the interlayer dielectric patterns 501 have a preset graphic density.

[0073] So far, a first light-transmitting layout 51 and a second light-transmitting layout 53 are respectively generated according to the initial layout 30. The first light-transmitting layout 51 includes a plurality of plug patterns 500, and the second light-transmitting layout 53 includes a plurality of liner layer patterns 501. The first light-transmitting layout 51 and the second light-transmitting layout 53 are combined to form a mask layout 54. When preparing a mask according to the mask layout, the plug patterns 500 and the liner layer patterns 501 respectively form different light-transmitting regions, and further, when performing photolithography using the mask, grooves with different depths are generated in the material to be etched. Compared with the existing single photolithography process that can only obtain grooves with the same depth, it is beneficial to reduce the process complexity and lower the production cost.

[0074] Figures 14 to 15 It is a schematic structural diagram of a mask according to an embodiment of the present invention.

[0075] Correspondingly, an embodiment of the present invention further provides a method for preparing a mask. Please refer to Figure 14 and Figure 15 and continue to refer to Figure 13 , Figure 15 is Figure 14 a schematic cross-sectional structure diagram along the XX1 direction in

[0076] and includes: providing a mask layout 54, the mask layout 54 includes a plurality of plug patterns 300 and a plurality of liner layer patterns 501 surrounding the plurality of plug patterns 300, and the plug patterns 300 and the liner layer patterns 501 have a preset pattern density; using the mask layout 54 to form a mask 60, the mask 60 includes a first light-transmitting region a formed by using the plug patterns 300 and a second light-transmitting region b formed by using the liner layer patterns 501, and the light transmittance of the first light-transmitting region a and the second light-transmitting region b is different.

[0077] In this embodiment, the mask 60 is used in combination with a positive photoresist, and the light transmittance of the first light-transmitting region a is greater than the light transmittance of the second light-transmitting region b. Specifically, the first light-transmitting region a can be fully light-transmitting, and the second light-transmitting region b can be semi-light-transmitting. In another embodiment, the mask can be used in combination with a negative photoresist, and the light transmittance of the first light-transmitting region is less than the light transmittance of the second light-transmitting region. Specifically, the first light-transmitting region can be semi-light-transmitting, and the second light-transmitting region can be fully light-transmitting.

[0078] It should be noted here that Figure 15 it is only used to illustrate the light transmission difference between the first light-transmitting region a and the second light-transmitting region b, and the specific structure of the mask 60 is not shown.

[0079] Figures 16 to 17 It is a schematic structural diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0080] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including:

[0081] Please continue to refer to Figure 13 , provide a mask layout 54, the mask layout 54 includes a plurality of plug patterns 300 and a plurality of liner layer patterns 501 surrounding the plurality of plug patterns 300, and the plug patterns 300 and the liner layer patterns 501 have a preset pattern density.

[0082] Please continue to refer to Figure 14 and Figure 15 , use the mask layout 54 to form a mask 60, the mask 60 includes a first light-transmitting region a formed by using the plug pattern 300 and a second light-transmitting region b formed by using the liner layer pattern 501, and the light transmittance of the first light-transmitting region a and the second light-transmitting region b is different.

[0083] Please refer to Figure 16 , provide a substrate 700; form a device layer 701 on the substrate 700, and an electrical interconnection structure 702 is provided in the device layer 701; use the mask 60 to form a first opening 703 and a second opening 704 in the device layer 701, the first opening 703 is patterned by using the first light-transmitting region a, the second opening 704 is patterned by using the second light-transmitting region b, the depth of the first opening 703 is greater than the depth of the second opening 704, and the first opening 703 exposes part of the electrical interconnection structure.

[0084] Please refer to Figure 17 , form a bonding interconnection structure 705 in the first opening 703 and the second opening 704.

[0085] The bonding interconnection structure 705 is used for mutual bonding between metal materials in wafer bonding.

[0086] Figure 18 It is a schematic flowchart of a mask layout design method according to another embodiment of the present invention.

[0087] The main difference between this embodiment and the previous embodiment is: the method for generating the second light-transmitting layout is different.

[0088] In the present embodiment, for the flowchart of the mask layout design method, please continue to refer to Figure 5 , Figure 6 , and the description of the previous embodiment; for the initial layout, please continue to refer to Figure 8 and the description of the previous embodiment; for the method of generating the first light-transmitting layout according to the initial layout, please continue to refer to Figures 8 to 10 , and the description of the previous embodiment, which will not be elaborated here.

[0089] In Figure 5 and Figure 6 , based on which, please refer to Figure 18 . In this embodiment, the method of generating the second light-transmitting layout includes the following steps:

[0090] S203a. According to the distribution of several plug patterns in the first light-transmitting layout, several cushion layer patterns are filled around the several plug patterns in the first light-transmitting layout, so that the plug patterns and the cushion layer patterns have the preset pattern density;

[0091] S203b. After obtaining several cushion layer patterns, several plug patterns in the first light-transmitting layout are removed, and the second light-transmitting layout is generated from the first light-transmitting layout.

[0092] The method of generating the second light-transmitting layout will be described in detail below with reference to the accompanying drawings.

[0093] Figures 19 to 21 is a structural schematic diagram of each step of the mask layout design method according to another embodiment of the present invention.

[0094] Please, on the basis of Figures 8 to 10 , continue to refer to Figure 19 . According to the distribution of several plug patterns 500 in the first light-transmitting layout 51, several cushion layer patterns 800 are filled around the several plug patterns 500 in the first light-transmitting layout 51, so that the plug patterns 500 and the cushion layer patterns 800 have the preset pattern density in the light-transmitting layout 51.

[0095] Please refer to Figure 20 , and continue to refer to Figure 8 . After obtaining several cushion layer patterns 800, several plug patterns 500 in the first light-transmitting layout 51 are removed, and the second light-transmitting layout 80 is generated from the first light-transmitting layout 51.

[0096] The second transparent layout 80 includes a pattern area m, the shape of the pattern area m and the position of the pattern area m in the second transparent layout 80 are the same as the shape of the second area II and the position of the second area II in the initial layout 30, and there are several liner layer patterns 800 in the pattern area m.

[0097] Please refer to Figure 21 , combine the first transparent layout 51 (as Figure 10 shown) and the second transparent layout 80 to form a mask layout 81. The mask layout 81 includes several plug patterns 500 and several liner layer patterns 800 surrounding the plug patterns 500. The plug patterns 500 and the liner layer patterns 800 have a preset pattern density.

[0098] Figures 22 to 23 is a schematic flow chart of a mask layout design method according to another embodiment of the present invention.

[0099] The main difference between this embodiment and the previous two embodiments is that both the method for generating the first transparent layout and the method for generating the second transparent layout are different.

[0100] In this embodiment, for the schematic flow chart of the mask layout design method, please continue to refer to Figure 5 , Figure 6 and the description of the previous embodiment; for the initial layout, please continue to refer to Figure 8 and the description of the previous embodiment, which will not be elaborated here.

[0101] On the basis of Figure 5 , please refer to Figure 22 . In this embodiment, the method for generating the first transparent layout according to the initial layout includes:

[0102] Step S202I, in the initial layout, identify several of the initial plug patterns according to the graphic size.

[0103] Step S202II, in the initial layout, identify and use the initial liner layer patterns that have an overlapping relationship with the initial plug patterns as the plug patterns according to the graphic overlapping relationship.

[0104] Step S202III, extract several of the plug patterns from the initial layout to obtain the first transparent layout. The first transparent layout includes several of the plug patterns, and the positions of the several plug patterns in the first transparent layout are the same as the positions of the plug patterns in the initial layout.

[0105] Hereinafter, the method for generating the first transparent layout according to the initial layout will be described in detail with reference to the accompanying drawings.

[0106] Figures 24 to 29 It is a structural schematic diagram of each step of the mask layout design method according to another embodiment of the present invention.

[0107] Please refer to Figure 24 , within the initial layout 30, according to the graphic size, identify a plurality of the initial plug graphics 300; within the initial layout 30, according to the graphic overlapping relationship, identify and use the initial liner layer graphic 400 that has an overlapping relationship with the initial plug graphic 300 as the plug graphic 901.

[0108] Please refer to Figure 25 , extract a plurality of the plug graphics 901 from the initial layout 30 to obtain the first light-transmitting layout 91, the first light-transmitting layout 91 includes a plurality of the plug graphics 901, and the positions of the plurality of the plug graphics 901 in the first light-transmitting layout 91 are the same as the positions of the plug graphic 901 in the initial layout 30.

[0109] Please refer to Figure 23 , in this embodiment, the method for generating the second light-transmitting layout includes the following steps:

[0110] Step S203I, within the initial layout, according to the graphic overlapping relationship, identify and use the initial liner layer graphic that has no overlapping relationship with the initial plug graphic as the liner layer graphic;

[0111] Step S203II, according to a plurality of the liner layer graphics, obtain the second light-transmitting layout, the second light-transmitting layout includes a plurality of the liner layer graphics, and the positions of the plurality of the liner layer graphics in the second light-transmitting layout are the same as the positions of the plurality of the liner layer graphics in the initial layout.

[0112] The method for generating the second light-transmitting layout will be described in detail below with reference to the accompanying drawings.

[0113] Please refer to Figure 27 , within the initial layout 30 (as shown in Figure 8 ), according to the graphic overlapping relationship, identify and use the initial liner layer graphic 400 that has no overlapping relationship with the initial plug graphic 300 as the liner layer graphic 902.

[0114] Please refer to Figure 28 , according to a plurality of the liner layer graphics 902, obtain the second light-transmitting layout 92, the second light-transmitting layout 92 includes a plurality of the liner layer graphics 902, and the positions of the plurality of the liner layer graphics 902 in the second light-transmitting layout 92 are the same as the positions of the plurality of the liner layer graphics 902 in the initial layout 30.

[0115] Please refer to Figure 29, merge the first light-transmitting layout 91 (as shown in Figure 25 ), and the second light-transmitting layout 92 (as shown in Figure 28 ) to form a mask layout 93. The mask layout 93 includes a plurality of plug patterns 901 and a plurality of liner layer patterns 902 surrounding the plug patterns 901. The plug patterns 901 and the liner layer patterns 902 have a preset pattern density.

[0116] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A mask layout design method, characterized in that, Including: Obtain an initial layout, the initial layout includes a first region and a second region surrounding the first region, there are several initial plug patterns in the first region, and there are several initial liner layer patterns in the first region and the second region. One of the initial plug patterns and one of the initial liner layer patterns overlap with each other, and each of the initial plug patterns is located within the contour range of the corresponding initial liner layer pattern; Generate a first light-transmitting layout according to the initial layout. The first light-transmitting layout includes several plug patterns. The positions of the plug patterns in the first light-transmitting layout are the same as the positions of the initial plug patterns in the initial layout, and the shapes of the plug patterns are the same as the shapes of the initial liner layer patterns; Generate a second light-transmitting layout. The second light-transmitting layout includes a graphic region. The shape of the graphic region and the position of the graphic region in the second light-transmitting layout are the same as the shape of the second region and the position of the second region in the initial layout. There are several liner layer patterns in the graphic region; Merge the first light-transmitting layout and the second light-transmitting layout to form a mask layout. The mask layout includes several plug patterns and several liner layer patterns surrounding the plug patterns. The plug patterns and the liner layer patterns have a preset graphic density.

2. The mask layout design method according to claim 1, wherein, The method for generating the first light-transmitting layout according to the initial layout includes: within the initial layout, identify the initial plug patterns according to the graphic size; extract several of the initial plug patterns from the initial layout to obtain a first transitional layout. The first transitional layout includes several of the initial plug patterns, and the positions of the initial plug patterns in the first transitional layout are the same as the positions of the initial plug patterns in the initial layout; perform an enlargement process on the sizes of the initial plug patterns in the first transitional layout to form the plug patterns, and use the first transitional layout to form the first light-transmitting layout.

3. The mask layout design method according to claim 2, characterized in that The method for generating the second light-transmitting layout includes: after removing several of the initial plug patterns, use the initial layout to form a second transitional layout. The second transitional layout includes several of the initial liner layer patterns; according to the relative positions of several of the initial plug patterns and several of the initial liner layer patterns in the initial layout, superpose the first light-transmitting layout and the second transitional layout, and remove the patterns that overlap with several of the plug patterns from several of the initial liner layer patterns. Use several of the initial liner layer patterns to form several of the liner layer patterns, and use the second transitional layout to form the second light-transmitting layout.

4. The mask layout design method according to claim 2, wherein, The method for generating the second light-transmitting layout includes: according to the distribution of several of the plug patterns in the first light-transmitting layout, fill several of the liner layer patterns around several of the plug patterns in the first light-transmitting layout, so that the plug patterns and the liner layer patterns have the preset graphic density in the first light-transmitting layout; after obtaining several of the liner layer patterns, remove several of the plug patterns in the first light-transmitting layout, and use the first light-transmitting layout to generate the second light-transmitting layout.

5. The mask layout design method according to claim 1, wherein The method for generating the first light-transmitting layout includes: within the initial layout, identifying a plurality of the initial plug patterns according to the pattern size; within the initial layout, identifying and taking the initial liner layer patterns that have an overlapping relationship with the initial plug patterns as the plug patterns according to the pattern overlapping relationship; extracting a plurality of the plug patterns from the initial layout to obtain the first light-transmitting layout, where the first light-transmitting layout includes a plurality of the plug patterns, and the positions of the plurality of the plug patterns within the first light-transmitting layout are the same as the positions of the plug patterns within the initial layout.

6. The mask layout design method according to claim 5, characterized in that The method for generating the second light-transmitting layout includes: within the initial layout, identifying and taking the initial liner layer patterns that have no overlapping relationship with the initial plug patterns as the liner layer patterns according to the pattern overlapping relationship; obtaining the second light-transmitting layout according to the plurality of the liner layer patterns, where the second light-transmitting layout includes a plurality of the liner layer patterns, and the positions of the plurality of the liner layer patterns within the second light-transmitting layout are the same as the positions of the plurality of the liner layer patterns within the initial layout.

7. The mask layout design method according to claim 1, wherein The plurality of the initial liner layer patterns include a plurality of functional metal patterns and a plurality of dummy metal patterns, and each of the functional metal patterns overlaps with the initial plug patterns; the plurality of the dummy metal patterns include a plurality of first dummy patterns surrounding the plurality of the functional metal patterns and a plurality of second dummy patterns surrounding the plurality of the first dummy patterns.

8. A method for preparing a photomask, characterized in that, Including: Providing a mask layout, where the mask layout includes a plurality of plug patterns and a plurality of liner layer patterns surrounding the plurality of the plug patterns, and the plug patterns and the liner layer patterns have a preset pattern density; Forming a mask using the mask layout, where the mask includes a first light-transmitting area formed by the plug patterns and a second light-transmitting area formed by the liner layer patterns, and the light transmittance of the first light-transmitting area and the second light-transmitting area is different.

9. A method for forming a semiconductor structure, characterized in that, Including: Providing a mask layout, where the mask layout includes a plurality of plug patterns and a plurality of liner layer patterns surrounding the plurality of the plug patterns, and the plug patterns and the liner layer patterns have a preset pattern density; Forming a mask using the mask layout, where the mask includes a first light-transmitting area formed by the plug patterns and a second light-transmitting area formed by the liner layer patterns, and the light transmittance of the first light-transmitting area and the second light-transmitting area is different; Providing a substrate; Forming a device layer on the substrate, where the device layer has an electrical interconnection structure therein; Using the mask to form a first opening and a second opening in the device layer, where the first opening is patterned by the first light-transmitting area, the second opening is patterned by the second light-transmitting area, the depth of the first opening is greater than the depth of the second opening, and the first opening exposes a part of the electrical interconnection structure; Forming a bonding interconnection structure in the first opening and the second opening.

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