Method for measuring overlay error and integrated circuit

Abstract

The invention provides a method for measuring overlay error and an integrated circuit. The method may include forming a first layer including a first region, a second region, and a third region having the same size; forming a second layer, the first region being not covered by the second layer, the second region being completely covered by the second layer, and the third region being partially covered by the second layer, the third region being to be partially covered by the second layer at a nominal proportion as designed; measuring a first resistance value of the first region, a second resistance value of the second region and a third resistance value of the third region; and determining an overlay error between the first layer and the second layer based on the first resistance value, the second resistance value and the third resistance value and the nominal ratio.

Description

Technical Field

[0001] The present disclosure generally relates to the field of integrated circuit manufacturing, and more particularly, to a method for measuring overlay error and an integrated circuit. Background Art

[0002] Currently, overlay error is measured using broadband light through a box in box structure. Overlay error is one of the core issues determining chip yield and performance in semiconductor manufacturing. With the evolution of process scaling and 3D integration technologies, its control accuracy will directly affect the feasibility of advanced processes. In addition, as devices continue to shrink, the requirements for overlay become more stringent, and optical methods for measuring overlay error may reach their limits. Summary of the Invention

[0003] An object of embodiments of the present disclosure is to provide a method and an integrated circuit for measuring overlay error by an electrical method.

[0004] Specifically, according to one aspect of the present disclosure, a method for measuring overlay error is proposed. The method includes: forming a first layer, the first layer including a first region, a second region, and a third region having the same size; forming a second layer, wherein the first region is not covered by the second layer, the second region is completely covered by the second layer, and the third region is partially covered by the second layer, wherein the third region is designed to be partially covered by the second layer in a nominal ratio; measuring a first resistance value of the first region, a second resistance value of the second region, and a third resistance value of the third region; and determining an overlay error between the first layer and the second layer based on the first resistance value, the second resistance value, the third resistance value, and the nominal ratio.

[0005] According to an embodiment of the present disclosure, the first layer may be an active layer or a gate layer, and the second layer may be an implantation layer.

[0006] According to an embodiment of the present disclosure, the first region, the second region, and the third region may have the same rectangular shape.

[0007] According to an embodiment of the present disclosure, determining the overlay error may include using the following equation to determine the overlay error:

[0008]

[0009] wherein, R1 is the first resistance value, R2 is the second resistance value, R3 is the third resistance value, P is the nominal ratio, and ΔP is the deviation from the nominal ratio due to the overlay error.

[0010] According to an embodiment of the present disclosure, each of the first region, the second region, and the third region may have the same rectangular shape. The third region may be designed to be covered by the second layer over the entire width within a nominal 50% length range. Determining the overlay error may include determining the overlay error using the following equation:

[0011]

[0012] where x is the overlay error in the length direction of the third region, R3 is the third resistance value, R1 is the first resistance value, R2 is the second resistance value, and L is the length of the rectangular shape.

[0013] According to an embodiment of the present disclosure, the length direction of the third region may be in the first direction, and the first layer may further include a fourth region extending in a second direction intersecting the first direction. The fourth region may have the same rectangular shape and may be designed to be covered by the second layer over the entire width within a nominal 50% length range.

[0014] According to an embodiment of the present disclosure, the measurement may further include measuring a fourth resistance value of the fourth region.

[0015] According to an embodiment of the present disclosure, determining the overlay error may include determining the overlay error using the following equation:

[0016]

[0017] where y is the overlay error in the length direction of the fourth region, R4 is the fourth resistance value, R1 is the first resistance value, R2 is the second resistance value, and L is the length of the rectangular shape.

[0018] According to an embodiment of the present disclosure, the length direction of one of the first region and the second region may be in the first direction, and the length direction of the other may be in the second direction.

[0019] According to an embodiment of the present disclosure, the measurement may include: forming pads respectively electrically connected to both ends of each of the first region to the fourth region; and measuring the first resistance value to the fourth resistance value through the pads.

[0020] According to an embodiment of the present disclosure, one end of each of the first region to the fourth region may be electrically connected to a common pad, and the other end may be electrically connected to respective corresponding pads.

[0021] According to another aspect of the present disclosure, an integrated circuit is provided. The integrated circuit includes: a first layer including a first region, a second region, and a third region having the same size; a second layer, wherein the first region is not covered by the second layer, the second region is completely covered by the second layer, and the third region is partially covered by the second layer, and wherein the third region is designed to be partially covered by the second layer in a nominal ratio; and circuit devices formed at least partially in the first layer and the second layer. The first region, the second region, and the third region are electrically isolated from the circuit devices. The first region, the second region, and the third region have corresponding first, second, and third resistance values. The first to third resistance values and the nominal ratio can be configured to determine the overlay error between the first layer and the second layer.

[0022] According to an embodiment of the present disclosure, the overlay error can be measured online or offline by an electrical test method, thereby realizing the monitoring of the overlay performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To more fully understand the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0024] Figure 1 FIG. shows a schematic diagram of an electrical structure for monitoring overlay performance according to an embodiment of the present disclosure.

[0025] Figure 2 FIG. shows a schematic diagram of an electrical structure for monitoring overlay performance according to another embodiment of the present disclosure.

[0026] Figure 3 FIG. shows a schematic cross-sectional view of a coverage example according to an embodiment of the present disclosure.

[0027] Figure 4 FIG. shows a schematic diagram of the overlay error in the X direction according to an embodiment of the present disclosure.

[0028] Figure 5 FIG. shows a schematic flowchart of a method for determining the overlay error according to an embodiment of the present disclosure.

[0029] Figure 6 FIG. is a schematic diagram of an integrated circuit according to an embodiment of the present disclosure.

[0030] In the drawings, the same or similar structures are identified by the same or similar reference numerals. DETAILED DESCRIPTION

[0031] Other aspects, advantages, and salient features of the present disclosure will become apparent to those skilled in the art from the following detailed description of exemplary embodiments of the present disclosure taken in conjunction with the drawings.

[0032] In the present disclosure, the terms "comprising" and "containing" and their derivatives are meant to include rather than limit; the term "or" is inclusive and means "and / or".

[0033] In this specification, the various embodiments described below for explaining the principles of the present disclosure are merely illustrative and should not be construed in any way as limiting the scope of the disclosure. The following description with reference to the accompanying drawings is used to assist in a comprehensive understanding of the exemplary embodiments of the present disclosure defined by the claims and their equivalents. The following description includes various specific details to aid understanding, but these details should be considered merely exemplary. Thus, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. In addition, descriptions of well-known functions and structures are omitted for clarity and conciseness. Further, throughout the drawings, the same reference numerals are used for similar functions and operations.

[0034] Figure 1 A schematic diagram of an electrical structure 100 for monitoring overlay performance according to an embodiment of the present disclosure is shown.

[0035] As Figure 1 shown, the electrical structure 100 may include a first pattern or first region 101, a second pattern or second region 103, and a third pattern or third region 105 formed in layer A (as shown by the dashed box in Figure 1 ). For example, layer A may be a layer in an integrated circuit where an active region or a polysilicon gate is formed. Here, the first region 101, the second region 103, and the third region 105 may have the same size for ease of subsequent calculation. In addition, the electrical structure 100 may further include a pattern formed in layer B (as shown by the shaded box in Figure 1 ). For example, layer B may be a layer in an integrated circuit where an implantation layer (e.g., a boron- or phosphorus-doped implantation layer) is formed. However, the present disclosure is not limited thereto, and layer A and layer B may be other layers that need to be aligned with each other in integrated circuit manufacturing.

[0036] As Figure 1 shown, the pattern in layer B may be formed such that the first region 101 may not be covered by layer B (i.e., no pattern is formed at the position of the first region 101 in layer B), the second region 103 may be completely covered by layer B (i.e., a pattern that completely covers the second region 103 may be formed at the position of the second region 103 in layer B; considering process margins, the pattern may be slightly larger than the second region 103), and the third region 105 may be partially covered by layer B (i.e., a pattern that partially covers the third region 105 may be formed at the position of the third region 105 in layer B).

[0037] Layer A and layer B can be formed on a substrate based on a mask. For example, the mask for layer A can include patterns corresponding to the first region 101, the second region 103, and the third region 105, and the mask for layer B can include patterns corresponding to the above patterns. When layer A and layer B are formed based on the masks respectively, there may be a registration error.

[0038] For example, assume that the third region 105 is designed to be partially covered by layer B in a nominal ratio P, that is, when the two layers are ideally perfectly aligned as designed, a portion of the third region 105 should be covered by layer B in the ratio P. However, in reality, there is a registration error, that is, the alignment between layer A and layer B deviates from the theoretical design value. For example, the third region 105, which is designed to be partially covered by layer B in the nominal ratio P, may be partially covered by layer B in the ratio P + ΔP after layer A and layer B are actually formed. That is, due to the registration error, a deviation ΔP from the nominal ratio P is caused.

[0039] According to an embodiment of the present disclosure, the registration error between the two layers (layer A and layer B) can be electrically measured through the above electrical structure 100. For example, the electrical characteristics such as resistance of the patterns / regions in layer A may be changed because they are (fully or partially) covered by the patterns / regions in layer B, and the degree of change in the electrical characteristics can be related to the covered ratio. Specifically, the first region 101 can maintain its electrical characteristics such as the resistance value substantially unchanged because it is not covered by layer B; the second region 103 may have a relatively large change in its electrical characteristics because it is fully covered by layer B; the third region 105 may have a relatively small change in its electrical characteristics because it is partially covered by layer B. The registration error (which can be characterized by the above ΔP) can be determined based on such a change in the electrical characteristics.

[0040] For the convenience of subsequent calculations, the first region 101, the second region 103, and the third region 105 can have the same size, so that (in the case where layer B is not formed) they can have substantially the same initial electrical characteristics such as resistance values. Figure 1 In the example shown, the first region 101, the second region 103, and the third region 105 can be formed into the same rectangular shape. Although in Figure 1 these three regions are shown as extending parallel to each other, the present disclosure is not limited thereto. In the absence of anisotropy, their respective directions can be arbitrarily selected. Of course, extending substantially parallel or orthogonal to each other is beneficial to the manufacturing process.

[0041] In one embodiment, the registration error between layer A and layer B can be determined based on the respective resistance values of the first region 101 to the third region 105 and the nominal ratio P, for example, according to the following formula:

[0042] ,

[0043] Wherein, R1 is the first resistance value of the first region 101, R2 is the second resistance value of the second region 103, R3 is the third resistance value of the third region 105, P is the nominal ratio, and ΔP is the deviation from the nominal ratio due to the overlay error.

[0044] According to an embodiment of the present disclosure, the resistance values of the first region 101 to the third region 105 can be measured through the pads electrically connected to both ends of each of the first region 101 to the third region 105.

[0045] In Figure 1 the illustrated example, the third region 105 is shown to be covered by the B layer over its entire width within a certain range in the length direction. In this case, the nominal ratio P can represent the ratio of the covered area to the length L of the rectangular shape, and ΔP can represent the offset between the two layers in the length direction, that is, the overlay error.

[0046] Figure 2 A schematic diagram of an electrical structure 200 for monitoring overlay performance according to another embodiment of the present disclosure is shown.

[0047] As Figure 2 shown, the electrical structure 200 can also include an A layer and a B layer, for which reference can be made to the description above in conjunction with Figure 1 and will not be elaborated here. As Figure 2 shown, in the A layer, four rectangular regions with the same dimensions (length L and width W) can be formed, where two regions are in the X direction and the other two regions are in the Y direction. For example, the first region 101 and the third region 105 can be in the X direction, and the second region 103 and the fourth region 107 can be in the Y direction. Here, the X direction can intersect (e.g., be perpendicular) with the Y direction. In addition, the length L of the first region 101 and the third region 105 is measured in the X direction, and the length L of the second region 103 and the fourth region 107 is measured in the Y direction.

[0048] Among the first region 101 to the fourth region 107, one region is completely covered by the B layer and the other region is completely open; for the remaining two regions, they can be partially covered by the B layer, for example, the nominal coverage ratio is 50% (i.e., 1 / 2). For example, in the embodiment, the first region 101 may not be covered by the B layer, the second region 103 may be completely covered by the B layer, and the third region 105 and the fourth region 107 may be partially covered by the B layer (the nominal ratio P is 50%). However, the present disclosure is not limited thereto, and the third region 105 and the fourth region 107 can be partially covered by the B layer at any nominal ratio as designed.

[0049] In this example, partial coverage regions extending respectively in the X direction and the Y direction are formed, i.e., the third region 105 and the fourth region 107. This is for more effectively measuring the overlay error in the X direction and the Y direction (as described above with reference to Figure 1 it is possible to obtain the overlay error in the length direction of the rectangular shape). However, the present disclosure is not limited thereto. For example, a partial coverage region extending in a direction between the X direction and the Y direction can be formed to obtain the overlay error in its length direction, and the overlay errors in the X direction and the Y direction can be obtained by vector decomposition.

[0050] In addition, in this example, two regions extend in the X direction and the other two regions extend in the Y direction, which can obtain a substantially symmetric structure. This is advantageous for electrical measurement. However, the present disclosure is not limited thereto. As described above, the extension direction of each region can be changed. For example, the first region 101 and the second region 103 can be exchanged.

[0051] As described above, when the pattern or region in the A layer is covered by the B layer, its electrical properties such as the resistance value may change. An example in which the A layer is covered by the B layer and the resistance value changes will be described below with reference to Figure 3 to describe an example in which the A layer is covered by the B layer and the resistance value changes.

[0052] Figure 3 FIG. shows a schematic cross-sectional view of a coverage example according to an embodiment of the present disclosure. As Figure 3 shown, the B layer can be an implantation region formed in the A layer by, for example, ion implantation, and the implanted impurities can change the conductivity of the A layer (e.g., the active layer or polysilicon). Therefore, when a certain region in the A layer is covered by the B layer, the resistance value of this region can change.

[0053] Returning to the reference Figure 2 , in the electrical structure 200, a common pad Pc can be provided to be electrically connected to one end of each of the first region 101, the second region 103, the third region 105, and the fourth region 107. In addition, a first pad P1, a second pad P2, a third pad P3, and a fourth pad P4 can be provided to be electrically connected to the other end of each of the first region 101, the second region 103, the third region 105, and the fourth region 107, respectively. That is, one end of each of the first region 101 to the fourth region 107 is electrically connected to the common common pad Pc, and the other end is electrically connected to its respective corresponding pad, e.g., the first pad P1, the second pad P2, the third pad P3, and the fourth pad P4.

[0054] In an embodiment, through the common pad Pc, and the first pad P1, the second pad P2, the third pad P3, and the fourth pad P4, the resistance values of the first region 101, the second region 103, the third region 105, and the fourth region 107 can be measured respectively. Here, the resistance value of the first region 101 can be R1, the resistance value of the second region 103 can be R2, the resistance value of the third region 105 can be R3, and the resistance value of the fourth region 107 can be R4. For example, a specific voltage can be applied through the pads, and the resistance values of the corresponding regions can be calculated by measuring the current flowing through each region.

[0055] However, the embodiment is not limited thereto. In other embodiments, pads can be formed that are electrically connected to both ends of each of the first region 101 to the fourth region 107, and through these pads, the first resistance value R1 to the fourth resistance value R4 can be measured.

[0056] As described above, the third region 105 can be designed to be covered by the B layer over the entire width in a nominal 50% length range, and the fourth region 107 can be designed to be covered by the B layer over the entire width in a nominal 50% length range. However, in practice, there can be a registration error between the B layer and the A layer. For example, it can be assumed that the registration error between the B layer and the A layer in the X direction is x, and the registration error between the B layer and the A layer in the Y direction is y. Therefore, it can be considered that in the actual situation, the third region 105 is not covered by the B layer in a nominal proportion of 50%, but there is a deviation with a registration error of x in the X direction, that is, the third region 105 can be covered by the B layer over the entire width in a length range of (50%L - x) in the length direction. Similarly, the fourth region 107 may not be covered by the B layer in a nominal proportion of 50%, but there is a deviation with a registration error of y in the Y direction, that is, the fourth region 107 can be covered by the B layer over the entire width in a length range of (50%L - y) in the length direction.

[0057] Figure 4 A schematic diagram showing the registration error in the X direction according to an embodiment of the present disclosure is shown.

[0058] Here, the third region 105 is described as an example. As described above, the registration error between the B layer and the A layer in the X direction can be x. For the sake of description, the positive (+) direction of the X direction can be defined as the direction from the uncovered part of the third region 105 to the covered part (this definition only affects the sign of the value, and does not affect the working principle of the inventive concept). The registration error x in the X direction can be a positive value or a negative value.

[0059] In Figure 4In (a) thereof, a schematic diagram is shown in which the overlay error between the B layer and the A layer in the X direction deviates to the left (i.e., x is negative). Therefore, a region (e.g., the third region 105) can be covered by the B layer within a length range of (50%L + |x|), i.e., (50%L - x). That is to say, the overlay error occurs in the direction along which the coverage of the A layer by the B layer increases in the X direction.

[0060] In addition, in Figure 4 In (b) thereof, a schematic diagram is shown in which the overlay error between the B layer and the A layer in the X direction deviates to the right (i.e., x is positive). Therefore, a region (e.g., the third region 105) can be covered by the B layer within a length range of (50% L - |x|), i.e., (50%L - x). That is to say, the overlay error occurs in the direction along which the coverage of the A layer by the B layer decreases in the X direction.

[0061] The following relationship may exist between the resistance value R1 of the first region 101, the resistance value R2 of the second region 103, the resistance value R3 of the third region 105, and the length (50%L - x) of the third region 105 actually covered by the B layer:

[0062] .

[0063] According to the above relationship, the overlay error x in the X direction can be determined as follows, i.e.,

[0064] .

[0065] In the same way, the overlay error y between the A layer and the B layer in the Y direction can also be determined:

[0066] .

[0067] Details are not described herein again.

[0068] Figure 5 A schematic flowchart of a method for determining an overlay error according to an embodiment of the present disclosure is shown.

[0069] As Figure 5 described, the method 500 according to this embodiment may include: forming a first layer in S502. The first layer includes a first region (e.g., Figure 1 or Figure 2 101), a second region (e.g., Figure 1 or Figure 2 103), and a third region (e.g., Figure 1 or Figure 2of 105). As described above, these regions may have the same rectangular shape, and more specifically, may have the same length and width. Additionally, a fourth region extending in a direction different from the third region may be formed (e.g., Figure 2 of 107). The fourth region may have the same rectangular shape as the first to third regions.

[0070] Method 500 may further include: forming a second layer in S504. The first region may not be covered by the second layer, the second region may be completely covered by the second layer, and the third region may be partially covered by the second layer. For example, the third region is designed to be partially covered by the second layer at a nominal ratio. Additionally, the fourth region is designed to be partially covered by the second layer at a nominal ratio. The nominal coverage ratios of the third region and the fourth region may be the same (e.g., 50%) or different. Regarding the first layer and the second layer and the coverage relationship between them, reference may be made to the A layer and the B layer described above Figures 1 to 4 described.

[0071] Method 500 may further include: measuring a first resistance value of the first region, a second resistance value of the second region, and a third resistance value of the third region in S506. Additionally, in the case where the fourth region is formed, a fourth resistance value of the fourth region may also be measured. For example, each resistance value may be measured by pads electrically connected to both ends of each region.

[0072] Method 500 may further include: determining the registration error between the first layer and the second layer based on the first resistance value, the second resistance value, the third resistance value, and the nominal ratio in S508.

[0073] For example, the following equation may be used to determine the registration error:

[0074]

[0075] where R1 is the first resistance value, R2 is the second resistance value, R3 is the third resistance value, P is the nominal ratio, and ΔP is the deviation from the nominal ratio due to the registration error.

[0076] In an embodiment, the third region may be designed to be covered by the second layer over the entire width within a nominal 50% length range. In this case, the following equation may be used to determine the registration error:

[0077]

[0078] where x is the registration error in the length direction of the third region, R3 is the third resistance value, R1 is the first resistance value, R2 is the second resistance value, and L is the length of the above rectangular shape.

[0079] In an embodiment, the fourth region may be designed to be covered by the second layer over the entire width within a nominal 50% length range. In this case, the following equation can be used to determine the overlay error:

[0080]

[0081] where y is the overlay error in the length direction of the fourth region, R4 is the fourth resistance value, R1 is the first resistance value, R2 is the second resistance value, and L is the length of the above-mentioned rectangular shape.

[0082] Figure 6 is a schematic diagram showing an integrated circuit according to an embodiment of the present disclosure.

[0083] As Figure 6 shown, the integrated circuit 600 according to this embodiment may include a first layer and a second layer. For example, the integrated circuit 600 can be fabricated by disposing multiple layers including the first layer and the second layer on a substrate and processing each layer (e.g., etching, implantation, etc.).

[0084] The integrated circuit 600 may include a device region and a test region. In the device region, electronic components for implementing the desired functions of the integrated circuit 600 can be formed, such as various active devices like transistors and passive devices like capacitors. These electronic components can be formed at least partially in the first layer and the second layer. For example, the active region or polysilicon gate of a transistor device can be formed in the first layer, and the implantation region in the transistor device can be formed in the second layer. In the test region, components for testing whether the integrated circuit 600 can properly implement its desired functions can be formed, such as the electrical structure for testing the overlay error described above with reference to Figures 1 to 4 Regarding this electrical structure and its method for measuring the overlay error, reference can be made to the above description and will not be elaborated here.

[0085] Note that the device region and the test region are only logically divided, not physically. For example, the device region and the test region can be separated from each other, or the test region can also be embedded in the device region. The test region can be electrically isolated from the device region.

[0086] As described above, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. However, the specific structure is not limited to the above embodiments, and the present disclosure also includes any design modifications that do not deviate from the gist of the present disclosure. Additionally, various modifications can be made to the present disclosure within the scope of the claims, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included within the technical scope of the present disclosure. Furthermore, components having the same effects described in the above embodiments can be mutually substituted.

Claims

1. A method for measuring overlay error, comprising: Forming a first layer, the first layer including a first region, a second region, and a third region having the same dimensions; Forming a second layer, wherein the first region is not covered by the second layer, the second region is completely covered by the second layer, and the third region is partially covered by the second layer, wherein the third region is designed to be partially covered by the second layer in a nominal ratio; Measuring a first resistance value of the first region, a second resistance value of the second region, and a third resistance value of the third region; and Determining an overlay error between the first layer and the second layer based on the first resistance value, the second resistance value, the third resistance value, and the nominal ratio.

2. The method according to claim 1, wherein, The first layer is an active layer or a gate layer, and the second layer is an implantation layer.

3. The method according to claim 1, wherein The first region, the second region, and the third region have the same rectangular shape.

4. The method according to claim 1, wherein Determining the overlay error includes using the following equation to determine the overlay error: wherein, R1 is the first resistance value, R2 is the second resistance value, R3 is the third resistance value, P is the nominal ratio, and ΔP is the deviation from the nominal ratio due to the overlay error.

5. The method according to claim 4, wherein, Each of the first region, the second region, and the third region has the same rectangular shape, wherein the third region is designed to be covered by the second layer over the entire width in a nominal 50% length range, and wherein determining the overlay error includes using the following equation to determine the overlay error: wherein, x is the overlay error in the length direction of the third region, R3 is the third resistance value, R1 is the first resistance value, R2 is the second resistance value, and L is the length of the rectangular shape.

6. The method according to claim 5, wherein, The length direction of the third region is in a first direction, The first layer further includes a fourth region extending in a second direction intersecting the first direction, the fourth region having the same rectangular shape and being designed to be covered by the second layer over the entire width in a nominal 50% length range, The measurement further includes measuring a fourth resistance value of the fourth region, Determining the overlay error includes using the following equation to determine the overlay error: wherein, y is the overlay error in the length direction of the fourth region, R4 is the fourth resistance value, R1 is the first resistance value, R2 is the second resistance value, and L is the length of the rectangular shape.

7. The method according to claim 6, wherein The length direction of one of the first region and the second region is in the first direction, and the length direction of the other is in the second direction.

8. The method according to claim 6, wherein, The measurement includes: Forming pads respectively electrically connected to both ends of each of the first region to the fourth region; and Measuring the first resistance value to the fourth resistance value through the pads.

9. The method according to claim 6, wherein, One end of each of the first region to the fourth region is electrically connected to a common pad, and the other end is electrically connected to its respective pad.

10. An integrated circuit, comprising: The first layer includes a first region, a second region, and a third region having the same size; The second layer, wherein the first region is not covered by the second layer, the second region is completely covered by the second layer, and the third region is partially covered by the second layer, wherein the third region is designed to be partially covered by the second layer in a nominal ratio; and Circuit devices formed at least partially in the first layer and the second layer, wherein the first region, the second region, and the third region are electrically isolated from the circuit devices, wherein the first region, the second region, and the third region have respective first, second, and third resistance values, wherein the first to third resistance values and the nominal ratio are configured to determine the overlay error between the first layer and the second layer.

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