High power supply rejection ratio low dropout linear regulator circuit with dynamic bias current

Abstract

The invention relates to the field of analog integrated circuit design, and discloses a high power supply rejection ratio low dropout linear regulator circuit with dynamic bias current, which comprises a power tube, a secondary operational amplifier, a voltage feedback loop, a current feedback loop, a Vds matching loop and an RC filter circuit, the low-dropout regulator is characterized in that an input stage and a second stage of an operational amplifier and a power supply of a power tube are separated, the input stage works in a small-ripple AVDD voltage domain to ensure that the LDO circuit has a high PSRR in a low-frequency band, the second stage and the power tube work in a large-ripple Vin voltage domain, the mirror image precision of the current of the power tube is ensured through a Vds matching loop and an RC filter circuit, and the current of the low-dropout regulator is improved. Therefore, the PSRR of the LDO circuit in middle and high frequency bands is improved.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit design, and particularly to a design technology of a Low-Dropout Regulator (LDO). Background Art

[0002] With the continuous development of electronic technology, more and more electronic devices have put forward higher requirements for the power supply circuit. Especially in application scenarios such as high-precision analog circuits and radio frequency circuits, power supply noise will directly affect the system performance. Low-Dropout Regulator (LDO) has been widely used in these fields due to its advantages such as low noise and fast response.

[0003] However, the traditional LDO circuit still has some limitations. First, the Power Supply Rejection Ratio (PSRR) of the LDO usually drops sharply in the high-frequency band, making it difficult to effectively suppress high-frequency noise interference generated by switching power supplies or load transients. Second, in order to improve the PSRR and load transient response, it is usually necessary to increase the bias current of the LDO, but this will lead to an increase in the static power consumption of the chip and reduce the efficiency. In addition, the traditional LDO circuit uses a single power supply, and the operational amplifier and the power transistor share a power supply with relatively large noise, which limits the improvement of the PSRR in the medium and high frequencies.

[0004] In order to solve the above problems, a new LDO design scheme is urgently needed. This scheme should be able to achieve high PSRR performance in the entire operating frequency band, especially significantly improve the power supply rejection ability in the medium and high frequency bands of the LDO. At the same time, the new design should also reduce the static power consumption as much as possible and ensure good load transient response ability. Summary of the Invention

[0005] The purpose of this application is to provide a high power supply rejection ratio low-dropout linear regulator circuit with dynamic bias current to solve the problems proposed in the above background art.

[0006] This application discloses a high power supply rejection ratio low-dropout linear regulator circuit with dynamic bias current, including:

[0007] A first power transistor MP, whose source is connected to the first power supply voltage Vin, the gate is connected to the control voltage output by the operational amplifier, and the drain outputs the load voltage Vout;

[0008] The first operational amplifier includes an input stage and a second stage. The input stage includes a differential input pair, one end connected to the reference voltage Vref and the other end connected to the feedback voltage Vfb. The working power supply of the input stage is the second power supply voltage AVDD, and the working power supply of the second stage is the first power supply voltage. Among them, the second power supply voltage is a power supply with small ripple, and the first power supply voltage is a power supply with larger ripple;

[0009] A voltage feedback loop for feeding back the feedback voltage after dividing the load voltage to the input stage of the first operational amplifier;

[0010] A current feedback loop includes a Vds matching loop and an RC filter circuit. The Vds matching loop is configured to monitor the drain-source voltage of the first power transistor and control its current. The RC filter circuit includes a first MOS transistor M8 and a first resistor R1 for improving the current mirror accuracy;

[0011] A first load is connected to the drain of the first power transistor;

[0012] Among them, the input stage operates in the second power supply voltage domain to ensure high PSRR in the low frequency band. The second stage and the first power transistor operate in the first power supply voltage domain, and high PSRR in the medium and high frequency bands is ensured through the Vds matching loop and the RC filter circuit.

[0013] In a preferred example, the gate of the first power transistor is connected to the gates of the second MOS transistor M7 and the third MOS transistor M9, and its drain is connected to the upper ends of the first ESR resistor Resr of the first load and the second feedback resistor Rf1.

[0014] In a preferred example, the input stage of the first operational amplifier includes:

[0015] A fourth MOS transistor M1 and a fifth MOS transistor M2, whose sources are short-circuited and connected to the negative pole of the first current source I1 and the drain of the sixth MOS transistor M14;

[0016] The gate of the fourth MOS transistor is connected to the reference voltage, and the drain is connected to the gate, drain of the seventh MOS transistor M3 and the left end of the second resistor R4;

[0017] The gate of the fifth MOS transistor is connected to the feedback voltage, and the drain is connected to the right end of the second resistor, the drain of the eighth MOS transistor M4 and the gate of the ninth MOS transistor M5;

[0018] The gate and drain of the seventh MOS transistor are short-circuited, and the sources of the seventh MOS transistor and the eighth MOS transistor are short-circuited and grounded;

[0019] The gate of the ninth MOS transistor is connected to the right end of the second resistor, the source is grounded, and the drain is connected to the drain of the tenth MOS transistor M10 and the gate of the third MOS transistor.

[0020] In a preferred example, the voltage feedback loop includes:

[0021] A second feedback resistor Rf1, whose upper end is connected to the load voltage, and the lower end is connected to the feedback voltage and the upper end of a third feedback resistor Rf2;

[0022] The third feedback resistor, whose upper end is connected to the feedback voltage and the lower end is grounded.

[0023] In a preferred example, in the current feedback loop:

[0024] The gates of the second MOS transistor, the third MOS transistor and the first power transistor are short-circuited, the current mirror ratio is 1:1, and it is connected to the drain of the tenth MOS transistor and the lower end of a third resistor R, and the upper end of the third resistor is connected to the first power supply voltage;

[0025] The sources of the second MOS transistor, the third MOS transistor and the first power transistor are connected to the first power supply voltage;

[0026] The drain of the second MOS transistor is connected to the negative pole of a second current source I2, the source of an eleventh MOS transistor M6 and the negative input terminal of a second operational amplifier amp1;

[0027] The drain of the third MOS transistor is connected to the negative pole of a third current source I3, the source of the tenth MOS transistor and the negative input terminal of a third operational amplifier amp2;

[0028] The drain and the gate of a twelfth MOS transistor M11 are short-circuited, connected to the drain of the eleventh MOS transistor and the right end of the first resistor, and the source is grounded;

[0029] The gate of a thirteenth MOS transistor M12 is connected to the gate of the first MOS transistor and the left end of the first resistor, and the source is grounded;

[0030] The drain and the gate of a fourteenth MOS transistor M13 are short-circuited and connected to the drain of the thirteenth MOS transistor, and the source is connected to the second power supply voltage;

[0031] The gates of the sixth MOS transistor and the fourteenth MOS transistor are short-circuited, the current mirror ratio is k:1, the sources are connected to the second power supply voltage, and the drains are connected to the sources of the fourth MOS transistor and the fifth MOS transistor.

[0032] In a preferred example, the Vds matching loop includes:

[0033] [[ID=

[0034] For the eleventh MOS transistor, its source is connected to the inverting input terminal of the second operational amplifier and short - circuits the lower end of the second current source and the drain of the second MOS transistor, its drain is connected to the drain of the twelfth MOS transistor, and its gate is connected to the output terminal of the second operational amplifier;

[0035] For the tenth MOS transistor, its source is connected to the inverting input terminal of the third operational amplifier and short - circuits the lower end of the third current source and the drain of the third MOS transistor, its drain is connected to the drain of the ninth MOS transistor, and its gate is connected to the output terminal of the third operational amplifier.

[0036] In a preferred example, in the RC filter circuit:

[0037] The gate of the first MOS transistor is short - circuited with the gate of the thirteenth MOS transistor and connected to the left end of the first resistor;

[0038] Both the source and the drain of the first MOS transistor are grounded;

[0039] The right end of the first resistor is connected to the gate of the twelfth MOS transistor.

[0040] In a preferred example, the first load includes:

[0041] A first ESR resistor Resr, whose upper end is connected to the load voltage and whose lower end is connected to the upper end of the first capacitor CL;

[0042] The lower end of the first capacitor is grounded;

[0043] A first output resistor Ro, whose upper end is connected to the load voltage and whose lower end is grounded.

[0044] In a preferred example, the input stage operates in the second power supply voltage domain, and the second stage and the first power transistor operate in the first power supply voltage domain, which not only ensures that the low - dropout linear regulator (LDO) has a high PSRR in the low - frequency band but also improves the PSRR in the medium - and high - frequency bands.

[0045] The high power supply rejection ratio low - dropout linear regulator circuit with dynamic bias current proposed in this application has the following beneficial effects:

[0046] By placing the input stage and the second stage of the first operational amplifier 15 in different power supply domains respectively, that is, the input stage operates in the small - ripple domain of the second power supply voltage AVDD, and the second stage and the first power transistor MP11 operate in the domain with larger ripple of the first power supply voltage Vin, it ensures that the LDO has a high PSRR in the low - frequency band. This power separation design makes the input stage immune to power supply ripple when processing the reference voltage Vref and the feedback voltage Vfb.

[0047] The introduction of the current feedback loop 13, including the Vds matching loop 14 and the RC filter circuit 12, significantly improves the PSRR performance of the LDO in the medium and high frequency bands. As Figure 4 shown, in the medium frequency band from 10 kHz to 2 MHz, the PSRR of the proposed solution in this application is significantly better than the traditional method. This is mainly due to the precise control of the drain-source voltage of the first power transistor MP11 by the Vds matching loop, and the improvement of the current mirror accuracy by the RC filter circuit.

[0048] The simulation results show that under the operating conditions of dropout voltage Vin - Vout = 150 mV and output current IL = 250 mA, the PSRR of the LDO in this application reaches more than 40 dB in the full frequency band. Compared with the traditional LDO, this application not only ensures a high PSRR in the low frequency band but also improves the PSRR in the medium and high frequency bands.

[0049] This application solves the problem of insufficient PSRR performance in the medium and high frequencies in traditional LDOs due to the common use of the same power supply for the operational amplifier and the power transistor through the structure of separate power supply for the input stage and the second stage of the first operational amplifier 15.

[0050] Through the Vds matching loop 14 and the RC filter circuit 12 composed of the first MOS transistor M8 and the first resistor R1, the current mirror accuracy of the first power transistor MP11 is ensured, effectively improving the PSRR of the LDO circuit in the medium and high frequency bands.

[0051] In summary, the high-PSRR LDO design based on dynamic bias current in this application achieves high PSRR performance in the full frequency band through the separate power supply of the first operational amplifier 15 and the optimized configuration of the current feedback loop 13, especially improving the PSRR performance in the medium and high frequency bands, providing a better solution for electronic systems that require high-quality power supply.

[0052] The specification of this application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too lengthy. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be technically combined with feature C. Then, the solution of A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution of A+B+C+E should be considered as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 3 is a schematic diagram of an application scenario of a high power supply rejection ratio low voltage dropout linear regulator circuit with dynamic bias current according to an embodiment of the present application.

[0054] Figure 2 4 is a system block diagram of a high power supply rejection ratio low voltage dropout linear regulator circuit with dynamic bias current according to an embodiment of the present application.

[0055] Figure 3 1 is a circuit schematic diagram of a high power supply rejection ratio low voltage dropout linear regulator circuit with dynamic bias current according to an embodiment of the present application.

[0056] Figure 4 This is a PSRR performance simulation comparison diagram of a high power supply rejection ratio low dropout linear regulator circuit with dynamic bias current according to an embodiment of the present application and a traditional LDO circuit. DETAILED DESCRIPTION

[0057] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0058] Description of some concepts:

[0059] Dynamic bias current refers to the technology of dynamically adjusting the bias current in the LDO circuit according to the load and operating status. Its purpose is to optimize the power supply rejection ratio (PSRR) while ensuring low static power consumption.

[0060] High PSRR (Power Supply Rejection Ratio) refers to the high ability of an LDO to suppress input power supply ripple and noise, usually expressed in decibels (dB), and is an important indicator to measure the performance of a voltage regulator.

[0061] Low Dropout Regulator (LDO) refers to a linear voltage regulator with a small input-output voltage difference, characterized by a low dropout voltage, and is suitable for power supply systems with strict requirements for voltage ripple.

[0062] An operational amplifier, that is, an op-amp, is divided into an input stage and a second stage in this application. The input stage receives the reference voltage Vref and the feedback voltage Vfb, and the second stage cooperates with the power transistor to control the load current.

[0063] Separate power supply, in this application, it means that the input stage of the op-amp, the second stage, and the power transistor are respectively connected to different power supply domains. The input stage operates in the second power supply AVDD domain with low ripple, while the second stage and the power transistor operate in the first power supply Vin domain with larger ripple, thereby reducing the interference of power supply ripple on sensitive signals.

[0064] The current feedback loop, in this application, refers to a closed-loop control network used to collect and feedback the output current state of the LDO. It includes a Vds matching loop and an RC filter circuit, used to precisely control the working state of the power transistor and improve the PSRR in the medium and high frequency bands.

[0065] The Vds matching loop, in this application, refers to a loop that monitors the drain-source voltage of the power transistor. Through the feedback control of the op-amp, it realizes the precise regulation of the power transistor current, ensures the accuracy of the current mirror, and thus improves the PSRR in the medium and high frequency bands.

[0066] The RC filter circuit, in this application, refers to a filter network composed of a MOS transistor (such as M8) and a resistor (such as R1), used to filter out the high-frequency ripple in the input power supply and improve the current mirror accuracy.

[0067] The following briefly describes some innovative points of this application:

[0068] By deeply analyzing the bottlenecks restricting the PSRR performance of traditional LDO circuits in different frequency bands, this application creatively proposes a design idea of a heterogeneous differential input stage based on the separation of dual power supply domains, and combines it with non-linear dynamic current feedback technology. Specifically, the input stage of the first op-amp 15 operates in the second power supply voltage AVDD (i.e., the power supply with small ripple) voltage domain, while the second stage and the first power transistor MP11 operate in the first power supply voltage Vin (the power supply with larger ripple) voltage domain. This power supply separation architecture that violates the conventional design intuition generates a non-linear complex synergistic effect with the current feedback loop 13 formed by the Vds matching loop 14 and the RC filter circuit 12 composed of the first MOS transistor M8 and the first resistor R1.

[0069] Under this multi-level collaborative mechanism, the high-purity reference signal obtained by the input stage in the AVDD domain is precisely amplified by the second stage, combined with the real-time monitoring and dynamic compensation adjustment of the drain-source voltage of the first power transistor MP11 through the current feedback loop 13, achieving the key performance index of PSRR greater than 40 dB across the entire frequency band under the harsh working conditions of Vin - Vout = 150 mV and IL = 250 mA. This technical solution that combines heterogeneous voltage domain isolation and precise current feedback has breakthroughly solved the inherent technical contradiction between low-frequency high PSRR and mid-high-frequency PSRR in the traditional LDO structure, realizing a qualitative change in the overall performance while taking into account multiple performance indicators, reflecting the multi-dimensional innovation of this application in system architecture, circuit topology, and working principle.

[0070] To make the objectives, technical solutions, and advantages of this application clearer, the following will further describe the implementation manners of this application in detail with reference to the accompanying drawings.

[0071] In the specification of this application, for the sake of clearer and more concise presentation of the article, some technical features are represented by English letter codes. It should be clear that for the technical features represented only by letter codes in this application, their meanings are exactly the same as those of the technical features represented by the corresponding Chinese names plus letter codes. For example, "Vin" and "the first power supply voltage Vin" refer to the same technical feature, "AVDD" and "the second power supply voltage AVDD" refer to the same technical feature, and other technical features represented by similar English letter codes are also equivalent to their corresponding technical features represented by Chinese names plus letter codes. When reading and understanding this application, please treat the technical features represented only by letter codes as equivalent to their corresponding technical features represented by Chinese names plus letter codes. Among them, the technical features involving English letter codes include but are not limited to:

[0072] Low Dropout Regulator (LDO);

[0073] Power Supply Rejection Ratio (PSRR);

[0074] The first power transistor MP;

[0075] The first power supply voltage Vin;

[0076] Load voltage Vout;

[0077] Reference voltage Vref;

[0078] Feedback voltage Vfb;

[0079] The second power supply voltage AVDD;

[0080] The first MOS transistor M8;

[0081] The first resistor R1;

[0082] The second MOS transistor M7;

[0083] The third MOS transistor M9;

[0084] The first ESR resistor Resr; the second feedback resistor Rf1; the fourth MOS transistor M1;

[0085] The fifth MOS transistor M2;

[0086] The first current source I1;

[0087] The sixth MOS transistor M14;

[0088] The seventh MOS transistor M3;

[0089] The second resistor R4;

[0090] The eighth MOS transistor M4;

[0091] The ninth MOS transistor M5;

[0092] The tenth MOS transistor M10;

[0093] The third feedback resistor Rf2; the second current source I2;

[0094] The eleventh MOS transistor M6; the second operational amplifier amp1;

[0095] The third current source I3;

[0096] The third operational amplifier amp2;

[0097] The twelfth MOS transistor M11; the thirteenth MOS transistor M12; the fourteenth MOS transistor M13;

[0098] The first capacitor CL;

[0099] The first output resistor Ro;

[0100] The third resistor R.

[0101] The first embodiment of the present application relates to a low dropout linear regulator circuit with a dynamic bias current and high power supply rejection ratio, comprising:

[0102] The first power transistor MP, 11, has its source connected to the first power supply voltage Vin, its gate connected to the control voltage output by the operational amplifier, and its drain outputting the load voltage Vout; the first operational amplifier 15 includes an input stage and a second stage. The input stage includes a differential input pair, one end connected to the reference voltage Vref and the other end connected to the feedback voltage Vfb. The operating power supply of the input stage is the second power supply voltage AVDD, and the operating power supply of the second stage is the first power supply voltage Vin. Among them, the second power supply voltage AVDD is a power supply with small ripple, and the first power supply voltage Vin is a power supply with larger ripple; the voltage feedback loop 16 is used to feedback the feedback voltage Vfb after dividing the load voltage Vout to the input stage of the first operational amplifier 15; the current feedback loop 13 includes a Vds matching loop 14 and an RC filter circuit 12. The Vds matching loop 14 is configured to monitor the drain-source voltage of the first power transistor 11 and control its current. The RC filter circuit 12 includes a first MOS transistor M8 and a first resistor R1, which are used to improve the current mirror accuracy; the first load 17 is connected to the drain of the first power transistor 11; among them, the input stage operates in the second power supply voltage AVDD voltage domain to ensure high PSRR in the low-frequency band, and the second stage and the first power transistor 11 operate in the first power supply voltage Vin voltage domain, and high PSRR in the medium-high frequency band is ensured through the Vds matching loop 14 and the RC filter circuit 12.

[0103] Optionally, referring to Figure 3 , the gate of the first power transistor MP, 11 is connected to the gates of the second MOS transistor M7 and the third MOS transistor M9, and its drain is connected to the upper ends of the first ESR resistor Resr of the first load 17 and the second feedback resistor Rf1.

[0104] Optionally, referring to Figure 3 , the input stage of the first operational amplifier 15 includes:

[0105] The fourth MOS transistor M1 and the fifth MOS transistor M2 have their sources short-circuited and connected to the negative pole of the first current source I1 and the drain of the sixth MOS transistor M14;

[0106] The gate of the fourth MOS transistor M1 is connected to the reference voltage Vref, and its drain is connected to the gates and drain of the seventh MOS transistor M3 and the left end of the second resistor R4;

[0107] The gate of the fifth MOS transistor M2 is connected to the feedback voltage Vfb, and its drain is connected to the right end of the second resistor R4, the drain of the eighth MOS transistor M4, and the gate of the ninth MOS transistor M5;

[0108] The gate and drain of the seventh MOS transistor M3 are short-circuited, and the sources of the seventh MOS transistor M3 and the eighth MOS transistor M4 are short-circuited and grounded;

[0109] The gate of the ninth MOS transistor M5 is connected to the right end of the second resistor R4, the source is grounded, and the drain is connected to the drain of the tenth MOS transistor M10 and the gate of the third MOS transistor M9.

[0110] Optionally, referring to Figure 3 , the voltage feedback loop 16 includes:

[0111] A second feedback resistor Rf1, whose upper end is connected to the load voltage Vout, and the lower end is connected to the feedback voltage Vfb and the upper end of the third feedback resistor Rf2;

[0112] The third feedback resistor Rf2, whose upper end is connected to the feedback voltage Vfb and the lower end is grounded.

[0113] Optionally, referring to Figure 3 , in the current feedback loop 13:

[0114] The gates of the second MOS transistor M7, the third MOS transistor M9, and the first power transistor MP are short-circuited, the current mirror ratio is 1:1, and it is connected to the drain of the tenth MOS transistor M10 and the lower end of the third resistor R, and the upper end of the third resistor R is connected to the first power supply voltage Vin;

[0115] The sources of the second MOS transistor M7, the third MOS transistor M9, and the first power transistor MP are connected to the first power supply voltage Vin;

[0116] The drain of the second MOS transistor M7 is connected to the negative pole of the second current source I2, the source of the eleventh MOS transistor M6, and the negative input terminal of the second operational amplifier amp1;

[0117] The drain of the third MOS transistor M9 is connected to the negative pole of the third current source I3, the source of the tenth MOS transistor M10, and the negative input terminal of the third operational amplifier amp2;

[0118] The drain and gate of the twelfth MOS transistor M11 are short-circuited, connected to the drain of the eleventh MOS transistor M6 and the right end of the first resistor R1, and the source is grounded;

[0119] The gate of the thirteenth MOS transistor M12 is connected to the gate of the first MOS transistor M8 and the left end of the first resistor R1, and the source is grounded;

[0120] The drain and gate of the fourteenth MOS transistor M13 are short-circuited and connected to the drain of the thirteenth MOS transistor M12, and the source is connected to the second power supply voltage AVDD;

[0121] The gates of the sixth MOS transistor M14 and the fourteenth MOS transistor M13 are short-circuited, the current mirror ratio is k:1, the source is connected to the second power supply voltage AVDD, and the drain is connected to the sources of the fourth MOS transistor M1 and the fifth MOS transistor M2.

[0122] Optionally, refer to Figure 3 , the Vds matching loop 14 includes:

[0123] The second operational amplifier amp1 and the third operational amplifier amp2, whose non-inverting inputs are both connected to the load voltage Vout;

[0124] The eleventh MOS transistor M6, whose source is connected to the inverting input of the second operational amplifier amp1 and shorts the lower end of the second current source I2 and the drain of the second MOS transistor M7, the drain is connected to the drain of the twelfth MOS transistor M11, and the gate is connected to the output of the second operational amplifier amp1;

[0125] The tenth MOS transistor M10, whose source is connected to the inverting input of the third operational amplifier amp2 and shorts the lower end of the third current source I3 and the drain of the third MOS transistor M9, the drain is connected to the drain of the ninth MOS transistor M5, and the gate is connected to the output of the third operational amplifier amp2.

[0126] Optionally, in the RC filter circuit 12:

[0127] The gate of the first MOS transistor M8 is shorted to the gate of the thirteenth MOS transistor M12 and connected to the left end of the first resistor R1;

[0128] Both the source and the drain of the first MOS transistor M8 are grounded;

[0129] The right end of the first resistor R1 is connected to the gate of the twelfth MOS transistor M11.

[0130] Optionally, refer to Figure 3 , the first load 17 includes:

[0131] A first ESR resistor Resr, whose upper end is connected to the load voltage Vout and the lower end is connected to the upper end of the first capacitor CL;

[0132] The lower end of the first capacitor CL is grounded;

[0133] A first output resistor Ro, whose upper end is connected to the load voltage Vout and the lower end is grounded.

[0134] Optionally, refer to Figure 3 , Figure 4 , operating the input stage in the second power supply voltage AVDD voltage domain and operating the second stage and the first power transistor 11 in the first power supply voltage Vin voltage domain can not only ensure that the LDO has a high PSRR in the low frequency band but also improve the PSRR in the medium and high frequency bands.

[0135] In order to make the technical solution of the present invention clearer, Figures 1 to 4 The preferred embodiments of the present invention are described in detail, but it should be understood that the described embodiments are only illustrative and not restrictive.

[0136] Figure 1 FIG. 1 is a schematic diagram of an application scenario of a high power supply rejection ratio low voltage drop linear regulator circuit with dynamic bias current of this embodiment. Figure 1 As shown, the 5V voltage is converted into a 1.95V voltage through a DC / DC switching power supply, and then further adjusted to a 1.8V voltage output through the high PSRR LDO circuit of the present application. Among them, the ripple of the 1.95V output voltage of the DC / DC switching power supply is ±20mV, and the operating frequency is 1MHz. Since the LDO of the present application has a high power supply rejection ratio PSRR, the 1.95V voltage can be adjusted to a stable output voltage of 1.8V, and its ripple can be controlled within 0.5mV. In the specific application scenario described in the briefing document, the operating frequency of the DC / DC switching power supply is 1MHz, the PSRR of the LDO of the present application is 40dB, the output current Iout is 500mA, the dropout voltage (the difference between the first power supply voltage Vin and the load voltage Vout) is 150mV, and the output filter part includes a 4.7uF first capacitor CL1 and a 2.2uF second capacitor CL2. At this time, a PSRR of 40dB is equivalent to a ripple attenuation ratio of 100 times, so the ±20mV ripple of the 1.95V input voltage can be suppressed to less than 0.2mV at the 1.8V output voltage after passing through the LDO circuit of this application. It should be noted that Figure 1 The 5V to 1.8V two-stage voltage-regulated output circuit shown is only a typical application scenario of the present invention. Those skilled in the art will understand that the high power supply rejection ratio low voltage dropout linear regulator circuit with dynamic bias current of the present invention can be applied to various occasions requiring a low ripple stable output voltage.

[0137] Figure 2 FIG. 1 is a circuit system block diagram of a high power supply rejection ratio low voltage drop linear regulator circuit with dynamic bias current according to the present embodiment. Figure 2As shown in the figure, the LDO system designed in this application mainly includes a first power transistor 11, a first operational amplifier 15, a voltage feedback loop 16, a current feedback loop 13, and a first load 17. Among them, the current feedback loop 13 further includes a Vds matching loop 14 and an RC filter circuit 12. The source of the first power transistor 11 is connected to the first power supply voltage Vin, the gate is connected to the control voltage output by the first operational amplifier 15, and the drain outputs the load voltage Vout to the first load 17. The first operational amplifier 15 includes an input stage and a second stage. The input stage is used to receive the differential input signals of the reference voltage Vref and the feedback voltage Vfb, and the second stage outputs the gate voltage of the first power transistor 11 after amplifying the differential input signals. Among them, the operating power supply of the input stage uses the second power supply voltage AVDD, and the operating power supply of the second stage uses the first power supply voltage Vin. The second power supply voltage AVDD is a small-ripple power supply, and the first power supply voltage Vin is a power supply with a larger ripple. The voltage feedback loop 16 is used to feedback the feedback voltage Vfb obtained by dividing the load voltage Vout to the input stage of the first operational amplifier 15 to form a voltage feedback closed-loop control. In the current feedback loop 13, the Vds matching loop 14 is used to monitor the drain-source voltage of the first power transistor 11 and control its current, and the RC filter circuit 12 is used to ensure the mirror accuracy of the power transistor current, thereby improving the PSRR of the LDO circuit in the medium and high frequency bands. The innovation of this application lies in that the input stage and the second stage of the first operational amplifier 15 are respectively powered by different power supplies. The input stage operates in the second power supply voltage AVDD domain with small ripple to ensure that the LDO has a high PSRR in the low frequency band; while the second stage and the first power transistor 11 operate in the first power supply voltage Vin domain with larger ripple, and through the synergistic effect of the Vds matching loop 14 and the RC filter circuit 12, the PSRR performance of the LDO in the medium and high frequency bands is improved.

[0138] Figure 3 is a preferred circuit schematic diagram of the low dropout linear regulator circuit with dynamic bias current in this embodiment. As Figure 3As shown, the LDO circuit of the present application mainly includes: a first power transistor MP11, a first operational amplifier 15, a voltage feedback loop 16, a current feedback loop 13, and a first load 17. Among them, the first power transistor MP11 is a P-channel MOS transistor, whose source is connected to the first power supply voltage Vin, and the gate is connected to the gates of the second MOS transistor M7 and the third MOS transistor M9, which jointly receive the control voltage output by the operational amplifier. The drain outputs the load voltage Vout and is connected to the first ESR resistor Resr and the upper end of the second feedback resistor Rf1 of the first load 17. The input stage of the first operational amplifier 15 adopts a differential input pair consisting of a fourth MOS transistor M1 and a fifth MOS transistor M2. Among them, the gate of M1 is connected to the reference voltage Vref, the gate of M2 is connected to the feedback voltage Vfb, and the sources of the two are short-circuited and connected to the negative electrode of the first current source I1 and the drain of the sixth MOS transistor M14. The drain of the fourth MOS transistor M1 is connected to the gate and drain of the seventh MOS transistor M3, respectively, and the left end of the second resistor R4. The drain of the fifth MOS transistor M2 is connected to the right end of the second resistor R4, the drain of the eighth MOS transistor M4, and the gate of the ninth MOS transistor M5. The sources of the seventh and eighth MOS transistors M3 and M4 are both grounded, and the gate and drain of M3 are short-circuited. The source of the ninth MOS transistor M5 is grounded, and its drain is connected to the drain of the tenth MOS transistor M10 and the gate of the third MOS transistor M9, respectively, forming the second-stage input of the first operational amplifier 15. The voltage feedback loop 16 is implemented by the second feedback resistor Rf1 and the third feedback resistor Rf2. The upper end of Rf1 is connected to the load voltage Vout, the lower end is connected to the feedback voltage Vfb and the upper end of Rf2, and the lower end of Rf2 is grounded. Rf1 and Rf2 act as a voltage divider, dividing Vout and feeding it back to the input of the first operational amplifier 15. The current feedback loop 13 includes a Vds matching loop 14 and an RC filter circuit 12. The gates of the second MOS transistor M7, the third MOS transistor M9, and the first power transistor MP are short-circuited, with a current mirror ratio of 1:1:n. These gates are connected to the drain of the tenth MOS transistor M10 and to the lower end of the third resistor R, whose upper end is connected to the first power supply voltage Vin. The sources of M7, M9, and MP are all connected to the first power supply voltage Vin. The drain of M7 is connected to the negative electrode of the second current source I2, the source of the eleventh MOS transistor M6, and the negative input of the second operational amplifier amp1, respectively. The drain of M9 is connected to the negative electrode of the third current source I3, the source of M10, and the negative input of the third operational amplifier amp2. The drain and gate of the twelfth MOS transistor M11 are short-circuited, connected to the drain of M6 and the right end of the first resistor R1, and its source is grounded. The gate of the thirteenth MOS transistor M12 is connected to the gate of the first MOS transistor M8 and the left end of R1, and its source is grounded. The drain and gate of the fourteenth MOS transistor M13 are short-circuited and connected to the drain of M12, and the source is connected to the second power supply voltage AVDD. M14 is short-circuited to the gate of M13, and the current mirror ratio is k:1. The source is connected to AVDD, and the drain is connected to the sources of M1 and M2.In the Vds matching loop 14, the positive input terminals of the second operational amplifier amp1 and the third operational amplifier amp2 are both connected to the load voltage Vo. Among them, the source of M6 and the drain of M7 are both connected to the negative input terminal of amp1, the drain of M6 is connected to the drain of M11, and the gate is connected to the output terminal of amp1. Similarly, the source of M10 and the drain of M9 are both connected to the negative input terminal of amp2, the drain of M10 is connected to the drain of M5, and the gate is connected to the output terminal of amp2. In the RC filter circuit 12, the gate of the first MOS transistor M8 is connected to the gate of M12 and the left end of the first resistor R1, the source and the drain are both grounded, and the right end of R1 is connected to the gate of M11. The first load 17 includes a first ESR resistor Resr, a first capacitor CL, and a first output resistor Ro. Among them, the upper end of Resr is connected to the load voltage Vo, the lower end is connected to the upper end of CL, and the lower end of CL is grounded. The upper end of Ro is also connected to the load voltage Vo, and the lower end is grounded. The innovation of this application is to supply power to the input stage and the second stage of the first operational amplifier 15 with different power supplies, and combine the Vds matching in the current feedback loop 13 and the RC filter circuit to improve the PSRR performance of the LDO in the medium and high frequency bands while ensuring high PSRR at low frequencies.

[0139] Figure 4 It is a simulation comparison diagram of the PSRR performance between the high power supply rejection ratio low dropout linear regulator circuit with dynamic bias current in this embodiment and the traditional LDO circuit. As Figure 4 shown, the abscissa is the frequency, and the ordinate is the power supply rejection ratio PSRR, with the unit of dB. The curve marked "traditional method" in the figure represents the PSRR simulation result of the existing LDO circuit in the prior art, and the curve marked "method of this application" represents the PSRR simulation result of the LDO circuit of this application. The simulation conditions are: the PSRR performance in the full frequency band when Vin - Vout = 150 mV and IL = 250 mA. From Figure 4From the simulation results, it can be seen that in the low-frequency band of 0 - 10 kHz and the high-frequency band of > 2 MHz, the PSRR performance of the LDO of the present application is basically equivalent to that of the existing technology LDO. However, in the mid-frequency band of 10 kHz - 2 MHz, the PSRR performance of the solution of the present application is significantly better than that of the traditional method, and the power supply rejection ratio is significantly improved. The main reason for this result is that the present application adopts a structure of separate power supply for the input stage and the second stage of the first operational amplifier 15, and a current feedback loop 13 including a Vds matching loop 14 and an RC filter circuit 12 is introduced at the first power transistor 11. In the low-frequency band, the input stage operates in the second power supply voltage AVDD domain with small ripple, so as to obtain a high PSRR. In the mid-high frequency band, the second stage and the first power transistor operate in the first power supply voltage Vin domain with larger ripple, but through the Vds matching loop and the RC filter circuit, the mirror accuracy of the POWER transistor current is ensured, thereby improving the PSRR of the LDO circuit in the mid-high frequency band. The simulation results show that when the LDO of the present application operates at a low DropOut voltage of Vin - Vout = 150 mV and IL = 250 mA, the PSRR in the full frequency band is greater than 40 dB, which verifies the effectiveness of the design solution of the present application.

[0140] Working principle:

[0141] The working principle of the LDO circuit of the present application is as follows: Refer to Figure 3, the input stage of the first operational amplifier 15 is composed of a differential input pair formed by the fourth MOS transistor M1 and the fifth MOS transistor M2. Their sources are shorted and connected to the negative pole of the first current source I1 and the drain of the sixth MOS transistor M14. The input stage operates in the second power supply voltage AVDD domain. AVDD is a power supply with small ripple, ensuring that the input stage has good anti-power supply ripple interference ability when receiving the reference voltage Vref and the feedback voltage Vfb, so that the LDO obtains a high PSRR in the low-frequency band. The second stage of the first operational amplifier 15 is driven by the ninth MOS transistor M5, and its gate is driven by the current mirror load formed by M3 and M4 from the output of the differential pair M1 and M2. The second stage operates in the first power supply voltage Vin domain, and Vin is a power supply with large ripple. The drain of M5 is connected to the drain of the tenth MOS transistor M10 and the gate of the third MOS transistor M9, and the control signal is transmitted to the gate of the first power transistor MP11 to achieve the linear regulation of the LDO. In the voltage feedback loop 16, the second feedback resistor Rf1 and the third feedback resistor Rf2 divide the load voltage Vout to generate the feedback voltage Vfb, which is fed back to the gate of the M2 in the input stage of the first operational amplifier 15 to form a differential comparison with the reference voltage Vref, realizing the closed-loop regulation of the LDO output voltage. The current feedback loop 13 includes a Vds matching loop 14 and an RC filter circuit 12. Among them, the Vds matching loop 14 is realized by the second operational amplifier amp1 and the third operational amplifier amp2. Specifically, the positive input terminal of amp1 is connected to the load voltage Vo, and the negative input terminal is connected to the lower end of the second current source I2, the drain of the second MOS transistor M7, and the source of the eleventh MOS transistor M6. The gate of M6 is connected to the output terminal of amp1 to form negative feedback. Similarly, the positive input terminal of amp2 is connected to the load voltage Vo, and the negative input terminal is connected to the lower end of the third current source I3, the drain of the third MOS transistor M9, and the source of the tenth MOS transistor M10. The gate of M10 is connected to the output terminal of amp2, also forming negative feedback. This configuration ensures that the drain-source voltages of M6 and M10 match the drain-source voltage of the first power transistor MP. In the RC filter circuit 12, the gates of the first MOS transistor M8 and the thirteenth MOS transistor M12 are shorted and connected to the left end of the first resistor R1. The source and drain are grounded, and the right end of the first resistor R1 is connected to the gate of the twelfth MOS transistor M11. M8 and R1 form an RC low-pass filter to filter out the high-frequency noise in the current signal and further improve the current mirroring accuracy. The gates of the second MOS transistor M7, the third MOS transistor M9, and the first power transistor MP are shorted, and the current mirroring ratio is 1:1:n, ensuring that their gate-source voltages are the same and forming an accurate current mirroring relationship. The current mirror is composed of the fourteenth MOS transistor M13 and the sixth MOS transistor M14, with a ratio of k:1, providing a stable bias current for the input stage.By placing the input stage of the first operational amplifier 15 in the second power supply voltage AVDD domain with small ripple, the second stage and the first power transistor MP in the first power supply voltage Vin domain, and using the Vds matching loop 14 and the RC filter circuit 12 to ensure the mirror accuracy of the power transistor current, the LDO of the present application achieves a PSRR performance higher than 40 dB in the full frequency band, especially improving the PSRR performance in the medium and high frequency bands of 10 kHz - 2 MHz.

[0142] To better understand the technical solution of the present application, a specific example will be described below. The details listed in this example are mainly for easy understanding and do not limit the protection scope of the present application.

[0143] As Figure 2 shown, the high power supply rejection ratio low dropout linear regulator circuit with dynamic bias current in this example includes a power transistor 11, a two-stage operational amplifier 15, a voltage feedback 16 loop, a current feedback 13 loop. The current feedback 13 loop includes a Vds matching loop 14, an RC filter circuit 12, and a load 17. The main control system includes a power transistor 11 and a two-stage operational amplifier 15. Through the voltage feedback 16 loop and the current feedback 13 loop, dual closed-loop control of the voltage and current of the main control system is achieved.

[0144] The circuit diagram of the high power supply rejection ratio low dropout linear regulator circuit with dynamic bias current in this example is as Figure 3 shown. The power supply of the five-transistor operational amplifier is separated from the power supplies of the second-stage operational amplifier and the power transistor, and the five-transistor operational amplifier operates in the AVDD voltage domain, where AVDD is a power supply with small ripple, to ensure that the LDO circuit has a high PSRR in the low frequency band. The second-stage operational amplifier and the power transistor operate in the Vin voltage domain, where Vin is a power supply with large ripple. Through the Vds matching loop and the RC filter circuit composed of MOS transistor M8 and resistor R1, the mirror accuracy of the power transistor current is ensured, thereby improving the PSRR of the LDO circuit in the medium and high frequency bands. The simulation results show that the LDO in this example operates at a low DropOut voltage Vin - Vout = 150 mV and IL = 250 mA, and the PSRR in the full frequency band is greater than 40 dB.

[0145] Furthermore, as Figure 3 shown, in the high power supply rejection ratio low dropout linear regulator circuit with dynamic bias current in this example, the power supply of the five-transistor operational amplifier is separated from the power supplies of the second-stage operational amplifier and the power transistor, and the five-transistor operational amplifier operates in the AVDD (power supply with small ripple) voltage domain to ensure that the LDO circuit has a high PSRR in the low frequency band. The second-stage operational amplifier and the power transistor operate in the Vin (power supply with large ripple) voltage domain. Through the Vds matching loop and the RC filter circuit composed of MOS transistor M8 and resistor R1, the mirror accuracy of the power transistor current is ensured, thereby improving the PSRR of the LDO circuit in the medium and high frequency bands.

[0146] Power transistor MP11, whose source is connected to the power supply Vin, whose gate is connected to the gates of MOS transistors M7 and M9, and whose drain is connected to the output Vout of the LDO, the upper end of resistor Rf1, the upper end of the ESR resistor Resr, and the upper end of the output resistor.

[0147] Second-stage operational amplifier 15, whose structure includes: input transistors M1 and M2, the sources of MOS transistors M1 and M2 are short-circuited and connected to the negative pole of current I1 and the drain of M14; the gate of MOS transistor M1 is connected to the Vref voltage, and the drain of MOS transistor M1 is connected to the gate, drain of M3 and the left end of resistor R4; the gate of MOS transistor M2 is connected to the Vfb voltage, and the drain of MOS transistor M2 is connected to the right end of resistor R4, the drain of MOS transistor M4 and the gate of MOS transistor M5; the gate and drain of MOS transistor M3 are short-circuited, and the sources of MOS transistors M3 and M4 are short-circuited and grounded; the gate of MOS transistor M5 is connected to the right end of resistor R4, the source of MOS transistor M5 is grounded, and the drain of the MOS transistor is connected to the drain of MOS transistor M10 and the gate of MOS transistor M9.

[0148] Voltage feedback 16 loop, whose structure includes: the upper end of resistor Rf1 is connected to Vout, the lower end is connected to the Vfb voltage and the upper end of resistor Rf2; the lower end of resistor Rf2 is grounded.

[0149] Current feedback 13 loop, whose structure includes: the gates of MOS transistors M7, M9, and MP are short-circuited together, the current mirror ratio is 1:1, connected to the drain of MOS transistor M10, and connected to the lower end of resistor R, the upper end of resistor R is connected to the power supply Vin; the sources of MOS transistors M7, M9, and MP are connected to the power supply Vin, the gate of MOS transistor M7 is connected to the negative pole of current mirror I2, the source of MOS transistor M6, and the negative input terminal of operational amplifier amp1; the drain of MOS transistor M9 is connected to the negative pole of current mirror I3, the source of MOS transistor M10, and the negative input terminal of operational amplifier amp2; the drain and gate of MOS transistor M11 are short-circuited, connected to the drain of MOS transistor M6 and the right end of resistor R1; the source of MOS transistor M11 is grounded; the gate of MOS transistor M12 is connected to the gate of MOS transistor M8 and the left end of resistor R1; the source of MOS transistor M12 is grounded, and the current mirror ratio of MOS transistors M11 and M12 is 1:1; the drain and gate of MOS transistor M13 are short-circuited and connected to the drain of MOS transistor M12, the source of MOS transistor M13 is connected to the power supply AVDD; the gates of MOS transistors M14 and M13 are short-circuited, and the current mirror ratio is k:1; the source of MOS transistor M14 is connected to the power supply AVDD; the drain of MOS transistor M14 is connected to the sources of MOS transistors M1 and M2.

[0150] The Vds matching loop 14 has a structure including: the source of MOS transistor M6 is connected to the inverting input terminal of operational amplifier amp1, and the lower end of current source I2 and the drain of MOS transistor M7 are shorted; the drain of MOS transistor M6 is connected to the drain of MOS transistor M11, and the gate of MOS transistor M6 is connected to the upper end of the output of operational amplifier amp1; the non-inverting input terminal of operational amplifier amp1 is connected to the output Vo of the LDO; similarly, the source of MOS transistor M10 is connected to the inverting input terminal of operational amplifier amp2, and the lower end of current source I3 and the drain of MOS transistor M9 are shorted; the drain of MOS transistor M10 is connected to the drain of MOS transistor M5, and the gate of MOS transistor M10 is connected to the upper end of the output of operational amplifier amp2; the non-inverting input terminal of operational amplifier amp2 is connected to the output Vo of the LDO.

[0151] The RC filter circuit 12 has a structure including: the gate of MOS transistor M8 is connected to the gate of MOS transistor M12 and shorted to the left end of resistor R1; the source and drain of MOS transistor M8 are both grounded; the right end of resistor R1 is connected to the gate of MOS transistor M11.

[0152] The load 17 has a structure including: the upper end of the ESR resistor Resr is connected to the output Vo of the LDO, the lower end of Resr is connected to the upper end of the capacitor; the lower end of the capacitor is connected to the ground; the upper end of the output resistor Ro is connected to the output Vo of the LDO; the lower end of the output resistor Ro is connected to the ground.

[0153] The simulation results are as Figure 4 shown. The comparison result graph of the simulation results between the traditional method and the technical solution of this example. It can be seen from the figure that in the low frequency band (0 - 10 kHz) and the high frequency band (> 2 MHz), the PSRR of the two methods is about the same. In the medium frequency band (10 kHz - 2 MHz), the PSRR of the method of this design is significantly higher than that of the traditional method, and the PSRR is significantly improved.

[0154] Compared with the prior art, the beneficial effects of this example are as follows:

[0155] Different from the traditional dynamic bias current LDO circuit, in this example, the power supply of the five-transistor operational amplifier is separated from the power supplies of the second-stage operational amplifier and the power transistor, which not only ensures that the LDO has a high PSRR in the low frequency band,

[0156] but also improves the PSRR in the medium and high frequency bands.

[0157] The above embodiments have the following technical effects:

[0158] By placing the input stage and the second stage of the first operational amplifier 15 in different power supply domains respectively, that is, the input stage operates in the domain of the second power supply voltage AVDD with small ripple, and the second stage and the first power transistor MP11 operate in the domain of the first power supply voltage Vin with larger ripple, it ensures that the LDO has a high PSRR in the low frequency band. This power supply separation design enables the input stage to be free from the interference of power supply ripple when processing the reference voltage Vref and the feedback voltage Vfb.

[0159] Introducing a current feedback loop 13, including a Vds matching loop 14 and an RC filter circuit 12, significantly improves the PSRR performance of the LDO in the medium and high frequency bands. As Figure 4 shown, in the medium frequency band from 10 kHz to 2 MHz, the PSRR of the solution of this application is significantly better than that of the traditional method. This is mainly due to the precise control of the drain-source voltage of the first power transistor MP11 by the Vds matching loop, and the improvement of the current mirror accuracy by the RC filter circuit.

[0160] The simulation results show that under the working conditions of the dropout voltage Vin - Vout = 150 mV and the output current IL = 250 mA of the LDO of this application, the PSRR in the full frequency band reaches more than 40 dB. Compared with the traditional LDO, this application not only ensures a high PSRR in the low frequency band but also improves the PSRR in the medium and high frequency bands.

[0161] This application solves the problem of insufficient PSRR performance in the medium and high frequencies caused by the sharing of the same power supply by the operational amplifier and the power transistor in the traditional LDO through the structure of separate power supply for the input stage and the second stage of the first operational amplifier 15.

[0162] By the Vds matching loop 14 and the RC filter circuit 12 composed of the first MOS transistor M8 and the first resistor R1, the mirror accuracy of the current of the first power transistor MP11 is ensured, effectively improving the PSRR of the LDO circuit in the medium and high frequency bands.

[0163] In summary, the high-PSRR LDO design based on dynamic bias current of this application realizes high-PSRR performance in the full frequency band through the optimized configuration of separate power supply for the first operational amplifier 15 and the current feedback loop 13, especially improving the PSRR performance in the medium and high frequency bands, providing a better solution for electronic systems requiring high-quality power supply.

[0164] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one" does not exclude the presence of additional identical elements in the process, method, article or device comprising said element. In the application documents of this patent, if it is mentioned that an act is performed according to a certain element, it means that the act is performed at least according to that element, including two cases: the act is performed only according to that element, and the act is performed according to that element and other elements. Expressions such as multiple, many times, various, etc. include 2, 2 times, 2 kinds, and more than 2, more than 2 times, more than 2 kinds.

[0165] All documents mentioned in this application are considered to be integrally included in the disclosure of this application so as to be used as a basis for modification if necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art can make various changes or modifications to this application, and these equivalent forms also fall within the scope claimed by this application.

Claims

1. A low dropout linear regulator circuit with a dynamic bias current and a high power supply rejection ratio, characterized in that, Comprising: A first power transistor (MP), whose source is connected to a first power supply voltage (Vin), the gate is connected to a control voltage output by an operational amplifier, and the drain outputs a load voltage (Vout); A first operational amplifier, including an input stage and a second stage, the input stage includes a differential input pair, one end is connected to a reference voltage (Vref), the other end is connected to a feedback voltage (Vfb), the operating power supply of the input stage is a second power supply voltage (AVDD), the operating power supply of the second stage is the first power supply voltage, wherein the second power supply voltage is a small-ripple power supply, and the first power supply voltage is a power supply with a larger ripple; A voltage feedback loop for feeding back the feedback voltage after dividing the load voltage to the input stage of the first operational amplifier; A current feedback loop, including a Vds matching loop and an RC filter circuit, the Vds matching loop is configured to monitor the drain-source voltage of the first power transistor and control its current, the RC filter circuit includes a first MOS transistor (M8) and a first resistor (R1) for improving the current mirror accuracy; A first load connected to the drain of the first power transistor; Wherein, the input stage operates in the second power supply voltage domain to ensure high PSRR in the low-frequency band, the second stage and the first power transistor operate in the first power supply voltage domain, and high PSRR in the medium and high-frequency bands is ensured by the Vds matching loop and the RC filter circuit.

2. The low dropout linear regulator circuit with a dynamic bias current as claimed in claim 1, wherein The gate of the first power transistor is connected to the gates of a second MOS transistor (M7) and a third MOS transistor (M9), and its drain is connected to the upper ends of a first ESR resistor (Resr) of the first load and a second feedback resistor (Rf1).

3. The low dropout linear regulator circuit with a dynamic bias current as described in claim 1, characterized in that, The input stage of the first operational amplifier includes: A fourth MOS transistor (M1) and a fifth MOS transistor (M2), whose sources are short-circuited and connected to the negative pole of a first current source (I1) and the drain of a sixth MOS transistor (M14); The gate of the fourth MOS transistor is connected to the reference voltage, and the drain is connected to the gates and drains of a seventh MOS transistor (M3) and the left end of a second resistor (R4); The gate of the fifth MOS transistor is connected to the feedback voltage, and the drain is connected to the right end of the second resistor, the drain of an eighth MOS transistor (M4), and the gate of a ninth MOS transistor (M5); The gate and drain of the seventh MOS transistor are short-circuited, and the sources of the seventh MOS transistor and the eighth MOS transistor are short-circuited and grounded; The gate of the ninth MOS transistor is connected to the right end of the second resistor, the source is grounded, and the drain is connected to the drain of a tenth MOS transistor (M10) and the gate of the third MOS transistor.

4. The high power supply rejection ratio low dropout linear regulator circuit with dynamic bias current as claimed in claim 1, wherein The voltage feedback loop includes: A second feedback resistor (Rf1), whose upper end is connected to the load voltage, and the lower end is connected to the feedback voltage and the upper end of a third feedback resistor (Rf2); The third feedback resistor, whose upper end is connected to the feedback voltage and the lower end is grounded.

5. The high power supply rejection ratio low dropout linear regulator circuit with dynamic bias current as claimed in claim 1, wherein In the current feedback loop: The gates of the second MOS transistor, the third MOS transistor, and the first power transistor are short-circuited, the current mirror ratio is 1:1, connected to the drain of the tenth MOS transistor and connected to the lower end of a third resistor (R), and the upper end of the third resistor is connected to the first power supply voltage; The sources of the second MOS transistor, the third MOS transistor, and the first power transistor are connected to the first power supply voltage; The drain of the second MOS transistor is connected to the negative electrode of the second current source (I2), the source of the eleventh MOS transistor (M6), and the negative input terminal of the second operational amplifier (amp1); The drain of the third MOS transistor is connected to the negative electrode of the third current source (I3), the source of the tenth MOS transistor, and the negative input terminal of the third operational amplifier (amp2); The drain and gate of the twelfth MOS transistor (M11) are short-circuited, connected to the drain of the eleventh MOS transistor and the right end of the first resistor, and the source is grounded; The gate of the thirteenth MOS transistor (M12) is connected to the gate of the first MOS transistor and the left end of the first resistor, and the source is grounded; The drain and gate of the fourteenth MOS transistor (M13) are short-circuited and connected to the drain of the thirteenth MOS transistor, and the source is connected to the second power supply voltage; The gates of the sixth MOS transistor and the fourteenth MOS transistor are short-circuited, the current mirror ratio is k:1, the sources are connected to the second power supply voltage, and the drains are connected to the sources of the fourth MOS transistor and the fifth MOS transistor.

6. The high power supply rejection ratio low dropout linear regulator circuit with dynamic bias current as claimed in claim 1, wherein The Vds matching loop includes: The second operational amplifier and the third operational amplifier, whose positive input terminals are both connected to the load voltage; The eleventh MOS transistor, whose source is connected to the negative input terminal of the second operational amplifier and short-circuits the lower end of the second current source and the drain of the second MOS transistor, the drain is connected to the drain of the twelfth MOS transistor, and the gate is connected to the output terminal of the second operational amplifier; The tenth MOS transistor, whose source is connected to the negative input terminal of the third operational amplifier and short-circuits the lower end of the third current source and the drain of the third MOS transistor, the drain is connected to the drain of the ninth MOS transistor, and the gate is connected to the output terminal of the third operational amplifier.

7. The low dropout linear regulator circuit with dynamic bias current as described in claim 1, characterized in that, In the RC filter circuit: The gates of the first MOS transistor and the thirteenth MOS transistor are short-circuited and connected to the left end of the first resistor; Both the source and the drain of the first MOS transistor are grounded; The right end of the first resistor is connected to the gate of the twelfth MOS transistor.

8. The high power supply rejection ratio low dropout linear regulator circuit with dynamic bias current according to claim 1, characterized in that The first load includes: A first ESR resistor (Resr), whose upper end is connected to the load voltage, and the lower end is connected to the upper end of the first capacitor (CL); The lower end of the first capacitor is grounded; A first output resistor (Ro), whose upper end is connected to the load voltage and the lower end is grounded.

9. The high power supply rejection ratio low dropout linear regulator circuit with dynamic bias current as claimed in claim 1, wherein Operating the input stage in the second power supply voltage domain and operating the second stage and the first power transistor in the first power supply voltage domain not only ensures that the low dropout linear regulator (LDO) has high PSRR in the low frequency band, but also improves the PSRR in the medium and high frequency bands.

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