Storage circuit, control method and control chip

Abstract

The invention discloses a storage circuit, a control method and a control chip. The storage circuit comprises a memory and a control circuit. The memory comprises a storage block and a backup block. The storage block stores a plurality of data sets. When an erasing request selects at least one data group in the plurality of data groups, the control circuit erases the backup block, copies all data groups which are not selected by the erasing request to the backup block, and activates the backup block to replace the storage block. After the backup block is activated, when an access request points to the storage block, the control circuit accesses the backup block.

Description

Technical Field

[0001] The present invention relates to a storage circuit, and more particularly to a storage circuit capable of erasing a specific data set on a specific page. Background Art

[0002] Generally, an electronic device usually has a memory for storing many settings, such as voltage settings. Since the erasing operation of the memory must clear an entire page at a time, the existing practice is to store the same type of attributes in the same page, which however results in a decrease in the utilization of the memory, wastes storage space, and increases costs. Summary of the Invention

[0003] The present invention provides a storage circuit, including a memory and a control circuit. The memory includes a storage block and a backup block. The storage block stores a plurality of data sets. When an erasing request selects at least one of the plurality of data sets, the control circuit erases the backup block, copies all the data sets not selected by the erasing request to the backup block, and activates the backup block to replace the storage block. After activating the backup block, when an access request points to the storage block, the control circuit accesses the backup block.

[0004] The present invention further provides a control method applicable to a storage circuit. The storage circuit has a first page and a second page. The control method of the present invention includes storing a plurality of data sets in the first page; when an erasing request selects at least one of the plurality of data sets, erasing the second page, copying all the data sets not selected by the erasing request to the second page, and activating the second page to replace the first page. After activating the second page, when an access request points to the first page, access the second page.

[0005] The present invention still further provides a control chip, including a main control circuit, a transmission circuit, and a storage circuit. The main control circuit issues an erasing request and an access request. The transmission circuit is coupled to the main control circuit for transmitting the erasing request and the access request. The storage circuit is coupled to the transmission circuit and includes a slave interface, a non-volatile memory, and a control circuit. The slave interface is coupled to the transmission circuit for receiving the erasing request and the access request. The non-volatile memory includes a storage block and a backup block. The storage block stores a plurality of data sets. The control circuit receives the erasing request and the access request from the transmission circuit through the slave interface. When the erasing request selects at least one of the plurality of data sets, the control circuit erases the backup block, copies all the data sets not selected by the erasing request to the backup block, and activates the backup block. After activating the backup block, when the access request points to the storage block, the control circuit accesses the backup block.

[0006] The control method of the present invention can be implemented via the storage circuit and control chip of the present invention, which are hardware or firmware capable of executing specific functions, or can be incorporated in a recording medium in the form of program code and implemented in combination with specific hardware. When the program code is loaded and executed by an electronic device, a processor, a computer or a machine, the electronic device, the processor, the computer or the machine becomes the storage circuit and control chip for implementing the present invention.

[0007] When an erase request selects at least one data group of a storage block, the control circuit copies all data groups not selected by the erase request to a backup block. Since the backup block stores all data groups not selected by the erase request, it is equivalent to only erasing the selected data groups. Since the control circuit does not actually need to erase all data groups of the storage block, the number of erasures of the storage block can be reduced, and the lifespan of the storage block can be extended. Description of the Drawings

[0008] Figure 1 Schematic diagram of the control chip of the present invention.

[0009] Figure 2 Schematic diagram of the storage circuit of the present invention.

[0010] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D Schematic diagram of the operation of the storage circuit of the present invention.

[0011] Figure 4 Schematic diagram of the flow of the control method of the present invention.

[0012] Symbol Description

[0013] 100: Control chip

[0014] 110: Main control circuit

[0015] 120: Bus circuit

[0016] 130: Storage circuit

[0017] 121: Advanced Extensible Interface Transfer Circuit

[0018] 122: Conversion circuit

[0019] 123: High-Performance Advanced Transfer Circuit

[0020] 210: Slave interface

[0021] 220: Control circuit

[0022] 230: Memory

[0023] 231, 232: Storage blocks

[0024] CFG0 to CFGn: data group

[0025] act_0, act_1: activation flag

[0026] old_0, old_1: page flag

[0027] S411 to S414: steps Detailed implementation manner

[0028] To make the objectives, features, and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings. The description of the present invention provides different embodiments to illustrate the technical features of different implementation manners of the present invention. Among them, the configuration of each component in the embodiments is for illustrative purposes and is not intended to limit the present invention. In addition, the partial repetition of the reference numerals in the drawings of the embodiments is for the purpose of simplifying the description and does not imply the relevance between different embodiments.

[0029] Figure 1 It is a schematic diagram of the control chip of the present invention. As shown in the figure, the control chip 100 includes a main control circuit 110, a bus circuit 120, and a storage circuit 130. The main control circuit 110 erases or accesses the data of the storage circuit 130 through the bus circuit 120. In a possible embodiment, the main control circuit 110 issues an erase request through the bus circuit 120, requesting the storage circuit 130 to delete the corresponding data. In another possible embodiment, the main control circuit 110 issues an access request through the bus circuit 120, requesting the storage circuit 130 to provide the corresponding data or store the corresponding data.

[0030] The present invention does not limit the number of main control circuits. In other embodiments, the control chip 100 has more main control circuits. In addition, the present invention also does not limit the type of the main control circuit 110. In a possible embodiment, the main control circuit 110 is a central processing unit (CPU) or a neural network computing accelerator (NPU).

[0031] The bus circuit 120 is coupled between the main control circuit 110 and the storage circuit 130 for signal and data transmission. For example, the bus circuit 120 may provide the erase request or access request issued by the main control circuit 110 to the storage circuit 130, or provide the output of the storage circuit 130 to the main control circuit 110. The present invention does not limit the architecture of the bus circuit 120. In a possible embodiment, the bus circuit 120 includes an Advanced eXtensible Interface (AXI) transmission circuit 121, a conversion circuit 122, and an advanced high performance bus (AHB) transmission circuit 123.

[0032] The AXI transmission circuit 121 is coupled between the main control circuit 110 and the conversion circuit 122. The conversion circuit 122 is used to perform the conversion between the AXI transmission protocol and the AHB transmission protocol. For example, the conversion circuit 122 may convert the signals on the AXI transmission circuit 121 from the AXI protocol to the AHB protocol, and then provide the converted result to the AHB transmission circuit 123. In another possible embodiment, the conversion circuit 122 converts the signals on the AHB transmission circuit 123 from the AHB protocol to the AXI protocol, and then provides the converted result to the AXI transmission circuit 121. The AHB transmission circuit 123 is coupled between the conversion circuit 122 and the storage circuit 130.

[0033] The storage circuit 130 is coupled to the bus circuit 120 and operates according to the requirements of the main control circuit 110. Figure 2 It is a schematic diagram of the storage circuit 130 of the present invention. As shown in the figure, the storage circuit 130 includes a slave interface 210, a control circuit 220, and a memory 230. The slave interface 210 is coupled to the bus circuit 120 for receiving an erase request or an access request from the main control circuit 110.

[0034] The control circuit 220 is coupled between the slave interface 210 and the memory 230, and accesses the memory 230 according to the requirements from the main control circuit 110. The present invention does not limit the type of the memory 230. In a possible embodiment, the memory 230 is a non-volatile memory, such as a read-only memory (ROM) or a flash memory. In another possible embodiment, the memory 230 is a volatile memory, such as a random access memory (RAM).

[0035] The memory 230 includes storage blocks 231 and 232, but it is not used to limit the present invention. The present invention does not limit the number of storage blocks. In other embodiments, the memory 230 has more storage blocks. In some embodiments, each storage block is a page. For example, the storage block 231 is a first page, and the storage block 232 is a second page. In another possible embodiment, each storage block has multiple pages.

[0036] The control circuit 220 writes data into the storage blocks 231 or 232 according to the access requests issued by the main control circuit 110. Assume that the storage block 231 is a valid block. In this example, the control circuit 220 writes the data groups CFG0 to CFGn into the storage block 231. The present invention does not limit the number of bits of each data group. In a possible embodiment, the data groups CFG0 to CFGn have the same number of bits, such as one word. In another possible embodiment, the number of bits of at least one of the data groups CFG0 to CFGn is different from that of another one of the data groups CFG0 to CFGn.

[0037] When an erase request selects at least one data group (such as CFG1) from the data groups CFG0 to CFGn, the control circuit 220 erases the storage block 232, and copies all the data groups that are not selected by the erase request (i.e., CF0, CFG2 to CFGn) except the selected data group (such as CFG1) to the storage block 232. After completing the copy operation, the control circuit 220 activates the storage block 232, and uses the storage block 232 to replace the storage block 231.

[0038] After activating the storage block 232, when an access request points to the storage block 231, the control circuit 220 accesses the storage block 232. For example, when the access request points to the data group CFG0 of the storage block 231, the control circuit 220 reads the data group CFG0 of the storage block 232 and outputs it through the slave interface 210. When the access request wants to write an external data to the storage block 231, the control circuit 220 writes the external data into the storage block 232. In this embodiment, the control circuit 220 copies the data groups of the storage block 231 (except the data group selected by the erase request) to the storage block 232, so the storage block 232 is called a backup block.

[0039] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D is a schematic diagram of the operation of the storage circuit 130 of the present invention. Please refer to Figure 3A, during an initial period, the control circuit 220 erases storage blocks 231 and 232. For example, after a mass erase operation, each storage unit in storage blocks 231 and 232 stores the value FFFF. In some embodiments, the control circuit 220 sets the value of the activation flag act_0 equal to 1 (or a specific value) according to an initial setting to indicate that storage block 231 is a valid block. Additionally, the control circuit 220 sets the value of the activation flag act_1 equal to 0 according to the initial setting to indicate that storage block 232 is an invalid block. In a possible embodiment, the main control circuit 110 may write an initial setting into the control circuit 220 through the bus circuit 120.

[0040] Next, please refer to Figure 3B , when an access request requests the control circuit 220 to store data groups CFG0 to CFGn, since storage block 231 is a valid block, the control circuit 220 writes data groups CFG0 to CFGn into storage block 231. When the control circuit 220 receives an erase request and the erase request selects data group CFG1, the control circuit 220 erases storage block 232 to avoid residual data in storage block 232.

[0041] Next, please refer to Figure 3C , after erasing storage block 232, the control circuit 220 performs a backup operation, backs up all data groups CFG0 and CFG2 to CFGn except data group CFG1 to storage block 232, and activates storage block 232. Since the control circuit 220 previously erased storage block 232, the residual data in storage block 232 can be avoided from affecting data groups CFG0 and CFG2 to CFGn.

[0042] After completing the backup operation, the control circuit 220 sets the value of the activation flag act_1 equal to the value 1 to indicate that storage block 232 is a valid block. Additionally, after completing the backup operation, the control circuit 220 sets the value of the activation flag act_0 equal to the value 0. In this example, before completing the backup operation, the value of the activation flag act_0 is equal to the value 1.

[0043] In this embodiment, the storage block 232 stores all data groups CFG0 and CFG2 to CFGn other than the data group CFG1, which is equivalent to only erasing the data group CFG1. Since the control circuit 220 does not need to erase all data groups in the storage block 231, the number of erasures of the storage block 231 can be reduced, and the lifespan of the storage block 231 can be extended. Therefore, when an access request points to the storage block 231, since the value of the activation flag act_1 is equal to a specific value, the control circuit 220 accesses the storage block 232. In other embodiments, when an access request points to the storage block 231, if the value of the activation flag act_1 is not equal to the specific value and the value of the activation flag act_0 is equal to the specific value, the control circuit 220 accesses the storage block 231.

[0044] The states of the activation flags act_0 and act_1 are shown in Table 1 below:

[0045] Table 1

[0046] act_0 act_1 valid block return 0 0 231 error 0 1 232 correct 1 0 231 correct 1 1 231 error

[0047] When the values of the activation flags act_0 and act_1 are 00, it indicates that an abnormal event has occurred, such as the failure of the full erasure operation of the control circuit 220. Therefore, the control circuit 220 reports an error message to the main control circuit 110 and regards the storage block 231 as a valid block.

[0048] In a possible embodiment, when an abnormal event occurs, the control circuit 220 rejects access requests from outside the control chip 100. For example, the control chip 100 has a debugging interface (not shown) for coupling to a debugging device (not shown). When an abnormal event occurs, the control circuit 220 rejects any instructions from the debugging device.

[0049] When the activation flags act_0 and act_1 are 01, it indicates that the control circuit 220 has copied the unselected data group to the storage block 232. Therefore, the control circuit 220 regards the storage block 232 as a valid block. When an access request points to the storage block 231, the control circuit 220 accesses the storage block 232. In this example, the storage block 232 replaces the storage block 231. Although the data groups in the storage block 231 are still retained, the control circuit 220 no longer uses the storage block 231.

[0050] When the activation flags act_0 and act_1 are 10, it indicates that the control circuit 220 has not copied the data group to the storage block 232. Therefore, the control circuit 220 sets the value of the activation flag act_1 to 0 and regards the storage block 231 as a valid block. When an access request points to the storage block 231, the control circuit 220 accesses the storage block 231.

[0051] When the activation flags act_0 and act_1 have the value 11, it indicates that an abnormal phenomenon has occurred. For example, before the control circuit 220 changes the value of the activation flag act_0 from 1 to 0, an interruption event (such as a power interruption) occurs. Therefore, the control circuit 220 reports an error message to the main control circuit 110 and designates the storage block 231 as a valid block.

[0052] In some embodiments, when an access request points to the storage block 231, the control circuit 220 accesses a valid block (storage block 231 or 232). For example, when the storage block 231 is a valid block, the control circuit 220 accesses the storage block 231 according to the access request, such as writing data to the storage block 231 or outputting the data group stored in the storage block 231. However, when the storage block 232 is a valid block, the control circuit 220 accesses the storage block 232, such as writing data to the storage block 232 or outputting the data group stored in the storage block 232.

[0053] In other embodiments, the control circuit 220 further sets the page flags old_0 and old_1. For example, please refer to Figure 3A , during initialization, after the control circuit 220 erases the storage blocks 231 and 232, it sets the values of the page flags old_0 and old_1 to the value 0.

[0054] Please refer to Figure 3B , after the control circuit 220 writes the data groups CFG0 to CFGn to the storage block 231, the control circuit 220 does not change the values of the page flags old_0 and old_1.

[0055] In Figure 3C , after the control circuit 220 copies the data groups CFG0 and CFG2 to CFGn to the storage block 232, the control circuit 220 sets the value of the page flag old_0 to 1, indicating that the storage block 231 is an old block. The control circuit 220 maintains the value of the page flag old_1 as 0. In some embodiments, after the control circuit 220 copies the data groups CFG0 and CFG2 to CFGn to the storage block 232, the control circuit 220 first sets the value of the page flag old_0 to 1 and then sets the value of the activation flag act_1 to 1.

[0056] In Figure 3DIn it, after the control circuit 220 sets the value of the activation flag act_1 to 1, the control circuit 220 maintains the value of the activation flag act_0 as 1. In this example, even though the value of the activation flag act_0 is 1, since the value of the page flag old_0 is 1, it indicates that the storage block 231 is an old block. Therefore, the control circuit 220 no longer accesses the storage block 231. At this time, the value of the activation flag act_1 is equal to 1, indicating that the storage block 232 is a valid block. Therefore, when an access request points to the storage block 231, the control circuit 220 uses the storage block 232 to replace the storage block 231.

[0057] The states of the activation flags act_0, act_1 and the page flags old_0, old_1 are shown in Table 2A as follows:

[0058] Table 2A

[0059]

[0060]

[0061] When both the activation flags act_0 and act_1 are the value 0, it indicates that an abnormal phenomenon occurs, such as a power interruption of the storage circuit 130. In addition, when the full erasure operation of the control circuit 220 fails, the activation flags act_0 and act_1 may both be the value 0. Therefore, the control circuit 220 reports an error message to the main control circuit 110 and regards the storage block 231 as a valid block.

[0062] When the activation flags act_0 and act_1 are the value 01, it indicates that the storage block 232 stores valid data. Therefore, the control circuit 220 ignores the values of the page flags old_0 and old_1 and regards the storage block 232 as a valid block.

[0063] In some embodiments, after a full erasure operation, the control circuit 220 first sets the value of the activation flag act_0 corresponding to the storage block 231 to 1 to set the storage block 231 as a main block. At this time, when an erasure request selects a specific data group (such as CFG1) of the storage block 231, the control circuit 220 backs up all data groups other than the specific data group (such as CFG0, CFG2 to CFGn) to the storage block 232. After completing the backup operation, the control circuit 220 first sets the value of the page flag old_0 corresponding to the storage block 231 to the value 1 (indicating that the storage block 231 is an old block), and then sets the value of the activation flag act_1 corresponding to the storage block 232 to 1. In this example, the values of the activation flag act_0, the page flag old_0, and the activation flag act_1 are sequentially set to 1. When the value of the activation flag act_0 is 0, the values of the page flag old_0 and the page flag old_1 are not set to 1. Therefore, in Table 2A, the cases where the activation flag act_0, the page flag old_0, the activation flag act_1, and the page flag old_1 are 0001, 0100, 0101, 0110, and 0111 do not exist.

[0064] In other embodiments, another state of the activation flags act_0, act_1 and the page flags old_0, old_1 is shown in Table 2B below:

[0065] Table 2B

[0066]

[0067]

[0068] When both activation flags act_0 and act_1 are 1, the control circuit 220 reads the page flags old_0, old_1. In a possible embodiment, if the page flag old_0 is 0, it indicates that an interrupt event has occurred, causing the control circuit 220 not to set the page flag old_0 to 1. Therefore, the control circuit 220 reports an error message and treats the storage block 231 as a valid block. In another possible embodiment, when both page flags old_0 and old_1 are all 1, it indicates that an abnormal event has occurred. Therefore, the control circuit 220 reports an error message and treats the storage block 231 as a valid block. In other embodiments, when the values of the page flags old_0 and old_1 are 10, it indicates that the storage block 231 is an old block. Therefore, the control circuit 220 treats the storage block 232 as a valid block. In this example, when an access request points to the storage block 231, the control circuit 220 accesses the storage block 231.

[0069] When the activation flags act_0 and act_1 have a value of 10, it indicates that the storage block 232 has not stored valid data. Therefore, the control circuit 220 regards the storage block 231 as a valid block. When the activation flags act_0 and act_1 have a value of 11, if the page flags old_0 and old_1 have a value of 10, it means that the storage block 231 is an old block, so the control circuit 220 regards the storage block 232 as a valid block. However, when the activation flags act_0 and act_1 have a value of 10, if the page flags old_0 and old_1 have a value of 11, it means that the storage block 232 is an old block, so the control circuit 220 regards the storage block 231 as a valid block.

[0070] In some embodiments, when the value of the activation flag (such as act_0 or act_1) is 0, it indicates that the control circuit 220 does not activate the corresponding storage block (such as 231 or 232). For example, when the activation flag act_1 has a value of 0, the control circuit 220 does not access the corresponding storage block 232 and does not set the page flag old_1 corresponding to the storage block 232 to a value of 1. Therefore, in Table 2B, the situation where the activation flag act_1 and the page flag old_1 have a value of 01 does not exist. In addition, the situation where the page flags old_0 and old_1 have a value of 11 does not exist.

[0071] The control circuit 220 determines whether an abnormal event has occurred through the activation flags act_0 and act_1. When an abnormal event occurs, the control circuit 220 uses the original storage block (such as 231) to ensure the normal operation of the control chip 100. Furthermore, the control circuit 220 may activate a protection function to reject access instructions from outside the control chip 100.

[0072] Figure 4 It is a schematic flowchart of the control method of the present invention. The control method of the present invention can exist in the form of program code. When the program code is loaded and executed by a machine, the machine becomes a storage circuit and a control chip for implementing the present invention. In a possible embodiment, the control method of the present invention is applicable to a storage circuit. The storage circuit has a first page and a second page.

[0073] First, store multiple data groups in a first page (step S411). The present invention does not limit the length of each data group. In a possible embodiment, each data group has the same data length, such as one word. In another possible embodiment, the data length of at least one of the multiple data groups is different from that of another data group. In some embodiments, since the second page has not stored valid data, step S411 sets the value of a first activation flag not equal to a specific value. Since the first page stores valid data, step S411 sets the value of a second activation flag equal to a specific value. In this example, the first activation flag corresponds to the second page, and the second activation flag corresponds to the first page.

[0074] Next, when an erasure request selects at least one of the multiple data groups, erase the second page (step S412), and then copy all the data groups among the multiple data groups that are not selected by the erasure request to the second page (step S413). For Figure 3C example, assuming that an erasure request selects data group CFG1, step S413 copies data groups CFG0, CFG2 to CFGn other than data group CFG1 to the second page. Since the second page does not store data group CFG1, it can be regarded that data group CFG1 has been erased.

[0075] Then, activate the second page to replace the first page (step S414). In a possible embodiment, since the second page is a new page and stores valid data, step S414 sets the value of the first activation flag equal to a specific value. In this example, since the first page is an old page, step S414 sets the value of the second activation flag not equal to the specific value. For example, step S414 sets the value of the first activation flag to change from value 0 to value 1, and sets the value of the second activation flag to change from value 1 to value 0.

[0076] In another possible embodiment, step S414 first sets the value of a page flag equal to a specific value to indicate that the first page is an old page, and then step S414 sets the value of the first activation flag equal to a specific value to indicate that the second page is a new page. In this example, step S414 may maintain the second activation flag so that the value of the second activation flag remains equal to the specific value. Since step S414 does not erase the second activation flag, the number of times the second activation flag is erased can be reduced, and the erasure time is not additionally increased.

[0077] In some embodiments, after the second page is activated, when an access request points to the first page, since the value of the first activation flag is equal to a specific value, it indicates that the second page is a valid page. Therefore, the second page is directly accessed. However, when the value of the first activation flag is not equal to the specific value, it indicates that the first page is a valid page. Therefore, when an access request points to the first page, the first page is accessed.

[0078] In other embodiments, during an initial period, the first page is erased, and according to an initial setting, the value of the second activation flag is set equal to a specific value. Therefore, when the storage circuit receives an access request, the storage circuit writes external data (or a data group) to the first page.

[0079] In other embodiments, step S413 further sets the value of a page flag equal to a specific value. In this example, after step S413 copies all data groups not selected by the erase request to the second page, step S413 first sets the value of a page flag equal to a specific value, and then sets the value of the first activation flag equal to that specific value. In some embodiments, step S413 may set the value of the second activation flag not equal to that specific value, or maintain the value of the first activation flag equal to that specific value.

[0080] When an access request points to the first page, the storage circuit accesses the first or second page according to the values of the first and second activation flags. For example, when the value of the first activation flag is not equal to a specific value and the value of the second activation flag is equal to that specific value, it indicates that the first page is a valid page. Therefore, the storage circuit accesses the first page according to the access request. However, when the value of the first activation flag is equal to a specific value and the value of the second activation flag is not equal to that specific value, it indicates that the second page is a valid page. Therefore, the storage circuit accesses the second page.

[0081] In other embodiments, when an access request points to the first page and the values of both the first and second activation flags are equal to a specific value, the storage circuit reads the value of a page flag. When the value of the page flag 1 is equal to a specific value, it indicates that the first page is an old page and the second page is a new page. Therefore, the storage circuit accesses the second page according to the access request. However, when the value of the page flag is not equal to that specific value, it indicates that the first page is a new page. Therefore, the storage circuit accesses the first page.

[0082] The control method of the present invention, or a specific form or a part thereof, may exist in the form of program code. The program code can be stored in a physical medium, such as a floppy disk, an optical disk, a hard disk, or any other machine-readable (such as computer-readable) storage medium, or a computer program product not limited to an external form. Wherein, when the program code is loaded and executed by a machine, such as a computer, this machine becomes a storage circuit and a control chip for participating in the present invention. The program code can also be transmitted through some transmission media, such as wires or cables, optical fibers, or any transmission form. Wherein, when the program code is received, loaded, and executed by a machine, such as a computer, this machine becomes a storage circuit and a control chip for participating in the present invention. When implemented in a general-purpose processing unit, the program code combined with the processing unit provides a unique device whose operation is similar to that of an application-specific logic circuit.

[0083] Unless otherwise defined, all terms (including technical and scientific terms) used herein are within the general understanding of those skilled in the art of the present invention. In addition, unless explicitly stated, the definitions of terms in a general dictionary should be interpreted as being consistent with their meanings in the articles of the relevant technical field, and should not be interpreted in an ideal state or an overly formal voice. Although terms such as "first", "second", etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. In the claims for patent, terms such as "first", "second", etc. are used as labels and do not intend to impose numerical requirements on their objects.

[0084] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. For example, the systems, devices, or methods described in the embodiments of the present invention can be implemented by physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A storage circuit, characterized in that, Comprising: A memory, comprising: A storage block for storing a plurality of data groups; and A backup block; and A control circuit for receiving an erase request, Wherein: When the erase request selects at least one of the plurality of data groups, the control circuit: Erases the backup block, Copies all the data groups among the plurality of data groups that are not selected by the erase request to the backup block, Activates the backup block to replace the storage block, After activating the backup block, when an access request points to the storage block, the control circuit accesses the backup block.

2. The storage circuit according to claim 1, wherein: After copying all the data groups among the plurality of data groups that are not selected by the erase request to the backup block, the control circuit sets the value of a first activation flag equal to a predetermined value, Before copying all the data groups among the plurality of data groups that are not selected by the erase request to the backup block, the control circuit sets the value of the first activation flag not equal to the predetermined value.

3. The storage circuit according to claim 2, wherein: When the access request points to the storage block and the value of the first activation flag is equal to the predetermined value, the control circuit accesses the backup block, When the access request points to the storage block and the value of the first activation flag is not equal to the predetermined value, the control circuit accesses the storage block.

4. The storage circuit according to claim 2, wherein: After copying all the data groups among the plurality of data groups that are not selected by the erase request to the backup block, the control circuit sets the value of a second activation flag not equal to the predetermined value, Before copying all the data groups among the plurality of data groups that are not selected by the erase request to the backup block, the value of the second activation flag is equal to the predetermined value.

5. The storage circuit according to claim 4, wherein During an initial period, the control circuit erases the storage block and sets the value of the second activation flag equal to the predetermined value according to an initial setting.

6. The storage circuit according to claim 5, wherein: After copying all the data groups among the plurality of data groups that are not selected by the erase request to the backup block, the control circuit first sets the value of a page flag equal to the predetermined value, and then sets the value of the first activation flag equal to the predetermined value.

7. The memory circuit according to claim 6, characterized in that, After copying all the data groups among the plurality of data groups that are not selected by the erase request to the backup block, the control circuit maintains the value of the second activation flag equal to the predetermined value.

8. A control method, characterized in that, Applicable to a storage circuit having a first page and a second page, the control method includes: Storing a plurality of data groups in the first page; When an erase request selects at least one of the plurality of data groups: Erases the second page; Copies all the data groups among the plurality of data groups that are not selected by the erase request to the second page; and Activates the second page to replace the first page; and After activating the second page, when an access request points to the first page, accesses the second page.

9. The control method according to claim 8, wherein Further comprising: After copying all data groups among the multiple data groups that are not selected by the erasure requirement to the second page, set the value of a first activation flag equal to a predetermined value. Before copying all data groups among the multiple data groups that are not selected by the erasure requirement to the second page, set the value of the first activation flag not equal to the predetermined value.

10. A control chip, characterized in that, Including: A main control circuit that issues an erasure requirement and an access requirement. A bus circuit coupled to the main control circuit for transmitting the erasure requirement and the access requirement. And A storage circuit coupled to the transmission circuit and including: A slave interface coupled to the transmission circuit for receiving the erasure requirement and the access requirement. A non-volatile memory including: A storage block that stores multiple data groups; and A backup block; and A control circuit that, through the slave interface, receives the erasure requirement and the access requirement from the transmission circuit. Wherein: When the erasure requirement selects at least one data group among the multiple data groups, the control circuit: Erases the backup block. Copies all data groups among the multiple data groups that are not selected by the erasure requirement to the backup block. Activates the backup block. After activating the backup block, when the access requirement points to the storage block, the control circuit accesses the backup block.

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