Test equipment, interface test method and equipment
By introducing programmable logic devices into the server test equipment to connect to the low-speed signal pins of the connector and PCIE slots, providing low-speed signals, it solves the complex problems of various test card preparations in the prior art, and achieves the effect of simplifying wiring and reducing material preparation costs.
Patent Information
- Application Number
- CN202510097751.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2025-07-29
AI Technical Summary
In the prior art, high-speed interface testing of servers requires the preparation of various types of test cards, which are complex in wiring, resulting in high material preparation costs and cumbersome operations.
A test device is adopted, including programmable logic devices, connectors and PCIE slots. The programmable logic devices are connected to the low-speed signal pins of the connectors and PCIE slots respectively, providing low-speed signals, and data interaction with the device under test through the test card, realizing the testing of various types of test interfaces and reducing material preparation.
It realizes the use of unified testing equipment and cards to test multiple types of test interfaces, simplifying the wiring process and reducing material preparation costs.
Smart Images
Figure CN120386672A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of servers, and in particular, to a test device, an interface test method, and a device. Background Art
[0002] Currently, high-speed interfaces are usually configured on computing devices, such as high-speed board-to-board connector module UBC interfaces, Mini Cooledge Input / Output (MCIO) interfaces, etc., to support the computing device to perform high-speed communication with other devices using the high-speed interfaces.
[0003] Before the computing device leaves the factory, the manufacturer usually tests the high-speed interfaces. Taking a server as an example, as Figure 1 shown, for the MCIO interface on the server, the types of boards connected externally are diverse. It can be connected to a Riser card (a server expansion card), an Open Compute Project Card (OCP) card (an open and pluggable acceleration card used in a server), a hard disk backplane, etc. Therefore, when testing the high-speed interface, multiple types of test cards need to be prepared, and the interface types of each test card are different, and different wiring methods are required, and the wiring method is complex. Summary of the Invention
[0004] Embodiments of this application provide a test device, an interface test method, and a device, which are used to test a DUT interface using a unified test card, reduce material preparation, and have simple wiring.
[0005] In a first aspect, an embodiment of this application provides a test device, including: a programmable logic device, at least one connector, and a Peripheral Component Interconnect Express (PCIE) slot connected to each of the connectors, where
[0006] the connector is used to plug into the DUT interface of the device under test, and the pins of the connector include high-speed signal pins and low-speed signal pins;
[0007] the PCIE slot is connected to the high-speed signal pins of the corresponding connector and is used to plug in a test card for testing the DUT interface, and the test card is used to perform data interaction with the device under test during the test;
[0008] the programmable logic device is respectively connected to the low-speed signal pins of each of the connectors and the low-speed signal pins of each of the PCIE slots, and is used to provide low-speed signals for the PCIE slots and the connectors, and perform functional tests on the low-speed signal pins of the DUT interface.
[0009] In the above test device, the high-speed signal pins of the PCIE slot are connected to the corresponding connectors, and the programmable logic device is respectively connected to the low-speed signal pins of each connector and the low-speed signal pins of each PCIE slot. After the connector is plugged into the DUT interface during the test process, a test card is plugged into the PCIE slot. The test card exchanges data with the DUT to test the high-speed signal pins of the DUT interface. The programmable logic device provides low-speed signals for the PCIE slot and the connector, and can test the low-speed signal pins of the DUT interface. In the solution of this application, the test device includes at least one connector, and the connector can be connected to different types of DUT interfaces. Therefore, only one test device is needed to test multiple types of DUT interfaces, and there is no need to prepare multiple types of test cards, reducing the material preparation.
[0010] In addition, in the test device provided by the embodiment of this application, the test card is plugged into the PCIE slot, and the test device is connected to the DUT through the connector, and the wiring is relatively simple.
[0011] In a possible implementation manner, the programmable logic device is further configured to: receive an instruction for changing the state of its own pins, and control the input and output states of its corresponding pins according to the indication of the instruction.
[0012] In the above test device, by controlling the input and output states of the pins of the programmable logic device, the programmable logic device can serve both to provide low-speed signals for the low-speed signal pins of the PCIE slot and the connector and to test the low-speed signal pins of the DUT interface.
[0013] In a possible implementation manner, the test device further includes:
[0014] A pull-up component, one end of which is connected to the positive power supply, and the other end is respectively connected to the low-speed signal pins of each of the connectors;
[0015] A pull-down component, one end of which is connected to the negative power supply, and the other end is respectively connected to the low-speed signal pins of each of the connectors;
[0016] A pull-up / down component controller, which is respectively connected to the programmable logic device, the pull-up component, and the pull-down component, and is configured to control the access state of the pull-up component and the access state of the pull-down component according to the instruction issued by the programmable logic device.
[0017] In the above test device, by controlling the access states of the pull-up component and the pull-down component, the level states of the respective low-speed signal pins of the connector can be adjusted. Furthermore, by measuring the actual level states of the respective low-speed signal pins of the interface under test, it is possible to test whether the pull-up resistors and pull-down resistors connected to the respective low-speed signal pins inside the interface under test are faulty.
[0018] In a possible implementation, the programmable logic device includes: a Complex Programmable Logic Device (CPLD), or a Field Programmable Gate Array (FPGA).
[0019] In a second aspect, an embodiment of the present application provides an interface test method, which is applied to a test device. The interface under test of the device under test is plugged into the connector of the test device. The method includes:
[0020] Receiving a test instruction for changing the state of the test device. The state of the test device includes one or more of the following: the state of the programmable logic device itself, the access state of the pull-up component, and the access state of the pull-down component;
[0021] After changing the state of the test device based on the test instruction, testing the interface under test.
[0022] In a possible implementation, the test instruction is used to instruct the programmable logic device to change the pin state of itself to an input state;
[0023] The testing of the interface under test includes:
[0024] When controlling the low-speed signal pins of the interface under test to output a preset level signal, obtaining a target level signal measured by itself;
[0025] When the target level signal is consistent with the preset level signal, determining that the connection between the low-speed signal pins of the interface under test and the connector is normal.
[0026] In the above method, after controlling the pin state of the programmable logic device to an input state, when controlling the low-speed signal pins of the interface under test to output a preset level signal, obtaining a target level signal measured by itself, comparing the target level signal with the preset level signal. If the target level signal is consistent with the preset level signal, it is determined that the connection between the low-speed signal pins of the interface under test and the connector is normal; otherwise, it is determined that the connection between the low-speed signal pins of the interface under test and the connector is abnormal, thereby realizing the interconnection test of the low-speed signal pins of the interface under test and the connector.
[0027] In a possible implementation, the test instruction is used to instruct the programmable logic device to change its own state to a communication signal interface state;
[0028] Testing the interface under test includes:
[0029] When controlling the low-speed signal pin of the interface under test to output a test communication signal, obtaining a target communication signal measured by itself;
[0030] When the target communication signal is consistent with the test communication signal, it is determined that the communication signal transmission between the low-speed signal pin of the interface under test and the connector is normal.
[0031] In a possible implementation, the communication signal includes any one of the following: Inter-Integrated Circuit (IIC) communication signal, Serial Peripheral Interface (SPI) communication signal, Universal Asynchronous Receiver / Transmitter (UART) communication signal.
[0032] In the above method, after controlling the programmable logic device to be in the communication signal interface state, when controlling the low-speed signal pin of the interface under test to output a test communication signal, obtaining the target communication signal measured by itself, comparing the target communication signal with the test communication signal, if the target communication signal is consistent with the test communication signal, it is determined that the communication signal transmission between the low-speed signal pin of the interface under test and the connector is normal, otherwise, it is determined that the communication signal transmission between the low-speed signal pin of the interface under test and the connector is abnormal, so as to implement the test of the communication signal transmission between the low-speed signal pin of the interface under test and the connector.
[0033] In a possible implementation, the test instruction is used to instruct the programmable logic device to change the state of its own pins to an input state and control the pull-up component to be connected to the test device;
[0034] Testing the interface under test includes:
[0035] Obtaining the level state of the low-speed signal pin of the interface under test;
[0036] When the level state of the low-speed signal pin of the interface under test is high level, it is determined that the pull-down resistor connected to the low-speed signal pin inside the interface under test is faulty.
[0037] In the above method, after controlling the pin state of the programmable logic device to the input state and using the programmable logic device to control the pull-up component to provide a pull-up resistor for the low-speed signal pin of the connector, if the pull-down resistor connected to the low-speed signal pin inside the DUT interface is normal, the level state of the low-speed signal pin should be low. In this case, obtain the level state of the low-speed signal pin of the DUT interface. If it is determined that the level state of the low-speed signal pin is high, it can be determined that the pull-down resistor connected to the low-speed signal pin inside the DUT interface is faulty, thereby realizing the test on whether the pull-down resistor connected to the low-speed signal pin inside the DUT interface is faulty.
[0038] In one possible implementation, the test instruction is used to instruct the programmable logic device to change its own pin state to the input state and control the pull-down component to be connected to the test device;
[0039] The testing of the DUT interface includes:
[0040] Obtain the level state of the low-speed signal pin of the DUT interface;
[0041] In the case where the level state of the low-speed signal pin of the DUT interface is low, determine that the pull-up resistor connected to the low-speed signal pin inside the DUT interface is faulty.
[0042] In the above method, after controlling the pin state of the programmable logic device to the input state and using the programmable logic device to control the pull-down component to provide a pull-down resistor for the low-speed signal pin of the connector, if the pull-up resistor connected to the low-speed signal pin inside the DUT interface is normal, the level state of the low-speed signal pin should be high. In this case, obtain the level state of the low-speed signal pin of the DUT interface. If it is determined that the level state of the low-speed signal pin is low, it can be determined that the pull-up resistor connected to the low-speed signal pin inside the DUT interface is faulty, thereby realizing the test on whether the pull-up resistor connected to the low-speed signal pin inside the DUT interface is faulty.
[0043] In a third aspect, an embodiment of the present application provides an interface testing device, which is applied to the programmable logic device in the testing device provided in the first aspect of the embodiments of the present application. The DUT interface of the DUT is plugged into the connector of the testing device. The device includes:
[0044] A receiving module, configured to receive a test instruction, where the test instruction is used to change the state of the testing device, and the state of the testing device includes one or more of the following: the state of the programmable logic device itself, the access state of the pull-up component, and the access state of the pull-down component;
[0045] A testing module, configured to test the DUT interface after changing the state of the testing device based on the test instruction.
[0046] In a possible implementation, the test instruction is used to instruct the programmable logic device to change the state of its own pins to an input state;
[0047] The test module is specifically configured to:
[0048] When controlling the low-speed signal pins of the interface under test to output a preset level signal, obtain the measured target level signal;
[0049] When the target level signal is consistent with the preset level signal, determine that the low-speed signal pins of the interface under test are normally connected to the connector.
[0050] In a possible implementation, the test instruction is used to instruct the programmable logic device to change its own state to a communication signal interface state;
[0051] The test module is specifically configured to:
[0052] When controlling the low-speed signal pins of the interface under test to output a test communication signal, obtain the measured target communication signal;
[0053] When the target communication signal is consistent with the test communication signal, determine that the communication signal transmission between the low-speed signal pins of the interface under test and the connector is normal.
[0054] In a possible implementation, the communication signal includes any one of the following: IIC communication signal, SPI communication signal, UART communication signal.
[0055] In a possible implementation, the test instruction is used to instruct the programmable logic device to change the state of its own pins to an input state and control the pull-up component to access the test device;
[0056] The test module is specifically configured to:
[0057] Obtain the level state of the low-speed signal pins of the interface under test;
[0058] When the level state of the low-speed signal pins of the interface under test is high level, determine that the pull-down resistor connected to the low-speed signal pins inside the interface under test is faulty.
[0059] In a possible implementation, the test instruction is used to instruct the programmable logic device to change the state of its own pins to an input state and control the pull-down component to access the test device;
[0060] The test module is specifically configured to:
[0061] Obtain the level status of the low-speed signal pin of the interface under test;
[0062] When the level status of the low-speed signal pin of the interface under test is low level, determine that the pull-up resistor connected to the low-speed signal pin inside the interface under test is faulty.
[0063] In a fourth aspect, an electronic device provided in an embodiment of the present application includes a programmable logic device and a memory. Among them, the memory stores a computer program. When the computer program is executed by the programmable logic device, the programmable logic device is caused to execute any one of the interface test methods in the second aspect above.
[0064] In a fifth aspect, a computer-readable storage medium provided in an embodiment of the present application includes a computer program. When the computer program runs on a test device, the computer program is used to cause the test device to execute any one of the interface test methods in the second aspect above.
[0065] In a sixth aspect, a computer program product provided in an embodiment of the present application includes a computer program, and the computer program is stored in a computer-readable storage medium; when a programmable logic device in a test device reads the computer program from the computer-readable storage medium, the programmable logic device executes the computer program, so that the test device executes any one of the interface test methods in the second aspect above.
[0066] In a seventh aspect, the present application further provides a computer chip, the chip is connected to a memory, and the chip is used to read and execute a software program stored in the memory, and execute any one of the interface test methods in the second aspect above.
[0067] For the possible technical effects of each of the above third aspect to seventh aspect, please refer to the description of the possible technical effects of various possible solutions in the second aspect above, and will not be repeated here. Description of the Drawings
[0068] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:
[0069] Figure 1 It is a schematic diagram of the connection of the server MCIO interface to different boards in an embodiment of the present application;
[0070] Figure 2 It is a schematic diagram of the functions of each pin of a UBC interface in an embodiment of the present application;
[0071] Figure 3Schematic structural diagram of a testing device provided by an embodiment of the present application;
[0072] Figure 4 Schematic structural diagram of another testing device provided by an embodiment of the present application;
[0073] Figure 5 Schematic flowchart of an interface testing method provided by an embodiment of the present application;
[0074] Figure 6 Schematic flowchart of the pull-down resistor testing process in the interface testing method provided by an embodiment of the present application;
[0075] Figure 7 Schematic principle diagram of the pull-down resistor testing provided by an embodiment of the present application;
[0076] Figure 8 Schematic flowchart of the pull-up resistor testing process in the interface testing method provided by an embodiment of the present application;
[0077] Figure 9 Schematic principle diagram of the pull-up resistor testing provided by an embodiment of the present application;
[0078] Figure 10 Schematic flowchart of the interconnection testing process in the interface testing method provided by an embodiment of the present application;
[0079] Figure 11 Schematic principle diagram of the interconnection testing provided by an embodiment of the present application;
[0080] Figure 12 Schematic flowchart of the IIC signal testing process in the interface testing method provided by an embodiment of the present application;
[0081] Figure 13 Schematic principle diagram of the IIC signal testing provided by an embodiment of the present application;
[0082] Figure 14 Schematic structural diagram of an interface testing device provided by an embodiment of the present application;
[0083] Figure 15 Schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners
[0084] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions of the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Apparently, the described embodiments are some, but not all, of the embodiments of the technical solutions of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments recorded in this application document without creative efforts belong to the scope protected by the technical solutions of this application.
[0085] The following describes the preferred embodiments of this application with reference to the accompanying drawings of the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the embodiments of this application and are not used to limit the embodiments of this application. And without conflict, the embodiments and features in the embodiments of this application can be combined with each other.
[0086] It should be noted that the measured interface mentioned in the embodiments of this application refers to an interface in which high-speed signal pins and low-speed signal pins are separated, such as a UBC interface, an MCIO interface, etc.
[0087] Taking the UBC interface as an example, as Figure 2 shown, it has a total of 37 pairs of pins. Except for the ground pins, it has 8 pairs of high-speed signal pins (high-speed signal RX and high-speed signal TX). Among them, the multiplexed input / output (multiplexed IO) pins can be used to transmit low-speed signals and can be used as low-speed signal pins. Since its high-speed signal pins and low-speed signal pins are separated, the high-speed signal pins and low-speed signal pins can be respectively subjected to functional tests.
[0088] The following will describe in detail the test equipment and interface test scheme mentioned in the embodiments of this application with reference to specific embodiments.
[0089] Refer to Figure 3 , which is a schematic diagram of a test system provided by an embodiment of this application.
[0090] The test system provided by the embodiments of this application includes a test device and a device under test. Among them, the device under test can be a server or other computing device. The test device includes: a programmable logic device 10, at least one connector 11, and a PCIE slot 12 connected to each connector 11.
[0091] The connector 11 is used to plug into the measured interface of the device under test. The pins of the connector 11 include high-speed signal pins and low-speed signal pins.
[0092] Among them, one or more connectors are included in the test device. During specific tests, different connectors can be respectively connected to different measured interfaces in the device under test.
[0093] The PCIE slot 12 is connected to the high-speed signal pins of the corresponding connector 11 and is used to plug in a test card for testing the DUT interface. The test card is used to perform data interaction with the DUT during the test.
[0094] In practical applications, in order to reduce the test cost, a test card with a lower cost can be selected.
[0095] The programmable logic device 10 is respectively connected to the low-speed signal pins of each connector 11 and the low-speed signal pins of each PCIE slot 12, and is used to provide low-speed signals for the connector 11 and the PCIE slot 12 and perform functional tests on the low-speed signal pins of the DUT interface.
[0096] Among them, the programmable logic device 10 can adopt a CPLD or an FPGA. The programmable logic device 10 can also receive an instruction for changing the state of its own pins, and control the input and output states of its corresponding pins according to the indication of the instruction.
[0097] It should be noted that the instruction for changing the state of the pins of the programmable logic device 10 mentioned in the embodiments of the present application can be sent by the processor of the DUT. Controlling the state of the test device by the DUT can facilitate the test of the DUT interface. Specifically, in implementation, the operating system (OS) in the processor of the DUT can also be connected to the test device through a USB-to-IIC conversion interface to send an instruction to the programmable logic device in the DUT to control the programmable logic device in the test device, so that the programmable logic device changes the state of the test device. Of course, in other embodiments of the present application, the instruction for changing the state of the pins of the programmable logic device 10 can also be sent by other devices, and the embodiments of the present application do not limit this.
[0098] In practical applications, when the pin state of the programmable logic device 10 is in the output state, the programmable logic device 10 provides low-speed signals for the low-speed signal pins of the PCIE slot and the connector. When the pin state of the programmable logic device 10 is in the input state, the programmable logic device 10 measures the low-speed signals output by the DUT interface and performs functional tests on the low-speed signal pins of the DUT interface.
[0099] In specific implementation, after a test card is inserted into the PCIE slot 12, the test card can perform data interaction with the device under test during the test. For example, after the processor of the device under test sends a signal to the test card through high-speed signal pins, the test card counts the signal and then feeds back the signal or the statistical result to the device under test to perform a functional test on the high-speed signal pins of the interface under test, such as testing the transmission rate, bit error rate, etc. The specific test method can adopt the method in the related technology and will not be elaborated here.
[0100] In specific implementation, the test device further includes: a pull-up component, one end of which is connected to the positive electrode of the power supply and the other end is respectively connected to the low-speed signal pins of each connector; a pull-down component, one end of which is connected to the negative electrode of the power supply and the other end is respectively connected to the low-speed signal pins of each connector; and a pull-up / down component controller 13, which is respectively connected to the programmable logic device 10, the pull-up component, and the pull-down component, and is used to control the access states of the pull-up component and the pull-down component according to the instructions issued by the programmable logic device 10.
[0101] It should be noted that when the pull-up / down component controller 13 controls the access states of the pull-up component and the pull-down component, it can control the pull-up component to separately provide a pull-up resistor for the low-speed signal pins of the connector 11 to test whether the pull-down resistor inside the interface under test is faulty, or control the pull-down component to separately provide a pull-down resistor for the low-speed signal pins of the connector 11 to test whether the pull-up resistor inside the interface under test is faulty, or control the pull-up component and the pull-down component not to provide pull-up and pull-down resistors to perform the interconnection test of the interface under test and the connector and the communication signal transmission test. Of course, in other embodiments of the present application, it is also possible to control the pull-up component and the pull-down component to simultaneously provide a pull-up resistor and a pull-down resistor for the low-speed signal pins of the connector 11 to perform other tests.
[0102] Among them, the pull-up component may include at least one resistor, and the pull-down component may include at least one resistor.
[0103] In one example, as Figure 4 shown, taking the connection method of a connector in the test device as an example, the test device includes a pull-up component 40, a pull-down component 41, and a pull-up / down component controller (not shown in the figure). The pull-up component 40 includes a pull-up resistor, one end of the pull-up resistor is connected to the positive electrode VCC of the power supply, and the other end is respectively connected to the low-speed signal pins of the connector. The pull-down component 41 includes a pull-down resistor, one end of the pull-down resistor is connected to the negative electrode (ground wire) of the power supply, and the other end is respectively connected to the low-speed signal pins of the connector.
[0104] The above introduced the test equipment provided by the embodiments of the present application. The embodiments of the present application also provide an interface test method. After the connector of the test equipment is plugged into the interface under test of the device under test, functional tests can be performed on the low-speed signal pins of the interface under test, where the test equipment is the test equipment provided by the embodiments of the present application.
[0105] As Figure 5 shown, an interface test method provided by the embodiments of the present application, the execution subject can be a programmable logic device in the test equipment, including:
[0106] S501, receive a test instruction, the test instruction is used to change the state of the test equipment, and the state of the test equipment includes one or more of the following: the state of the programmable logic device itself, the access state of the pull-up component, and the access state of the pull-down component.
[0107] S502, after changing the state of the test equipment based on the test instruction, test the interface under test.
[0108] It should be noted that the test instruction can be sent by the device under test or by other devices, and the embodiments of the present application do not limit this. In practical applications, the test instruction may also include other parameters or information, such as the interface identifier for testing (used to indicate the specific interface under test), the test type, etc. In other embodiments of the present application, the test instruction can also be used to indicate the start of the test or the test sequence, etc.
[0109] Specifically testing the interface under test may include, but is not limited to: interconnection testing, communication signal transmission testing, pull-down resistor testing, and pull-up resistor testing, which will be described separately in combination with specific embodiments below.
[0110] As Figure 6 shown, when performing pull-down resistor testing, the test instruction is used to instruct the programmable logic device to change the state of its own pin to the input state and control the pull-down component to access the test equipment. After the programmable logic device changes the state of the test equipment, specifically test the interface under test, including:
[0111] S601, obtain the level state of the low-speed signal pin of the interface under test.
[0112] S602, when the level state of the low-speed signal pin of the interface under test is high level, determine that there is a fault in the pull-down resistor connected to the low-speed signal pin inside the interface under test.
[0113] As Figure 7As shown, when testing the pull-down resistor of the low-speed signal pin of the interface under test, the pin state of the programmable logic device is controlled to be in the input state, and the pull-up component provides a pull-up resistor for the low-speed signal pin of the connector. At this time, if the pull-down resistor connected to the low-speed signal pin of the interface under test is normal, the level state of the low-speed signal pin of the interface under test should be low level. Therefore, by measuring the level state of the low-speed signal pin of the interface under test, it can be determined whether the pull-down resistor connected to the low-speed signal pin of the interface under test is faulty.
[0114] If the level state of the low-speed signal pin of the interface under test is high level, it can be determined that the pull-down resistor connected to the low-speed signal pin inside the interface under test is faulty. On the contrary, if the level state of the low-speed signal pin of the interface under test is low level, it can be determined that the pull-down resistor connected to the low-speed signal pin inside the interface under test is normal.
[0115] It should be noted that there are multiple low-speed signal pins of the interface under test. When testing whether the pull-down resistor connected to the low-speed signal pin is faulty, multiple low-speed signal pins can be tested simultaneously or separately. The embodiments of the present application do not limit this.
[0116] As Figure 8 shown, when performing the pull-up resistor test, the test instruction is used to instruct the programmable logic device to change its own pin state to the input state and control the pull-down component to be connected to the test device. After the programmable logic device changes the state of the test device, the interface under test is specifically tested, including:
[0117] S801, obtain the level state of the low-speed signal pin of the interface under test.
[0118] S802, when the level state of the low-speed signal pin of the interface under test is low level, determine that the pull-up resistor connected to the low-speed signal pin inside the interface under test is faulty.
[0119] As Figure 9 shown, when testing the pull-up resistor of the low-speed signal pin of the interface under test, the pin state of the programmable logic device is controlled to be in the input state, and the pull-down component provides a pull-down resistor for the low-speed signal pin of the connector. At this time, if the pull-up resistor connected to the low-speed signal pin of the interface under test is normal, the level state of the low-speed signal pin of the interface under test should be high level. Therefore, by measuring the level state of the low-speed signal pin of the interface under test, it can be determined whether the pull-up resistor connected to the low-speed signal pin of the interface under test is faulty.
[0120] If the level state of the low-speed signal pin of the interface under test is high level, it can be determined that the pull-up resistor connected to the low-speed signal pin inside the interface under test is normal. On the contrary, if the level state of the low-speed signal pin of the interface under test is low level, it can be determined that the pull-up resistor connected to the low-speed signal pin inside the interface under test is faulty.
[0121] It should be noted that there are multiple low-speed signal pins on the interface under test. When testing whether the pull-up resistors connected to the low-speed signal pins are faulty, multiple low-speed signal pins can be tested simultaneously or separately. The embodiments of the present application do not limit this.
[0122] As Figure 10 shown, when performing the interconnection test, the test instruction is used to instruct the programmable logic device to change the state of its own pins to the input state. After the programmable logic device changes the state of the test device, the interface under test is specifically tested, including:
[0123] S1001, when controlling the low-speed signal pins of the interface under test to output a preset level signal, obtain the measured target level signal.
[0124] S1002, when the target level signal is consistent with the preset level signal, determine that the connection between the low-speed signal pins of the interface under test and the connector is normal.
[0125] As Figure 11 shown, after controlling the state of the pins of the programmable logic device to the input state and controlling the low-speed signal pins of the interface under test to output a preset level signal, at this time, there is no need for the pull-up component and the pull-down component to provide the pull-up and pull-down resistors. Obtain the target level signal measured by the programmable logic device, compare the target level signal with the preset level signal. If the target level signal is consistent with the preset level signal, it is determined that the connection between the low-speed signal pins of the interface under test and the connector is normal; otherwise, it is determined that the connection between the low-speed signal pins of the interface under test and the connector is abnormal.
[0126] It should be noted that since the main body performing the interface test is the processor of the device under test, the target level signal measured by the programmable logic device can be sent to the processor of the device under test in the form of an IIC signal through a USB to IIC conversion interface.
[0127] As Figure 12 shown, when performing the communication signal transmission test, the test instruction is used to instruct the programmable logic device to change its state to the communication signal interface state. After the programmable logic device changes the state of the test device, the interface under test is specifically tested, including:
[0128] S1201, when controlling the low-speed signal pins of the interface under test to output a test communication signal, obtain the measured target communication signal.
[0129] S1202, when the target communication signal is consistent with the test communication signal, determine that the communication signal transmission between the low-speed signal pins of the interface under test and the connector is normal.
[0130] Among them, the programmable logic device changes its own state to the communication signal interface state, which can be specifically achieved by changing the pin state of itself to the input state. The communication signals include, but are not limited to, IIC communication signals, SPI communication signals, and UART communication signals.
[0131] As Figure 13 shown, after controlling the programmable logic device to be in the communication signal interface state, when controlling the low-speed signal pin of the DUT interface to output a test communication signal, there is no need for the pull-up component and the pull-down component to provide pull-up and pull-down resistors at this time. Obtain the target communication signal measured by the programmable logic device, and compare the target communication signal with the test communication signal. If the target communication signal is consistent with the test communication signal, it is determined that the communication signal transmission between the low-speed signal pin of the DUT interface and the connector is normal; otherwise, it is determined that the communication signal transmission between the low-speed signal pin of the DUT interface and the connector is abnormal.
[0132] It should be noted that since the main body for performing the interface test is the processor of the DUT, the target communication signal measured by the programmable logic device can be sent to the processor of the DUT through a USB-to-IIC adapter.
[0133] Based on the same inventive concept, an embodiment of the present application further provides an interface test device, which is applied to the programmable logic device in the test equipment provided in the embodiment of the present application. The DUT interface of the DUT is plugged into the connector of the test equipment. As Figure 14 shown, it is a schematic structural diagram of the interface test device 1400, which may include:
[0134] A receiving module 1401, configured to receive a test instruction, where the test instruction is used to change the state of the test equipment, and the state of the test equipment includes one or more of the following: the state of the programmable logic device itself, the access state of the pull-up component, and the access state of the pull-down component;
[0135] A test module 1402, configured to test the DUT interface after changing the state of the test equipment based on the test instruction.
[0136] In a possible implementation manner, the test instruction is used to instruct the programmable logic device to change the pin state of itself to the input state;
[0137] The test module 1402 is specifically configured to:
[0138] When controlling the low-speed signal pin of the DUT interface to output a preset level signal, obtain the measured target level signal;
[0139] When the target level signal is consistent with the preset level signal, it is determined that the low-speed signal pin of the DUT interface is normally connected to the connector.
[0140] In a possible implementation, the test instruction is used to instruct the programmable logic device to change its own state to a communication signal interface state;
[0141] The test module 1402 is specifically configured to:
[0142] When controlling the low-speed signal pin of the interface under test to output a test communication signal, obtain the measured target communication signal;
[0143] When the target communication signal is consistent with the test communication signal, determine that the communication signal transmission between the low-speed signal pin of the interface under test and the connector is normal.
[0144] In a possible implementation, the communication signal includes any one of the following: IIC communication signal, SPI communication signal, UART communication signal.
[0145] In a possible implementation, the test instruction is used to instruct the programmable logic device to change the state of its own pin to an input state and control the pull-up component to access the test device;
[0146] The test module 1402 is specifically configured to:
[0147] Obtain the level state of the low-speed signal pin of the interface under test;
[0148] When the level state of the low-speed signal pin of the interface under test is high level, determine that the pull-down resistor connected to the low-speed signal pin inside the interface under test is faulty.
[0149] In a possible implementation, the test instruction is used to instruct the programmable logic device to change the state of its own pin to an input state and control the pull-down component to access the test device;
[0150] The test module 1402 is specifically configured to:
[0151] Obtain the level state of the low-speed signal pin of the interface under test;
[0152] When the level state of the low-speed signal pin of the interface under test is low level, determine that the pull-up resistor connected to the low-speed signal pin inside the interface under test is faulty.
[0153] It should be noted that the division of units in the embodiments of the present application is illustrative. It is only a logical function division, and there may be other division methods in actual implementation. In the embodiments of the present application, the various functional units may be integrated in one processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit. The above integrated units may be implemented in the form of hardware or in the form of software functional units.
[0154] The above embodiments can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded or executed on a computer, the processes or functions according to the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server or data center that includes one or more collections of available media. The available media can be magnetic media (such as floppy disks, hard disks, magnetic tapes), optical media (such as DVDs), or semiconductor media. The semiconductor media can be a solid-state drive (SSD).
[0155] In a simple embodiment, those skilled in the art can conceive that the electronic device in the above embodiments can adopt Figure 15 the form shown. Specifically, the electronic device can be various types of handheld devices or smart terminals, etc.
[0156] Such as Figure 15 the electronic device 1500 shown, which includes at least one programmable logic device 1501, a memory 1502, and optionally, a communication interface 1503.
[0157] The memory 1502 can be a volatile memory, such as a random access memory; the memory can also be a non-volatile memory, such as a read-only memory, a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD), or the memory 1502 is any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1502 can be a combination of the above memories.
[0158] In the embodiments of the present application, the specific connection medium between the above programmable logic device 1501 and the memory 1502 is not limited.
[0159] The programmable logic device 1501 can be a CPLD, an FPGA, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, artificial intelligence chips, chip-on-chip, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. When the programmable logic device 1501 communicates with other devices, it can transmit data through the communication interface 1503, such as receiving parameters input by the object.
[0160] When the electronic device adopts Figure 15 the form shown, Figure 15 the programmable logic device 1501 in it can call the computer-executable instructions stored in the memory 1502, so that the electronic device can execute the interface test method in any of the above method embodiments.
[0161] Specifically, Figure 14 the functions / implementation processes of the sending module 1401 and the testing module 1402 in Figure 15 can all be implemented by the programmable logic device 1501 in it calling the computer-executable instructions stored in the memory 1502.
[0162] Those skilled in the art should understand that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.
[0163] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of the processes and / or blocks in the flowchart and / or block diagram can also be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.
[0164] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means implements the functions in the processFigure 1 one process or multiple processes and / or blocks Figure 1 the functions specified in one block or multiple blocks.
[0165] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 the one block or multiple blocks.
[0166] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the scope of the embodiments of the present application. In this way, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the embodiments of the present application are also intended to include these changes and modifications.
Claims
1. A testing device, characterized in that, Comprising: A programmable logic device, at least one connector, and a Peripheral Component Interconnect Express (PCIE) slot connected to each of the connectors, wherein, The connector is used for plugging into the DUT interface of the device under test, and the pins of the connector include high-speed signal pins and low-speed signal pins; The PCIE slot is connected to the high-speed signal pins of the corresponding connector and is used for plugging in a test card for testing the DUT interface, and the test card is used for data interaction with the device under test during the test; The programmable logic device is respectively connected to the low-speed signal pins of each connector and the low-speed signal pins of each PCIE slot, and is used for providing low-speed signals to the PCIE slot and the connector, and performing functional tests on the low-speed signal pins of the DUT interface.
2. The device according to claim 1, characterized in that, The programmable logic device is further used for: receiving an instruction for changing the state of its own pins, and controlling the input and output states of its corresponding pins according to the indication of the instruction.
3. The device according to claim 2, characterized in that, The test device further comprises: A pull-up component, one end of which is connected to the positive pole of the power supply and the other end of which is respectively connected to the low-speed signal pins of each connector; A pull-down component, one end of which is connected to the negative pole of the power supply and the other end of which is respectively connected to the low-speed signal pins of each connector; A pull-up and pull-down component controller, which is respectively connected to the programmable logic device, the pull-up component, and the pull-down component, and is used for controlling the access state of the pull-up component and the access state of the pull-down component according to the instruction issued by the programmable logic device.
4. The device according to any one of claims 1 to 3, characterized in that, The programmable logic device includes: a Complex Programmable Logic Device (CPLD) or a Field Programmable Gate Array (FPGA).
5. An interface testing method, characterized in that, Applied to a test device, the DUT interface of the device under test is plugged into the connector of the test device, and the method comprises: Receiving a test instruction for changing the state of the test device, and the state of the test device includes one or more of the following: the state of the programmable logic device itself, the access state of the pull-up component, and the access state of the pull-down component; After changing the state of the test device based on the test instruction, testing the DUT interface.
6. The method according to claim 5, characterized in that, The test instruction is used to instruct the programmable logic device to change the state of its own pins to the input state; The testing of the DUT interface includes: Under the condition of controlling the low-speed signal pins of the DUT interface to output a preset level signal, acquiring the measured target level signal; When the target level signal is consistent with the preset level signal, determining that the connection between the low-speed signal pins of the DUT interface and the connector is normal.
7. The method according to claim 5, characterized in that, The test instruction is used to instruct the programmable logic device to change its state to the communication signal interface state; The testing of the DUT interface includes: Under the condition of controlling the low-speed signal pins of the DUT interface to output a test communication signal, acquiring the measured target communication signal; When the target communication signal is consistent with the test communication signal, determining that the communication signal transmission between the low-speed signal pins of the DUT interface and the connector is normal.
8. The method according to claim 5, characterized in that, The test instruction is used to instruct the programmable logic device to change the state of its own pin to the input state and control the pull-up component to access the test device; The testing of the interface under test includes: Obtaining the level state of the low-speed signal pin of the interface under test; When the level state of the low-speed signal pin of the interface under test is high level, determining that there is a fault in the pull-down resistor connected to the low-speed signal pin inside the interface under test.
9. The method according to claim 5, wherein The test instruction is used to instruct the programmable logic device to change the state of its own pin to the input state and control the pull-down component to access the test device; The testing of the interface under test includes: Obtaining the level state of the low-speed signal pin of the interface under test; When the level state of the low-speed signal pin of the interface under test is low level, determining that there is a fault in the pull-up resistor connected to the low-speed signal pin inside the interface under test.
10. An electronic device, characterized in that, It includes a programmable logic device and a memory. Among them, the memory stores a computer program. When the computer program is executed by the programmable logic device, the programmable logic device executes the steps of any one of claims 5 to 9.