Cable interconnection detection method and device, storage medium and program product

Abstract

The invention discloses a cable interconnection detection method and device, a storage medium and a program product, and relates to the technical field of servers. A first storage module and a first switch are introduced, the first storage module is connected with a to-be-detected interface through the first switch, and after the to-be-detected interface is connected with a to-be-detected interface of an opposite-end device, the to-be-detected interface can be connected with the to-be-detected interface of the opposite-end device; according to the embodiment of the invention, the second verification information of the opposite-end equipment is acquired, and then the second verification information can be matched with the local interconnection topology information to verify whether the cable is correctly connected or not. The cable interconnection detection efficiency and accuracy are improved, cable interconnection detection can be automatically carried out after alternating current power-on, and connection errors are corrected as soon as possible.

Description

Technical Field

[0001] This application relates to the technical field of servers, and particularly to a method and device for detecting cable interconnection, a storage medium, and a program product. Background Art

[0002] It is a current trend that multiple server nodes are interconnected to meet the needs of diversified services. Accurate cable interconnection between server nodes is the basis for the stable operation of the server.

[0003] In related technologies, the error rate can be reduced through preventive design of cables. However, both the detection efficiency and the accuracy are relatively low. Summary of the Invention

[0004] This application provides a method and device for detecting cable interconnection, a storage medium, and a program product, so as to improve the accuracy and detection efficiency of cable interconnection detection between servers.

[0005] This application provides a cable interconnection detection circuit, including:

[0006] A first interface to be detected;

[0007] A first storage module for storing first verification information; the first verification information is determined according to the first interconnection topology information corresponding to the first interface to be detected;

[0008] A first switch, with its first input end connected to the first interface to be detected and its output end connected to the first storage module, for conducting a second channel between the first interface to be detected and the first storage module when the first interface to be detected is connected to a second interface to be detected of a peer device; the second channel is used to transmit the first verification information to the cable interconnection detection circuit of the peer device;

[0009] A first controller, connected to the first interface to be detected, for obtaining second verification information through the first interface to be detected and determining a first detection result according to the second verification information and the first interconnection topology information; the second verification information is determined according to the second interconnection topology information corresponding to the second interface to be detected.

[0010] This application provides a server, including: a first node and a second node;

[0011] The cable interconnection detection circuit of the first node includes: a first interface to be detected, a first storage module, a first switch, and a first controller; the cable interconnection detection circuit of the second node includes: a second interface to be detected, a second storage module, a second switch, and a second controller;

[0012] A first storage module for storing first verification information; the first verification information is determined according to the first interconnection topology information corresponding to the first interface to be detected;

[0013] A second storage module for storing second verification information; the second verification information is determined according to second interconnection topology information corresponding to a second interface to be detected.

[0014] A first switch for conducting a second channel between the first interface to be detected and the first storage module when the first interface to be detected is connected to the second interface to be detected.

[0015] A second switch for conducting a second channel between the second interface to be detected and the second storage module when the first interface to be detected is connected to the second interface to be detected.

[0016] A first controller for obtaining the second verification information through the second channel corresponding to the second switch and determining a first detection result according to the second verification information and the first interconnection topology information.

[0017] A second controller for obtaining the first verification information through the second channel corresponding to the first switch and determining a second detection result according to the first verification information and the second interconnection topology information.

[0018] This application provides a method for detecting cable interconnection, which is applied to a cable interconnection detection circuit. The cable interconnection detection circuit includes: a first controller, a first switch, a first interface to be detected, and a first storage module; a first input end of the first switch is connected to the first interface to be detected, and an output end is connected to the first storage module; the first controller is connected to the first interface to be detected.

[0019] The method includes:

[0020] Obtaining second verification information when the first interface to be detected is connected to a second interface to be detected of a peer device; the second verification information is stored in a second storage module of the peer device and is determined according to second interconnection topology information corresponding to the second interface to be detected.

[0021] Determining a first detection result according to the second verification information and the first interconnection topology information corresponding to the first interface to be detected.

[0022] This application further provides a cable interconnection detection device, including:

[0023] An obtaining module for obtaining second verification information when the first interface to be detected is connected to a second interface to be detected of a peer device; the second verification information is stored in a second storage module of the peer device and is determined according to second interconnection topology information corresponding to the second interface to be detected.

[0024] A determining module for determining a first detection result according to the second verification information and the first interconnection topology information corresponding to the first interface to be detected.

[0025] The present application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above cable interconnection detection methods when executing the computer program.

[0026] The present application also provides a computer-readable storage medium storing a computer program, wherein the computer program implements the steps of any of the above cable interconnection detection methods when executed by a processor.

[0027] The present application also provides a computer program product including a computer program, and the computer program implements the steps of any of the above cable interconnection detection methods when executed by a processor.

[0028] Through the present application, a first storage module and a first switch are introduced, and the first storage module is connected to the interface to be detected through the first switch. After the interface to be detected is connected to the interface to be detected of the peer device, the second verification information of the peer device can be obtained, and then the second verification information can be matched with the local interconnection topology information to verify whether the cable is correctly connected. This improves the efficiency and accuracy of cable interconnection detection, and can realize automatic cable interconnection inspection after AC power-on to correct connection errors early. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0030] Figure 1 Schematic diagram of the interconnection topology of the server provided by the embodiment of the present application;

[0031] Figure 2 Schematic structure of the cable interconnection detection circuit provided by the embodiment of the present application Figure 1 ;

[0032] Figure 3a Schematic structure of the cable interconnection detection circuit provided by the embodiment of the present application Figure 2 ;

[0033] Figure 3b Schematic diagram of the structure of the server provided by the embodiment of the present application;

[0034] Figure 4 Schematic flow chart of the cable interconnection detection method provided by the embodiment of the present application;

[0035] Figure 5 Schematic diagram of the structure of the cable interconnection detection device provided by the embodiment of the present application;

[0036] Figure 6 A structural schematic diagram of the electronic device provided for this application. Specific embodiments

[0037] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.

[0038] It should be noted that in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0039] The CPU of a single server has limitations in function. With the progress of server technology and the increase in diverse business requirements, the demand for higher-performance servers has become more urgent. Therefore, two server design concepts have emerged: scale-up and scale-out.

[0040] Among them, Scale-up is to meet the needs of business growth by improving the hardware performance of a single server, integrating more CPU, memory, storage and other resources in one server to process more business; scale-out is to expand the processing power of the system by increasing the number of servers, forming a server cluster with multiple servers, and jointly coping with high-traffic business requirements through reasonable task allocation.

[0041] Whether it is scale-up or scale-out, interconnection is the basis for its implementation. Especially for scale-up servers, the number of CPUs in a single server node is limited (usually 1 / 2 / 4), and it is necessary to interconnect through cables between server nodes to converge the CPU resources of multiple nodes together.

[0042] For scale-up multi-way servers, the number of CPUs is large and the cable interconnection topology is complex. To save costs, there are generally only a few cable specifications and the interfaces are the same, which poses risks such as misconnection. Problems such as improper connection or connection error may cause some server nodes to fail or the entire machine to malfunction.

[0043] The Scale-up multi-server has powerful single-machine performance and is generally responsible for more critical services. Therefore, stricter requirements are imposed on the reliability of the server and so on.

[0044] Based on the above multi-server interconnection requirements, the correct detection of the cable interconnection situation between multiple servers is the basis for ensuring the normal operation of the multi-server topology.

[0045] In the related art, cables are commonly used materials in servers and are widely applied in servers. To avoid incorrect cable connections during server installation and maintenance and improve the reliability and maintenance efficiency of the system, there are a series of preventive designs. For example, the connector structures are inconsistent, and connectors with different functions cannot be connected to each other. For connectors and cables of the same specification, anti-fooling cannot be achieved. The colors are inconsistent. For example, in the scenario where the cable interfaces are the same but the lengths are different, the cable categories are distinguished by colors. This design can assist in the assembly of server cables, but it cannot ensure that the cables are interconnected exactly as designed. Especially in the scenario of a large number of cable interconnections, human factors may still lead to incorrect cable connections. Through interface numbers and cable labels, the interconnection relationship is prompted. This design is similar to the second one and can improve the assembly efficiency, but it also cannot completely avoid the problem of incorrect cable connections. However, the above-mentioned ways of preventive design for cables rely on manual inspection, which has a probability of error. Moreover, the inspection efficiency is low. If the error is not found during the previous assembly, the problem can only be discovered when the machine is powered on and running or fails. It is necessary to shut down and power off the server and then assemble the cables again, which affects the server business and maintenance.

[0046] To solve the above technical problems, the inventors of this application have found that the interconnection topology information of two devices to be connected can be verified. Specifically, a storage module can be set at each server node to store the verification information generated according to the interconnection topology information of the devices. Then, after the interfaces of two server nodes are connected, the verification information of each other is read mutually and matched with the local interconnection topology information to perform automatic detection of the interconnection correctness. Based on this, an embodiment of this application provides a cable interconnection detection circuit.

[0047] To enable those skilled in the art of this technology to better understand the solution of this application, the following further details this application in conjunction with the accompanying drawings and specific implementation manners.

[0048] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the cable interconnection detection method depends, the specific application environment architecture or specific hardware architecture is described herein. To cope with different business requirements and computing types, the server can have multiple interconnection topology designs, such as full interconnection topology, symmetric topology, etc., and there are some trade-offs for the internal interconnection bandwidth of server nodes and the interconnection bandwidth between nodes. The cable interconnection detection method provided by the embodiments of this application can be applicable to multiple scenarios suitable for cable interconnection. Refer toFigure 1 , Figure 1 is a schematic diagram of the interconnection topology of the server provided by the embodiment of the present application. As Figure 1 shown, the interconnection topology includes three servers, Server 1, Server 2, and Server 3. Each server includes n central processing units (CPUs) (n is generally 1 / 2 / 4, without limitation), and each CPU has two external interfaces A and B (the number of interfaces varies according to different CPU designs and interconnection topology designs, and this embodiment does not limit it). The servers are interconnected through cables to form an interconnection architecture.

[0049] Figure 2 is a schematic diagram of the structure of the cable interconnection detection circuit provided by the embodiment of the present application Figure 1 , as Figure 2 shown, the cable interconnection detection circuit includes: a first interface to be detected 204, a first storage module 203, a first switch 202, and a first controller 201. The first storage module 203 is used to store first verification information; the first verification information is determined according to the first interconnection topology information corresponding to the first interface to be detected 204. The first switch 202, with its first input terminal connected to the first interface to be detected 204 and its output terminal connected to the first storage module 203, is used to conduct the second channel between the first interface to be detected 204 and the first storage module 203 when the first interface to be detected 204 is connected to the second interface to be detected of the peer device; the second channel is used to transmit the first verification information to the cable interconnection detection circuit of the peer device. The first controller 201, connected to the first interface to be detected 204, is used to obtain second verification information through the first interface to be detected 204 and determine a first detection result according to the second verification information and the first interconnection topology information; the second verification information is determined according to the second interconnection topology information corresponding to the second interface to be detected.

[0050] In this embodiment, the first interface to be detected 204 refers to the interface for cable connection. The first interface to be detected 204 can be each interface in the server node that needs to be interconnected with other nodes by cables. For example, it can be Figure 1 the A and B interfaces of the CPU shown, or it can also be the interfaces of the memory or other components.

[0051] The first storage module 203 can be a non-volatile memory, such as an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Ferroelectric Random Access Memory (FRAM), a Magnetoresistive Random Access Memory (MRAM), a Non-Volatile Random Access Memory (NVRAM), etc. Optionally, in order to break through the limitations in capacity, speed, and functionality and meet the detection requirements of high-complexity server interconnection topologies, the first storage module 203 can be a hierarchical storage structure. Specifically, it includes a metadata memory and a distributed storage pool. Among them, the metadata memory can use EEPROM to store metadata, that is, verification information such as topology verification keys and a storage pool routing table. Each node of the distributed storage can use a new type of non-volatile memory and be interconnected through a PCIe / CXL bus. By adopting a hierarchical storage structure and combining the metadata memory and the distributed storage pool, the limitations of traditional storage in capacity, speed, and functionality are broken through, and the detection requirements of high-complexity server interconnection topologies are met. The new type of non-volatile memory interconnected through the PCIe / CXL bus further improves the performance and flexibility of the system.

[0052] The first controller 201 can be a Baseboard Management Controller (BMC). The BMC is an independent control unit in hardware such as servers and industrial devices. It is usually integrated on the motherboard and connected to the system through a dedicated network interface (such as RJ45) or an internal bus (such as I2C, SPI).

[0053] In this embodiment, the first interconnection topology information includes the information and connection correspondence of each to-be-detected interface of each server node that each first to-be-detected interface 204 needs to connect to. Exemplarily, taking Server 1, Server 2, and Server 3 as examples, Server 1 includes three interfaces X1, X2, and X3, Server 2 includes three interfaces Y1, Y2, and Y3, and Server 3 includes two interfaces Z1 and Z2. Assuming the correct connection relationships are X1Y2, X2Z1, X3Y1, and Y3Z2. Then for Server 1, in order to reduce the storage amount, it can only include the connection relationships related to its own device. For example, its first interconnection topology information can include X1Y2, X2Z1, and X3Y1.

[0054] The first verification information is the information obtained after processing such as converting and / or encrypting the first interconnection topology information, and the verification information includes the corresponding connection relationships between interfaces in the first interconnection topology information.

[0055] In this embodiment, the first storage module 203 uses the I2C interface for data access. By using the I2C interface, the first storage module 203 can achieve efficient and reliable data access in the system, while simplifying the hardware design and system integration, and is suitable for various application scenarios.

[0056] In the specific working process, after AC power-on, when the first interface to be detected 204 is connected to the second interface to be detected of the peer device, the first switch 202 is turned on, allowing the first verification information in the first storage module 203 to be transmitted to the peer device through the second channel. The cable interconnection detection circuit of the peer device will receive the first verification information and may perform corresponding processing or verification. The first verification information can be verified with the second interconnection topology information corresponding to the peer device stored locally in the peer device to determine whether the two match, and then the detection result can be obtained. At the same time, the first controller 201 can obtain the second verification information provided by the peer device through the first interface to be detected 204. The first controller 201 compares the received second verification information with the first interconnection topology information stored locally to determine whether the connection conforms to the expected topology structure. According to the comparison result, the first controller 201 generates the first detection result to indicate the correctness of the connection.

[0057] The cable interconnection detection circuit provided by the embodiment of the present application, by introducing the first storage module 203 and the first switch 202, and connecting the first storage module 203 to the interface to be detected through the first switch 202, can obtain the second verification information of the peer device after the interface to be detected is connected to the interface to be detected of the peer device, and then the second verification information can be matched with the local interconnection topology information to verify whether the cable is correctly connected. The cable interconnection detection efficiency and accuracy are improved, and it can be realized that the cable interconnection check is automatically performed after AC power-on to correct the connection error as early as possible.

[0058] In some embodiments, the second input terminal of the first switch 202 is connected to the first interface to be detected 204; the first controller 201 is configured to store the first verification information in the first storage module 203 when the first switch 202 selects the first channel between the first controller 201 and the first storage module 203.

[0059] In this embodiment, the first switch 202 can be a switching switch, which can realize the switching between two channels. Specifically, through the switching control of the first switch 202, the first storage module 203 can be connected to the first controller 201, and the first storage module 203 can also be connected to the first interface to be detected 204.

[0060] In the specific implementation process, the first channel can be switched to connect the first controller 201 to the first storage module 203. The first controller 201 stores the first check information generated according to the first interconnection topology information in the first storage module 203, or updates the first check information already stored in the first storage module 203, so that the first check information in the first storage module 203 is always consistent with the latest first interconnection topology information, because the first interconnection topology information can be updated. Then, the second channel can be switched, so that the peer device can read the first check information stored in the first storage module 203 from the first storage module 203 through the first interface to be detected 204 via the second channel.

[0061] The cable interconnection detection circuit provided by the embodiment of the present application realizes flexible switching between two channels by using a switching switch, significantly improving the efficiency and flexibility of the system in terms of check information management and transmission. Specifically, the design of the first switch 202 allows a connection to be established between the first controller 201 and the first storage module 203, enabling the system to timely store or update the latest first check information to the first storage module 203 to ensure its consistency with the current interconnection topology information. This dynamic update mechanism adapts to changes in the topology information and avoids connection errors caused by information lag. In addition, by switching to the second channel, the peer device can read the check information stored in the first storage module 203 through the first interface to be detected 204, realizing effective transmission and verification of the information. Overall, this design not only improves the adaptability and reliability of the system, but also reduces the maintenance complexity, enhancing the stability and performance of the overall system, and is applicable to network environments that require high dynamicity and high reliability.

[0062] In some embodiments, the control end of the first switch 202 is connected to the first controller 201; the first controller 201 is further configured to obtain the connection state of the first interface to be detected 204 and perform switching control on the first switch 202 according to the connection state.

[0063] In this embodiment, the channel switching control of the first switch 202 can be controlled by the first controller 201. Specifically, the first controller 201 can detect whether the first interface to be detected 204 is in a connected state. When it is in a non-connected state, the first channel can be switched so that the first controller 201 updates the first check information in the first storage module 203 or stores the first check information in the first storage module 203. When it is in a connected state, the second channel can be switched so that the peer device reads the check information from the first storage module 203 through the connected interface to be detected, the interconnected cable, and the second channel.

[0064] The cable interconnection detection circuit provided by the embodiment of the present application realizes intelligent management of channel switching by connecting the control end of the first switch 202 to the first controller 201, further enhancing the automation and response capabilities of the system. Specifically, the first controller 201 can detect the connection status of the first interface to be detected 204 in real time and dynamically control the channel switching of the first switch 202 according to this status. When the interface is not connected, the system automatically switches to the first channel, enabling the first controller 201 to update or store the latest verification information to the first storage module 203 to ensure the timeliness and accuracy of the information. When the interface is connected, the system switches to the second channel, allowing the peer device to read the verification information from the first storage module 203 through the connected interface and cable, realizing the effective transmission and verification of the information. This design not only improves the flexibility and adaptability of the system, reduces the need for manual intervention, but also ensures the information consistency and reliability during the connection process, enhancing the stability and performance of the overall system, and is applicable to a dynamically changing network environment.

[0065] In some embodiments, the first verification information is pre-stored in the first storage module 203 through an offline burn-in file.

[0066] In the specific implementation process, before device deployment, the first verification information is first generated in a secure and controlled environment. This process may include extracting relevant connection relationships from the designed interconnection topology information and formatting and encrypting them. The generated verification information is packaged into a burn-in file, which contains the verification information required by the device.

[0067] In the device manufacturing or configuration stage, the verification information in the burn-in file is written into the first storage module 203 of the device through a dedicated burn-in device or tool. This offline burn-in method ensures the accuracy of the verification information and reduces the complexity and time of on-site configuration.

[0068] Since the verification information is generated and burned in a controlled environment, the security of the information is improved, avoiding potential security vulnerabilities that may occur during on-site configuration.

[0069] The cable interconnection detection circuit provided by the embodiment of the present application pre-stores verification information by means of an offline burn-in file, providing an efficient and secure verification information management solution, which is applicable to network environments that require high reliability and rapid deployment.

[0070] In some embodiments, the cable interconnection detection circuit further includes a first basic input / output system; the first basic input / output system is connected to the first controller 201 and is used to store the first interconnection topology information corresponding to the first interface to be detected 204 and send the interconnection topology information to the first controller 201.

[0071] In this embodiment, the first Basic Input / Output System (BIOS) may pre-store at least one interconnection topology information.

[0072] Exemplarily, as Figure 3a shown, the BIOS (i.e., the first Basic Input / Output System) records the first interconnection topology information corresponding to the server node. The first interconnection topology information can be set as required and updated by upgrading the BIOS file.

[0073] The BMC (i.e., the first controller 201) collects the first interconnection topology information, generates the first check information based on the first interconnection topology information, detects the connection status of the interface to be detected (interface Ax / Bx), or detects the instruction input by the user, and then performs switching control of the first switch 202 (I2C MUX) based on the connection status and / or the input instruction, so as to implement the processing of the detection logic and output detection results such as interconnection error information.

[0074] The I2C MUX (i.e., the first switch 202) switches the I2C link. The BMC controls the switching logic through the GPIO_SW signal and can select the first channel BMC - I2C - EEPROM or the second channel interface Ax / Bx - I2C - EEPROM.

[0075] The EEPROM (i.e., the first storage module 203) is an electrically erasable programmable read-only memory. The BMC generates check information according to the topology and stores the first check information generated according to the first interconnection topology information in the EEPROM through the I2C bus. The first check information can be pre-stored in the EEPROM by off-line burning a file, or can be updated online to the EEPROM through the I2C bus of the BMC.

[0076] The interface Ax / Bx (i.e., the first interface to be detected 204), such as the external interconnection interface of the CPU of the server node, may further include an I2C signal and a presence signal Present_N in addition to the CPU bus signal. The presence signal is used to indicate whether the first interface to be detected 204 is in a connected state.

[0077] In the specific implementation process, after AC power-on, the first controller 201 can read the pre-stored multiple interconnection topology information from the first Basic Input / Output System, and can receive the selection of the multiple interconnection topology information by the user through the interface operation, so as to realize the update of the first interconnection topology information. The flexibility is improved.

[0078] The cable interconnection detection circuit provided by the embodiment of the present application realizes flexible management of interconnection topology information by integrating the first basic input / output system in the cable interconnection detection circuit, significantly improving the adaptability of the system. Specifically, the BIOS pre-stores various interconnection topology information. After the device is powered on, the first controller 201 can read it and select the topology information suitable for the current application through the user interface. This design not only enhances the flexibility of the system and the convenience of user operation, but also supports quickly adapting to changes in network configuration, reduces downtime, improves the availability and reliability of the system, and is applicable to complex network environments that require frequent adjustment.

[0079] The embodiment of the present application also provides a server, including: a first node and a second node; the cable interconnection detection circuit of the first node includes: a first interface to be detected 204, a first storage module 203, a first switch 202, and a first controller 201; the cable interconnection detection circuit of the second node includes: a second interface to be detected, a second storage module, a second switch, and a second controller; the first storage module 203 is used to store first verification information; the first verification information is determined according to the first interconnection topology information corresponding to the first interface to be detected 204; the second storage module is used to store second verification information; the second verification information is determined according to the second interconnection topology information corresponding to the second interface to be detected; the first switch 202 is used to conduct a second channel between the first interface to be detected 204 and the first storage module 203 when the first interface to be detected 204 is connected to the second interface to be detected; the second switch is used to conduct a second channel between the second interface to be detected and the second storage module when the first interface to be detected 204 is connected to the second interface to be detected; the first controller 201 is used to obtain the second verification information through the second channel corresponding to the second switch, and determine a first detection result according to the second verification information and the first interconnection topology information; the second controller is used to obtain the first verification information through the second channel corresponding to the first switch 202, and determine a second detection result according to the first verification information and the second interconnection topology information.

[0080] The cable interconnection detection circuit provided by the embodiment of the present application realizes automated interconnection topology detection and verification by integrating the cable interconnection detection circuit in the first node and the second node of the server. Each node stores and manages its interconnection topology information and verification information, and the controller obtains the verification information of the other node through the switch mechanism for comparison, thereby automatically generating a detection result. This design not only improves the reliability of the system and prevents failures caused by incorrect connections, but also helps engineers quickly identify and correct connection problems through a real-time error detection and feedback mechanism. In addition, the flexible channel switching and dynamic adaptation capabilities simplify network maintenance and management, ensuring the stable operation of the system under different configurations, and are suitable for complex network environments that require high reliability and fast response.

[0081] Exemplarily, as Figure 3b shown, BIOS1 (i.e., the first basic input / output system) records the first interconnection topology information of the first node. This first interconnection topology information can be set as required and updated by upgrading the BIOS file.

[0082] BMC1 (i.e., the first controller 201) collects the first interconnection topology information, generates the first check information based on this first interconnection topology information, detects the connection status of the interface to be detected (interface Ax / Bx1), or detects the instructions input by the user, and then performs switching control of the first switch 202 (I2C MUX1) based on the connection status and / or input instructions, thereby realizing the processing of the detection logic and outputting the first detection results such as interconnection error information.

[0083] I2C MUX1 (i.e., the first switch 202) switches the I2C link. BMC1 controls the switching logic through the GPIO_SW signal and can select the first channel BMC1 - I2C–EEPROM1 or the second channel interface Ax / Bx1 - I2C–EEPROM1.

[0084] EEPROM1 (i.e., the first storage module 203), an electrically erasable programmable read-only memory. BMC1 generates check information according to the topology and stores the first check information generated according to the first interconnection topology information in EEPROM1 through the I2C bus. The first check information can be pre-stored in EEPROM1 through an offline burn-in file, or can be updated online to EEPROM1 through the I2C bus of BMC1.

[0085] Interface Ax / Bx1 (i.e., the first interface to be detected 204), such as the external interconnection interface of the CPU of the server node. In addition to the CPU bus signal, it can also include the I2C signal and the presence signal Present_N. The presence signal is used to indicate whether the first interface to be detected 204 is in a connected state.

[0086] BIOS2 (i.e., the second basic input / output system) records the first interconnection topology information of the second node. This second interconnection topology information can be set as required and updated by upgrading the BIOS file.

[0087] BMC2 (i.e., the second controller) collects the second interconnection topology information, generates the second check information based on this second interconnection topology information, detects the connection status of the interface to be detected (interface Ax / Bx2), or detects the instructions input by the user, and then performs switching control of the second switch (I2C MUX2) based on the connection status and / or input instructions, thereby realizing the processing of the detection logic and outputting detection results such as interconnection error information.

[0088] The I2C MUX2 (i.e., the second switch) switches the I2C link. The BMC2 controls the switching logic through the GPIO_SW signal and can select the first channel BMC2 - I2C–EEPROM2 or the second channel interface Ax / Bx2 - I2C–EEPROM2.

[0089] The EEPROM2 (i.e., the second storage module) is an electrically erasable programmable read-only memory. The BMC2 generates check information according to the topology and stores the first check information generated according to the first interconnection topology information in the EEPROM2 through the I2C bus. The first check information can be pre-stored in the EEPROM2 by burning an offline file or updated online to the EEPROM2 through the I2C bus of the BMC2.

[0090] The interface Ax / Bx2 (i.e., the second interface to be detected), such as the external interconnection interface of the CPU of the server node, may include an I2C signal and a presence signal Present_N in addition to the CPU bus signal. The presence signal is used to indicate whether the second interface to be detected is in a connected state.

[0091] In the specific implementation process, in Server 1 (the first node) and Server 2 (the second node), after AC power-on, at this time, BIOS1 and BIOS2, BMC1 and BMC2, I2C MUX1 and I2C MUX2, and EEPROM1 and EEPROM2 are all powered on and working.

[0092] The BMC1 obtains the first interconnection topology information set in the BIOS1, compares the first interconnection topology information with the first check information stored in the EEPROM1, and confirms whether the two match. If they do not match, it indicates that the first interconnection topology information in the BIOS1 has been updated. The BMC1 can generate new first check information according to the currently updated first interconnection topology information and update it to the EEPROM1 through the I2C bus. Similarly, the BMC2 obtains the second interconnection topology information set in the BIOS2, compares the second interconnection topology information with the second check information stored in the EEPROM2, and confirms whether the two match. If they do not match, it indicates that the second interconnection topology information in the BIOS2 has been updated. The BMC2 can generate new second check information according to the currently updated second interconnection topology information and update it to the EEPROM2 through the I2C bus. Thus, the correct check information of each node is stored in the EEPROM1 and the EEPROM2.

[0093] The BMC1 detects whether the cable of the detection interface Ax / Bx1 is in place, that is, whether the first interface to be detected 204 is in a connected state. If the cable is not in place, the Present_n signal is 1 (high level), the I2C MUX1 is the default first channel, BMC1–I2C1–I2C MUX1–EEPROM1; if the cable is in place, the Present_n signal is 0 (low level), the BMC1 controls the GPIO_SW signal to select the second channel, interface Ax / Bx1–I2C2_2–I2C MUX1–EEPROM1. Similarly, the BMC2 detects whether the cable of the detection interface Ax / Bx2 is in place, that is, whether the second interface to be detected is in a connected state. If the cable is not in place, the Present_n signal is 1 (high level), the I2C MUX2 is the default first channel, BMC2–I2C1–I2C MUX2–EEPROM2; if the cable is in place, the Present_n signal is 0 (low level), the BMC2 controls the GPIO_SW signal to select the second channel, interface Ax / Bx2–I2C2_2–I2C MUX2–EEPROM2.

[0094] When the cable is assembled in place, the Present_n signal is 0 (low level), the I2C MUX selects the I2C signal of the interface to the EEPROM, and the links of BMC1–I2C1_2–I2C MUX2 –EEPROM2 and BMC2–I2C2_2–I2C MUX1–EEPROM1 are both connected. If the cable is not assembled in place, the Present_n signal is not set to 0, and the BMC will display the interface of the unconnected cable as an error message and the misalignment position in the interface to remind the engineer to check the cable assembly and install the cable correctly.

[0095] After the cable is assembled in place and the links of the second channel of the first switch 202 and the second switch are connected, the BMC1 reads the second check information stored in the EEPROM2 and checks it against the first interconnection topology information in the BIOS1 to confirm whether they match. Similarly, the BMC2 reads the second check information stored in the EEPROM1 and checks it against the second interconnection topology information in the BIOS2 to confirm whether they match.

[0096] If both the first detection result obtained by the BMC1 and the second detection result obtained by the BMC2 indicate a match, it means that the cable assembly between the first node and the second node meets the topology requirements. If any one of the first detection result obtained by the BMC1 and the second detection result obtained by the BMC2 indicates a mismatch, the error information and misalignment position of the cable connection will be displayed in the interface to remind the engineer to check the cable assembly and install the cable correctly.

[0097] Specifically, if the information in BIOS1 and EEPROM2 does not match during the BMC1 check, since this check is based on the first interconnection topology information in BIOS1, it indicates that the second interface to be detected on the second node is incorrectly connected; if the information in BIOS2 and EEPROM1 does not match during the BMC2 check, since this check is based on the second interconnection topology information in BIOS2, it indicates that the first interface to be detected 204 on the first node is incorrectly connected.

[0098] If the first detection result of BMC1 indicates that the first interconnection topology information does not match the second check information, indicating a cable interconnection error, then BMC1 does not allow the first node server to execute the power-on instruction, and the server power-on instruction is invalid. The cable interconnection error information needs to be resolved first. If the first detection result of BMC1 indicates that the check information matches, the first node server is allowed to execute the power-on instruction. Similarly, if the second detection result of BMC2 indicates that the second interconnection topology information does not match the first check information, indicating a cable interconnection error, then BMC2 does not allow the second node server to execute the power-on instruction, and the server power-on instruction is invalid. The cable interconnection error information needs to be resolved first. If the second detection result of BMC2 indicates that the check information matches, the second node server is allowed to execute the power-on instruction.

[0099] The cable interconnection detection circuit provided in the embodiments of the present application integrates a cable interconnection detection circuit in the server node, realizing automatic detection and verification of the interconnection topology, significantly improving the reliability and maintenance efficiency of the system. Using the basic input / output system (BIOS) and the programmable read-only memory (EEPROM), the system can automatically obtain and store the interconnection topology information, and the controller (BMC) can verify the correctness of the connection in real time. The I2C multiplexer (I2C MUX) realizes flexible channel switching to ensure correct operation in different connection states. When a connection error is detected, the system will display specific error information on the interface to remind the engineer to check and correct it. Only when the check information matches, the system allows the node server to execute the power-on instruction, effectively preventing system failures caused by incorrect connections. This design not only improves the stability and reliability of the system, but also simplifies network maintenance and management, and is applicable to complex network environments that require high reliability and fast response.

[0100] Figure 4 It is a schematic flowchart of the cable interconnection detection method provided in the embodiments of the present application, as Figure 4As shown, an embodiment of the present application provides a method for detecting cable interconnection, which is applied to a cable interconnection detection circuit. The cable interconnection detection circuit includes: a first controller, a first switch, a first interface to be detected, and a first storage module; a first input end of the first switch is connected to the first interface to be detected, and an output end is connected to the first storage module; the first controller is connected to the first interface to be detected; a detailed description of the method is as follows:

[0101] 401. When the first interface to be detected is connected to a second interface to be detected of a peer device, obtain second verification information; the second verification information is stored in a second storage module of the peer device and is determined according to second interconnection topology information corresponding to the second interface to be detected.

[0102] The execution entity of this embodiment is the first controller.

[0103] Specifically, after AC power-on, when the first interface to be detected is connected to the second interface to be detected of the peer device, the first switch is turned on, allowing the first verification information in the first storage module to be transmitted to the peer device through the second channel. The cable interconnection detection circuit of the peer device will receive the first verification information and may perform corresponding processing or verification. The first verification information can be verified against the second interconnection topology information corresponding to the peer device stored locally in the peer device to determine whether they match, and then obtain a detection result. At the same time, the first controller can obtain the second verification information provided by the peer device through the first interface to be detected. The first controller compares the received second verification information with the first interconnection topology information stored locally to determine whether the connection conforms to the expected topological structure. According to the comparison result, the first controller generates a first detection result to indicate the correctness of the connection.

[0104] In this embodiment, the first interface to be detected refers to an interface for cable connection. The first interface to be detected can be an interface in each server node that needs to perform cable interconnection with other nodes. For example, it can be Figure 1 the A and B interfaces of the CPU shown, or it can also be an interface of the memory or other components.

[0105] The first storage module can be a non-volatile memory, such as an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Ferroelectric Random Access Memory (FRAM), a Magnetoresistive Random Access Memory (MRAM), a Non-Volatile Random Access Memory (NVRAM), etc. Optionally, in order to break through the limitations in capacity, speed, and functionality and meet the detection requirements of high-complexity server interconnection topologies, the first storage module can be a hierarchical storage structure. Specifically, it includes a metadata memory and a distributed storage pool. Among them, the metadata memory can use EEPROM to store metadata, that is, verification information such as topology verification keys and storage pool routing tables. Each node of the distributed storage can use a new type of non-volatile memory and be interconnected through a PCIe / CXL bus. By adopting a hierarchical storage structure and combining the metadata memory and the distributed storage pool, the limitations of traditional storage in capacity, speed, and functionality are broken through, and the detection requirements of high-complexity server interconnection topologies are met. The new type of non-volatile memory interconnected through a PCIe / CXL bus further improves the performance and flexibility of the system.

[0106] The first controller can be a Baseboard Management Controller (BMC). The BMC is an independent control unit in hardware such as servers and industrial devices. It is usually integrated on the motherboard and connected to the system through a dedicated network interface (such as RJ45) or an internal bus (such as I2C, SPI).

[0107] In this embodiment, the first interconnection topology information includes the information and connection correspondence of each to-be-detected interface of each server node that each first to-be-detected interface needs to connect to. Exemplarily, taking Server 1, Server 2, and Server 3 as examples, Server 1 includes three interfaces X1, X2, and X3, Server 2 includes three interfaces Y1, Y2, and Y3, and Server 3 includes two interfaces Z1 and Z2. Assuming the correct connection relationships are X1Y2, X2Z1, X3Y1, and Y3Z2. Then for Server 1, in order to reduce the storage amount, it can only include the connection relationships related to its own device. For example, its first interconnection topology information can include X1Y2, X2Z1, and X3Y1.

[0108] The first verification information is the information obtained after processing the first interconnection topology information through conversion and / or encryption, etc. The verification information includes the corresponding connection relationships between interfaces in the first interconnection topology information.

[0109] In this embodiment, the first storage module uses the I2C interface for data access. By using the I2C interface, the first storage module can achieve efficient and reliable data access in the system, while simplifying the hardware design and system integration, and is suitable for various application scenarios.

[0110] 402. Determine the first detection result according to the second verification information and the first interconnection topology information corresponding to the first interface to be detected.

[0111] Specifically, after obtaining the second verification information, the second verification information includes the correct interface connection relationship corresponding to the second interface to be detected of the peer device, and the first interconnection topology information includes the correct interface connection relationship corresponding to the first interface to be detected of its own device. After matching and comparing the two pieces of information, it can be known whether the interface that the first interface to be detected needs to be correctly connected to is the same interface in the two pieces of information. If so, it indicates a match; if not, it indicates a mismatch.

[0112] As can be seen from the above description, the cable interconnection detection method provided by the embodiments of the present application realizes efficient connection correctness verification by automatically obtaining and verifying the interconnection topology information between devices. When the first interface to be detected is connected to the second interface to be detected of the peer device, the system can automatically obtain the second verification information stored in the peer device and compare it with the local interconnection topology information, thereby generating a detection result. This method effectively improves the reliability of the system, ensures the accuracy of the connection between devices, and reduces the possibility of human errors. Through the automated detection process, engineers can quickly identify and solve connection problems, simplify network maintenance and management, and are applicable to complex network environments that require high reliability and fast response. And the detection timing of this detection method can be after AC power-on and before DC startup, which can quickly detect cable connection errors, correct them in time, and improve the efficiency of correct cable interconnection.

[0113] In some embodiments, in order to improve flexibility, the first controller can be used to write the verification information to the first storage module. The second input end of the first switch is connected to the first interface to be detected; before obtaining the second verification information, it can further include: when the first switch selects the first channel between the first controller and the first storage module, storing the first verification information in the first storage module.

[0114] The cable interconnection detection method provided by the embodiments of the present application is designed such that the second input terminal of the first switch is connected to the first interface to be detected. When the system selects the channel between the first controller and the first storage module, the first verification information can be automatically stored in the first storage module. This method ensures that the verification information is correctly stored before the connection is established, providing a reliable data basis and thus improving the accuracy of the detection results. The automated storage process not only simplifies the operation process, reduces manual intervention, but also enhances the flexibility and efficiency of the system. In addition, by ensuring the correctness of the data transmission path, the risk of errors is reduced, and system maintenance is simplified, making it suitable for complex network environments that require high precision and high reliability.

[0115] In some embodiments, there can be multiple ways to control the switching of the first switch.

[0116] In one implementable way, the automatic switching can be based on specific conditions. Specifically, the control terminal of the first switch is connected to the first controller; after storing the first verification information in the first storage module, it further includes: obtaining the connection status of the first interface to be detected; if the connection status indicates that the first interface to be detected is in a connected state, then perform switching control on the first switch to select the second channel between the first interface to be detected and the first storage module. The cable interconnection detection method provided by the embodiments of the present application enables the system to automatically switch channels based on specific conditions by connecting the control terminal of the first switch to the first controller. Specifically, after storing the first verification information in the first storage module, the system will obtain the connection status of the first interface to be detected. If the connection status indicates that the interface is connected, the system will automatically switch the first switch to select the second channel between the first interface to be detected and the first storage module. This automatic switching mechanism brings significant beneficial effects: First, it improves the system's response speed and operation efficiency, reducing the need for manual intervention. Second, through automated channel switching, the correctness and timeliness of data transmission are ensured, reducing the risk of errors. In addition, this design enhances the flexibility and adaptability of the system, enabling it to better cope with dynamically changing network environments and being suitable for application scenarios that require high reliability and fast response.

[0117] In another implementable manner, to facilitate the operability of the user, an interface operation can be provided for switching control, and it is convenient to uniformly check after the user believes that the cable connection is completed, avoiding the frequent occurrence of error messages. After storing the first verification information in the first storage module, it further includes: displaying a first interface; the first interface includes a detection start control; in response to a touch operation on the start control, controlling the first switch to connect the first interface to be detected and the second channel of the first storage module. The cable interconnection detection method provided by the embodiments of the present application optimizes the user operation experience and the detection process by providing a user interface for switching control. After storing the first verification information, the system displays an interface including a detection start control. The user can start the detection through a touch operation after confirming that the cable connection is completed. This design reduces the frequent error messages during the connection process, reduces the interference and false alarm risks, and enables the user to uniformly check at an appropriate time. By simplifying the operation process and enhancing the system reliability, this method not only improves the user's operation flexibility and experience, but also ensures the accuracy of the detection results, and is suitable for application scenarios that require high precision and user participation.

[0118] In some embodiments, the circuit further includes a first basic input / output system connected to the first controller; before storing the first verification information in the first storage module, it further includes: obtaining first interconnection topology information stored in the first basic input / output system; generating first verification information according to the first interconnection topology information.

[0119] Specifically, by adding a first basic input / output system (BIOS) connected to the first controller, the generation and storage process of the verification information is further improved. Specifically, before storing the first verification information in the first storage module, the system first obtains the stored first interconnection topology information from the BIOS. As the basic firmware of the system, the BIOS is usually used to initialize hardware components and provide runtime services, so it stores the basic configuration and interconnection information of the device. By obtaining the first interconnection topology information from the BIOS, the system can ensure that the used topology information is the latest and most accurate. This information includes key data such as the connection structure between devices and the interface configuration. Subsequently, the system generates the first verification information according to the obtained interconnection topology information. The verification information is usually a form of encoding or summary of the topology information, which is used for subsequent connection verification and error detection.

[0120] The method provided by the embodiments of the present application utilizes the reliability and authority of the BIOS to obtain the interconnection information of the device, ensuring the accuracy and consistency of the verification information. In this way, the system can be fully prepared before storing the verification information, reducing the possibility of errors, and improving the reliability and effectiveness of the entire detection process.

[0121] In some embodiments, to improve flexibility, the first interconnection topology information may be updated. To maintain the consistency of the check information, the check information also needs to be updated. After storing the first check information in the first storage module, the method further includes: obtaining the third interconnection topology information corresponding to the first interface to be detected currently stored in the first basic input / output system; obtaining the first check information stored in the first storage module; if the third interconnection topology information does not match the first check information, generating third check information according to the third interconnection topology information, and storing the third check information in the first storage module.

[0122] The method provided by the embodiments of the present application significantly improves flexibility and data consistency by introducing a dynamic update mechanism for interconnection topology information and check information. When the stored first check information does not match the current interconnection topology information, the system automatically generates and updates new check information. This method ensures that the system can quickly adapt to changes in hardware configurations, maintaining data consistency and accuracy. Through an automated update process, the system reduces manual intervention, lowers maintenance complexity, and enhances the reliability of detection results. This design is particularly suitable for dynamically changing network environments, ensuring that the system can flexibly respond to various changes, improving overall reliability and usability.

[0123] In some embodiments, the interconnection topology information may be updated through a display interface provided by the first controller for easy user operation. Before obtaining the third interconnection topology information corresponding to the first interface to be detected currently stored in the first basic input / output system, the method further includes: obtaining multiple candidate interconnection topology information pre-stored in the first basic input / output system; displaying the multiple candidate interconnection topology information on the second interface; and determining the third interconnection topology information from the multiple candidate interconnection topology information in response to a touch operation on the second interface. The method provided by the embodiments of the present application enables users to conveniently update the interconnection topology information through the display interface provided by the first controller, thereby enhancing the operability and flexibility of the system. The system first obtains multiple candidate interconnection topology information from the BIOS and displays it on the interface. Users can select the appropriate topology information through touch operations. This design allows users to easily browse and select the most suitable configuration, reducing operation complexity and error risks, while improving the flexibility and adaptability of the system. The interface-based operation method not only simplifies the maintenance process but also supports personalized configuration, enhancing the user experience and the reliability of the system.

[0124] In some embodiments, after determining the first detection result based on the second verification information and the first interconnection topology information corresponding to the first interface to be detected, the method further includes: displaying the first detection result on a third interface for presentation. The method provided by the embodiments of the present application significantly improves the user's operation convenience and information acquisition efficiency by presenting the first detection result on the third interface. After the detection is completed, the result is immediately displayed on the interface, providing quick feedback to help the user quickly understand the system status. This design enhances the operation transparency, enabling the user to clearly see the output of the detection process, facilitating the quick diagnosis and solution of problems. In addition, the intuitive interface presentation reduces the requirements for the user's technical background, improves the user experience, and supports the user in making more informed decisions. Generally speaking, this design optimizes the timeliness and accuracy of information transmission and is suitable for application scenarios that require quick feedback and problem solving.

[0125] In this embodiment, the first detection result refers to the preliminary conclusion obtained by analyzing the second verification information and the interconnection topology information corresponding to the first interface to be detected. For example, the information matches and the interconnection is correct, or the information does not match and the interconnection is incorrect, etc. The first detection result may include the name and location of the faulty interface.

[0126] In some embodiments, displaying the first detection result on a third interface for presentation includes: if the first detection result indicates that the first interconnection topology information does not match the second verification information, then using the second interface to be detected as the faulty location and displaying the faulty location on the third interface. The method provided by the embodiments of the present application significantly improves the fault diagnosis efficiency by presenting the first detection result on the third interface, especially when the detection result shows that the first interconnection topology information does not match the second verification information, marking the second interface to be detected as the faulty location and presenting it. The user can quickly identify and locate the fault point in the system, reducing the time and effort for troubleshooting. Even non-professional users can understand the problem through the intuitive interface, lowering the technical threshold. In addition, the clear indication of the faulty location supports the user to quickly take repair measures, reducing the system downtime and enhancing the system reliability and user experience. Through the transparent presentation of information, the user's trust in the system is also enhanced.

[0127] In some embodiments, after determining the first detection result based on the second verification information and the first interconnection topology information corresponding to the first interface to be detected, the following steps are further included: If the first detection result indicates that the first interconnection topology information does not match the second verification information, before executing the power-on instruction, the power-on instruction is invalidated. The method provided in the embodiments of the present application, by determining the first detection result, if the result shows that the first interconnection topology information does not match the second verification information, invalidates the power-on instruction before executing it. This design effectively prevents the system from starting under incorrect configurations, avoiding potential faults and hardware damage. This not only improves the reliability and stability of the system, but also protects the hardware security and extends the service life of the device. In addition, by detecting and handling problems in advance, the maintenance and repair costs are reduced, and the economic benefits are improved. As a result, users can use the system with more confidence and enjoy higher security and an optimized user experience.

[0128] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0129] Figure 5 It is a schematic structural diagram of the cable interconnection detection device provided in the embodiments of the present application. As Figure 5 shown, the embodiments of the present application also provide a cable interconnection detection device, including: an acquisition module 501 and a determination module 502.

[0130] The acquisition module 501 is configured to obtain the second verification information when the first interface to be detected is connected to the second interface to be detected of the peer device; the second verification information is stored in the second storage module of the peer device and is determined according to the second interconnection topology information corresponding to the second interface to be detected;

[0131] The determination module 502 is configured to determine the first detection result according to the second verification information and the first interconnection topology information corresponding to the first interface to be detected.

[0132] The cable interconnection detection device provided by the embodiments of the present application realizes efficient verification of connection correctness by automatically acquiring and verifying interconnection topology information between devices. When the first interface to be detected is connected to the second interface to be detected of the peer device, the system can automatically acquire the second verification information stored in the peer device and compare it with the local interconnection topology information to generate a detection result. This method effectively improves the reliability of the system, ensures the accuracy of the connection between devices, and reduces the possibility of human errors. Through the automated detection process, engineers can quickly identify and solve connection problems, simplify network maintenance and management, and are applicable to complex network environments that require high reliability and quick response. Moreover, the detection timing of this detection method can be after AC power-on and before DC startup, which can quickly detect cable connection errors, correct them in time, and improve the efficiency of correct cable interconnection.

[0133] In some embodiments, the second input terminal of the first switch is connected to the first interface to be detected; the determination module 502 is further configured to: when the first switch selects the first channel between the first controller and the first storage module, store the first verification information in the first storage module.

[0134] In some embodiments, the control terminal of the first switch is connected to the first controller; the determination module 502 is further configured to: acquire the connection state of the first interface to be detected; if the connection state indicates that the first interface to be detected is in a connected state, perform switching control on the first switch to select the second channel between the first interface to be detected and the first storage module.

[0135] In some embodiments, the determination module 502 is further configured to: display the first interface; the first interface includes a detection start control; in response to a touch operation on the start control, control the first switch to select the second channel between the first interface to be detected and the first storage module.

[0136] In some embodiments, the circuit further includes a first basic input / output system connected to the first controller; the acquisition module 501 is further configured to: acquire the first interconnection topology information stored in the first basic input / output system; generate the first verification information according to the first interconnection topology information.

[0137] In some embodiments, the acquisition module 501 is further configured to: acquire the third interconnection topology information corresponding to the first interface to be detected currently stored in the first basic input / output system; acquire the first verification information stored in the first storage module; if the third interconnection topology information does not match the first verification information, generate third verification information according to the third interconnection topology information and store the third verification information in the first storage module.

[0138] In some embodiments, the obtaining module 501 is further configured to: obtain a plurality of candidate interconnection topology information pre-stored in the first basic input / output system; display the plurality of candidate interconnection topology information on a second interface; and in response to a touch operation on the second interface, determine third interconnection topology information from the plurality of candidate interconnection topology information.

[0139] In some embodiments, the determining module 502 is further configured to: display the first detection result on a third interface for presentation.

[0140] In some embodiments, the determining module 502 is specifically configured to: if the first detection result indicates that the first interconnection topology information does not match the second verification information, use the second interface to be detected as the error location and display the error location on the third interface.

[0141] In some embodiments, the determining module 502 is further configured to: if the first detection result indicates that the first interconnection topology information does not match the second verification information, invalidate the power-on instruction before executing the power-on instruction.

[0142] For the description of the features in the corresponding embodiments of the cable interconnection detection device, reference can be made to the relevant description in the corresponding embodiments of the cable interconnection detection method, which will not be elaborated here one by one.

[0143] Figure 6 This is a schematic structural diagram of the electronic device provided in this application. As Figure 6 shown, the electronic device 60 provided in this embodiment includes: at least one processor 601 and a memory 602. Optionally, the electronic device 60 further includes a communication component 603. Among them, the processor 601, the memory 602, and the communication component 603 are connected through a bus.

[0144] In a specific implementation process, at least one processor 601 executes the computer execution instructions stored in the memory 602, so that at least one processor 601 executes the above-mentioned cable interconnection detection method embodiment.

[0145] For the specific implementation process of the processor 601, reference can be made to the above method embodiment, and its implementation principle and technical effects are similar, which will not be elaborated here in this embodiment.

[0146] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in combination with the application can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.

[0147] The memory may include a random access memory (RAM), and may also include non-volatile memory (NVM), such as at least one disk memory.

[0148] The bus may be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the buses in the drawings of this application are not limited to only one bus or one type of bus.

[0149] The embodiments of the present application also provide a computer-readable storage medium, in which a computer program is stored, and the computer program is configured to execute the steps in any of the above XX method embodiments when running.

[0150] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROMs), random access memories (RAMs), mobile hard disks, magnetic disks, or optical discs, etc., various media that can store computer programs.

[0151] The embodiments of the present application also provide a computer program product, the above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the cable interconnection detection method.

[0152] Embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which when executed by a processor implements the steps in any of the above-described embodiments of the cable interconnection detection method.

[0153] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0154] The above has introduced in detail a cable interconnection detection method provided by the present application. Specific examples are used herein to illustrate the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A cable interconnection detection circuit, characterized in that, Including: The first interface to be detected; The first storage module, configured to store the first verification information; The first verification information is determined according to the first interconnection topology information corresponding to the first interface to be detected; The first switch, with its first input terminal connected to the first interface to be detected and its output terminal connected to the first storage module, is configured to conduct the second channel between the first interface to be detected and the first storage module when the first interface to be detected is connected to the second interface to be detected of the peer device; the second channel is used to transmit the first verification information to the cable interconnection detection circuit of the peer device; The first controller, connected to the first interface to be detected, is configured to obtain the second verification information through the first interface to be detected and determine the first detection result according to the second verification information and the first interconnection topology information; the second verification information is determined according to the second interconnection topology information corresponding to the second interface to be detected.

2. The circuit according to claim 1, wherein, The second input terminal of the first switch is connected to the first interface to be detected; The first controller is configured to store the first verification information in the first storage module when the first switch selects the first channel between the first controller and the first storage module.

3. The circuit according to claim 2, characterized in that, The control terminal of the first switch is connected to the first controller; The first controller is further configured to obtain the connection state of the first interface to be detected and perform switching control on the first switch according to the connection state.

4. The circuit according to claim 1, characterized in that, The first verification information is pre-stored in the first storage module through an offline burn-in file.

5. The circuit according to any one of claims 1-4, characterized in that, It further includes a first basic input / output system; The first basic input / output system, connected to the first controller, is configured to store the first interconnection topology information corresponding to the first interface to be detected and send the interconnection topology information to the first controller.

6. A server, characterized in that, Including: The first node and the second node; The cable interconnection detection circuit of the first node includes: the first interface to be detected, the first storage module, the first switch and the first controller; the cable interconnection detection circuit of the second node includes: the second interface to be detected, the second storage module, the second switch and the second controller; The first storage module is configured to store the first verification information; the first verification information is determined according to the first interconnection topology information corresponding to the first interface to be detected; The second storage module is configured to store the second verification information; the second verification information is determined according to the second interconnection topology information corresponding to the second interface to be detected; The first switch is configured to conduct the second channel between the first interface to be detected and the first storage module when the first interface to be detected is connected to the second interface to be detected; The second switch is configured to conduct the second channel between the second interface to be detected and the second storage module when the first interface to be detected is connected to the second interface to be detected; The first controller is configured to obtain the second verification information through the second channel corresponding to the second switch and determine the first detection result according to the second verification information and the first interconnection topology information; The second controller is configured to obtain the first verification information through a second channel corresponding to the first switch, and determine a second detection result according to the first verification information and the second interconnection topology information.

7. A method for detecting cable interconnection, characterized in that, Applied to the cable interconnection detection circuit, the cable interconnection detection circuit includes: a first controller, a first switch, a first interface to be detected, and a first storage module; a first input end of the first switch is connected to the first interface to be detected, and an output end is connected to the first storage module; the first controller is connected to the first interface to be detected; The method includes: When the first interface to be detected is connected to a second interface to be detected of a peer device, obtain second verification information; the second verification information is stored in a second storage module of the peer device and is determined according to second interconnection topology information corresponding to the second interface to be detected; Determine a first detection result according to the second verification information and first interconnection topology information corresponding to the first interface to be detected.

8. The method according to claim 7, wherein A second input end of the first switch is connected to the first interface to be detected; before obtaining the second verification information, it further includes: When the first switch selects a first channel between the first controller and the first storage module, store the first verification information in the first storage module.

9. The method according to claim 8, wherein A control end of the first switch is connected to the first controller; after storing the first verification information in the first storage module, it further includes: Obtain the connection state of the first interface to be detected; If the connection state indicates that the first interface to be detected is in a connected state, perform switching control on the first switch to select a second channel between the first interface to be detected and the first storage module.

10. The method according to claim 8, wherein After storing the first verification information in the first storage module, it further includes: Display a first interface; the first interface includes a detection start control; In response to a touch operation on the start control, control the first switch to select a second channel between the first interface to be detected and the first storage module.

11. The method according to claim 8, characterized in that, The circuit further includes a first basic input / output system connected to the first controller; before storing the first verification information in the first storage module, it further includes: Obtain the first interconnection topology information stored in the first basic input / output system; Generate the first verification information according to the first interconnection topology information.

12. The method according to claim 11, wherein After storing the first verification information in the first storage module, it further includes: Obtain third interconnection topology information corresponding to the first interface to be detected currently stored in the first basic input / output system; Obtain the first verification information stored in the first storage module; If the third interconnection topology information does not match the first verification information, generate third verification information according to the third interconnection topology information, and store the third verification information in the first storage module.

13. The method according to claim 12, wherein Before obtaining the third interconnection topology information corresponding to the first interface to be detected currently stored in the first basic input / output system, it further includes: Obtain multiple candidate interconnection topology information pre-stored in the first basic input / output system; Display multiple pieces of the candidate interconnection topology information on a second interface; In response to a touch operation on the second interface, determine the third interconnection topology information from the multiple pieces of candidate interconnection topology information.

14. The method according to claim 7, wherein After determining the first detection result according to the second verification information and the first interconnection topology information corresponding to the first interface to be detected, it further includes: Display the first detection result on a third interface for presentation.

15. The method according to claim 14, wherein The displaying the first detection result on the third interface for presentation includes: If the first detection result indicates that the first interconnection topology information does not match the second verification information, use the second interface to be detected as the error location and display the error location on the third interface.

16. The method according to claim 7, wherein After determining the first detection result according to the second verification information and the first interconnection topology information corresponding to the first interface to be detected, it further includes: If the first detection result indicates that the first interconnection topology information does not match the second verification information, before executing the power-on instruction, invalidate the power-on instruction.

17. A cable interconnection detection device, characterized in that, It includes: An acquisition module, configured to acquire second verification information when a first interface to be detected is connected to a second interface to be detected of a peer device; The second verification information is stored in a second storage module of the peer device and is determined according to the second interconnection topology information corresponding to the second interface to be detected; A determination module, configured to determine a first detection result according to the second verification information and the first interconnection topology information corresponding to the first interface to be detected.

18. An electronic device, characterized in that, It includes: A memory, configured to store a computer program; A processor, configured to implement the steps of the cable interconnection detection method according to any one of claims 7 to 16 when executing the computer program.

19. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program, when executed by a processor, implements the steps of the cable interconnection detection method according to any one of claims 7 to 16.

20. A computer program product, comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the cable interconnection detection method according to any one of claims 7 to 16.

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