Arithmetic square root approximate calculation device and calculation method based on maximum negative correlation

Abstract

The invention provides an arithmetic square root approximate calculation device and method based on maximum negative correlation, and belongs to the field of integrated circuit design. The circuit comprises a linear feedback shift register, a comparator, a square root calculation unit, a positive correlation median generation unit, a half-value scaling unit, a division unit and a delay unit. According to the arithmetic square root circuit approximate calculation device based on the maximum negative correlation, the minimum obtained mean square error (MSE) can reach 0.0031, and good precision is achieved.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and relates to an arithmetic square root approximation calculation device and calculation method based on maximum negative correlation. Background Art

[0002] Stochastic computing is a relatively novel approximation computing paradigm that uses a random number sequence composed of "0" and "1" to encode a numerical value with the occurrence probability of "1" therein. This computing paradigm has low cost and high fault tolerance, so it has attracted much attention from researchers in recent years.

[0003] In the fields of image processing, digital signal analysis, etc., the demand for square root operations is very large. However, currently, the square root circuits based on stochastic computing generally have poor accuracy. Therefore, the present application designs an arithmetic square root circuit approximation calculation device and calculation method based on maximum negative correlation. Summary of the Invention

[0004] Based on the above problems, the present invention provides an arithmetic square root approximation calculation device and calculation method based on maximum negative correlation.

[0005] The present invention is realized by the following technical solutions: An arithmetic square root approximation calculation device based on maximum negative correlation includes a linear feedback shift register, a comparator, a square root calculation unit, a positive correlation median generation unit, a half-value scaling unit, a division unit, and a delay unit; the linear feedback shift register includes exclusive-OR gates and N D flip-flops, one input terminal of the comparator is used to input an N-bit binary number, N is equal to the number of bits of the linear feedback shift register, the other input terminals of the comparator CMP are all connected to the Q terminals of the N D flip-flops in the linear feedback shift register, and the comparator CMP and the delay unit are both connected to the square root calculation unit; the Q terminal of one of the D flip-flops and the terminal are respectively connected to the half-value scaling unit and the positive correlation median generation unit, the other input terminal of the half-value scaling unit is connected to the square root calculation unit, the output terminal of the half-value scaling unit is respectively connected to one input terminal of the positive correlation median generation unit and port 1 of the division unit, the output terminal of the positive correlation median generation unit is connected to the selection terminal of the division unit, the output terminal of the division unit is connected to the delay unit, and the delay unit is respectively connected to the other input terminal of the square root calculation unit and port 0 of the division unit.

[0006] Preferably, the square root calculation unit is a two-input OR gate.

[0007] Preferably, the half-value scaling unit is a two-input AND gate.

[0008] Preferably, the positive correlation median generation unit is a two-input OR gate.

[0009] Preferably, the division unit is a multiplexer MUX2.

[0010] Preferably, the delay unit uses a D flip-flop.

[0011] Preferably, when the linear feedback shift register is 4-bit, the Q terminal of the second D flip-flop L2 is connected to another input terminal of the half-value scaling unit, and the terminal is connected to the positive correlation median generation unit.

[0012] Preferably, when the linear feedback shift register is 5-bit, the Q terminal of one of the first to third D flip-flops is connected to another input terminal of the half-value scaling unit, and the terminal is connected to the positive correlation median generation unit.

[0013] Preferably, when the linear feedback shift register is 6-bit, the Q terminal of one of the first to fourth D flip-flops is connected to another input terminal of the half-value scaling unit, and the terminal is connected to the positive correlation median generation unit.

[0014] Preferably, when the linear feedback shift register is 7-bit, the Q terminal of one of the third to fifth D flip-flops is connected to another input terminal of the half-value scaling unit, and the terminal is connected to the positive correlation median generation unit.

[0015] Preferably, when the linear feedback shift register is 8-bit, the Q terminal of one of the second to sixth D flip-flops is connected to another input terminal of the half-value scaling unit, and the terminal is connected to the positive correlation median generation unit.

[0016] Preferably, when the linear feedback shift register is 9-bit, the Q terminal of one of the first to seventh D flip-flops is connected to another input terminal of the half-value scaling unit, and the terminal is connected to the positive correlation median generation unit.

[0017] Preferably, when the linear feedback shift register is 10-bit, the Q terminal of one of the third to eighth D flip-flops is connected to another input terminal of the half-value scaling unit, and the terminal is connected to the positive correlation median generation unit.

[0018] A calculation method for an arithmetic square root approximation calculation device based on the above maximum negative correlation includes the following steps: S1. Perform multiple charge and discharge operations on the linear feedback shift register to make its internal state have an initial state where not all bits are "0"; perform a single charge and discharge operation on the division unit and the delay unit respectively, so that the delay unit and the division unit each have their own initial bit; S2. Input an N-bit binary number from one input terminal of the comparator. The N-bit binary number IN is the data to be square-rooted, and N is the same as the number of bits of the linear feedback shift register; the comparator compares the value represented by the output bit of the linear feedback shift register with the value represented by the binary number IN; S3. The square root calculation unit performs an "OR" logical operation on the bit output by the comparator CMP and the bit output by the delay unit; S4. The half-value scaling unit performs a logical "AND" calculation on the bit output by the square root calculation unit and the bit output by the Q terminal of one of the D flip-flops in the linear feedback shift register; S5. Use the positive correlation median generation unit to perform a logical "OR" calculation on the bit output by the half-value scaling unit and the bit output by the D flip-flop in the linear feedback shift register The D flip-flop mentioned in step S5 is the same flip-flop as the D flip-flop mentioned in step S4; S6. Use the division unit to select between the bit output by the half-value scaling unit and the bit output by the positive correlation median generation unit, and then use the delay unit to delay the bit output by the division unit. The bit output by the delay unit is sent to the square root calculation unit and fed back to the division unit for selection in the next clock cycle. The square root calculation unit OR1 first adds the bit output by the comparator CMP and the bit output by the delay unit, and then subtracts the product of the two bits. In this way, the calculation process for one clock cycle is completed; then, according to the clock signal, the internal state of the 8-bit linear feedback shift register is shifted and updated to obtain a new state different from the previous state; S7. Repeat the calculation process described in steps S2 to S6 N - 2 times. That is to say, the present application performs a total of N - 1 clock cycle calculation processes to obtain the final accurate calculation result ; where N is the same as the number of bits of the binary number IN.

[0019] Preferably, in step S1, the number of charge and discharge operations performed on the linear feedback shift register is N - 1, and N is the same as the number of bits of the linear feedback shift register.

[0020] Preferably, in step S2, the comparator compares the value represented by the binary number formed by the output bits of the linear feedback shift register with the value represented by the binary number IN; if the binary number IN is greater than the value represented by the binary number formed by the output bits of the 8-bit linear feedback shift register, then the comparator outputs bit "1", if the value represented by the binary number IN is less than or equal to the value represented by the binary number formed by the output bits of the 8-bit linear feedback shift register, then the comparator CMP outputs bit "0"; wherein, in the first clock cycle, the output bits of the linear feedback shift register refer to the initial bits obtained by the linear feedback shift register through multiple charge and discharge operations in step S1.

[0021] Compared with the prior art, the beneficial technical effects of the present application are: An approximate calculation device for an arithmetic square root circuit based on maximum negative correlation proposed by the present invention directly utilizes the random sequence formed by the bits output by the Q terminal and the terminal of the same D flip-flop in the linear feedback shift register in chronological order, which exhibits maximum negative correlation. Moreover, the values represented by the random sequences formed by the bits output by the Q terminal and the terminal of the same D flip-flop in all clock cycles in chronological order are both 0.5; Since the value represented by the random sequence formed by the bits output by the Q terminal of the D flip-flop in all clock cycles in chronological order is 0.5, this makes the value OUT1 represented by the random sequence formed by the bits output by the half-value scaling unit in all clock cycles in chronological order equal to half of the value OUT represented by the random sequence formed by the bits output by the square root calculation unit in all clock cycles in chronological order, that is ; And the terminal of the D flip-flop has a value of 0.5 represented by the random sequence formed by the bits output in all clock cycles in chronological order, and the correlation value between the random sequence formed by the bits output by the half-value scaling unit in all clock cycles in chronological order and the random sequence formed by the bits output by the terminal of the D flip-flop in chronological order is -1, that is, it exhibits maximum negative correlation. This enables the positive correlation median generation unit to accurately add the bits output by the terminal of the D flip-flop and the bits output by the half-value scaling unit, effectively improving the accuracy of the arithmetic square root approximation calculation of the present application; moreover, from all clock cycles, the value OUT2 represented by the random sequence formed by the bits output by the positive correlation median generation unit in all clock cycles in chronological order is equal to 1 / 2 (that is, the The value represented by the random sequence formed by the bits output from the terminal in chronological order) and the value OUT1 represented by the random sequence formed by the bits output by the half-value scaling unit in all clock cycles; due to the The value represented by the random sequence formed by the bits output from the terminal in chronological order is 1 / 2, and when calculating OUT1, the value 0.5 represented by the random sequence formed by the bits output from the Q terminal of the D flip-flop in chronological order is also used. Therefore, the values represented by the random sequences formed by the bits output from the Q terminal and the terminal in chronological order in all clock cycles are both 0.5, which can further improve the accuracy of the approximate calculation of the arithmetic square root in this application. Moreover, through experimental simulation, it can be seen that the mean square error MSE that can be achieved by the arithmetic square root circuit approximate calculation device based on the maximum negative correlation in this application can reach as low as 0.0031 at least, with better accuracy. Brief Description of the Drawings

[0022] Figure 1 is the logic circuit diagram of the arithmetic square root approximate calculation device based on random calculation described in Embodiment 1; Figure 2 is the logic circuit diagram of the arithmetic square root approximate calculation device based on random calculation described in Embodiment 2; Figure 3 is the logic circuit diagram of the arithmetic square root approximate calculation device based on random calculation described in Embodiment 3; Figure 4 is the logic circuit diagram of the arithmetic square root approximate calculation device based on random calculation described in Embodiment 4; Figure 5 is the logic circuit diagram of the arithmetic square root approximate calculation device based on random calculation described in Embodiment 5; Figure 6 is the logic circuit diagram of the arithmetic square root approximate calculation device based on random calculation described in Embodiment 6; Figure 7 is the logic circuit diagram of the arithmetic square root approximate calculation device based on random calculation described in Embodiment 7; Figure 8 is the logic circuit diagram of the arithmetic square root approximate calculation device based on random calculation described in Embodiment 8. Detailed Embodiments

[0023] To facilitate those skilled in the art to understand the technical content of the present invention, the following further explains the invention content in conjunction with the drawings. The description here is only for explaining the present invention and does not limit the present invention.

[0024] Embodiment 1: As Figure 1As shown in the figure, the present invention proposes an arithmetic square root approximation calculation device based on maximum negative correlation, which includes a linear feedback shift register, a comparator CMP, a square root calculation unit, a positive correlation median generation unit, a half-value scaling unit, a division unit, and a delay unit; the linear feedback shift register includes exclusive-OR gates and D flip-flops, and the number of D flip-flops is equal to the number of bits of the linear feedback shift register; Among them, the linear feedback shift register adopted in the first embodiment is an 8-bit linear feedback shift register in the prior art. The 8-bit linear feedback shift register includes an exclusive-OR gate INOR and eight D flip-flops, and the eight D flip-flops are respectively represented as L1, L2, L3, L4, L5, L6, L7, and L8 in Figure 1 this application. In this application, the square root calculation unit is a two-input OR gate, called OR gate OR1, the half-value scaling unit is a two-input AND gate, the positive correlation median generation unit is a two-input OR gate, called OR gate OR2, the division unit uses a multiplexer MUX2 in the prior art, and the delay unit uses a D flip-flop in the prior art.

[0025] In this application, one input terminal of the comparator is used as the input terminal of the entire arithmetic square root approximation calculation device based on random calculation, and is used to input an N-bit binary number, where N is the same as the number of bits of the linear feedback shift register; the other input terminals of the comparator CMP are all connected to the Q terminals of the N D flip-flops in the linear feedback shift register; specifically, in the first embodiment, one input terminal of the comparator CMP is used to input an 8-bit binary number, and the other input terminals of the comparator CMP are all connected to the Q terminals of the eight D flip-flops in the 8-bit linear feedback shift register. The output terminal of the comparator CMP is connected to one input terminal of the square root calculation unit, and the output terminal of the square root calculation unit is connected to one input terminal of the half-value scaling unit. The Q terminal of the fifth D flip-flop L5 of the 8-bit linear feedback shift register is connected to the other input terminal of the half-value scaling unit. The output terminal of the half-value scaling unit is respectively connected to one input terminal of the positive correlation median generation unit and port 1 of the division unit. The terminal of the above D flip-flop Ln is connected to the other input terminal of the positive correlation median generation unit. In this embodiment, the terminal of the fifth D flip-flop L5 is connected to the other input terminal of the positive correlation median generation unit. The output terminal of the positive correlation median generation unit is connected to the selection terminal of the division unit. The output terminal of the division unit is connected to the input terminal of the delay unit. The output terminal of the delay unit is respectively connected to the other input terminal of the square root calculation unit and port 0 of the division unit.

[0026] In the 8-bit linear feedback shift register of the first embodiment, the first input terminal of the exclusive OR gate INOR is connected to the output terminal of the second D flip-flop L2, the second input terminal of the exclusive OR gate INOR is connected to the output terminal of the third D flip-flop L3, the third input terminal of the exclusive OR gate INOR is connected to the output terminal of the fourth D flip-flop L4, the fourth input terminal of the exclusive OR gate INOR is connected to the output terminal of the eighth D flip-flop L8, and the output terminal of the exclusive OR gate INOR is connected to the input terminal of the eighth D flip-flop L8.

[0027] A calculation method of an arithmetic square root approximation calculation device based on the above maximum negative correlation includes the following steps: S1. Perform multiple charge and discharge operations on the 8-bit linear feedback shift register to make it have an initial state where not all are "0". Among them, the number of charge and discharge operations is 2 N -1, N is the same as the number of bits of the linear feedback shift register. In the first embodiment, N is 8; perform a charge and discharge operation on the division unit and the delay unit respectively to make the delay unit and the division unit have their respective initial bits; S2. Input an N-bit binary number IN from one input terminal of the comparator CMP. The N-bit binary number IN is the data to be square-rooted. N is the same as the number of bits of the 8-bit linear feedback shift register. Figure 1 in1, in2, in3, in4, in5, in6, in7, and in8 in it constitute the 8-bit binary number IN input in the first embodiment; the comparator CMP compares the value represented by the binary number IN with the value represented by the binary number formed by the output bits of the 8-bit linear feedback shift register; if the value represented by the binary number IN is greater than the value represented by the binary number formed by the output bits of the 8-bit linear feedback shift register, then the comparator CMP outputs a bit "1", if the value represented by the binary number IN is less than or equal to the value represented by the binary number formed by the output bits of the 8-bit linear feedback shift register, then the comparator CMP outputs a bit "0"; among them, in the first clock cycle, the output bit of the 8-bit linear feedback shift register refers to the initial bit obtained by multiple charge and discharge operations in the 8-bit linear feedback shift register in step S1; In this application, in each clock cycle, the comparator CMP compares the value represented by the binary number formed by the output bits of the 8-bit linear feedback shift register with the value represented by the binary number IN. If the value represented by the binary number IN is greater than the value represented by the binary number formed by the output bits of the 8-bit linear feedback shift register, then the comparator CMP outputs a bit "1". If the value represented by the binary number IN is less than or equal to the value represented by the binary number formed by the output bits of the 8-bit linear feedback shift register, then the comparator CMP outputs a bit "0". After all clock cycles end, the bits output by the comparator CMP in all clock cycles form a random sequence in chronological order. The probability value of the occurrence of bit "1" in this random sequence is the same as the value represented by the binary number IN. Since the probability value of bit "1" in the above random sequence is the same as the value represented by the binary number IN, therefore, the above random sequence can be used to represent the binary number IN to be square-rooted. The value represented by the random sequence formed by the bits output by the comparator in all clock cycles in chronological order is X. S3. Use the square root calculation unit to perform an "OR" logic operation on the bits output by the comparator CMP and the bits output by the delay unit. Among them, in the first clock cycle, the bit output by the delay unit refers to the initial bit obtained by the delay unit through one charge and discharge in step S1. The square root calculation unit is used to first add the bits output by the comparator CMP and the bits output by the delay unit, and then subtract the product of the two bits. In step S3 of this application, the delay unit outputs a bit in each clock cycle. After all clock cycles end, the bits output by the delay unit in all clock cycles form a random sequence in chronological order. S4. Use the half-value scaling unit to perform a logical "AND" calculation on the bits output by the square root calculation unit and the bits output by the Q terminal of the fifth D flip-flop L5 in the linear feedback shift register. In step S4, the bits output by the Q terminal of the fifth D flip-flop L5 in the 8-bit linear feedback shift register in all clock cycles form a random sequence in chronological order. The probability value of the occurrence of bit "1" in this random sequence is 0.5.

[0028] Since random computing represents numerical values using probability values (instead of deterministic 0 / 1), for example: if the probability of bit "1" appearing in a bit stream is p, then in random computing, the probability p of bit "1" appearing in the bit stream is the numerical value represented by the bit stream; if the probability of bit "1" appearing in another bit stream is q, then in random computing, the probability q of bit "1" appearing in the bit stream is the numerical value represented by the bit stream. In this application, the half-value scaling unit uses a two-input AND gate. The half-value scaling unit outputs 1 only when both input bits are 1; that is, if the probability P(A = 1) of bit "1" appearing in input bit stream A is p, the probability P(B = 1) of bit "1" appearing in input bit stream B is q, and bit stream A and bit stream B are uncorrelated, then the probability P(output = 1) that the half-value scaling unit outputs a bit of "1" is:

[0029] Specifically in this application, after all clock cycles end, the bits output by the square root calculation unit in all clock cycles form a random sequence in time sequence. This random sequence is essentially a bit stream; the bits output by the Q terminal of the fifth D flip-flop L5 in all clock cycles form another random sequence in time sequence. The probability value of bit "1" appearing in this random sequence is 0.5. This random sequence is essentially another bit stream; both of the above two random sequences are used as inputs to the half-value scaling unit, and the correlation value between the above two random sequences is 0, that is, they are uncorrelated. The calculation method of the correlation value is as described below; In this application, from the perspective of all clock cycles, the function of the half-value scaling unit is to multiply the above two random sequences. The value OUT1 represented by the random sequence formed by the bits output by the half-value scaling unit in all clock cycles in time sequence is equal to half of the numerical value OUT represented by the random sequence formed by the bits output by the square root calculation unit in all clock cycles in time sequence, that is ; S5. Use the positive correlation median generation unit to perform a logical "OR" calculation on the bits output by the half-value scaling unit and the bits output by the Q terminal of the fifth D flip-flop L5 in the linear feedback shift register ; After all clock cycles end, the bits output by the half-value scaling unit in all clock cycles form a random sequence in time sequence; the bits output by the Q terminal of the fifth D flip-flop L5 form another random sequence in time sequence. The probability value of bit "1" appearing in this random sequence is 0.5; since the random sequence output by the Q terminal of the fifth D flip-flop L5 in all clock cycles in time sequence and the The random sequence output by the terminal in accordance with the timing in all clock cycles has the maximum negative correlation, and the random sequence output by the Q terminal of the fifth D flip-flop L5 in accordance with the timing in all clock cycles is logically ANDed with the random sequence output by the square root calculation unit in accordance with the timing in all clock cycles. This makes the positions where the bit '1' appears in the random sequence output by the half-value scaling unit in accordance with the timing in all clock cycles must be the positions where the bit '1' appears simultaneously in the random sequence output by the Q terminal of the fifth D flip-flop L5 in accordance with the timing in all clock cycles and the random sequence output by the square root calculation unit in accordance with the timing in all clock cycles. That is to say, the positions where the bit '1' appears in the random sequence output by the half-value scaling unit in accordance with the timing in all clock cycles are part or all of the positions where the bit '1' appears in the random sequence output by the Q terminal of the fifth D flip-flop L5 in accordance with the timing in all clock cycles. Therefore, the bits output by the half-value scaling unit in all clock cycles form a random sequence in accordance with the timing and the fifth D flip-flop L5 The correlation value between the bits output by the terminal in accordance with the timing to form another random sequence is -1, that is, the above two random sequences have the maximum negative correlation, and both are used as the inputs of the positive correlation median generation unit; In this application, the two-input OR gate OR2 is used in the positive correlation median unit, and the operation logic of the two-input OR gate OR2 is: ; when the probability P(C = 1) that the bit '1' appears in the bit stream C input to the two-input OR gate OR2 is p', the probability P(D = 1) that the bit '1' appears in the bit stream D input is q', and the bit stream C and the bit stream D have the maximum negative correlation, ; In this application, the fifth D flip-flop L5 The value represented by the random sequence formed by the bits output by the terminal in accordance with the timing is 0.5. The value represented by the random sequence formed by the bits output by the half-value scaling unit in all clock cycles in accordance with the timing is OUT1, and OUT1 is equal to , and OUT is the value represented by the random sequence formed by the bits output by the square root calculation unit in all clock cycles in accordance with the timing, and this value is less than or equal to 1. Therefore, in this application, the sum of the values represented by the two input bit streams of the positive correlation median unit is less than or equal to 1, that is Therefore, This makes the value OUT2 represented by the random sequence formed by the bits output by the positive correlation median generation unit in all clock cycles in accordance with the timing equal to 1 / 2 (that is, the value represented by the random sequence formed by the bits output by the Q terminal of the fifth D flip-flop L5 in accordance with the timing) plus the value OUT1 represented by the random sequence formed by the bits output by the half-value scaling unit in all clock cycles in accordance with the timing, that is 。

[0030] S6. The division unit is used to select the bits output by the half-value scaling unit and the bits output by the positive correlation median generation unit, and then the delay unit delays the bits output by the division unit. The bits output by the delay unit are sent to the square root calculation unit and fed back to the division unit for selection in the next clock cycle. The square root calculation unit OR1 first adds the bits output by the comparator CMP and the bits output by the delay unit, and then subtracts the product of the two bits. In this way, the calculation process of one clock cycle is completed. Then, according to the clock signal, the internal state of the 8-bit linear feedback shift register is shifted and updated to obtain a new state different from the previous state. In this application, the division unit uses a MUX_2 selector.

[0031] It can be calculated (the calculation method of the correlation value is as shown below) that in this application, the correlation value between the random sequence output by the half-value scaling unit in chronological order in all clock cycles and the random sequence output by the positive correlation median generation unit in chronological order in all clock cycles is 1, that is, it has the maximum positive correlation. This application uses the division unit to implement the division function and output OUT3. The calculation formula of OUT3 is: , where OUT1 is the value represented by the random sequence composed of the bits output by the half-value scaling unit in all clock cycles in chronological order, OUT2 is the value represented by the random sequence composed of the bits output by the positive correlation median generation unit in all clock cycles in chronological order, and OUT is the value represented by the random sequence composed of the bits output by the square root calculation unit in all clock cycles in chronological order; In this application, the division unit uses an existing MUX_2 selector. Therefore, the essence of implementing the division function by the division unit in this application is to utilize the selection function of the MUX_2 selector. The principle analysis of the division unit implementing the division function is as follows: In this application, when the bit input to the selection terminal of the MUX_2 selector by the positive correlation median generation unit is "1", the MUX_2 selector outputs the bit input through port 1 of the MUX_2 selector by the half-value scaling unit; when the bit input to the selection terminal of the MUX_2 selector by the positive correlation median generation unit is "0", the MUX_2 selector outputs the bit input through port 0 of the MUX_2 selector by the delay unit; the probability of bit "1" in the random sequence output by the MUX_2 selector in chronological order in all clock cycles , the probability of bit "1" in the random sequence output by the half-value scaling unit in chronological order in all clock cycles , the probability of bit "1" in the random sequence output by the positive correlation median generation unit in chronological order in all clock cycles The probability of bit "0" in the random sequence output by the positive correlation median generation unit in all clock cycles in chronological order And the probability of bit "1" in the random sequence output by the delay unit in all clock cycles in chronological order The relationship between them is as shown in Equation (1): (1) In Equation (1), represents the probability of bit "1" in the random sequence output by the MUX_2 selector in all clock cycles in chronological order represents the probability of bit "1" in the random sequence output by the half-value scaling unit in all clock cycles in chronological order, and this probability is equal to OUT1 represents the probability of bit "1" in the random sequence output by the delay unit in all clock cycles in chronological order represents the probability of bit "1" in the random sequence output by the positive correlation median generation unit in all clock cycles in chronological order, and this probability is equal to OUT2 represents the probability of bit "0" in the random sequence output by the positive correlation median generation unit in all clock cycles in chronological order

[0032] Since the delay unit only delays the bits output by the MUX_2 selector, therefore, the random sequence formed by the bits fed back by the delay unit to the MUX_2 selector in all clock cycles in chronological order is the same as the random sequence formed by the bits output by the MUX_2 selector in all clock cycles in chronological order, that is, p(G = 1)=p(Z = 1), where p(G = 1) represents the probability of bit "1" appearing in the random sequence G, and p(Z = 1) represents the probability of bit "1" appearing in the random sequence G; since p(F = 0)=1 - p(F = 1), therefore, substituting p(F = 0)=1 - p(F = 1) and p(G = 1)=p(Z = 1) into Equation (1) gives p(Z = 1)=p(E = 1)p(F = 1)+p(Z = 1)[1 - p(F = 1)], and after simplification, we can get: (2); In Equation (2), 、 、 represent the same meanings as in Equation (1) respectively; Also, because the correlation value between the random sequence output by the half-value scaling unit in all clock cycles in chronological order and the random sequence output by the positive correlation median generation unit in all clock cycles in chronological order is 1, so , Since in this application, P(E = 1) = OUT / 2 and P(F = 1) = (OUT + 1) / 2, so P(E = 1) < P(F = 1). Therefore, , formula (2) can be further simplified to

[0033] S7. Repeat the calculation process described in steps S2 to S6 N - 2 times. That is to say, this application performs a total of 2 N - 1 clock cycle of calculation process to obtain the final accurate calculation result ; where N is the same as the number of bits of the binary number IN.

[0034] In this application, after all clock cycles end, the bits output by the delay unit in all clock cycles form a random sequence in time sequence; the bits output by the comparator CMP form another random sequence in time sequence; through calculation (the calculation method of the correlation value is as shown below), the correlation between the above two random sequences is 0, that is, they are uncorrelated; in this application, the square root calculation unit uses a two-input OR gate OR1, and the logic of the square root calculation unit is: (4) In formula (4), P(H = 1) represents the value X represented by the random sequence formed by the bits output by the comparator in all clock cycles in time sequence, and P(L = 1) represents the value represented by the random sequence formed by the bits output by the delay unit in all clock cycles in time sequence, that is .

[0035] In this application, the bits input to the square root calculation unit by the delay unit in all clock cycles form a random sequence in time sequence; the correlation value between the bits input to the square root calculation unit by the comparator CMP in all clock cycles and another random sequence formed in time sequence is 0. At this time, ; so, , Since in the above formula, P(H = 1) represents the value X represented by the random sequence formed by the bits output by the comparator in all clock cycles in time sequence, and P(L = 1) represents the value represented by the random sequence formed by the bits output by the delay unit in all clock cycles in time sequence, that is , therefore, (5) In formula (5), X represents the value represented by the random sequence formed by the bits output by the comparator in all clock cycles in sequence, and OUT represents the value represented by the random sequence formed by the bits output by the square root calculation unit in all clock cycles in sequence; therefore, by solving the equation described in formula (5), it can be known that the value OUT represented by the random sequence formed by the bits output by the square root calculation unit in all clock cycles in sequence in this application is .

[0036] In this application, to determine whether there is a maximum negative correlation, a maximum positive correlation or no correlation between different random sequences, the correlation value can be calculated through the following correlation value calculation method to make a determination. When the correlation value between two random sequences is +1, it is determined that the two random sequences have a maximum positive correlation. When the correlation value between two random sequences is 0, it is determined that the two random sequences have no correlation. When the correlation value between two random sequences is -1, it is determined that the two random sequences have a maximum negative correlation; among them, the correlation value calculation method includes the following steps: a) Calculate the absolute value of the difference between the product of the values represented by the two random sequences after the bitwise "AND" logical operation and the product of the values represented by the above two random sequences respectively; b) Calculate the difference between the minimum value among the values represented by the above two random sequences respectively and the product of the values represented by the above two random sequences respectively; c) Calculate the ratio between the absolute value of the difference obtained in step a) and the difference calculated in step b); this ratio is the correlation value. For example: when the value represented by the random sequence obtained after the bitwise "AND" logical operation on two random sequences is equal to the product of the values represented by the above two random sequences respectively, the difference between the value represented by the random sequence obtained after the bitwise "AND" logical operation on two random sequences and the product of the values represented by the above two random sequences respectively is 0, that is, the correlation value is 0.

[0037] In this application, the correlation represents the coincidence degree of the positions where the bit "1" appears in two random sequences. When the positions where the bit "1" appears in the two random sequences completely coincide, the correlation is the largest, regarded as the correlation value being 1; when the value represented by the random sequence obtained after the bitwise "AND" logical operation on the two random sequences (the value represented by the random sequence is the probability value of the bit "1" appearing in the random sequence) is equal to the product of the values represented by the above two random sequences respectively, it is regarded as having no correlation, that is, the correlation value is 0; when the positions where the bit "1" appears in the two random sequences completely do not coincide, the correlation is the smallest, regarded as the correlation value being -1.

[0038] Example 2: The difference between Example 2 and Example 1 is that: In the arithmetic square root approximation calculation device based on maximum negative correlation: In the second embodiment, the Q terminal of the second D flip-flop L2 of the 8-bit linear feedback shift register is connected to another input terminal of the half-value scaling unit, and the terminal is connected to another input terminal of the positive correlation median generation unit, as Figure 2 shown; In a calculation method of an arithmetic square root approximation calculation device based on the above maximum negative correlation: Replace the fifth D flip-flop L5 with the second D flip-flop L2.

[0039] Embodiment 3: The difference between Embodiment 3 and Embodiment 1 is that: In the arithmetic square root approximation calculation device based on maximum negative correlation: In Embodiment 3, the linear feedback shift register used is a 4-bit linear feedback shift register. The 4-bit linear feedback shift register includes an exclusive OR gate INOR and four D flip-flops. The four D flip-flops are Figure 3 respectively represented as L1, L2, L3, and L4 in; In the 4-bit linear feedback shift register, the first input terminal of the exclusive OR gate INOR is connected to the output terminal of the first D flip-flop L1, the fourth input terminal of the exclusive OR gate INOR is connected to the output terminal of the fourth D flip-flop L4, and the output terminal of the exclusive OR gate INOR is connected to the input terminal of the fourth D flip-flop L4; Connect the Q terminal of the second D flip-flop L2 of the 4-bit linear feedback shift register to another input terminal of the half-value scaling unit, and the terminal is connected to another input terminal of the positive correlation median generation unit; as Figure 3 shown; In a calculation method of an arithmetic square root approximation calculation device based on the above maximum negative correlation: Replace the fifth D flip-flop L5 in the 8-bit linear feedback shift register with the second D flip-flop L2 in the 4-bit linear feedback shift register; Perform 15 charge and discharge operations on the 4-bit linear feedback shift register to make it have an initial state where not all are "0" inside; The input binary number is a 4-bit binary number, Figure 3 in1, in2, in3, and in4 shown in, that is, constitute the 4-bit binary number IN input in this Embodiment 3.

[0040] Embodiment 4: The difference between Embodiment 4 and Embodiment 1 is that: In the arithmetic square root approximation calculation device based on maximum negative correlation: In Embodiment 4, the linear feedback shift register used is a 5-bit linear feedback shift register. The 5-bit linear feedback shift register includes an exclusive OR gate INOR and five D flip-flops, and the five D flip-flops are respectively denoted as L1, L2, L3, L4, and L5 in Figure 4 ; in the 5-bit linear feedback shift register, the second input terminal of the exclusive OR gate INOR is connected to the output terminal of the second D flip-flop L2, the fifth input terminal of the exclusive OR gate INOR is connected to the output terminal of the fifth D flip-flop L5, and the output terminal of the exclusive OR gate INOR is connected to the input terminal of the fifth D flip-flop L5; Connect the Q terminal of the third D flip-flop L3 of the 5-bit linear feedback shift register to the other input terminal of the half-value scaling unit, and the terminal of the third D flip-flop L3 is connected to the other input terminal of the positive correlation median generation unit; as Figure 4 shown; (2) In the calculation method of an arithmetic square root approximation calculation device based on the above maximum negative correlation: Replace the fifth D flip-flop L5 in the 8-bit linear feedback shift register with the third D flip-flop L3 in the 5-bit linear feedback shift register; Perform 31 charge and discharge operations on the 5-bit linear feedback shift register to make it have an initial state where not all are "0" inside; The input binary number is a 5-bit binary number, Figure 4 in1, in2, in3, in4, and in5 shown in, that is, the 5-bit binary number IN input in Embodiment 4 of this example.

[0041] Embodiment 5: The difference between Embodiment 5 and Embodiment 1 is that: (1) In the arithmetic square root approximation calculation device based on the maximum negative correlation: In Embodiment 3, the linear feedback shift register used is a 6-bit linear feedback shift register. The 6-bit linear feedback shift register includes an exclusive OR gate INOR and six D flip-flops, and the six D flip-flops are respectively denoted as L1, L2, L3, L4, L5, and L6 in Figure 5 ; in the 6-bit linear feedback shift register, the first input terminal of the exclusive OR gate INOR is connected to the output terminal of the first D flip-flop L1, the sixth input terminal of the exclusive OR gate INOR is connected to the output terminal of the sixth D flip-flop L6, and the output terminal of the exclusive OR gate INOR is connected to the input terminal of the sixth D flip-flop L6; Connect the Q terminal of the second D flip-flop L2 of the 6-bit linear feedback shift register to the other input terminal of the half-value scaling unit, and the terminal of the second D flip-flop L2 is connected to the other input terminal of the positive correlation median generation unit; as Figure 5 shown; (2) In the calculation method of an arithmetic square root approximation calculation device based on the above maximum negative correlation: Replace the fifth D flip - flop L5 in the 8 - bit linear feedback shift register with the second D flip - flop L2 in the 6 - bit linear feedback shift register; Perform 63 charge - discharge operations on the 6 - bit linear feedback shift register to make it have an initial state where not all are "0" inside; The input binary number is a 6 - bit binary number, Figure 5 in1, in2, in3, in4, in5, and in6 shown in are the 6 - bit binary number IN input in the fifth embodiment.

[0042] Embodiment Six: The difference between Embodiment Six and Embodiment One is: (1) In the arithmetic square root approximation calculation device based on the maximum negative correlation: In Embodiment Three, the linear feedback shift register used is a 7 - bit linear feedback shift register. The 7 - bit linear feedback shift register includes an exclusive - OR gate INOR and seven D flip - flops. The seven D flip - flops are Figure 6 respectively represented as L1, L2, L3, L4, L5, L6, and L7 in ; In the 7 - bit linear feedback shift register, the third input terminal of the exclusive - OR gate INOR is connected to the output terminal of the third D flip - flop L3, the seventh input terminal of the exclusive - OR gate INOR is connected to the output terminal of the seventh D flip - flop L7, and the output terminal of the exclusive - OR gate INOR is connected to the input terminal of the seventh D flip - flop L7; Connect the Q terminal of the fourth D flip - flop L4 of the 7 - bit linear feedback shift register to another input terminal of the half - value scaling unit, and the terminal to another input terminal of the positive - correlation median generation unit; As shown in Figure 6 ; (2) In the calculation method of an arithmetic square root approximation calculation device based on the above maximum negative correlation: Replace the fifth D flip - flop L5 in the 8 - bit linear feedback shift register with the fourth D flip - flop L4 in the 7 - bit linear feedback shift register; Perform 127 charge - discharge operations on the 7 - bit linear feedback shift register to make it have an initial state where not all are "0" inside; The input binary number is a 7 - bit binary number, Figure 6 in1, in2, in3, in4, in5, in6, and in7 shown in are the 7 - bit binary number IN input in the sixth embodiment.

[0043] Embodiment Seven: The difference between Embodiment Seven and Embodiment One is: In the arithmetic square root approximation calculation device based on maximum negative correlation: In the third embodiment, the linear feedback shift register used is a 9-bit linear feedback shift register. The 9-bit linear feedback shift register includes an exclusive OR gate INOR and nine D flip-flops. The nine D flip-flops are respectively represented as L1, L2, L3, L4, L5, L6, L7, L8, and L9 in Figure 7 ; In the 9-bit linear feedback shift register, the fourth input terminal of the exclusive OR gate INOR is connected to the output terminal of the fourth D flip-flop L4, the ninth input terminal of the exclusive OR gate INOR is connected to the output terminal of the ninth D flip-flop L9, and the output terminal of the exclusive OR gate INOR is connected to the input terminal of the ninth D flip-flop L9; Connect the Q terminal of the sixth D flip-flop L6 of the 9-bit linear feedback shift register to the other input terminal of the half-value scaling unit, and the terminal to the other input terminal of the positive correlation median generation unit; As Figure 7 shown; In the calculation method of an arithmetic square root approximation calculation device based on the above-mentioned maximum negative correlation: Replace the fifth D flip-flop L5 in the 8-bit linear feedback shift register with the sixth D flip-flop L6 in the 9-bit linear feedback shift register; Perform 511 charge and discharge operations on the 9-bit linear feedback shift register to make it have an initial state where not all are "0" inside; The input binary number is a 9-bit binary number, Figure 7 in1, in2, in3, in4, in5, in6, in7, in8, and in9 shown in

[0044] Embodiment Eight: The difference between Embodiment Eight and Embodiment One is: In the arithmetic square root approximation calculation device based on maximum negative correlation: In the third embodiment, the linear feedback shift register used is a 10-bit linear feedback shift register. The 10-bit linear feedback shift register includes an exclusive OR gate INOR and ten D flip-flops. The ten D flip-flops are respectively represented as L1, L2, L3, L4, L5, L6, L7, L8, L9, and L9 in Figure 8 ; In the 10-bit linear feedback shift register, the third input terminal of the exclusive OR gate INOR is connected to the output terminal of the third D flip-flop L3, the tenth input terminal of the exclusive OR gate INOR is connected to the output terminal of the tenth D flip-flop L10, and the output terminal of the exclusive OR gate INOR is connected to the input terminal of the tenth D flip-flop L10; Connect the Q terminal of the seventh D flip-flop L7 of the 10-bit linear feedback shift register to another input terminal of the half-value scaling unit, and connect the terminal to another input terminal of the positive correlation median generation unit; as Figure 8 shown; (3) In a calculation method of an arithmetic square root approximation calculation device based on the above maximum negative correlation: Replace the fifth D flip-flop L5 in the 8-bit linear feedback shift register with the seventh D flip-flop L7 in the 10-bit linear feedback shift register; Perform 1023 charge and discharge operations on the 10-bit linear feedback shift register to make it have an initial state where not all are "0" inside; The input binary number is a 10-bit binary number, Figure 8 in1, in2, in3, in4, in5, in6, in7, in8, in9, and in10 shown in the figure are the 10-bit binary number IN input in the eighth embodiment of the present application.

[0045] This application also conducts square root calculation tests on different arithmetic square root approximation calculation devices based on random calculation. Among them, the differences in different arithmetic square root approximation calculation devices based on random calculation are mainly reflected in the following aspects: 1. The number of bits of the linear feedback shift register is different; 2. The half-value scaling unit, the positive correlation median generation unit are connected to different D flip-flops Ln in the linear feedback shift register. The test results are shown in Tables 1 to 14: Table 1 shows that: the linear feedback shift register is a 4-bit linear feedback shift register, and the half-value scaling unit is connected to the Q terminal of the D flip-flop Ln, and the positive correlation median generation unit is connected to the terminal to obtain the test result - the average value MSE of the mean absolute error of the square root test of the arithmetic square root approximation calculation device based on random calculation; For example, L2 recorded in the third column of the first row means that: the half-value scaling unit is connected to the Q terminal of the second D flip-flop L2 in the 4-bit linear feedback shift register, and the positive correlation median generation unit is connected to the second D flip-flop L2 in the 4-bit linear feedback shift register terminal. The third column in Table 1 actually shows the square root test result - the average value MSE of the mean absolute error of the arithmetic square root approximation calculation device described in Embodiment 3 of the present application. The test result is 0.0075 recorded in the third column of the second row; As for the arithmetic square root approximation calculation device based on random calculation tested in the second column, the fourth column, and the fifth column, the difference from the arithmetic square root approximation calculation device based on random calculation tested in the third column is only that: the half-value scaling unit and the positive correlation median generation unit are connected to different D flip-flops Ln in the 4-bit linear feedback shift register.

[0046] Table 1

[0047] As can be seen from Table 1, when the linear feedback shift register is a 4-bit linear feedback shift register, and the half-value scaling unit is connected to the Q terminal of the second D flip-flop L2 in the 4-bit linear feedback shift register, and the positive correlation median generation unit is connected to the terminal of the second D flip-flop L2, the arithmetic square root approximation calculation device based on random calculation obtained has a relatively high calculation accuracy for square root calculation, and the average value MSE of the mean absolute error can reach 0.0075.

[0048] Table 2 To verify that the arithmetic square root approximation calculation device based on random calculation obtained by "connecting the half-value scaling unit to the Q terminal of the D flip-flop Ln in the 4-bit linear feedback shift register and connecting the positive correlation median generation unit to the terminal" has better calculation accuracy for square root calculation compared to the arithmetic square root approximation calculation device obtained by "connecting the positive correlation median generation unit to the Q terminal of the D flip-flop Ln in the 4-bit linear feedback shift register and connecting the half-value scaling unit to the terminal" of the D flip-flop Ln, this application also tested the arithmetic square root approximation calculation device based on random calculation obtained by "connecting the positive correlation median generation unit to the Q terminal of the D flip-flop Ln in the 4-bit linear feedback shift register and connecting the half-value scaling unit to the terminal" of the D flip-flop Ln, and the test results are shown in Table 2: Table 2

[0049] Obviously, as can be seen from Table 1 and Table 2, the arithmetic square root approximation calculation device based on random calculation obtained by "connecting the half-value scaling unit to the Q terminals of the D flip-flops L1, L2, or L3 in the 4-bit linear feedback shift register and connecting the positive correlation median generation unit to the terminal" of the D flip-flop Ln has better calculation accuracy for square root calculation compared to the arithmetic square root approximation calculation device obtained by "connecting the positive correlation median generation unit to the Q terminals of the D flip-flops L1, L2, or L3 in the 4-bit linear feedback shift register and connecting the half-value scaling unit to the terminal" of the D flip-flop Ln. Taking the third column as an example, "connecting the half-value scaling unit to the Q terminal of the second D flip-flop L2 in the 4-bit linear feedback shift register and connecting the positive correlation median generation unit to the second D flip-flop L2's The square root approximation calculation device based on random calculation obtained by connecting the Q terminal of the second D flip-flop L2 in the 4-bit linear feedback shift register to the "positive correlation median generation unit" and connecting the second D flip-flop L2 to the The MSE obtained by performing square root calculation on the "terminal" can be improved by (0.0159 - 0.0075) / 0.0159×100% = 52.83%.

[0050] Similarly: Table 3 shows that: the linear feedback shift register is a 5-bit linear feedback shift register, and the half-value scaling unit is connected to the Q terminal of the D flip-flop Ln, and the positive correlation median generation unit is connected to the D flip-flop Ln The test result - the average value of the mean squared error (MSE) of the square root approximation calculation device based on random calculation obtained by connecting the "terminal" for square root testing; Among them, the fourth column in Table 3 actually shows the square root test result - the average value of the mean squared error (MSE) of the square root approximation calculation device described in Embodiment 4, and the test result is 0.0063 recorded in the fourth column of the second row; Table 3

[0051] It can be seen from Table 3 that when the linear feedback shift register is a 5-bit linear feedback shift register, the half-value scaling unit is connected to the Q terminal of the first D flip-flop L1, the second L2, or the third D flip-flop L3, and the positive correlation median generation unit is connected to the corresponding flip-flop The square root approximation calculation device based on random calculation obtained by connecting the "terminal" can achieve better square root calculation accuracy; in particular, the square root approximation calculation device obtained by connecting the half-value scaling unit to the Q terminal of the third D flip-flop L3 and the positive correlation median generation unit to the third D flip-flop L3 has a high calculation accuracy for square root calculation, and the average value of the mean squared error (MSE) of the average absolute error can reach 0.0063.

[0052] Table 4 shows that: the linear feedback shift register is a 5-bit linear feedback shift register, and the positive correlation median generation unit is connected to the Q terminal of the D flip-flop Ln, and the half-value scaling unit is connected to the D flip-flop Ln The test result - the average value of the mean squared error (MSE) of the square root approximation calculation device based on random calculation obtained by connecting the "terminal" for square root testing.

[0053] Table 4

[0054] Obviously, as can be seen from Table 3 and Table 4, the "half-value scaling unit is connected to the Q terminals of D flip-flops L1, L2, L3, or L4 in the 5-bit linear feedback shift register, and the positive correlation median generation unit is connected to the terminals" of the arithmetic square root approximation calculation device based on random calculation is compared with the "positive correlation median generation unit is connected to the Q terminals of D flip-flops L1, L2, L3, or L4, and the half-value scaling unit is connected to the terminals" for square root calculation, and better calculation accuracy can be achieved.

[0055] Taking the fourth column as an example, the fourth column is essentially the test result of the arithmetic square root approximation calculation device based on random calculation described in Embodiment 4. It can be seen from the fourth column that the arithmetic square root approximation calculation device obtained by "connecting the half-value scaling unit to the Q terminal of the third D flip-flop L3 in the 5-bit linear feedback shift register and connecting the positive correlation median generation unit to the terminals" is compared with the "positive correlation median generation unit is connected to the Q terminal of the third D flip-flop L3 in the 5-bit linear feedback shift register, and the half-value scaling unit is connected to the terminals" for square root calculation, and the MSE can be improved by (0.0155 - 0.0063) / 0.0155×100% = 59.35%.

[0056] Similarly: Table 5 shows: The linear feedback shift register is a 6-bit linear feedback shift register, and the half-value scaling unit is connected to the Q terminal of D flip-flop Ln, and the positive correlation median generation unit is connected to the terminals" of the arithmetic square root approximation calculation device based on random calculation for the test result of square root test - the average value of the mean squared error MSE; Among them, the third column in Table 5 essentially shows the test result of the square root test of the arithmetic square root approximation calculation device described in Embodiment 5 - the average value of the mean squared error MSE, and the test result is 0.0031 recorded in the third column of the second row; Table 5

[0057] It can be seen from Table 5 that when the linear feedback shift register is a 6-bit linear feedback shift register, the half-value scaling unit is connected to the Q terminals of the first D flip-flop L1, the second D flip-flop L2, the third D flip-flop L3, or the fourth D flip-flop L4, and the positive correlation median generation unit is connected to the corresponding flip-flop's The arithmetic square root approximation calculation devices obtained based on random calculation at the end can all achieve better square root calculation accuracy; in particular, the half-value scaling unit is connected to the Q end of the second D flip-flop L2 in the 6-bit linear feedback shift register, and the positive correlation median generation unit is connected to the The arithmetic square root approximation calculation device obtained based on random calculation at the end has a relatively high calculation accuracy for square root calculation, and the average value MSE of the mean absolute error can reach 0.0031.

[0058] Table 6 shows that: the linear feedback shift register is a 6-bit linear feedback shift register, and the positive correlation median generation unit is connected to the Q end of the D flip-flop Ln, and the half-value scaling unit is connected to the end of the arithmetic square root approximation calculation device obtained based on random calculation for square root testing - the average value MSE of the mean absolute error.

[0059] Table 6

[0060] Obviously, it can be seen from Table 5 and Table 6 that for the arithmetic square root approximation calculation device obtained by "connecting the half-value scaling unit to the Q ends of the D flip-flops L1, L2, L3, L4, or L5 in the 6-bit linear feedback shift register, and connecting the positive correlation median generation unit to the end" compared with the case of "connecting the positive correlation median generation unit to the Q ends of the D flip-flops L1, L2, L3, L4, or L5, and connecting the half-value scaling unit to the end" for square root calculation, better calculation accuracy can be achieved.

[0061] Taking the third column as an example, the third column is actually the test result of the arithmetic square root approximation calculation device described in Embodiment 5. It can be seen from the third column that for the arithmetic square root approximation calculation device obtained by "connecting the half-value scaling unit to the Q end of the second D flip-flop L2 in the 6-bit linear feedback shift register, and connecting the positive correlation median generation unit to the end" compared with the case of "connecting the positive correlation median generation unit to the Q end of the second D flip-flop L2 in the 6-bit linear feedback shift register, and connecting the half-value scaling unit to the end" for square root calculation, the MSE can be improved by (0.0060 - 0.0031) / 0.0060 × 100% = 48.33%.

[0062] Table 7 shows that: the linear feedback shift register is a 7-bit linear feedback shift register, and the half-value scaling unit is connected to the Q end of the D flip-flop Ln, and the positive correlation median generation unit is connected to the The test result of the square root calculation test on the arithmetic square root approximation calculation device based on random calculation obtained at the end - the average value MSE of the mean absolute error; Among them, the fifth column in Table 7 actually shows the square root calculation test result of the arithmetic square root approximation calculation device described in Example 6 based on random calculation - the average value MSE of the mean absolute error, and the test result is 0.0057 recorded in the second row and the fifth column; Table 7

[0063] As can be seen from Table 7, when the linear feedback shift register is a 7 - bit linear feedback shift register, the half - value scaling unit is connected to the Q - end of the third D - flip - flop L3, the fourth D - flip - flop L4, or the fifth D - flip - flop L5, and the positive - correlation median generation unit is connected to the end of the corresponding flip - flop, the arithmetic square root approximation calculation device based on random calculation obtained at the end can achieve better square root calculation accuracy. In particular, when the half - value scaling unit is connected to the Q - end of the fourth D - flip - flop L4 and the positive - correlation median generation unit is connected to the end of the fourth D - flip - flop L4, the arithmetic square root approximation calculation device based on random calculation obtained at the end has a higher calculation accuracy for square root calculation, and the average value MSE of the mean absolute error can reach 0.0057.

[0064] Table 8 shows the test result of the square root calculation test on the arithmetic square root approximation calculation device based on random calculation obtained when the linear feedback shift register is a 7 - bit linear feedback shift register, and the positive - correlation median generation unit is connected to the Q - end of the D - flip - flop Ln and the half - value scaling unit is connected to the end of the D - flip - flop Ln. - the average value MSE of the mean absolute error.

[0065] Table 8

[0066] Obviously, as can be seen from Table 7 and Table 8, the arithmetic square root approximation calculation device based on random calculation obtained by "connecting the half - value scaling unit to the Q - end of the D - flip - flops L3, L4, L5, or L6 in the 7 - bit linear feedback shift register and connecting the positive - correlation median generation unit to the end" has better calculation accuracy for square root calculation compared to the case of "connecting the positive - correlation median generation unit to the Q - end of the D - flip - flops L3, L4, L5, or L6 and connecting the half - value scaling unit to the end".

[0067] Taking the fifth column as an example, the fifth column is essentially the test result of the arithmetic square root approximation calculation device based on random calculation described in Embodiment 6. From the fifth column, it can be seen that the arithmetic square root approximation calculation device based on random calculation obtained by "the half-value scaling unit is connected to the Q terminal of the fourth D flip-flop L4 in the 7-bit linear feedback shift register, and the positive correlation median generation unit is connected to the terminal" has an MSE improvement of (0.0115 - 0.0057) / 0.0115×100% = 50.43% compared to the square root calculation obtained by "the positive correlation median generation unit is connected to the Q terminal of the fourth D flip-flop L4 in the 7-bit linear feedback shift register, and the half-value scaling unit is connected to the terminal".

[0068] Table 9 shows that: the linear feedback shift register is an 8-bit linear feedback shift register, and for the arithmetic square root approximation calculation device based on random calculation obtained by connecting the half-value scaling unit to the Q terminal of D flip-flop Ln and the positive correlation median generation unit to the terminal, the test result - the average value of the mean squared error (MSE) of the square root test; Among them, the sixth column in Table 9 essentially shows the square root test result - the average value of the mean squared error (MSE) of the arithmetic square root approximation calculation device described in Embodiment 1, and the test result is 0.0065 recorded in the second row and sixth column; Table 9

[0069] From Table 9, it can be seen that when the linear feedback shift register is an 8-bit linear feedback shift register, and the half-value scaling unit is connected to the Q terminals of the second D flip-flop L2, the third D flip-flop L3, the fourth D flip-flop L4, the fifth D flip-flop L5, or the sixth D flip-flop L6, and the positive correlation median generation unit is connected to the terminal of the corresponding flip-flop, the arithmetic square root approximation calculation device based on random calculation can achieve better square root calculation accuracy; in particular, the arithmetic square root approximation calculation device obtained by connecting the half-value scaling unit to the Q terminal of the fifth D flip-flop L5 and the positive correlation median generation unit to the terminal has a relatively high calculation accuracy for square root calculation, and the MSE can reach 0.0065.

[0070] Table 10 shows that: the linear feedback shift register is an 8-bit linear feedback shift register, and the positive correlation median generation unit is connected to the Q terminal of D flip-flop Ln, and the half-value scaling unit is connected to the Test result of the square root calculation of the approximate arithmetic square root calculation device based on random calculation obtained at the end - average value of the mean squared error (MSE).

[0071] Table 10

[0072] Obviously, as can be seen from Table 9 and Table 10, for the approximate arithmetic square root calculation device based on random calculation obtained by "connecting the Q - terminals of D - flip - flops L1, L2, L3, L4, L5, L6, or L7 in the 8 - bit linear feedback shift register to the half - value scaling unit, and connecting the positive - correlation median generation unit to the terminals" of the corresponding D - flip - flops, compared with the case of "connecting the Q - terminals of D - flip - flops L1, L2, L3, L4, L5, L6, or L7 in the 8 - bit linear feedback shift register to the positive - correlation median generation unit, and connecting the half - value scaling unit to the terminals" of the corresponding D - flip - flop L3 for square root calculation, it can achieve better calculation accuracy.

[0073] Taking the sixth column as an example, the sixth column is essentially the test result of the approximate arithmetic square root calculation device based on random calculation described in Embodiment 4. From the sixth column, it can be seen that for the approximate arithmetic square root calculation device obtained by "connecting the Q - terminal of the fifth D - flip - flop L5 in the 8 - bit linear feedback shift register to the half - value scaling unit and connecting the positive - correlation median generation unit to the terminals", compared with the case of "connecting the Q - terminal of the fifth D - flip - flop L5 in the 8 - bit linear feedback shift register to the positive - correlation median generation unit and connecting the half - value scaling unit to the terminals" for square root calculation, the MSE can be improved by (0.0112 - 0.0065) / $0.0112\times100\% = 41.96\%$.

[0074] Table 11 shows that: when the linear feedback shift register is a 9 - bit linear feedback shift register, and the half - value scaling unit is connected to the Q - terminal of D - flip - flop Ln and the positive - correlation median generation unit is connected to the terminals of D - flip - flop Ln, the test result of the square root calculation of the approximate arithmetic square root calculation device based on random calculation - average value of the mean squared error (MSE); Among them, the seventh column in Table 11 essentially shows the square root test result - average value of the mean squared error (MSE) of the approximate arithmetic square root calculation device described in Embodiment 7, and the test result is 0.0069 recorded in the second row and seventh column; Table 11

[0075] As can be seen from Table 11, when the linear feedback shift register is a 9-bit linear feedback shift register, the half-value scaling unit is connected to the Q terminal of D flip-flop L1, D flip-flop L2, D flip-flop L3, D flip-flop L4, D flip-flop L5, D flip-flop L6 or D flip-flop L7, and the positive-correlation median generation unit is connected to the terminal of the corresponding flip-flop, the arithmetic square root approximation calculation device based on random calculation can achieve better square root calculation accuracy; in particular, when the half-value scaling unit is connected to the Q terminal of the sixth D flip-flop L6 and the positive-correlation median generation unit is connected to the terminal of the sixth D flip-flop L6, the arithmetic square root approximation calculation device based on random calculation has relatively high calculation accuracy for square root calculation, and the MSE can reach 0.0069.

[0076] Table 12 shows that: when the linear feedback shift register is a 9-bit linear feedback shift register, and the positive-correlation median generation unit is connected to the Q terminal of D flip-flop Ln and the half-value scaling unit is connected to the terminal of D flip-flop Ln, the test result - MSE of the arithmetic square root approximation calculation device based on random calculation for square root testing.

[0077] Table 12

[0078] Obviously, as can be seen from Tables 11 and 12, for the arithmetic square root approximation calculation device based on random calculation obtained by "connecting the half-value scaling unit to the Q terminal of D flip-flops L1, L2, L3, L4, L5, L6, L7 or L8 in the 9-bit linear feedback shift register, and connecting the positive-correlation median generation unit to the terminal of the corresponding D flip-flop", compared with the case of "connecting the positive-correlation median generation unit to the Q terminal of D flip-flops L1, L2, L3, L4, L5, L6, L7 or L8, and connecting the half-value scaling unit to the terminal of the corresponding D flip-flop L3" for square root calculation, it can achieve better calculation accuracy.

[0079] Taking the seventh column as an example, the seventh column is actually the test result of the arithmetic square root approximation calculation device described in Embodiment 7. As can be seen from the seventh column, for the arithmetic square root approximation calculation device obtained by "connecting the half-value scaling unit to the Q terminal of the sixth D flip-flop L6 in the 9-bit linear feedback shift register and connecting the positive-correlation median generation unit to the terminal of the sixth D flip-flop L6", compared with the case of "connecting the positive-correlation median generation unit to the Q terminal of the sixth D flip-flop L6 in the 9-bit linear feedback shift register and connecting the half-value scaling unit to the The MSE obtained by taking the square root of the "end" can be improved by (0.0112 - 0.0069) / 0.0112×100% = 38.39%.

[0080] Table 13 shows that: the linear feedback shift register is a 10-bit linear feedback shift register, and the half-value scaling unit is connected to the Q end of the D flip-flop Ln, and the positive correlation median generation unit is connected to the end of the D flip-flop Ln to obtain the test result - MSE of the square root test of the arithmetic square root approximation calculation device based on random calculation; Among them, the eighth column in Table 13 actually shows the square root test result of the arithmetic square root approximation calculation device described in Example 8 - the average value of the mean absolute error MSE, and the test result is 0.0071 recorded in the second row and the eighth column; Table 13

[0081] As can be seen from Table 13, when the linear feedback shift register is a 10-bit linear feedback shift register, the half-value scaling unit is connected to the Q ends of the D flip-flops L3, L4, L5, L6, L7 or L8, and the positive correlation median generation unit is connected to the ends of the corresponding flip-flops, the arithmetic square root approximation calculation device based on random calculation can achieve better square root calculation accuracy; in particular, the arithmetic square root approximation calculation device obtained by connecting the half-value scaling unit to the Q end of the seventh D flip-flop L7 and the positive correlation median generation unit to the seventh D flip-flop L7 has a higher calculation accuracy for square root calculation, and the MSE can reach 0.0071.

[0082] Table 14 shows that: the linear feedback shift register is a 10-bit linear feedback shift register, and the positive correlation median generation unit is connected to the Q end of the D flip-flop Ln, and the half-value scaling unit is connected to the end of the D flip-flop Ln to obtain the test result - MSE of the square root test of the arithmetic square root approximation calculation device based on random calculation.

[0083] Table 14

[0084] Obviously, as can be seen from Tables 13 and 14, "the half-value scaling unit is connected to the Q ends of the D flip-flops L3, L4, L5, L6, L7, L8 or L9 in the 9-bit linear feedback shift register, and the positive correlation median generation unit is connected to the The square root approximation calculation device based on random calculation obtained by connecting the Q terminals of D flip-flops L3, L4, L5, L6, L7, L8, or L9 to the "positive correlation median generation unit" and connecting the half-value scaling unit to the corresponding terminal" for square root calculation can achieve better calculation accuracy.

[0085] Taking the eighth column as an example, the eighth column is actually the test result of the square root approximation calculation device based on random calculation described in the eighth embodiment. From the eighth column, it can be seen that "the half-value scaling unit is connected to the Q terminal of the seventh D flip-flop L7 in the 9-bit linear feedback shift register, and the positive correlation median generation unit is connected to the seventh D flip-flop L7 terminal", the square root approximation calculation device based on random calculation obtained is compared with "the positive correlation median generation unit is connected to the Q terminal of the seventh D flip-flop L7 in the 9-bit linear feedback shift register, and the half-value scaling unit is connected to the seventh D flip-flop L7 terminal", and the MSE obtained by square root calculation can be improved by (0.0111 - 0.0071) / 0.0111×100% = 36.04%.

[0086] Those of ordinary skill in the art will realize that the above examples are for helping readers understand the principle of the present invention and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific deformations and combinations that do not depart from the essence of the present invention based on the technical revelations disclosed in the present invention, and these deformations and combinations are still within the protection scope of the present invention.

Claims

1. An arithmetic square root approximation calculation device based on maximum negative correlation, characterized in that: It includes a linear feedback shift register, a comparator, a square root calculation unit, a positive correlation median generation unit, a half-value scaling unit, a division unit, and a delay unit; The linear feedback shift register includes exclusive-OR gates and N D flip-flops, where N is equal to the number of bits of the linear feedback shift register; one input terminal of the comparator is used to input a binary number, and the other input terminals of the comparator are all connected to the Q terminals of all D flip-flops in the linear feedback shift register. The comparator CMP and the delay unit are both connected to the square root calculation unit; the Q terminal of one of the D flip-flops and the terminal are respectively connected to the half-value scaling unit and the positive correlation median generation unit. The other input terminal of the half-value scaling unit is connected to the square root calculation unit. The output terminal of the half-value scaling unit is respectively connected to one input terminal of the positive correlation median generation unit and port 1 of the division unit. The output terminal of the positive correlation median generation unit is connected to the selection terminal of the division unit. The output terminal of the division unit is connected to the delay unit. The delay unit is respectively connected to the other input terminal of the square root calculation unit and port 0 of the division unit.

2. The arithmetic square root approximation calculation device based on maximum negative correlation according to claim 1, wherein: The division unit is a multiplexer MUX2.

3. The arithmetic square root approximation calculation device based on maximum negative correlation according to claim 1, characterized in that: When the linear feedback shift register is 4-bit, the Q terminal of the second D flip-flop L2 is connected to another input terminal of the half-value scaling unit, and the terminal is connected to the positive correlation median generation unit.

4. An arithmetic square root approximation calculation device based on maximum negative correlation according to claim 1, characterized in that: When the linear feedback shift register is 5-bit, the Q terminal of one of the first to third D flip-flops is connected to another input terminal of the half-value scaling unit, and the terminal is connected to the positive-correlation median generation unit.

5. The arithmetic square root approximation calculation device based on maximum negative correlation according to claim 1, wherein: When the linear feedback shift register is 6-bit, the Q terminal of one of the first to fourth D flip-flops is connected to another input terminal of the half-value scaling unit, and the terminal is connected to the positive correlation median generation unit.

6. The arithmetic square root approximation calculation device based on maximum negative correlation according to claim 1, characterized in that: When the linear feedback shift register is 7-bit, the Q terminal of one of the D flip-flops from the third to the fifth D flip-flop is connected to another input terminal of the half-value scaling unit, and the terminal is connected to the positive correlation median generation unit.

7. An arithmetic square root approximation calculation device based on maximum negative correlation according to claim 1, characterized in that: When the linear feedback shift register is 8-bit, the Q terminal of one of the second to sixth D flip-flops is connected to another input terminal of the half-value scaling unit, and the terminal is connected to the positive correlation median generation unit.

8. An arithmetic square root approximation calculation device based on maximum negative correlation according to claim 1, characterized in that: When the linear feedback shift register is 9-bit, the Q terminal of one of the first to seventh D flip-flops is connected to another input terminal of the half-value scaling unit, and the terminal is connected to the positive correlation median generation unit.

9. An arithmetic square root approximation calculation device based on maximum negative correlation according to claim 1, characterized in that: When the linear feedback shift register is 10-bit, the Q terminal of one of the third to eighth D flip-flops is connected to another input terminal of the half-value scaling unit, and the terminal is connected to the positive correlation median generation unit.

10. A calculation method of an arithmetic square root approximation calculation device based on the above maximum negative correlation, characterized in that: The arithmetic square root approximation calculation device based on the above maximum negative correlation is the arithmetic square root approximation calculation device described in claim 1. The calculation method of the arithmetic square root approximation calculation device based on the above maximum negative correlation includes the following steps: S1. Perform multiple charge and discharge operations on the linear feedback shift register to make it have an initial state where not all bits are "0"; perform one charge and discharge operation on the division unit and the delay unit respectively to make the delay unit and the division unit have their respective initial bits; S2. Input an N-bit binary number from one input terminal of the comparator. The N-bit binary number IN is the data to be square-rooted, and N is the same as the number of bits of the linear feedback shift register; the comparator compares the value represented by the binary number formed by the output bits of the linear feedback shift register with the value represented by the binary number IN; S3. The square root calculation unit performs an "OR" logical operation on the bits output by the comparator CMP and the bits output by the delay unit; S4. The half-value scaling unit performs a logical "AND" calculation on the bits output by the square root calculation unit and the bits output by the Q terminal of one of the D flip-flops in the linear feedback shift register; S5. Use the positive-correlation median generation unit to perform a logical "OR" calculation on the bits output by the half-value scaling unit and the bits output by the D flip-flops in the linear feedback shift register. The D flip-flop described in step S5 is the same flip-flop as the D flip-flop described in step S4; The D flip-flop described in step S5 is the same flip-flop as the D flip-flop described in step S4; S6. Use the division unit to select the bits output by the half-value scaling unit and the bits output by the positive correlation median generation unit, and then use the delay unit to delay the bits output by the division unit. The bits output by the delay unit are sent to the square root calculation unit and fed back to the division unit for selection in the next clock cycle. The square root calculation unit OR1 first adds the bits output by the comparator CMP and the bits output by the delay unit, and then subtracts the product of the two bits. In this way, the calculation process of one clock cycle is completed; then, according to the clock signal, the internal state of the 8-bit linear feedback shift register is shifted and updated to obtain a new state different from the previous state; S7. Repeat the calculation process described in steps S2 to S6 N - two times to obtain the final accurate calculation result .

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