Simulation logic system design method, electronic equipment and storage medium

Abstract

The invention provides a method for simulating a logic system design by using a hardware simulation tool, and a programmable logic device of the hardware simulation tool is connected to a daughter card through an interface adapter. The interface adapter comprises a plurality of first pins used for being connected to the programmable logic device, a plurality of second pins used for being connected to the daughter card and at least one third pin used for reading values of the plurality of first pins or the plurality of second pins; the memory is used for storing and configuring a connection relationship among the plurality of first pins, the plurality of second pins and the at least one third pin, and the method comprises the following steps: determining that a connection error exists between the hardware simulation tool and the daughter card; in response to the connection error, obtaining an updated connection relationship between the plurality of first pins and the plurality of second pins; and configuring the connection between the first pin and the second pin according to the updated connection relationship.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a method, electronic device, and storage medium for simulating logic system design. Background Art

[0002] A hardware simulation tool (e.g., a prototype verification board or a hardware emulator) can prototype and debug a logic system design that includes one or more modules. The logic system design can be, for example, an integrated circuit (ASIC) or a system-on-chip (SOC) for a specific application. Therefore, the logic system design tested in the simulation tool can also be called a design under test (DUT). The simulation tool can simulate the DUT through one or more configurable components (e.g., a field programmable gate array (FPGA)), including executing various operations of the DUT, thereby testing and verifying the functions of each module of the DUT before manufacturing. By connecting a variety of peripheral daughter cards to the simulation tool, the effect of the DUT and various peripherals running as a complete system can also be tested.

[0003] There are many softwares to match the hardware simulation tools, such as compilers, synthesizers, debuggers, etc.

[0004] The compiler compiles the source code of the logic system design, the synthesizer converts the logic system design into a netlist and burns it into the FPGA, and the debugger performs some simple debugging. It's understood that these software runs on the host computer connected to the hardware emulation tool.

[0005] When connecting multiple peripheral daughter cards to the hardware emulation tool, cable connection errors may occur. These cable connection errors may be caused by user errors during connection or by pin configuration errors in the logic system design. Summary of the Invention

[0006] A first aspect of the present application provides a method for simulating a logic system design using a hardware simulation tool. A programmable logic device of the hardware simulation tool is connected to a daughter card via an interface adapter. The interface adapter includes: a plurality of first pins for connecting to the programmable logic device of the hardware simulation tool, a plurality of second pins for connecting to the daughter card, and at least one third pin for reading values of the plurality of first pins or the plurality of second pins; and a memory for storing a connection relationship configuring connections between the plurality of first pins, the plurality of second pins, and the at least one third pin. The method includes: determining that a connection error exists between the hardware simulation tool and the daughter card; in response to the connection error, obtaining an updated connection relationship between the plurality of first pins and the plurality of second pins; and configuring a connection between the plurality of first pins and the plurality of second pins according to the updated connection relationship.

[0007] A second aspect of the present application provides an electronic device, including: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method as described in the first aspect.

[0008] A third aspect of the present application provides a non-transitory computer-readable storage medium storing a set of instructions of a computer, the set of instructions being configured to cause the computer to perform the method as described in the first aspect when executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the present application or related technologies, the following will briefly introduce the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings in the following description are only embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0010] Figure 1 The structural schematic diagram of an exemplary host according to an embodiment of the present application is shown.

[0011] Figure 2 The schematic diagram of a simulation system according to an embodiment of the present application is shown.

[0012] Figure 3 The schematic diagram of another simulation system according to an embodiment of the present application is shown.

[0013] Figure 4 The schematic diagram of an interface adapter according to an embodiment of the present application is shown.

[0014] Figure 5 The schematic diagram of another exemplary interface adapter according to an embodiment of the present application is shown.

[0015] Figure 6 A schematic diagram of another exemplary interface adapter according to an embodiment of the present application is shown.

[0016] Figure 7 A schematic diagram of a hardware simulation system according to an embodiment of the present application is shown.

[0017] Figure 8 A flowchart of a method for simulating a logic system design using a hardware simulation tool according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0018] In order to make the objectives, technical solutions and advantages of this application more clear, this application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0019] It should be noted that, unless otherwise defined, the technical or scientific terms used in this application should have the usual meaning understood by people with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0020] As mentioned above, cable connection errors may occur when connecting multiple peripheral daughter cards to the hardware emulation tool. These cable connection errors may be caused by errors made by the user when connecting cables (typically there can be dozens of cables, making them very error-prone) (for example, incorrect cable connections) or by pin configuration errors in the logic system design.

[0021] Generally, when an error occurs due to a user connection error, the hardware emulation system may require the user to reconnect; when a configuration pin error occurs, the hardware emulation system may require the user to reconfigure and recompile.

[0022] This shows that once an error occurs, users need to spend a lot of time adjusting the physical connection or pin configuration.

[0023] How to facilitate users to adjust cable connection errors is a technical problem that needs to be solved urgently.

[0024] Figure 1 FIG1 shows a schematic diagram of the structure of the host 100 according to an embodiment of the present application. The host 100 may be an electronic device running a simulation system.Figure 1 As shown, the host 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Among them, the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively connected to each other inside the electronic device through the bus 110.

[0025] The processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. The processor 102 may be used to execute functions related to the technologies described in this application. In some embodiments, the processor 102 may further include multiple processors integrated as a single logic component. As Figure 1 shown, the processor 102 may include multiple processors 102a, 102b, and 102c.

[0026] The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, the simulation test system for simulating a test design may be a computer program stored in the memory 104. As Figure 1 shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the method of positioning errors in this application) and data to be processed (e.g., the memory may store temporary code generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard disk, a solid state drive (SSD), a flash memory, a memory stick, etc.

[0027] The network interface 106 may be configured to provide communication between the host 100 and other external devices via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination of the above. It can be understood that the type of the network is not limited to the above specific examples. In some embodiments, the network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0028] The peripheral interface 108 can be configured to connect the host 100 to one or more peripheral devices to achieve information input and output. For example, the peripheral devices can include input devices such as keyboards, mice, touchpads, touchscreens, microphones, various sensors, etc., and output devices such as displays, speakers, vibrators, indicator lights, etc.

[0029] The bus 110 can be configured to transfer information between various components of the host 100 (such as the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as internal buses (e.g., processor - memory bus), external buses (USB ports, PCI - E buses), etc.

[0030] It should be noted that although the above - mentioned electronic device architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in the specific implementation process, this electronic device architecture may also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above - mentioned electronic device architecture may also only include the components necessary to implement the solution of the embodiments of the present application, and do not necessarily include all the components shown in the figure.

[0031] Figure 2 A schematic diagram of a simulation system 200 according to an embodiment of the present application is shown.

[0032] As Figure 2 shown, the simulation system 200 can include a simulation tool 202 and a host 100 connected to the simulation tool 202.

[0033] The simulation tool 202 is a hardware system for simulating a design under test (DUT). The simulation tool 202 can be a prototype verification board or a hardware emulator. A design under test can include multiple modules. The design under test can be a combinational logic circuit, a sequential logic circuit, or a combination of the two. The simulation tool 202 can include one or more configurable circuits (e.g., FPGA) for simulating the design under test.

[0034] The simulation tool 202 can include an interface unit 2022 for communicatively coupling with the host 100 to enable communication between the host 100 and the simulation tool 202. In some embodiments, the interface unit 2022 can include one or more interfaces with electrical connection capabilities. For example, the interface unit 2022 can include RS232 interfaces, USB interfaces, LAN ports, fiber optic interfaces, IEEE1394 (FireWire interfaces), etc. In some embodiments, the interface unit 2022 can be a wireless network interface. For example, the interface unit 2022 can be a WIFI interface, a Bluetooth interface, etc.

[0035] The host 100 can transmit the compiled DUT, debug instructions, etc. to the simulation tool 202 via the interface unit 2022. The simulation tool 202 can also transmit simulation data, etc. to the host 100 via the interface unit 2022.

[0036] The simulation tool 202 may further include a memory 2024 for storing simulation data (e.g., various signal values) generated by the design under test during the simulation process. In some embodiments, the signal values generated by the design under test during the simulation process can be directly read by the host 100. It can be understood that the memory 2024 can also be independent of the simulation tool 202, for example, using an external memory.

[0037] The simulation tool 202 may further include a programmable logic device (e.g., FPGA) 2026 for implementing the logic system design hardware onto the programmable logic device. It can be understood that the simulation tool 202 may include multiple programmable logic devices, which is only an example in the figure.

[0038] In addition to being connected to the host 100, the simulation tool 202 can also be connected to one or more daughter cards 204 via the interface unit 2022.

[0039] The daughter card is used to provide peripherals to the DUT to form a complete electronic system when using the simulation tool 202 for prototype verification. Prototype verification refers to a verification method that, before the chip is taped out, tries to restore the real usage scenario of the chip as much as possible to verify whether the chip functions accurately and completely. The daughter card 204 can include a memory daughter card (e.g., providing a DDR memory interface), a communication daughter card (e.g., providing multiple network interfaces or a wireless network card interface), etc. The daughter card 204 can refer to all peripherals.

[0040] The host 100 can be used to configure the simulation tool 202 to simulate a design under test. The design under test can be a complete logic system design or one or more modules of a complete logic system design. In some embodiments, the host 100 can be a virtual host in a cloud computing system. The logic system design (e.g., ASIC or System-On-Chip) can be designed by a hardware description language (e.g., Verilog, VHDL, System C, or System Verilog). The host 100 configuring the simulation tool 202 can include configuring the simulation environment (e.g., the connection relationship between multiple simulation tools 202 or the connection relationship between the simulation tool and the daughter card), etc.

[0041] The host 100 can compile the logic system design in source code form into an executable file. From a design perspective, the logic system design can include the design under test and a test bench corresponding to the design under test.

[0042] From a comprehensive perspective, the logical system design can include synthesizable parts and non-synthesizable parts. The synthesizable parts usually correspond to the actual physical design (e.g., a chip), while the non-synthesizable parts usually include initialization modules, test benches, etc. The executable file formed after compilation of the non-synthesizable parts can usually be run by the host 100. The synthesizable parts still need to be synthesized after compilation to form a bit file. The bit file can be used to configure the FPGA 2026 to run according to the design requirements of the synthesizable parts.

[0043] The host 100 can receive a request from the user to debug the design under test. As described above, the design under test can include one or more modules. The description of the design under test can be completed in a hardware description language. The host 100 can perform synthesis based on the description of the design under test to generate, for example, a gate-level circuit netlist (not shown) of the design under test. The gate-level circuit netlist of the design under test can be loaded into the simulation tool 202 to run, and then a circuit structure corresponding to the design under test can be formed in the simulation tool 202. Therefore, the circuit structure of the design under test can be obtained according to the description, and correspondingly, the circuit structure of each block in the design under test can also be obtained similarly.

[0044] As described above, when the daughter card 204 is connected to the simulation tool 202, a cable connection error may occur due to a wiring error or a configuration error.

[0045] In view of the above problems, an embodiment of the present application provides a novel structure of a simulation tool.

[0046] Figure 3 A schematic diagram of another simulation system 300 according to an embodiment of the present application is shown.

[0047] The simulation system 300 can include a hardware simulation tool 302, a daughter card 204, a host 100, and a host 304.

[0048] Different from the general structure, outside the interface unit 2022, the memory 2024, and the programmable logic device 2026, the simulation tool 302 further includes an interface adapter 3022.

[0049] The interface adapter 3022 is connected to the daughter card 204, the programmable logic device 2026, and the host 304. The host 304 and the host 100 can be the same host or different hosts. Here, for the sake of distinction, different hosts are taken as an example for illustration.

[0050] Figure 4 A schematic diagram of the interface adapter 3022 according to an embodiment of the present application is shown.

[0051] As Figure 4As shown, after the logic system design is configured into the FPGA 2026, n + 1 leads of the FPGA 2026 are configured as n + 1 pins pin_00, pin_01, pin_02, …, pin_0n of the logic system design. n can be a positive integer greater than 1. It can be understood that the FPGA 2026 has at least n + 1 leads, and the configured leads are only at least a part of all the leads of the FPGA 2026. Generally, the pins pin_00, pin_01, pin_02, …, pin_0n are used as inputs or outputs of the logic system design. It can be understood that the n + 1 pins pin_00, pin_01, pin_02, …, pin_0n of the logic system design can be connected to the interface adapter 3022 via the interface 202 of the hardware simulation tool 302. That is to say, the connection of the interface adapter 3022 to the programmable logic device (e.g., FPGA) 2026 can be indirect (e.g., via an additional interface). It can be understood that in the description of the embodiments of the present application, any connection includes a direct connection or an indirect connection.

[0052] The interface adapter 3022 may include a plurality of first pins A0, A1, A2, …, An for connecting to the programmable logic device 2026 and a plurality of second pins B0, B1, B2, …, Bn for connecting to the daughter card 204. The interface adapter 3022 may further include a third pin Am, Bo, etc.

[0053] In some embodiments, the pins Am, etc. and the plurality of first pins A0, A1, A2, …, An are arranged on one side of the interface adapter 3022 for connecting to the hardware simulation tool 302. Therefore, the pins A0, A1, A2, …, An, …Am can be referred to as internal connection pins. The pins Bo, etc. and the plurality of second pins B0, B1, B2, …, Bn are arranged on the other side of the interface adapter 3022 for connecting to the daughter card 204. Therefore, the pins B0, B1, B2, …, Bn can be referred to as external connection pins. It can be understood that the arrangement of the pins is not necessarily limited to both sides.

[0054] It can be seen that the number m + 1 of the internal connection pins can be a positive integer greater than or equal to n + 1; the number o + 1 of the external connection pins can be a positive integer greater than or equal to n + 1.

[0055] The third pins Am, Bo can be used to read the values of the plurality of first pins or the plurality of second pins. Specifically, it will be further described later.

[0056] The interface adapter 3022 may include a memory 3024 for storing the connection relationship between the plurality of first pins and the plurality of second pins. The connection relationship is, for example, that pin A0 is connected to pin B0.

[0057] The interface adapter 3022 can configure the connection between the first pin and the second pin of the interface adapter 3022 according to the above connection relationship.

[0058] Corresponding to the FPGA 2026, the daughter card 204 may also include n + 1 pins pin_10, pin_11, pin_12, …, pin_1n.

[0059] In Figure 4 In the embodiment of, according to the design intention, the pins pin_00, pin_01, pin_02, …, pin_0n of the logic system design should be respectively connected to the pins pin_10, pin_11, pin_12, …, pin_1n of the daughter card 204.

[0060] As stated in this application, the cable connection error may be caused by configuration errors and physical lead connection errors (e.g., ribbon cable connection errors).

[0061] Figure 5 FIG. shows a schematic diagram of another exemplary interface adapter 3022 according to an embodiment of this application.

[0062] In some embodiments, as Figure 5 shown, due to user configuration errors, the pin that should have been configured as pin_00 is configured as pin_01, and the pin that should have been configured as pin_01 is configured as pin_00. For the existing connection method (i.e., the pins of the FPGA 2026 are directly connected to the corresponding pins of the daughter card 204), pin_01 will be connected to pin_10, and pin_00 will be connected to pin_11. Compared with the correct connection where pin_00 is connected to pin_10 and pin_01 is connected to pin_11, a connection error occurs. In the prior art, it is necessary to reconfigure the logic system design, generate a new bit file, and correspondingly reconfigure the FPGA 2026, which consumes a lot of time. Figure 5 The embodiment of can quickly correct the error by using the interface adapter 3022 of this application.

[0063] After the user locates the configuration errors of pin_00 and pin_01, the user can dynamically modify the connection relationship between the multiple first pins and the multiple second pins in the interface adapter 3022 via the host 304. In some embodiments, the user can implement the modification of the connection relationship in the memory 3024 in the host 304. For example, compared with the default connection where the first pin A0 is connected to the second pin B0 and the first pin A1 is connected to the second pin B1, the connection relationship can be modified to the first pin A0 is connected to the second pin B1 and the first pin A1 is connected to the second pin B0.

[0064] In this way, the misconfigured pin_01 can be connected to the second pin B1 after passing through the first pin A0 of the interface adapter 3022, and finally connected to the pin pin_11 of the daughter card 204 to form a correct connection.

[0065] Similarly, the misconfigured pin_00 can also be correctly connected to the pin pin_10.

[0066] In this way, the user can correct the incorrect connection without recompiling and configuring the FPGA 2026, improving the efficiency.

[0067] The above embodiments are described by taking configuration errors as examples. It can be understood that other types of connection errors can be corrected similarly.

[0068] Figure 6 FIG. shows a schematic diagram of another exemplary interface adapter 3022 according to an embodiment of the present application.

[0069] In some embodiments, one first pin of the interface adapter 3022 can be connected to more than two second pins, and one second pin can be connected to more than two first pins.

[0070] For example, as Figure 6 shown, the first pin An can be connected to the second pin Bn and the third pin Bo. In this way, without affecting the normal verification of the logic system design, the user can also read the value of the first pin An through the pin Bo, and further read the value of Pin_0n connected to the first pin An. That is to say, without affecting the normal verification of the logic system design, the user can directly observe the output of the FPGA 2026 by using the interface adapter 3022, thus reducing the additional occupation of the limited IO resources of the FPGA.

[0071] Similarly, the second pin Bn can be connected to the first pin An and the third pin Am. In this way, the user can also read the value of the second pin Bn through the third pin Am, and further read the value of Pin_1n connected to the second pin Bn.

[0072] In some embodiments, the interface adapter can be independent of the hardware simulation tool.

[0073] Figure 7 FIG. shows a schematic diagram of a hardware simulation system 700 according to an embodiment of the present application.

[0074] As Figure 7As shown, the hardware simulation system 700 can be used to connect to the first host 100 and the daughter card 204 to simulate a logic system design, and includes: a hardware simulation tool 702 for connecting to the first host 100 and the daughter card 204 to simulate a logic system design; and an interface adapter 704 connecting the hardware simulation tool 702 and the daughter card 204.

[0075] The hardware simulation tool 702 can include: a programmable logic device for implementing the logic system design (e.g., Figure 7 the FPGA 2026 in); and a first interface 2022 connecting the programmable logic device and the first host 100.

[0076] The interface adapter 704 is also connected to the second host 304.

[0077] The interface adapter 704 further includes: a plurality of first pins for connecting to the first interface (e.g., Figure 4 A0~An of), a plurality of second pins for connecting to the daughter card (e.g., Figure 4 B0~Bn of) and at least one third pin for reading the plurality of first pins or the plurality of second pins (e.g., Figure 4 Am or Bo of etc.); a memory (e.g., Figure 4 3024 of), for storing the connection relationship (e.g., Figure 5 the connection relationship shown) configuring the connection between the plurality of first pins, the plurality of second pins and the at least one third pin. It can be understood that although Figure 4 and Figure 5 the described interface adapter is integrated with the hardware simulation tool, the structure of the interface adapter is the same.

[0078] In addition, in some embodiments, the first host 100 and the second host 304 can be the same host or different hosts, and they are described separately here only for distinction.

[0079] By providing an interface adapter (separate or as part of the hardware simulation tool) to the hardware simulation tool in the hardware simulation system, the connection relationship between the pins can be flexibly adjusted, thereby avoiding reconfiguration, recompilation and reconnecting caused by connection errors, and improving the verification efficiency of the logic system design.

[0080] The embodiment of the present application also provides a method for simulating a logic system design using a hardware simulation tool.

[0081] Figure 8 shows a method for using a hardware simulation tool (e.g., Figure 7Flowchart of a method 800 for simulating a hardware emulation tool 702 of a logic system design. The method 800 may be executed by a host 304 connected to an interface adapter (e.g., Figure 7 interface adapter 704).

[0082] The programmable logic device of the hardware emulation tool (e.g., Figure 7 FPGA 2026) is connected to a daughter card (e.g., Figure 7 daughter card 204) via the interface adapter. The interface adapter includes: a plurality of first pins for connecting to the programmable logic device of the hardware emulation tool (e.g., Figure 6 pins A0 to An), a plurality of second pins for connecting to the daughter card (e.g., Figure 6 pins B0 to Bn), and at least one third pin for reading the values of the plurality of first pins or the plurality of second pins (e.g., Figure 6 pin Am or Bo); and a memory (e.g., Figure 6 memory 3024) for storing a connection relationship (such as Figure 6 the connection relationship between the respective pins) configuring the connection between the plurality of first pins, the plurality of second pins, and the at least one third pin. The method 800 may include the following steps.

[0083] In step 802, determine that there is a connection error between the hardware emulation tool and the daughter card (e.g., Figure 6 the connection error caused by the configuration error in the dashed box).

[0084] In step 804, in response to the connection error, obtain an updated connection relationship between the plurality of first pins and the plurality of second pins (e.g., configure pin A0 to be connected to pin B1; configure pin A1 to be connected to pin B0). In some embodiments, the updated connection relationship may be manually completed by the user. In other embodiments, the updated connection relationship may be automatically completed by the host 304. For example, the host 304 may detect the error and the type of the error; for the type of the configuration error, the host 304 may automatically analyze the cause of the error and correct it according to the error.

[0085] In step 806, configure the connection between the plurality of first pins and the plurality of second pins according to the updated connection relationship. For example, the host 304 may update the connection relationship in the memory 3024. The connection relationship in the memory 3024 may be stored in a table form. The processor (e.g., a routing chip or a switching chip) on the interface adapter 704 may update the connection relationship of the pins according to the above connection relationship.

[0086] In some embodiments, method 800 may include: implementing the logic system design on the programmable logic device according to the description of the logic system design (e.g., the source file of the logic system design or the compiled netlist, etc.) and the configuration file. Usually, this step appears in the early stage of simulating the logic system design using a hardware simulation tool, that is, the stage of configuring and compiling the logic system design. Different from software simulation, due to the particularity of the hardware, the user needs to configure the simulation environment (e.g., the running frequency, the connection assignment of pins, etc.), and the generated configuration file will be compiled together with the logic system design.

[0087] The method 800 further includes: modifying the configuration file or the description of the logic system design according to the updated connection relationship. Since there are many pins in a large-scale logic system design, always letting the user modify manually will create a lot of additional workload and the possibility of errors. In the embodiments of the present application, the host 304 may determine the errors in the configuration file or the description of the logic system design according to the updated connection relationship, and make corresponding modifications.

[0088] For example, when the host 304 learns that the updated connection relationship includes configuring pin A0 to be connected to pin B1 and pin A1 to be connected to pin B0, the host 304 may further determine that there are errors in the assignment of pins pin_01 and pin_00 of the logic system design, and make corresponding modifications.

[0089] This can greatly reduce the burden on the user to modify the configuration file or the description of the logic system design, and improve the verification efficiency of the large-scale logic system design.

[0090] In some embodiments, the plurality of first pins include a target first pin, the plurality of second pins include a target second pin, and the at least one third pin includes a target third pin. The method further includes: configuring in the connection relationship the target first pin (e.g., Figure 6 pin An) to be connected to the target second pin (e.g., Figure 6 pin Bn) and the target third pin (e.g., Figure 6 pin Bo); or configuring in the connection relationship the target second pin (e.g., Figure 6 pin Bn) to be connected to the target first pin (e.g., Figure 6 pin An) and the target third pin (e.g., Figure 6 pin Am).

[0091] In this way, the user can use Bo to read the value of An or use Am to read the value of Bn. Therefore, by using the interface adapter of the embodiments of the present application, the user can use the third pin to read the value of the first pin or the second pin, so as to better observe the operation of the logic system design without occupying the IO resources of the FPGA.

[0092] By providing an interface adapter (either separately or as part of the hardware simulation tool) to the hardware simulation tool in the hardware simulation system, the connection relationship between the pins can be flexibly adjusted, thereby avoiding reconfiguration, recompilation, and reconnecting caused by connection errors, and improving the verification efficiency of the logic system design.

[0093] The embodiments of the present application also provide an electronic device. The electronic device may be Figure 1 the electronic device 100. The electronic device 100 may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to execute method 800.

[0094] The embodiments of the present application also provide a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores a set of instructions of a computer, and the set of instructions is used to cause the electronic device to execute method 800 when being executed.

[0095] Some embodiments of the present application are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain implementations, multitasking and parallel processing are also possible or may be advantageous.

[0096] Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is only exemplary, and is not intended to imply that the scope of the present application (including the claims) is limited to these examples; under the idea of the present application, the technical features between the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present application as described above, which are not provided in detail for the sake of brevity.

[0097] Although the present application has been described in conjunction with specific embodiments of the present application, many substitutions, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0098] This application is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Accordingly, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application shall be included within the scope of protection of this application.

Claims

1. A method for simulating a logic system design using a hardware simulation tool, wherein a programmable logic device of the hardware simulation tool is connected to a daughter card via an interface adapter, and the interface adapter includes: A plurality of first pins of a programmable logic device for connecting to the hardware emulation tool, a plurality of second pins for connecting to the daughter card, and at least one third pin for reading values of the plurality of first pins or the plurality of second pins; And a memory for storing a connection relationship that configures connections between the plurality of first pins, the plurality of second pins, and the at least one third pin, the method comprising: Determining that a connection error exists between the hardware emulation tool and the daughter card; In response to the connection error, obtaining an updated connection relationship between the plurality of first pins and the plurality of second pins; and Configuring the connections between the plurality of first pins and the plurality of second pins according to the updated connection relationship.

2. The method of claim 1, further comprising: Implementing the logic system design on the programmable logic device according to the description of the logic system design and the configuration file, Wherein, the method further comprises: Modifying the configuration file or the description of the logic system design according to the updated connection relationship.

3. The method according to claim 1, wherein The plurality of first pins include a target first pin, the plurality of second pins include a target second pin, and the at least one third pin includes a target third pin, the method further comprising: Configuring, in the connection relationship, the target first pin to be connected to the target second pin and the target third pin; or Configuring, in the connection relationship, the target second pin to be connected to the target first pin and the target third pin.

4. An electronic device, comprising: A memory for storing a set of instructions; And At least one processor configured to execute the set of instructions to cause the electronic device to perform the method according to any one of claims 1-3.

5. A non-transitory computer-readable storage medium, the non-transitory computer-readable storage medium storing a set of computer instructions that, when executed, cause the computer to perform the method according to any one of claims 1-3.

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