Bit stream verification method and device, equipment, storage medium and program product

Abstract

The invention relates to the technical field of electronic design, and discloses a bit stream verification method and device, equipment, a storage medium and a program product.The bit stream verification method comprises the steps that an execution file corresponding to a target test case is executed, and a bit stream file and a routing file of the target test case are obtained; determining configuration information of the target test case based on the bit stream file and the routing file, and configuring a test file of the target test case based on the configuration information; based on the routing file, configuring an input signal and a reference model corresponding to the target test case; and based on the input signal, respectively testing the test file and the reference model, and determining a bit stream verification result of the target test case. Thus, simulation verification of the bit stream file of the target integrated circuit is deconstructed, simulation verification of the bit stream file is performed on each test unit in the target integrated circuit, simulation verification of the bit stream file is realized through the reference model, simulation of the bit stream file is simplified, simulation efficiency of the bit stream file is further improved, and simulation time is shortened.

Description

Technical Field

[0001] The present invention relates to the field of electronic design technology, and particularly relates to a bitstream verification method, apparatus, device, storage medium, and program product. Background Art

[0002] In the design process of an FPGA (Field Programmable Gate Array), users usually need to define a circuit through a hardware description language, such as VHDL, Verilog, etc., and use a synthesis tool to generate a bitstream file in order to load the design into the FPGA. The bitstream file determines the configuration of the internal resources of the FPGA and directly affects the performance and power consumption of the system. Therefore, it is necessary to verify the correctness of the bitstream file to ensure the correctness of the circuit function. However, since the FPGA contains multiple modules and has a complex internal structure, the simulation of the bitstream file takes a long time and the simulation efficiency is low. Summary of the Invention

[0003] In view of this, the present invention provides a bitstream verification method, apparatus, device, storage medium, and program product to solve the problems of low simulation efficiency and long time consumption of the bitstream file.

[0004] In a first aspect, the present invention provides a bitstream verification method applied to a field programmable gate array circuit. The method includes: Executing an execution file corresponding to a target test case to obtain a bitstream file and a routing file of the target test case; the target test case is a test case corresponding to a target test unit in a target integrated circuit; Determining configuration information of the target test case based on the bitstream file and the routing file, and configuring a test file of the target test case based on the configuration information; Configuring an input signal and a reference model corresponding to the target test case based on the routing file; Testing the test file and the reference model respectively based on the input signal to determine a bitstream verification result of the target test case.

[0005] In an optional implementation manner, determining configuration information of the target test case based on the bitstream file and the routing file includes: Obtaining a first coordinate corresponding to the target test case from the routing file; Converting the first coordinate to obtain a second coordinate; Obtaining configuration information from the bitstream file based on the second coordinate.

[0006] In an optional implementation manner, configuring an input signal and a reference model corresponding to the target test case based on the routing file includes: Search for the routing file to obtain the input signals corresponding to the target test cases; Based on the signal types of the input signals, assign values to the input signals to configure the input signals; Based on the association relationship between the output signals and the input signals in the routing file, construct a reference model.

[0007] In an alternative embodiment, based on the input signals, test the test file and the reference model respectively to determine the bitstream verification result of the target test case, including: Based on the input signals, perform a simulation test on the test file to obtain the first output signal; Input the input signals into the reference model to obtain the second output signal; Compare the first output signal with the second output signal to obtain the bitstream verification result.

[0008] In an alternative embodiment, compare the first output signal with the second output signal to obtain the bitstream verification result, including: If the first output signal is the same as the second output signal, determine that the bitstream verification result is that the bitstream configuration is correct; If the first output signal is different from the second output signal, determine that the bitstream verification result is that the bitstream configuration is incorrect.

[0009] In an alternative embodiment, the method further includes: Split the logic units included in the target integrated circuit to obtain multiple target test units; Write test cases corresponding to the multiple target test units respectively to obtain multiple target test cases and execution files corresponding to the multiple target test cases.

[0010] In a second aspect, the present invention provides a bitstream verification device applied to a field programmable gate array circuit. The device includes: A test case execution module for executing the execution file corresponding to the target test case to obtain the bitstream file and the routing file of the target test case; the target test case is the test case corresponding to the target test unit in the target integrated circuit; A test file configuration module for determining the configuration information of the target test case based on the bitstream file and the routing file, and configuring the test file of the target test case based on the configuration information; A reference model configuration module for configuring the input signals and the reference model corresponding to the target test case based on the routing file; A verification result determination module for testing the test file and the reference model respectively based on the input signals to determine the bitstream verification result of the target test case.

[0011] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the bitstream verification method according to the first aspect or any corresponding embodiment thereof.

[0012] In a fourth aspect, the present invention provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to cause a computer to perform the bitstream verification method according to the first aspect or any corresponding embodiment thereof.

[0013] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, and the computer instructions are used to cause a computer to perform the bitstream verification method according to the first aspect or any corresponding embodiment thereof.

[0014] The bitstream verification method provided by the present invention verifies the bitstream files of each target test unit in a target integrated circuit by executing test cases corresponding to the target test units in the target integrated circuit, thereby deconstructing the simulation verification of the bitstream file of the target integrated circuit, and performing the simulation verification of the bitstream files of each test unit in the target integrated circuit respectively, so as to improve the simulation efficiency of the bitstream file and shorten the simulation time. At the same time, by configuring the test file, input signal and reference model corresponding to the target test case, the simulation verification of the bitstream file is realized, thereby simplifying the simulation of the bitstream file and further improving the simulation efficiency of the bitstream file and shortening the simulation time. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1 is a flowchart of the bitstream verification method according to an embodiment of the present invention; Figure 2 is a flowchart of another bitstream verification method according to an embodiment of the present invention; Figure 3 is a flowchart of yet another bitstream verification method according to an embodiment of the present invention; Figure 4 is a flowchart of still another bitstream verification method according to an embodiment of the present invention; Figure 5 is a structural block diagram of the bitstream verification device according to an embodiment of the present invention; Figure 6 It is a schematic diagram of the hardware structure of the computer device according to an embodiment of the present invention. Detailed implementation manners

[0017] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0018] In the design process of an FPGA (Field Programmable Gate Array), a user usually needs to define a circuit through a hardware description language, such as VHDL, Verilog, etc., and use a synthesis tool to generate a bitstream file so as to load the design into the FPGA. The bitstream file determines the configuration of the internal resources of the FPGA and directly affects the performance and power consumption of the system. Therefore, it is necessary to verify the correctness of the bitstream file to ensure the correctness of the circuit function. However, since the FPGA internally contains multiple modules and has a complex internal structure, the simulation of the bitstream file takes a long time and the simulation efficiency is low.

[0019] Based on this, an embodiment of the present invention provides a bitstream verification method. The method executes an execution file corresponding to a target test case to obtain a bitstream file and a routing file of the target test case; the target test case is a test case corresponding to a target test unit in a target integrated circuit; based on the bitstream file and the routing file, configuration information of the target test case is determined, and based on the configuration information, a test file of the target test case is configured; based on the routing file, an input signal and a reference model corresponding to the target test case are configured; based on the input signal, the test file and the reference model are respectively tested to determine a bitstream verification result of the target test case. In this way, by executing the test cases corresponding to the target test units in the target integrated circuit, the bitstream files of each target test unit in the target integrated circuit are respectively verified, so as to deconstruct the simulation verification of the bitstream file of the target integrated circuit, and the bitstream files of each test unit in the target integrated circuit are respectively subjected to simulation verification, thereby improving the simulation efficiency of the bitstream file and shortening the simulation time; at the same time, by configuring the test file, input signal and reference model corresponding to the target test case, the simulation verification of the bitstream file is realized, thereby simplifying the simulation of the bitstream file and further improving the simulation efficiency of the bitstream file and shortening the simulation time.

[0020] According to an embodiment of the present invention, there is provided an embodiment of a bitstream verification method. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0021] In this embodiment, a bitstream verification method is provided, which can be used in a field-programmable gate array circuit. Figure 1 It is a flowchart of the bitstream verification method according to an embodiment of the present invention, as Figure 1 shown, this process includes the following steps: Step S101, execute the execution file corresponding to the target test case to obtain the bitstream file and routing file of the target test case.

[0022] In an embodiment of the present invention, the target test case is a test case corresponding to a target test unit in the target integrated circuit; the target integrated circuit is an integrated circuit that needs to perform simulation verification on the bitstream file. All the logic units included in the target integrated circuit are target test units. That is to say, the simulation of the bitstream file of the target integrated circuit is split according to the logic units it contains, and the bitstream file of the target integrated circuit is simulated by simulating the bitstream files of the logic units it contains.

[0023] In an embodiment of the present invention, the execution file corresponding to the target test case is used to execute the processes related to design and configuration in the EDA software, such as synthesis, mapping, place, route, bitgen, etc., to obtain the bitstream file, routing file, and wiring file corresponding to the target test case. Among them, the bitstream file contains all the configuration information of the target integrated circuit, such as logic unit configuration, wiring resources, and I / O configuration, etc.; the routing file and wiring file contain the specific wiring information between the logic units in the target integrated circuit.

[0024] In an alternative embodiment, in order to implement the simulation of the bitstream file of the target integrated circuit, the present invention splits the logic units included in the target integrated circuit to obtain multiple target test units, then writes the test cases corresponding to the multiple target test units respectively to obtain multiple target test cases and the execution files corresponding to the multiple target test cases. Then, execute the execution files corresponding to the obtained multiple target test cases respectively to perform simulation verification on the multiple target test cases respectively, obtain the bitstream verification results of the multiple target test cases, and obtain the bitstream verification result of the target integrated circuit based on the bitstream verification results of the multiple target test cases.

[0025] Step S102: Based on the bitstream file and the routing file, determine the configuration information of the target test case, and configure the test file of the target test case based on the configuration information.

[0026] In the embodiment of the present invention, the configuration information of the target test case is located based on the bitstream file and the routing file, and the configuration information of the target test case is extracted. The test file of the target test case is configured based on the extracted configuration information, so as to perform a simulation test on the bitstream file of the target test case according to the test file of the target test case.

[0027] Step S103: Based on the routing file, configure the input signal and the reference model corresponding to the target test case.

[0028] In the embodiment of the present invention, the routing file is searched to extract the input signal and the output signal corresponding to the target test case, and a reference model is constructed according to the input signal and the output signal. The reference model is used as a comparison reference object for the simulation verification of the target test case, and the output of the reference model is used as the correct output of the simulation test of the target test case, so as to verify the correctness of the result of the simulation test of the target test case.

[0029] Step S104: Based on the input signal, test the test file and the reference model respectively to determine the bitstream verification result of the target test case.

[0030] In the embodiment of the present invention, the configured input signal is respectively input to the test file and the reference model, so as to perform simulation tests on the test file and the reference model respectively, obtain the result of the actual simulation output of the target test case and the simulation result for reference comparison, and compare the two to determine the bitstream verification result of the target test case.

[0031] In an optional implementation manner, simulation tests are respectively performed on the target test cases corresponding to each target test unit in the target integrated circuit to obtain the bitstream verification results of each target test unit, and the bitstream verification result of the target integrated circuit is determined based on the bitstream verification results of each target test unit.

[0032] The bitstream verification method provided by the embodiment of the present invention verifies the bitstream files of each target test unit in the target integrated circuit by executing the test cases corresponding to the target test units in the target integrated circuit, so as to deconstruct the simulation verification of the bitstream file of the target integrated circuit, and perform simulation verification of the bitstream files on each test unit in the target integrated circuit respectively, thereby improving the simulation efficiency of the bitstream file and shortening the simulation time. At the same time, by configuring the test file, input signal and reference model corresponding to the target test case, the simulation verification of the bitstream file is realized, thereby simplifying the simulation of the bitstream file and further improving the simulation efficiency of the bitstream file and shortening the simulation time.

[0033] In this embodiment, a bitstream verification method is provided, which can be used in a field programmable gate array circuit. Figure 2 It is a flowchart of another bitstream verification method according to an embodiment of the present invention, as Figure 2 shown, and this process includes the following steps: Step S201, execute the execution file corresponding to the target test case to obtain the bitstream file and the routing file of the target test case. For details, please refer to Figure 1 Step S101 of the embodiment shown, which will not be elaborated here.

[0034] Step S202, based on the bitstream file and the routing file, determine the configuration information of the target test case, and configure the test file of the target test case based on the configuration information.

[0035] Specifically, step S202 includes: Step S2021, obtain the first coordinates corresponding to the target test case from the routing file.

[0036] In the embodiment of the present invention, search the routing file to query the coordinates corresponding to the target test unit, which are the first coordinates, and extract the first coordinates to further determine the coordinates of the configuration information of the target test unit in the bitstream file.

[0037] Step S2022, convert the first coordinates to obtain the second coordinates.

[0038] In the embodiment of the present invention, after obtaining the first coordinates, convert the first coordinates according to a preset coordinate conversion algorithm to obtain the coordinates of the configuration information of the target test unit in the bitstream file, that is, the second coordinates.

[0039] Step S2023, based on the second coordinates, obtain the configuration information from the bitstream file.

[0040] In the embodiment of the present invention, search and extract the relevant information at the second coordinates in the bitstream file to obtain the configuration information of the target test unit.

[0041] Step S203, based on the routing file, configure the input signal and the reference model corresponding to the target test case. For details, please refer to Figure 1 Step S103 of the embodiment shown, which will not be elaborated here.

[0042] Step S204, based on the input signal, test the test file and the reference model respectively to determine the bitstream verification result of the target test case. For details, please refer to Figure 1 Step S104 of the embodiment shown, which will not be elaborated here.

[0043] In this embodiment, a bitstream verification method is provided, which can be used in a field programmable gate array circuit. Figure 3 It is a flowchart of another bitstream verification method according to an embodiment of the present invention, as Figure 3 shown. The process includes the following steps: Step S301, execute the execution file corresponding to the target test case to obtain the bitstream file and routing file of the target test case. For details, please refer to Figure 1 step S101 of the embodiment shown herein, which will not be elaborated herein.

[0044] Step S302, based on the bitstream file and routing file, determine the configuration information of the target test case, and configure the test file of the target test case based on the configuration information. For details, please refer to Figure 1 step S102 of the embodiment shown herein, which will not be elaborated herein.

[0045] Step S303, configure the input signal and reference model corresponding to the target test case based on the routing file.

[0046] Specifically, step S303 includes: Step S3031, search the routing file to obtain the input signal corresponding to the target test case.

[0047] In the embodiment of the present invention, the routing file is searched to determine the target test case, that is, the signal name of the input signal corresponding to the target test unit, so as to determine the input signal corresponding to the target test case.

[0048] Step S3032, assign values to the input signal based on the signal type of the input signal to configure the input signal.

[0049] In the embodiment of the present invention, according to the different signal types of the input signal, the value assignment methods for the input signal are also different. According to the signal type of the input signal, determine the value assignment method for the input signal, and assign values to the input signal according to this value assignment method, so as to complete the configuration of the input signal.

[0050] In an alternative embodiment, when assigning values and configuring the input signal, considering some specific conditions or constraints that the input signal needs to meet, the test boundary conditions and limit signal values of the input signal can also be set, and the corresponding signal values can be configured according to different functional modes, so that the configured input signal can meet the simulation verification of all functional modes of the target test unit. At the same time, a random assignment method can be used to generate multiple groups of input signals to cover multiple test scenarios.

[0051] Step S3033, construct a reference model based on the association relationship between the output signal and the input signal in the routing file.

[0052] In an embodiment of the present invention, the routing file contains the logical function of its corresponding target test unit, and the logical function characterizes the operations through which the input signal passes to obtain the output signal after entering the target test unit. Based on the logical function of the target test unit in the routing file, the correlation relationship between the output signal and the input signal is obtained, and a reference model is constructed based on this correlation relationship; that is, the input of the reference model is consistent with the input signal of the target test unit, and the output of the reference model is consistent with the output signal of the target test unit. Thus, the output of the reference model can fully represent the output of the target test unit, making the simulation verification of the bitstream file for the target test unit using the output of the reference model as a reference more reliable and accurate.

[0053] Step S304: Based on the input signal, test the test file and the reference model respectively to determine the bitstream verification result of the target test case. For details, please refer to Figure 1 Step S104 of the embodiment shown, which will not be elaborated here.

[0054] In this embodiment, a bitstream verification method is provided, which can be used in a field programmable gate array circuit. Figure 4 It is a flowchart of another bitstream verification method according to an embodiment of the present invention. As Figure 4 shown, this process includes the following steps: Step S401: Execute the execution file corresponding to the target test case to obtain the bitstream file and the routing file of the target test case. For details, please refer to Figure 1 Step S101 of the embodiment shown, which will not be elaborated here.

[0055] Step S402: Based on the bitstream file and the routing file, determine the configuration information of the target test case, and configure the test file of the target test case based on the configuration information. For details, please refer to Figure 1 Step S102 of the embodiment shown, which will not be elaborated here.

[0056] Step S403: Based on the routing file, configure the input signal and the reference model corresponding to the target test case. For details, please refer to Figure 1 Step S103 of the embodiment shown, which will not be elaborated here.

[0057] Step S404: Based on the input signal, test the test file and the reference model respectively to determine the bitstream verification result of the target test case.

[0058] Specifically, step S404 includes: Step S4041: Based on the input signal, perform a simulation test on the test file to obtain a first output signal.

[0059] In an embodiment of the present invention, the configuration information of a test file is loaded in the top-level file of the simulation platform of the EDA software, and the test file is simulated and tested based on the input signal, so as to obtain a first output signal.

[0060] Step S4042: Input the input signal into the reference model to obtain a second output signal.

[0061] In an embodiment of the present invention, the input signal is input into the reference model to obtain the output of the reference model, which is the second output signal.

[0062] Step S4043: Compare the first output signal with the second output signal to obtain a bitstream verification result.

[0063] In an embodiment of the present invention, if the first output signal is consistent with the second output signal, it is determined that the bitstream verification result is that the bitstream configuration is correct; if the first output signal is inconsistent with the second output signal, it is determined that the bitstream verification result is that the bitstream configuration is incorrect.

[0064] In an alternative embodiment, if the bitstream verification result of the target test unit in the target integrated circuit is that the bitstream configuration is incorrect, it is determined that the bitstream simulation of the target integrated circuit fails; at this time, the target test unit with an incorrect bitstream configuration is the source of the problem of the failed bitstream simulation of the target integrated circuit. Therefore, the target test unit with an incorrect bitstream verification result can be problem-located to quickly determine the reason for the failed bitstream simulation of the target integrated circuit. If the bitstream verification results of all target test units in the target integrated circuit are that the bitstream configuration is correct, it is determined that the bitstream simulation of the target integrated circuit passes.

[0065] In this embodiment, a bitstream verification device is further provided. This device is used to implement the above embodiments and preferred embodiments, and those that have been described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that can achieve a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware is also possible and contemplated.

[0066] This embodiment provides a bitstream verification device, which is applied to a field programmable gate array circuit, as Figure 5 shown, including: A test case execution module 501, configured to execute an execution file corresponding to a target test case to obtain a bitstream file and a routing file of the target test case; the target test case is a test case corresponding to a target test unit in the target integrated circuit; A test file configuration module 502, configured to determine the configuration information of the target test case based on the bitstream file and the routing file, and configure the test file of the target test case based on the configuration information; The reference model configuration module 503 is used to configure the input signal and the reference model corresponding to the target test case based on the routing file; The verification result determination module 504 is used to test the test file and the reference model respectively based on the input signal, and determine the bitstream verification result of the target test case.

[0067] In an alternative embodiment, the test file configuration module 502 includes: The first coordinate acquisition unit is used to acquire the first coordinate corresponding to the target test case from the routing file; The coordinate conversion unit is used to convert the first coordinate to obtain the second coordinate; The configuration information acquisition unit is used to acquire the configuration information from the bitstream file based on the second coordinate.

[0068] In an alternative embodiment, the reference model configuration module 503 includes: The input signal acquisition unit is used to search the routing file to obtain the input signal corresponding to the target test case; The input signal configuration unit is used to assign values to the input signal based on the signal type of the input signal to configure the input signal; The reference module construction unit is used to construct a reference model based on the association relationship between the output signal and the input signal in the routing file.

[0069] In an alternative embodiment, the verification result determination module 504 includes: The test file simulation unit is used to perform a simulation test on the test file based on the input signal to obtain the first output signal; The reference model simulation unit is used to input the input signal into the reference model to obtain the second output signal; The output signal comparison unit is used to compare the first output signal with the second output signal to obtain the bitstream verification result.

[0070] In an alternative embodiment, the output signal comparison unit is used to: If the first output signal is consistent with the second output signal, it is determined that the bitstream verification result is that the bitstream configuration is correct; If the first output signal is inconsistent with the second output signal, it is determined that the bitstream verification result is that the bitstream configuration is incorrect.

[0071] In an alternative embodiment, the device further includes: The logic unit splitting unit is used to split the logic units included in the target integrated circuit to obtain a plurality of target test units; A test case acquisition unit is configured to respectively write test cases corresponding to a plurality of target test units to obtain a plurality of target test cases and execution files corresponding to the plurality of target test cases.

[0072] The further function descriptions of the above-mentioned respective modules and units are the same as those in the corresponding embodiments above, and will not be elaborated here.

[0073] The bitstream verification device in this embodiment is presented in the form of functional units. Here, the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0074] An embodiment of the present invention further provides a computer device having the above-mentioned Figure 5 shown bitstream verification device.

[0075] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of a computer device provided by an optional embodiment of the present invention. As Figure 6 shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including a high-speed interface and a low-speed interface. Each component communicates with each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a set of blade servers, or a multi-processor system). Figure 6 Taking one processor 10 as an example in

[0076] The processor 10 can be a central processing unit, a network processor, or a combination thereof. Among them, the processor 10 can further include a hardware chip. The above-mentioned hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The above-mentioned programmable logic device can be a complex programmable logic device, a field programmable gate array, a general array logic, or any combination thereof.

[0077] Among them, the memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiments.

[0078] The memory 20 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the computer device and the like. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 may optionally include a memory remotely provided with respect to the processor 10, and these remote memories may be connected to the computer device through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0079] The memory 20 may include a volatile memory, for example, a random access memory; the memory may also include a non-volatile memory, for example, a flash memory, a hard disk, or a solid-state drive; the memory 20 may further include a combination of the above types of memories.

[0080] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or communication networks.

[0081] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code originally stored in a remote storage medium or a non-temporary machine-readable storage medium and to be downloaded through a network and stored in a local storage medium, so that the method described herein can be stored in such software processed on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium may also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiment is implemented.

[0082] A part of the present invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can call or provide the methods and / or technical solutions according to the present invention through the operations of the computer. Those skilled in the art should understand that the forms of existence of computer program instructions in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Herein, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible by the computer.

[0083] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the present invention.

Claims

1. A bitstream verification method, characterized in that, Applied to a field programmable gate array circuit, the method includes: Executing an execution file corresponding to a target test case to obtain a bitstream file and a routing file of the target test case; the target test case is a test case corresponding to a target test unit in a target integrated circuit; Based on the bitstream file and the routing file, determining configuration information of the target test case, and configuring a test file of the target test case based on the configuration information; Based on the routing file, configuring an input signal and a reference model corresponding to the target test case; Based on the input signal, testing the test file and the reference model respectively to determine a bitstream verification result of the target test case.

2. The method according to claim 1, wherein The determining the configuration information of the target test case based on the bitstream file and the routing file includes: Obtaining a first coordinate corresponding to the target test case from the routing file; Converting the first coordinate to obtain a second coordinate; Based on the second coordinate, obtaining the configuration information from the bitstream file.

3. The method according to claim 1, characterized in that, The configuring the input signal and the reference model corresponding to the target test case based on the routing file includes: Searching the routing file to obtain an input signal corresponding to the target test case; Based on the signal type of the input signal, assigning a value to the input signal to configure the input signal; Based on the association relationship between an output signal and the input signal in the routing file, constructing the reference model.

4. The method according to claim 1, characterized in that, The testing the test file and the reference model respectively based on the input signal to determine the bitstream verification result of the target test case includes: Based on the input signal, performing a simulation test on the test file to obtain a first output signal; Inputting the input signal into the reference model to obtain a second output signal; Comparing the first output signal with the second output signal to obtain the bitstream verification result.

5. The method according to claim 4, wherein The comparing the first output signal with the second output signal to obtain the bitstream verification result includes: If the first output signal is consistent with the second output signal, determining that the bitstream verification result is that the bitstream configuration is correct; If the first output signal is inconsistent with the second output signal, determining that the bitstream verification result is that the bitstream configuration is incorrect.

6. The method according to claim 1, wherein The method further includes: Splitting logic units included in a target integrated circuit to obtain a plurality of target test units; Writing test cases corresponding to the plurality of target test units respectively to obtain the plurality of target test cases and execution files corresponding to the plurality of target test cases.

7. A bitstream verification device, characterized in that Applied to a field programmable gate array circuit, the device includes: A test case execution module, configured to execute an execution file corresponding to a target test case to obtain a bitstream file and a routing file of the target test case; the target test case is a test case corresponding to a target test unit in a target integrated circuit; A test file configuration module, configured to determine configuration information of the target test case based on the bitstream file and the routing file, and configure a test file of the target test case based on the configuration information; A reference model configuration module, configured to configure the input signals and the reference model corresponding to the target test case based on the routing file; A verification result determination module, configured to perform tests on the test file and the reference model respectively based on the input signals, and determine the bitstream verification result of the target test case.

8. A computer device, characterized in that, Comprising: A memory and a processor, the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to execute the bitstream verification method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, Computer instructions are stored on the computer-readable storage medium, and the computer instructions are used to cause a computer to execute the bitstream verification method according to any one of claims 1 to 6.

10. A computer program product, characterized in that, Comprising computer instructions, the computer instructions are used to cause a computer to execute the bitstream verification method according to any one of claims 1 to 6.

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