Pcb package design method, apparatus, terminal, and medium

Abstract

The application discloses a pcb package design method and device, a terminal and a medium, and relates to the technical field of data processing. The method comprises the following steps: obtaining historical characteristic data corresponding to preprocessing; generating a preset design scheme model, and obtaining a first package design scheme according to the historical characteristic data; optimizing the first package design scheme based on a preset package design target, and obtaining a second package design scheme; updating the preset design scheme model according to the second package design scheme and the historical characteristic data, and obtaining an updated preset design scheme model; and obtaining a target package design scheme according to the historical characteristic data by using the updated preset design scheme model. The application aims to significantly improve the accuracy and reliability of package design through a data-driven intelligent design process, so as to adapt to different package specifications of customers.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and particularly relates to a pcb package design method and device, a terminal and a medium. BACKGROUND

[0002] The package in the pcb is a physical interface between electronic components and circuit boards. The core functions of the package include: providing mechanical fixation and dust and moisture protection for components (such as BGA packaging fixed by bottom solder balls); realizing the conduction of component pins and PCB wires through pads (for example, the pinless design of QFN packaging is connected through side pads); the packaging structure directly affects the heat dissipation efficiency (such as the metal heat sink of TO-220 packaging can quickly dissipate the heat of power devices); reducing signal interference through impedance control (such as the micro-hole wiring in HDI technology reduces high-speed signal attenuation).

[0003] In the current mainstream package design, BGA packaging has become the mainstream, and the solder ball pitch has been reduced from 1.0mm to 0.4mm to meet the needs of mobile phones and wearable devices; the chip-scale package (CSP) thickness is less than 0.3mm, which is suitable for miniature sensors and other scenarios; Altium Designer, Eagle and other tools integrate package library management and support IPC-7351 standard pad automatic generation; modular design library covers 3000+ package types such as SOP and QFP.

[0004] However, the existing package design method still has the following deficiencies: although Altium Designer provides package graphic drawing function, it needs to manually adjust the pad pitch; it depends on later physical testing (such as X-ray detection of BGA virtual welding), which cannot completely predict manufacturing defects in the early simulation; some package details still rely on experienced engineers to manually think and intervene and manually optimize, which may cause human negligence, and thus the package design scheme does not meet the actual application requirements or does not meet the relevant index rules. SUMMARY

[0005] The main purpose of the present application is to provide a pcb package design method, device, terminal and medium, which significantly improves the accuracy and reliability of the package design through a data-driven intelligent design process.

[0006] To achieve the above purpose, the present application provides a pcb package design method, which comprises:

[0007] Obtaining pre-processed historical feature data, wherein the historical feature data is used to represent the historical design condition and historical working state of the package;

[0008] A first packaging body design scheme is obtained according to the historical characteristic data through the preset design scheme generation model;

[0009] The first packaging body design scheme is optimized based on a preset packaging body design target to obtain a second packaging body design scheme;

[0010] The preset design scheme generation model is updated according to the second packaging body design scheme and the historical characteristic data to obtain an updated preset design scheme generation model;

[0011] A target packaging body design scheme is obtained according to the historical characteristic data through the updated preset design scheme generation model.

[0012] Specifically, the historical characteristic data corresponding to the preprocessing is obtained, including:

[0013] A historical design parameter is obtained, wherein the historical design parameter is used to represent a historical design condition of a packaging body;

[0014] Performance data corresponding to the historical design parameter is obtained through a preset simulation tool according to the historical design parameter;

[0015] The historical design parameter and the performance data are merged to obtain merged characteristic data;

[0016] The merged characteristic data is subjected to feature standardization processing to obtain the historical characteristic data corresponding to the preprocessing.

[0017] Specifically, the preset design scheme generation model includes an input layer, a gated recurrent unit layer, a fully connected network layer, and an output layer;

[0018] The first packaging body design scheme is obtained according to the historical characteristic data through the preset design scheme generation model, including:

[0019] A historical characteristic vector is obtained through the input layer according to the historical characteristic data;

[0020] A dynamic thermal resistance feature vector is obtained through the gated recurrent unit layer according to the historical characteristic vector;

[0021] A spatial feature vector is obtained through the fully connected network layer according to the historical characteristic vector;

[0022] The first packaging body design scheme is obtained through the output layer according to the dynamic thermal resistance feature vector and the spatial feature vector.

[0023] Specifically, the output layer includes a first fully connected layer and a second fully connected layer, an activation function of the first fully connected layer is a ReLU function, and an activation function of the second fully connected layer is a linear activation function, and the first package design scheme includes a predicted key indicator vector, where the predicted key indicator vector is used to represent the design performance of the package.

[0024] The first package design scheme is obtained through the output layer according to the dynamic thermal resistance feature vector and the spatial feature vector.

[0025] A first intermediate vector is obtained through the first fully connected layer according to the dynamic thermal resistance feature vector and the spatial feature vector.

[0026] The predicted key indicator vector is obtained through the second fully connected layer according to the first intermediate vector.

[0027] Specifically, the output layer includes an encoder layer and a decoder layer, and the first package design scheme includes a predicted pad layout scheme corresponding to the package.

[0028] The first package design scheme is obtained through the output layer according to the dynamic thermal resistance feature vector and the spatial feature vector.

[0029] A first latent space vector and a second latent space vector are obtained through the encoding layer according to the dynamic thermal resistance feature vector and the spatial feature vector, where the first latent space vector is used to represent a mean value corresponding to the latent space, and the second latent space vector is used to represent a standard deviation corresponding to the latent space.

[0030] A sampling vector is sampled from a Gaussian distribution in the latent space according to the first latent space vector and the second latent space vector.

[0031] The predicted pad layout scheme is obtained through the decoding layer according to the sampling vector.

[0032] Specifically, the first package design scheme is optimized based on a preset package design target to obtain a second package design scheme, including:

[0033] A target function and a constraint condition corresponding to the target function are constructed by a preset simulation tool based on the preset package design target and the first package design scheme, as shown in the following formula:

[0034]

[0035]

[0036]

[0037]

[0038] wherein, represents the highest working temperature of the package, represents the signal path impedance fluctuation corresponding to the package, represents the interface stress between the chip and the substrate, represents the weight corresponding to the highest working temperature of the package, represents the weight corresponding to the signal path impedance fluctuation, represents the weight corresponding to the interface stress, represents the packaging area corresponding to the package, represents the manufacturing cost corresponding to the package, represents the maximum packaging area corresponding to the package, represents the maximum manufacturing cost corresponding to the package, represents the optimization target of the objective function;

[0039] Based on the objective function and the constraint condition, the second package design scheme is screened from the first package design scheme.

[0040] Specifically, the updating of the preset design scheme generation model according to the second package design scheme and the historical characteristic data to obtain an updated preset design scheme generation model comprises:

[0041] The second package design scheme and the historical characteristic data are subjected to feature normalization processing to obtain training data;

[0042] Through the input layer, a training feature vector is obtained according to the training data;

[0043] Through the gated recurrent unit layer, a training dynamic thermal resistance feature vector is obtained according to the training feature vector;

[0044] Through the fully connected network layer, a training spatial feature vector is obtained according to the training feature vector;

[0045] Through the encoding layer, a first training latent space vector and a second training latent space vector are obtained according to the training dynamic thermal resistance feature vector and the training spatial feature vector, wherein the first training latent space vector is used to represent the training mean value corresponding to the latent space, and the second training latent space vector is used to represent the training standard deviation corresponding to the latent space;

[0046] Based on the training mean and the training standard deviation, a training relative entropy value between a spatial distribution of the latent space and a standard normal distribution is calculated;

[0047] Through a back propagation algorithm, model weights and model biases in the preset design scheme generation model are adjusted according to the training relative entropy value, to obtain an adjusted preset design scheme generation model.

[0048] Based on the training data, the adjusted preset design scheme generation model is iteratively trained until the training relative entropy value is less than a preset threshold, to obtain the updated preset design scheme generation model.

[0049] To achieve the above object, the present application further provides a pcb package design device, the device comprising:

[0050] A first unit is configured to obtain preprocessed historical feature data, wherein the historical feature data is used to represent historical design conditions and historical working states of a package.

[0051] A second unit is configured to obtain a first package design scheme from a preset design scheme generation model according to the historical feature data.

[0052] A third unit is configured to optimize the first package design scheme based on a preset package design target, to obtain a second package design scheme.

[0053] A fourth unit is configured to update the preset design scheme generation model according to the second package design scheme and the historical feature data, to obtain an updated preset design scheme generation model.

[0054] A fifth unit is configured to obtain a target package design scheme from the updated preset design scheme generation model according to the historical feature data.

[0055] To achieve the above object, the present application further provides a terminal comprising a memory storing a plurality of instructions; and a processor loading the instructions from the memory to execute steps in any of the methods provided by the present application.

[0056] To achieve the above object, the present application further provides a medium storing a plurality of instructions, which are suitable for being loaded by a processor to execute steps in any of the methods provided by the present application.

[0057] The pcb package design method, device, terminal and medium provided by the present application can first acquire historical feature data corresponding to preprocessing, wherein the historical feature data is used to represent the historical design condition and historical working state of the package; then, a preset design scheme generation model is used to obtain a first package design scheme according to the historical feature data; then, the first package design scheme is optimized based on a preset package design target to obtain a second package design scheme; then, the preset design scheme generation model is updated according to the second package design scheme and the historical feature data to obtain an updated preset design scheme generation model; finally, a more reliable target package design scheme is obtained according to the historical feature data by using the updated preset design scheme generation model, so as to better meet the market demand for the diversified specifications of the package. BRIEF DESCRIPTION OF DRAWINGS

[0058] Figure 1 The flowchart of the method provided by the embodiment of the present application is shown in the figure.

[0059] Figure 2 The structure diagram of the device provided by the embodiment of the present application is shown in the figure.

[0060] Figure 3 The structure diagram of the terminal provided by the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0061] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0062] Since the existing package design means still has the following deficiencies: although Altium Designer provides package graphic drawing function, the pad spacing needs to be adjusted manually; it depends on later physical test (such as X-ray detection of BGA virtual welding) and cannot completely predict manufacturing defects in early simulation; the setting of some package details still depends on the manual thinking intervention and manual optimization of experienced engineers, which may cause human negligence and lead to that the package design scheme does not meet the actual application requirements or does not meet the relevant index rules.

[0063] Therefore, the pcb package design method, device, terminal and medium provided by the embodiments of the present application are used to solve the actual technical problems.

[0064] In some embodiments, the device can be integrated in an electronic device, which can be a terminal, a server or the like.

[0065] In some embodiments, the server can also be implemented in the form of a terminal.

[0066] The server can be a stand-alone physical server, a server cluster or a distributed system composed of multiple physical servers, a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and basic cloud computing services such as big data and artificial intelligence platforms.

[0067] The terminal can be a smart phone, a tablet computer, a notebook computer, a desktop computer, a smart speaker, a smart watch, and the like, but is not limited thereto. The terminal and the server can be directly or indirectly connected through wired or wireless communication, which is not limited in the present application.

[0068] The following will be described in detail. It should be noted that the serial numbers of the following embodiments do not limit the preferred order of the embodiments.

[0069] The present application provides a pcb package design method, such as Figure 1 , for the packaging of chips, the specific process of the method can be as follows:

[0070] S110, obtaining historical feature data corresponding to preprocessing, wherein the historical feature data is used to represent the historical design condition and the historical working state of the package.

[0071] In some embodiments, the historical feature data corresponding to preprocessing is obtained, including the step contents of S111 to S114 as follows:

[0072] S111, obtaining historical design parameters, wherein the historical design parameters are used to represent the historical design condition of the package.

[0073] In some embodiments, the historical design parameters can be derived from an EDA tool (such as Cadence Allegro), and the historical parameters can include:

[0074] Pad layout (coordinates, size, spacing);

[0075] Material properties (substrate dielectric constant, copper layer thermal conductivity).

[0076] S112, obtaining performance data corresponding to the historical design parameters by a preset simulation tool according to the historical design parameters.

[0077] In some embodiments, the historical design parameters can be imported into the preset simulation tool to obtain performance data corresponding to the historical design parameters. For example, the performance data shown below can be obtained through a preset simulation tool (such as ANSYS Icepak, HFSS):

[0078] thermal field distribution (temperature gradient, hot spot position);

[0079] electrical performance parameters (signal delay, impedance discontinuity point).

[0080] S113, merging the historical design parameters and the performance data to obtain merged feature data.

[0081] S114, performing feature standardization processing on the merged feature data to obtain historical feature data corresponding to the preprocessing.

[0082] In some embodiments, correlation analysis (Pearson coefficient) and principal component analysis (PCA) can be used to eliminate redundant features (such as the pin shape parameter in the historical design parameters of the package body which is weakly related to temperature). Then, the merged feature data is normalized to adapt to parameters with large dimensional differences (such as dielectric layer thickness: 0.1mm~1mm, pin density: 10 pins / cm²~100 pins / cm²), and parameters exceeding the process range (such as dielectric layer thickness <0.05mm) are truncated to the allowed interval.

[0083] S120, obtaining a first package design scheme according to the historical feature data through a preset design scheme generation model.

[0084] In some embodiments, the preset design scheme generation model includes an input layer, a gated recurrent unit layer, a fully connected network layer, and an output layer.

[0085] Specifically, the preset design scheme generation model obtains a first package design scheme according to the historical feature data, which includes the following steps of S121 to S124:

[0086] S121, obtaining a historical feature vector according to the historical feature data through the input layer.

[0087] In some embodiments, the historical feature data can include the following contents:

[0088] package parameters: length, width, height (mm), number of pins, substrate material (one-hot encoding), copper pillar thickness (mm);

[0089] Environmental conditions: power consumption (W), operating temperature (℃), input signal frequency (GHz).

[0090] The historical feature data is basic description information of the package design, which is used to provide original data for subsequent network layers.

[0091] S122, obtaining a dynamic thermal resistance feature vector through the gating recurrent unit layer according to the historical feature vector.

[0092] In some embodiments, the gating recurrent unit layer can be a gating recurrent unit (GRU) based network structure, and the gating recurrent unit layer can include three layers of GRU, i.e., a first layer of GRU, a second layer of GRU, and a third layer of GRU.

[0093] Specifically, the input corresponding to the first layer of GRU comes from the historical feature vector, which can include time sequence related information in the package parameters and environmental conditions, such as dynamic thermal load and other parameters changing with time. The output corresponding to the first layer of GRU can be a time sequence feature representation processed by the first layer of GRU, and the output corresponding to the first layer of GRU captures the short-term dependence relationship in the input data and transmits it to the second layer of GRU.

[0094] It should be noted that the input corresponding to the second layer of GRU is the output corresponding to the first layer of GRU, and the time sequence feature further refined by the second layer of GRU can capture a longer-term dependence relationship, and the output corresponding to the second layer of GRU is obtained, and the output corresponding to the second layer of GRU is transmitted to the third layer of GRU.

[0095] It should be noted that the input corresponding to the third layer of GRU is the output corresponding to the second layer of GRU, and the more comprehensive and abstract time sequence feature representation obtained by processing the third layer of GRU is the dynamic thermal resistance feature vector.

[0096] S123, obtaining a spatial feature vector through the fully connected network layer according to the historical feature vector.

[0097] In some embodiments, the fully connected network layer can be a network structure including multiple layers of fully connected layers.

[0098] Specifically, the fully connected network layer receives spatial feature related information in the package parameters and environmental conditions from the historical feature vector, such as pad layout topology, and performs multi-step extraction on the input spatial features to obtain a spatial feature vector that can represent complex spatial relationships.

[0099] S124, obtaining the first package design scheme according to the dynamic thermal resistance feature vector and the space feature vector through the output layer.

[0100] In some embodiments, the output layer comprises a first fully connected layer and a second fully connected layer, the activation function of the first fully connected layer is a ReLU function, the activation function of the second fully connected layer is a linear activation function, and the first package design scheme comprises a predicted key indicator vector, wherein the predicted key indicator vector is used to represent the design performance of the package.

[0101] Specifically, the obtaining the first package design scheme according to the dynamic thermal resistance feature vector and the space feature vector through the output layer comprises the following steps of S1241a-S1242a as shown below:

[0102] S1241a, obtaining a first intermediate vector according to the dynamic thermal resistance feature vector and the space feature vector through the first fully connected layer.

[0103] S1242a, obtaining the predicted key indicator vector according to the first intermediate vector through the second fully connected layer.

[0104] It should be noted that, assuming that the dimension of the combined representation vector composed of the dynamic thermal resistance feature vector and the space feature vector is n, the combined representation vector is input to the first fully connected layer to obtain a first intermediate vector with a dimension of m, wherein m is usually less than n, which is used for further compression and extraction of features.

[0105] It should be noted that the first intermediate vector with a dimension of m is input to the second fully connected layer to obtain a predicted key indicator vector with a dimension of k, wherein k is the number of key indicators to be predicted, such as maximum temperature, signal crosstalk value, etc.

[0106] In some embodiments, the output layer can further comprise an encoder layer and a decoder layer, and the first package design scheme comprises a predicted pad layout scheme corresponding to the package.

[0107] Specifically, the obtaining the first package design scheme according to the dynamic thermal resistance feature vector and the space feature vector through the output layer comprises the following steps of S1241b-S1243b as shown below:

[0108] S1241b, obtaining, by the encoding layer, a first latent space vector and a second latent space vector according to the dynamic thermal resistance feature vector and the spatial feature vector, wherein the first latent space vector is used to represent a mean value corresponding to the latent space, and the second latent space vector is used to represent a standard deviation corresponding to the latent space.

[0109] It should be noted that the dynamic thermal resistance feature vector and the spatial feature vector are input into the encoding layer to obtain the first latent space vector and the second latent space vector, wherein the first latent space vector is used to represent a mean value corresponding to the latent space, and the second latent space vector is used to represent a standard deviation corresponding to the latent space. The role of the encoder layer is to map the input features to the distribution of the latent space, rather than directly to a certain point. By outputting the mean value and the standard deviation, it can be described as a Gaussian distribution in the latent space, and the latent variable is obtained by sampling from this distribution. For example, if the dimension of the latent space is d, then the output of the encoder layer is two d-dimensional vectors, which are used to represent the mean value and the standard deviation, respectively.

[0110] S1242b, sampling a sampling vector from a Gaussian distribution in the latent space according to the first latent space vector and the second latent space vector.

[0111] It should be noted that the sampling vector is obtained by reparameterization from the Gaussian distribution according to the mean value and the standard deviation output by the encoding layer.

[0112] S1243b, obtaining the predicted pad layout scheme according to the sampling vector by the decoding layer.

[0113] It should be noted that the sampling vector is input into the decoding layer, and the decoding layer decodes the vector in the latent space into a representation of the pad layout. At the same time, a fully connected layer and a suitable activation function (such as a Sigmoid function) can be used to map the output to a suitable range, for example, to map the position coordinates of each pad to between 0 and 1, representing the relative position in the packaging area. For example, the predicted pad layout scheme can be represented by a two-dimensional matrix.

[0114] S130, optimizing the first packaging body design scheme based on a preset packaging body design target to obtain a second packaging body design scheme.

[0115] In some embodiments, the preset packaging body design target can include the following contents:

[0116] Minimize maximum junction temperature value: Ensure the thermal management performance of the chip package, avoid device failure, performance degradation (such as transistor threshold voltage drift, shortened life) caused by overheating; accordingly, set the corresponding thermal constraints, such as limiting the maximum junction temperature value, setting the thermal resistance threshold of the heat dissipation path, etc., reduce heat accumulation by optimizing the density of heat dissipation vias, material selection (such as high thermal conductivity substrate) and layout design;

[0117] Minimize impedance fluctuation value: Ensure signal integrity (SI), reduce reflection, crosstalk and loss in signal transmission process, and ensure reliable transmission of high-speed signals (such as GHz level data bus); accordingly, set the corresponding electrical constraints (pin impedance matching, pad layout topology optimization), control the impedance fluctuation within the design allowed range (such as ±10% target impedance) by adjusting the pin pitch, dielectric layer thickness and trace structure;

[0118] Minimize interface stress standard deviation: Improve the mechanical reliability of the package, reduce stress concentration (such as solder joint cracking, package warping) caused by mismatch of thermal expansion coefficient (CTE); accordingly, set the corresponding mechanical constraints (warping ≤0.1mm, material mechanical performance parameters), that is, reduce uneven stress distribution by optimizing solder joint distribution, support structure (such as enhanced frame) and material combination.

[0119] Package area does not exceed the set area: Meet the miniaturization and high-density integration requirements (such as mobile device chip packaging) to balance performance and space limitations;

[0120] Manufacturing cost does not exceed the maximum cost budget: Control material cost (such as avoiding the use of expensive heat dissipation materials) and process cost (such as simplifying the manufacturing process, reducing the number of layers or special process steps) to ensure the economic efficiency of the design.

[0121] It should be noted that the preset package design target is to form a high-performance, low-cost and manufacturable chip package design scheme to achieve a package design that balances electrical performance, heat dissipation efficiency, mechanical reliability and engineering constraints.

[0122] It should be noted that the preset package design target is to form a high-performance, low-cost and manufacturable chip package design scheme to achieve a package design that balances electrical performance, heat dissipation efficiency, mechanical reliability and engineering constraints.

[0123] S131, based on the preset package design target and the first package design scheme, construct the objective function and the corresponding constraint conditions of the objective function as shown in the following formula by using a preset simulation tool:

[0124]

[0125]

[0126]

[0127]

[0128] wherein, represents the maximum operating temperature of the package, represents the signal path impedance fluctuation corresponding to the package, represents the interface stress between the chip and the substrate, represents the weight corresponding to the maximum operating temperature of the package, represents the weight corresponding to the signal path impedance fluctuation, represents the weight corresponding to the interface stress, represents the packaging area corresponding to the package, represents the manufacturing cost corresponding to the package, represents the maximum packaging area corresponding to the package, represents the maximum manufacturing cost corresponding to the package, represents the optimization target of the objective function.

[0129] S132, filtering the second package design scheme from the first package design scheme based on the objective function and the constraint condition.

[0130] In some embodiments, step S132 can include the following steps of S1321-S1326:

[0131] S1321, generating an initial population from the relevant parameters or layout information of the first package design scheme. For example, if the first package design scheme contains multiple different layout variants or parameter combinations, these can be used as individuals of the initial population.

[0132] In some embodiments, the first package design scheme contains 10 different layout variants, each of which has the following key parameters: packaging area (unit: mm 2 ), BGA solder ball number, substrate material cost (unit: dollars), maximum temperature of the package (unit: °C), signal path impedance fluctuation (unit: Ω), interface stress between the chip and the substrate (unit: MPa). These 10 layout variants constitute the initial population, and each layout variant is an individual in the population. For example, the parameters of individual 1 can be: packaging area 80mm 2 , BGA solder ball number 120, substrate material cost 1.5 dollars, maximum temperature of the package 70°C, signal path impedance fluctuation 2Ω, interface stress between the chip and the substrate 50 MPa.

[0133] S1322, for each individual in the initial population, calculate the fitness value of the individual according to the objective function, and a poor fitness value or a certain penalty can be given to the individual that does not meet the constraint condition, so as to promote the algorithm to search in the direction of meeting the constraint condition.

[0134] In some embodiments, for each individual in the initial population, the fitness value is calculated according to the objective function. For example, the fitness value of individual 1 is 0.4x70+0.3x2+0.3x50=28+0.6+15=43.6. Then check whether each individual meets the constraint condition. Suppose the packaging area of individual 2 is 110 mm 2 , which does not meet the constraint condition of packaging area ≤ 100 mm 2 , if a poor fitness value, such as 1000 (much larger than the fitness value of the individual that meets the constraint condition), is given to individual 2, the individual that does not meet the constraint condition is punished, so as to promote the algorithm to search in the direction of meeting the constraint condition.

[0135] S1323, select some individuals from the current population according to the fitness value of the individual as the parent individual for generating the next generation population. The purpose of selection is to make the individual with higher fitness value have a greater chance of being selected, so as to pass its excellent genes to the next generation. For example, roulette selection, tournament selection and other algorithms can be used for screening.

[0136] In some embodiments, roulette selection algorithm is used to select the parent individual from the current population. The basic idea of roulette selection algorithm is that the probability of being selected of each individual is proportional to its fitness value. The individual with better (smaller) fitness value has a greater probability of being selected.

[0137] For example, first, calculate the selection probability of each individual. Suppose the fitness value of individual 1 is 43.6 and the fitness value of individual 2 is 1000, the reciprocal of the fitness value is processed first (because it is to find the minimum value, the smaller the fitness value is the better), and the reciprocal of individual 1 is 1 / 43.6≈0.023, and the reciprocal of individual 2 is 1 / 1000=0.001. Then calculate the sum of the reciprocals of all individuals, suppose the sum of the reciprocals of other individuals is 0.1, then the selection probability of individual 1 is 0.023 / (0.023+0.001+0.1)≈0.19, and the selection probability of individual 2 is 0.001 / (0.023+0.001+0.1)≈0.008. Then, selection is made by means of random number. For example, generate a random number between 0 and 1, if the random number falls within the probability interval of individual 1, select individual 1 as the parent individual. Suppose 5 parent individuals are to be selected, through multiple generation of random numbers and comparison, 5 parent individuals are finally selected.

[0138] S1324, the selected parent individuals are subjected to crossover and mutation operations to generate new offspring individuals. The crossover operation can exchange part of the genes of two parent individuals to produce new gene combinations; the mutation operation randomly changes some genes of the individuals to increase the diversity of the population and avoid the algorithm falling into local optimization. It should be particularly noted that the crossover and mutation operations need to be reasonably defined according to specific design parameters and structures.

[0139] Specifically, for the crossover operation, it is assumed that the two selected parent individuals are individual 1 and individual 2. For the BGA pad layout, the “region-preserving crossover” method is adopted. The power / ground pin positions are fixed, and the signal pin coordinates are randomly exchanged.

[0140] For example, the signal pin coordinates of individual 1 are [(1, 2), (3, 4), (5, 6)], and the signal pin coordinates of individual 2 are [(2, 3), (4, 5), (6, 7)]. A crossover point is randomly selected, assuming the 2nd coordinate, then the signal pin coordinates of the offspring individual 1 after crossover are [(1, 2), (4, 5), (6, 7)], and the signal pin coordinates of the offspring individual 2 are [(2, 3), (3, 4), (5, 6)].

[0141] Specifically, for the mutation operation, for the high-temperature region (such as the pad corresponding to the power amplifier), the number of heat dissipation vias is forcibly increased by 20%. Assuming that individual 1 originally has 10 heat dissipation vias in the high-temperature region, after mutation, the number of heat dissipation vias in this region becomes 10x(1+20%) = 12. At the same time, it is prohibited to arrange ground vias within 50 μm around high-frequency signal pins (to avoid impedance discontinuity). If it is found during mutation that there is a ground via within 50 μm around a high-frequency signal pin, it will be removed. Through crossover and mutation operations, new offspring individuals are generated.

[0142] S1325, the offspring individuals generated by the crossover and mutation operations together with the parent individuals form a new population. Returning to the step of calculating the fitness value of each individual according to the target function, the above process is repeatedly performed until a preset termination condition is met, which can be reaching a certain number of iterations, the change of the target function being less than a certain threshold, the diversity of the population being lower than a certain level, or finding a solution that meets certain performance requirements, etc.

[0143] In some embodiments, the offspring individuals generated by the crossover and mutation operations are combined with the parent individuals to form a new population. Then, the process returns to step S1322, and the fitness values of each individual in the new population are recalculated. The above process is repeatedly performed until a preset termination condition is met. Assume that the set termination condition is to reach 100 iterations. Each time an iteration is performed, the population is updated, and the individuals in the population gradually evolve in a better direction.

[0144] S1326, when the termination condition is met, the optimal individual in the current population is selected as the second package design scheme screened out.

[0145] In some embodiments, the termination condition is met when 100 iterations are reached. At this time, the individual with the minimum fitness value in the current population is selected as the second package design scheme screened out. Assume that the individual 5 in the current population has the minimum fitness value, and the parameter and layout information of the individual 5 constitute the second package design scheme, for example, the package area is 90 mm 2 , the number of BGA solder balls is 125, the substrate material cost is 1.8 dollars, the maximum temperature of the package is 65℃, the signal path impedance fluctuation is 1.5Ω, and the interface stress between the chip and the substrate is 45 MPa. This scheme minimizes the value of the objective function under the premise of meeting the constraint conditions, and the second package design scheme is a relatively better package design scheme.

[0146] S140, according to the second package design scheme and the historical characteristic data, the preset design scheme generation model is updated to obtain an updated preset design scheme generation model.

[0147] It should be noted that the updating of the preset design scheme generation model according to the second package design scheme and the historical characteristic data to obtain an updated preset design scheme generation model includes the steps of S141 to S149 as follows:

[0148] S141, the second package design scheme and the historical characteristic data are subjected to feature normalization processing to obtain training data.

[0149] In some embodiments, the various design parameters, performance indicators and other data contained in the second package design scheme are integrated with the historical characteristic data.

[0150] Specifically, the second package design scheme and the historical feature data are subjected to feature normalization processing. Since different features can have different dimensions and value ranges, normalization can eliminate dimensional differences, making the model more easily converge and learn the rules in the data. For example, for package size, pin density, dielectric layer thickness and other parameters, the Min-Max normalization method is used to map them to a fixed interval such as [0, 1] or [-1, 1], to obtain training data available for training of the preset design scheme generation model.

[0151] S142, obtaining a training feature vector according to the training data through the input layer.

[0152] It should be noted that the training data subjected to feature normalization is input to the input layer of the preset design scheme generation model. The number of neurons of the input layer corresponds to the feature dimension of the training data, ensuring that all input feature information can be completely received. The input layer performs simple linear transformation on the received training data, converting it into the training feature vector, which contains numerical information of all input features.

[0153] S143, obtaining a training dynamic thermal resistance feature vector according to the training feature vector through the gated recurrent unit layer.

[0154] It should be noted that the gated recurrent unit layer learns and extracts dynamic thermal resistance related information in the training feature vector through its internal gating mechanism (update gate, reset gate, etc.), which can capture the rules of changes of thermal resistance over time or other related factors, integrate and refine the dynamic thermal resistance related information, and finally output the training dynamic thermal resistance feature vector. The training dynamic thermal resistance feature vector highlights the dynamic change characteristics of the package thermal performance, reflecting the change trend of the thermal resistance under different conditions.

[0155] S144, obtaining a training spatial feature vector according to the training feature vector through the fully connected network layer.

[0156] It should be noted that the fully connected network layer can include multiple fully connected layers. Through the fully connected network layer, the training feature vector is subjected to nonlinear transformation and feature combination. Each layer of neurons is connected to all neurons of the previous layer, and the input data is weighted and summed through a weight matrix and a bias term and processed through an activation function (such as a ReLU function), to gradually extract deep features related to the spatial structure of the package, and finally generate the training spatial feature vector. The training spatial feature vector contains important feature information of the package in the spatial dimension.

[0157] S145, obtaining a first training latent space vector and a second training latent space vector according to the training dynamic thermal resistance feature vector and the training space feature vector through the encoding layer, wherein the first training latent space vector is used to represent a training mean value corresponding to the latent space, and the second training latent space vector is used to represent a training standard deviation corresponding to the latent space.

[0158] It should be noted that the encoding layer receives the training dynamic thermal resistance feature vector from the gated recurrent unit layer and the training space feature vector from the fully connected network layer, maps the input training feature vector to the latent space, and outputs two vectors, i.e., the first training latent space vector and the second training latent space vector. The first training latent space vector is used to represent a training mean value corresponding to the latent space, reflecting the central tendency of the data distribution in the latent space; and the second training latent space vector is used to represent a training standard deviation corresponding to the latent space, reflecting the dispersion degree of the data distribution in the latent space. The latent space is a low-dimensional vector space, and by encoding the high-dimensional input features, the complex encapsulated feature information is compressed into a space that is easier to process and understand, while retaining the key features and distribution information of the data.

[0159] S146, calculating a training relative entropy value between the space distribution of the latent space and the standard normal distribution based on the training mean value and the training standard deviation.

[0160] It should be noted that based on the first training latent space vector (training mean value) and the second training latent space vector (training standard deviation), the actual distribution of the latent space (which can be assumed to be Gaussian distribution) can be determined; at the same time, the standard normal distribution is known as a reference distribution.

[0161] Specifically, the training relative entropy value is calculated by the corresponding calculation formula as shown below:

[0162]

[0163] wherein, represents the training relative entropy value, represents the dimension of the latent space, represents the training mean value of the latent space distribution in the i-th dimension, represents the training standard deviation of the latent space distribution in the i-th dimension, represents the log variance of the latent space distribution in the i-th dimension.

[0164] ​​​The training relative entropy value reflects a deviation between a latent space distribution learned by the preset design scheme generation model and an ideal standard normal distribution; therefore, the smaller the relative entropy value, the closer the two distributions.

[0165] S147, adjusting model weights and model biases in the preset design scheme generation model according to the training relative entropy value through a back propagation algorithm, to obtain an adjusted preset design scheme generation model.

[0166] It should be noted that the back propagation algorithm is an optimization algorithm for training a neural network, based on the idea of gradient descent, by calculating the gradient of the training relative entropy value on the model weights and biases, to adjust the parameters of the model, so that the training relative entropy value, i.e. the loss function value, gradually decreases.

[0167] Specifically, according to the calculated training relative entropy value, the back propagation algorithm starts from the output layer (i.e. the place where the relative entropy value is calculated) and reversely calculates the gradient of each network layer. For the weights and biases of each layer, adjust according to the size and direction of the gradient; by continuously adjusting the model weights and model biases in the preset design scheme generation model, an adjusted preset design scheme generation model is obtained, so that the model is more close to the standard normal distribution in the learning of the latent space distribution, thereby improving the performance of the model.

[0168] S148, repeating the steps of obtaining a training feature vector from the input layer according to the training data to adjusting the model weights and model biases in the preset design scheme generation model according to the training relative entropy value through a back propagation algorithm, to obtain an adjusted preset design scheme generation model, until the training relative entropy value is less than a preset threshold.

[0169] It should be noted that each iteration, the preset design scheme generation model will be based on new training data for forward propagation calculation (from the input layer to the encoding layer, to calculate the training relative entropy value), and then adjust the parameters through the back propagation algorithm. With the increase of the number of iterations, the preset design scheme generation model continuously learns the features and rules in the training data, and the distribution of the latent space gradually approaches the standard normal distribution, and the training relative entropy value gradually decreases. After each iteration, check whether the training relative entropy value is less than the preset threshold. The preset threshold is a measure set according to actual demand and experience, used to judge whether the preset design scheme generation model has converged to an acceptable degree. If the training relative entropy value is still greater than the preset threshold, continue to the next iteration; if the training relative entropy value is less than the preset threshold, it means that the preset design scheme generation model has reached a good state in the learning of the latent space distribution, and the performance of the preset design scheme generation model meets the set requirements, at this time the iteration training can be stopped.

[0170] S149, obtaining the updated preset design scheme generation model according to the training relative entropy value less than the preset threshold value through the back propagation algorithm.

[0171] It should be noted that when the training relative entropy value is less than the preset threshold value, the last parameter fine-tuning is performed on the model based on the training relative entropy value at this time through the back propagation algorithm, and the updated preset design scheme generation model is obtained. The updated preset design scheme generation model is obtained through multiple iteration training and optimization on the basis of fusing the second package design scheme and the historical feature data. Compared with the initial preset design scheme generation model, the updated preset design scheme generation model can better generate a package design scheme meeting the actual requirements, for example, the generated design scheme is more optimized in terms of multi-physical field performance, size and cost constraints, etc.

[0172] S150, obtaining a target package design scheme according to the historical feature data through the updated preset design scheme generation model.

[0173] It should be noted that the updated preset design scheme generation model can generate a target package design scheme meeting the requirements through a complex feature extraction, encoding and decoding process according to the historical feature data, and provide effective support and guidance for the design of the chip package. At the same time, after obtaining the target package design scheme, further verification and evaluation can be performed thereon, for example, the thermal performance, electrical performance and mechanical performance of the package are simulated and analyzed through a preset simulation tool, and it is checked whether the preset design target and constraint condition are met. If not, the model can be further fine-tuned or re-input data for calculation until a target package design scheme meeting the requirements is obtained.

[0174] In summary, the pcb package design method provided in the present application significantly improves the accuracy and reliability of the package design through an intelligent design process driven by data, forms a high-performance, low-cost and manufacturable chip package design scheme, and takes into account the electrical performance, heat dissipation efficiency, mechanical reliability and engineering constraints, thereby significantly improving the accuracy and reliability of the package design.

[0175] In order to better implement the above method, the pcb package design device provided in the embodiments of the present application can be integrated in an electronic device, which can be a terminal, a server or the like. The terminal can be a mobile phone, a tablet computer, a smart Bluetooth device, a notebook computer, a personal computer or the like. The server can be a single server or a server cluster composed of multiple servers.

[0176] For example, in the embodiment, the pcb package design apparatus is integrated in the terminal, and the method of the embodiment is described in detail.

[0177] For example, as shown in Figure 2 The pcb package design apparatus 200 can include a first unit 201, a second unit 202, a third unit 203, a fourth unit 204, and a fifth unit 205, and the apparatus includes:

[0178] The first unit is configured to obtain pre-processed historical feature data, wherein the historical feature data is used to represent the historical design condition and the historical working state of the package.

[0179] The second unit is configured to obtain a first package design scheme according to the historical feature data by using a preset design scheme generation model.

[0180] The third unit is configured to optimize the first package design scheme based on a preset package design target to obtain a second package design scheme.

[0181] The fourth unit is configured to update the preset design scheme generation model according to the second package design scheme and the historical feature data to obtain an updated preset design scheme generation model.

[0182] The fifth unit is configured to obtain a target package design scheme according to the historical feature data by using the updated preset design scheme generation model.

[0183] In specific implementation, each unit can be implemented as an independent entity, or can be combined as the same or several entities, and the specific implementation of each unit can be referred to the method embodiment above, which will not be described here.

[0184] As can be seen from the above, the embodiment can significantly improve the accuracy and reliability of the package design, so as to better meet the market demand for various specifications of the package.

[0185] The embodiment also provides an electronic device, which can be a terminal, a server, etc. The terminal can be a mobile phone, a tablet computer, a smart Bluetooth device, a notebook computer, a personal computer, etc. The server can be a single server or a server cluster composed of multiple servers, etc.

[0186] In some embodiments, the product processing apparatus can also be integrated in multiple electronic devices, for example, the product processing apparatus can be integrated in multiple servers, and the multiple servers can be used to implement the pcb package design method of the embodiment.

[0187] In this embodiment, the electronic device will be described in detail as a terminal, for example, such as... Figure 3 As shown, it illustrates a structural schematic diagram of the terminal 300 involved in an embodiment of this application. Specifically:

[0188] The terminal 300 may include components such as a processor 301 with one or more processing cores, a memory 302 with one or more media, a power supply 303, an input module 304, and a communication module 305. Those skilled in the art will understand that... Figure 3 The terminal 300 structure shown does not constitute a limitation on the terminal 300, and may include more or fewer components than shown, or combine certain components, or have different component arrangements. Wherein:

[0189] The processor 301 is the control center of the terminal 300. It connects various parts of the terminal 300 via various interfaces and lines, and performs various functions and processes data by running or executing software programs and / or modules stored in the memory 302, and by calling data stored in the memory 302, thereby providing overall monitoring of the terminal 300. In some embodiments, the processor 301 may include one or more processing cores; in some embodiments, the processor 301 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. It is understood that the modem processor may also not be integrated into the processor 301.

[0190] The memory 302 can be used to store software programs and modules. The processor 301 executes various functional applications and data processing by running the software programs and modules stored in the memory 302. The memory 302 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, application programs required for at least one function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the terminal 300, etc. In addition, the memory 302 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0191] The terminal 300 also includes a power supply 303 to supply power to each of the components. In some embodiments, the power supply 303 can be logically connected to the processor 301 through a power management system, so that the power management system can manage charging, discharging, and power consumption management, etc. The power supply 303 can also include one or more DC or AC power sources, recharging systems, power failure detection circuits, power converters or inverters, power status indicators, etc.

[0192] The terminal 300 can also include an input module 304, which can be used to receive input digital or character information, and generate keyboard, mouse, joystick, optical or trackball signal inputs related to user settings and function controls.

[0193] The terminal 300 can also include a communication module 305, which in some embodiments can include a wireless module through which the terminal 300 can perform short-range wireless transmission, thereby providing the user with wireless broadband Internet access. For example, the communication module 305 can be used to help the user send and receive emails, browse web pages, and access streaming media, etc.

[0194] In some further schemes, the terminal 300 can also include a display unit, etc., which will not be described here. In particular, in the present embodiment, the processor 301 in the terminal 300 will load one or more executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and run the application programs stored in the memory 302 by the processor 301, thereby implementing various functions, such as:

[0195] Obtaining historical characteristic data corresponding to pre-processing, wherein the historical characteristic data is used to represent historical design conditions and historical working states of the package;

[0196] Generating a preset design scheme generation model, and obtaining a first package design scheme according to the historical characteristic data;

[0197] Optimizing the first package design scheme based on a preset package design target, and obtaining a second package design scheme;

[0198] Updating the preset design scheme generation model according to the second package design scheme and the historical characteristic data, and obtaining an updated preset design scheme generation model;

[0199] Obtaining a target package design scheme according to the historical characteristic data through the updated preset design scheme generation model.

[0200] The specific implementation of each of the above operations can be referred to the previous embodiments, which will not be described here.

[0201] As can be seen from the above, the embodiments of the present application can significantly improve the precision and reliability of the package design, so as to better meet the market demand for various specifications of the package.

[0202] Those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions or by controlling relevant hardware by the instructions, which can be stored in a medium and loaded and executed by a processor.

[0203] To this end, the embodiments of the present application provide a medium, which stores a plurality of instructions capable of being loaded by a processor to execute the steps in any of the pcb package design methods provided by the embodiments of the present application. For example, the instructions can execute the following steps:

[0204] Obtaining historical feature data corresponding to pre-processing, wherein the historical feature data is used to represent the historical design condition and the historical working state of the package;

[0205] Obtaining a first package design scheme by a preset design scheme generation model according to the historical feature data;

[0206] Optimizing the first package design scheme based on a preset package design target to obtain a second package design scheme;

[0207] Updating the preset design scheme generation model according to the second package design scheme and the historical feature data to obtain an updated preset design scheme generation model;

[0208] Obtaining a target package design scheme by the updated preset design scheme generation model according to the historical feature data.

[0209] The medium can include a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0210] According to an aspect of the present application, a computer program product or computer program is provided, which includes computer instructions stored in a medium. A processor of a computer device reads the computer instructions from the medium, and the processor executes the computer instructions to make the computer device execute the method provided in the various optional implementation manners provided in the above embodiments.

[0211] Since the instructions stored in the medium, the steps in any of the pcb package design methods provided by the embodiments of the present application can be performed, thus the beneficial effects that can be achieved by any of the pcb package design methods provided by the embodiments of the present application can be achieved, details of which are described above, and will not be repeated here.

[0212] The above describes in detail the pcb package design method, device, terminal and medium provided by the embodiments of the present application. The principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A method of designing a pcb package, the method comprising: The method comprises: acquiring historical feature data corresponding to preprocessing, wherein the historical feature data is used to represent historical design conditions and historical working conditions of the package; generating a first package design scheme according to the historical feature data through a preset design scheme generation model; optimizing the first package design scheme based on a preset package design target to obtain a second package design scheme; updating the preset design scheme generation model according to the second package design scheme and the historical feature data to obtain an updated preset design scheme generation model; obtaining a target package design scheme according to the historical feature data through the updated preset design scheme generation model; the optimization of the first package design scheme based on the preset package design target to obtain the second package design scheme comprises: constructing a target function and a constraint condition corresponding to the target function shown in the following formula based on the preset package design target and the first package design scheme through a preset simulation tool: wherein, represents the maximum operating temperature of the package, represents the signal path impedance fluctuation corresponding to the package, represents the interface stress between the chip and the substrate, represents the weight corresponding to the maximum operating temperature of the package, represents the weight corresponding to the signal path impedance fluctuation, represents the weight corresponding to the interface stress, represents the packaging area corresponding to the package, represents the manufacturing cost corresponding to the package, represents the maximum packaging area corresponding to the package, represents the maximum manufacturing cost corresponding to the package, represents the optimization target of the objective function; obtaining the second package design scheme from the first package design scheme based on the target function and the constraint condition.

2. The method of claim 1, wherein, The acquisition of the historical feature data corresponding to preprocessing comprises: acquiring historical design parameters, wherein the historical design parameters are used to represent historical design conditions of the package; obtaining performance data corresponding to the historical design parameters according to the historical design parameters through a preset simulation tool; merging the historical design parameters and the performance data to obtain merged feature data; performing feature standardization processing on the merged feature data to obtain the historical feature data corresponding to preprocessing.

3. The method of claim 1, wherein, The preset design scheme generation model comprises an input layer, a gated recurrent unit layer, a fully connected network layer and an output layer; the generation of the first package design scheme according to the historical feature data through the preset design scheme generation model comprises: obtaining a historical feature vector according to the historical feature data through the input layer; obtaining a dynamic thermal resistance feature vector according to the historical feature vector through the gated recurrent unit layer; obtaining a spatial feature vector according to the historical feature vector through the fully connected network layer; obtaining the first package design scheme according to the dynamic thermal resistance feature vector and the spatial feature vector through the output layer.

4. The method of claim 3, wherein, The output layer comprises a first fully connected layer and a second fully connected layer, the activation function of the first fully connected layer is a ReLU function, the activation function of the second fully connected layer is a linear activation function, and the first package design scheme comprises a predicted key indicator vector, wherein the predicted key indicator vector is used to represent the design performance of the package; the generation of the first package design scheme according to the dynamic thermal resistance feature vector and the spatial feature vector through the output layer comprises: obtaining a first intermediate vector according to the dynamic thermal resistance feature vector and the spatial feature vector through the first fully connected layer; The second full connection layer is configured to obtain the predicted key indicator vector according to the first intermediate vector.

5. The method of claim 3, wherein, The output layer includes an encoder layer and a decoder layer, and the first package design scheme includes a package corresponding prediction pad layout scheme; The output layer is configured to obtain the first package design scheme according to the dynamic thermal resistance feature vector and the spatial feature vector, including: The encoder layer is configured to obtain a first latent space vector and a second latent space vector according to the dynamic thermal resistance feature vector and the spatial feature vector, wherein the first latent space vector is used to represent a mean value of a latent space, and the second latent space vector is used to represent a standard deviation of the latent space; The first latent space vector and the second latent space vector are used to sample a sampling vector from a Gaussian distribution in the latent space; The decoder layer is configured to obtain the prediction pad layout scheme according to the sampling vector.

6. The method of claim 5, wherein, The second package design scheme and the historical feature data are used to update the preset design scheme generation model to obtain an updated preset design scheme generation model, including: The second package design scheme and the historical feature data are subjected to feature normalization processing to obtain training data; The input layer is configured to obtain a training feature vector according to the training data; The gated recurrent unit layer is configured to obtain a training dynamic thermal resistance feature vector according to the training feature vector; The full connection network layer is configured to obtain a training spatial feature vector according to the training feature vector; The encoder layer is configured to obtain a first training latent space vector and a second training latent space vector according to the training dynamic thermal resistance feature vector and the training spatial feature vector, wherein the first training latent space vector is used to represent a training mean value of a latent space, and the second training latent space vector is used to represent a training standard deviation of the latent space; Based on the training mean value and the training standard deviation, a training relative entropy value between a spatial distribution of the latent space and a standard normal distribution is calculated; The preset design scheme generation model is adjusted according to the training relative entropy value by using a back propagation algorithm to obtain an adjusted preset design scheme generation model; The adjusted preset design scheme generation model is iteratively trained based on the training data until the training relative entropy value is less than a preset threshold, and the updated preset design scheme generation model is obtained.

7. A device for designing a pcb package, said device being arranged to implement the method according to any one of claims 1 to 6, characterized in that, The device includes: A first unit configured to obtain historical feature data corresponding to preprocessing, wherein the historical feature data is used to represent historical design conditions and historical working states of a package; A second unit configured to obtain a first package design scheme according to the historical feature data by using a preset design scheme generation model; A third unit configured to optimize the first package design scheme based on a preset package design target to obtain a second package design scheme; a fourth unit, configured to update the preset design scheme generation model according to the second packaging body design scheme and the historical characteristic data, to obtain an updated preset design scheme generation model; a fifth unit, configured to obtain a target packaging body design scheme according to the historical characteristic data by using the updated preset design scheme generation model.

8. A terminal, characterized by comprising: A processor and a memory are included, and the memory stores a plurality of instructions; the processor loads the instructions from the memory to execute the steps in the method of any one of claims 1-6.

9. A medium characterized by, The medium stores a plurality of instructions, and the instructions are suitable for being loaded by the processor to execute the steps in the method of any one of claims 1-6.

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