Memory controller performing training and operating method thereof

Abstract

The memory controller includes: a multi-phase clock generator that generates first to Nth clocks having N different phases; a write clock generator that generates a monitor signal having a logic state corresponding to a bit of the data pattern; a duty ratio regulator which regulates the duty ratio of the first clock to the Nth clock; a skew adjuster that adjusts skew of at least one of the first to Nth clocks; and a training circuit controlling a training operation for adjusting the duty ratio and skew of the first to Nth clocks, in which during a first training process in which the duty ratio of the first to Nth clocks is adjusted, the skew of the first to Nth clocks is adjusted. First to Nth monitoring signals having waveforms corresponding to the first to Nth clocks are generated using data patterns having different values, and a duty ratio of each of the first to Nth clocks is adjusted based on a result of monitoring each duty ratio of the first to Nth monitoring signals.

Description

Cross - reference to Related Applications

[0001] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2024 - 0012661, filed with the Korean Intellectual Property Office on January 26, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] One or more example embodiments of the present disclosure relate to a storage controller, and more particularly, to a storage controller that performs training on various clocks and data and a method of operating the storage controller. Background Art

[0003] A storage controller or a system - on - chip (SoC) including a storage controller may communicate with a storage device via a high - speed interface. For example, an SoC may include an integrated circuit having multiple components or multiple intellectual properties (IPs) of an electronic system integrated therein, and may perform training on the storage device before communicating with the storage device. For example, the SoC may perform various types of training operations such as ZQ calibration, reference voltage training, data training, and clock signal training.

[0004] In addition, serializer / deserializer (SERDES) operations are required for high - speed operation of a memory interface, and a multi - phase clock signal related to SERDES operations may be used. In this regard, when the duty cycle and / or skew of the multi - phase clock signal generated inside the storage controller is distorted, the effective window margin for data transmission and reception is reduced, which results in reduced stability during high - speed operation. According to the related art, a method of monitoring and adjusting the duty cycle of the clock signal inside the storage device through a training operation has been proposed. However, since the correction of the duty cycle and / or skew distortion of the multi - phase clock signal and data inside the storage controller cannot be correctly performed, improving the stability of high - speed operation in the memory interface is limited. Summary of the Invention

[0005] One or more example embodiments of the present disclosure provide a storage controller and a method of operating the storage controller, the storage controller being configured to adjust the duty cycle and / or skew of a multi - phase clock signal and data inside the storage controller through a training operation.

[0006] According to one aspect of an exemplary embodiment of the present disclosure, there is provided a storage controller, including: a multiphase clock generator configured to generate a first clock to an Nth clock having N different phases (where N is an integer equal to or greater than 2); a write clock generator configured to receive a data pattern and generate a monitoring signal having a logical state corresponding to a bit of the data pattern in synchronization with an edge of the first clock to the Nth clock during a training process; a duty cycle regulator configured to regulate a duty cycle of the first clock to the Nth clock based on a plurality of duty cycle control codes set during the training process; a skew regulator configured to regulate a skew of at least one of the first clock to the Nth clock based on a skew control code set during the training process; and a training circuit configured to control a training operation for regulating the duty cycle and at least one skew of the first clock to the Nth clock, the training operation including a plurality of training processes including the training process, wherein, during a first training process of regulating the duty cycle of the first clock to the Nth clock, a first monitoring signal to an Nth monitoring signal having waveforms corresponding to the first clock to the Nth clock are generated using data patterns having different values, and the duty cycle of the first clock to the Nth clock is regulated based on a result of monitoring the duty cycle of the first monitoring signal to the Nth monitoring signal.

[0007] According to one aspect of an exemplary embodiment of the present disclosure, there is provided a method of operating a storage controller, the method including: generating a first clock, a second clock, a third clock, and a fourth clock having a 90-degree phase difference from each other; generating a monitoring signal corresponding to waveforms of the first clock to the fourth clock by sampling bits of a data pattern in synchronization with edges of the first clock to the fourth clock; sending the monitoring signal to a storage device; receiving duty cycle information representing a result of monitoring the duty cycle of the monitoring signal from the storage device; and regulating the duty cycle of the first clock to the fourth clock based on the duty cycle information.

[0008] According to one aspect of an exemplary embodiment of the present disclosure, a method of operating a storage controller is provided, the method including: generating first to Nth clocks (where N is an integer equal to or greater than 2) having a 90-degree phase difference from each other; generating first to Nth monitoring signals corresponding to waveforms of the first to Nth clocks based on the first to Nth clocks and a data pattern; adjusting a duty cycle of each of the first to Nth clocks based on results of monitoring duty cycles of the first to Nth monitoring signals while changing the duty cycles of the first to Nth clocks during a training process; adjusting a skew of at least one of the first to Nth clocks based on results of monitoring duty cycles of the first to Nth monitoring signals while changing a skew of at least one of the first to Nth clocks during a training process; writing first to Nth data into a storage device while changing a duty cycle of the data and receiving the first to Nth data from the storage device synchronously with a write clock having a frequency twice that of each of the first to Nth clocks; and adjusting the duty cycle of the data based on a comparison result between an effective window size of data received synchronously with a rising edge of the write clock and an effective window size of data received synchronously with a falling edge of the write clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Exemplary embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram showing a storage system including a storage controller according to one or more exemplary embodiments;

[0011] Figure 2A and Figure 2B is a waveform diagram showing an example of a four-phase clock signal and a write clock;

[0012] Figure 3 is a block diagram showing an example of a storage controller and a storage system including the storage controller according to one or more exemplary embodiments;

[0013] Figure 4 is a block diagram showing an example of transmission of duty cycle information according to one or more exemplary embodiments;

[0014] Figure 5 is a block diagram showing a system-on-chip (SoC) employing a storage controller according to one or more exemplary embodiments;

[0015] Figure 6 is a flowchart showing a method of operating a storage controller according to one or more exemplary embodiments;

[0016] Figure 7Shows the waveforms of the first to fourth selection signals when the duty cycles of the first to fourth clocks are distorted;

[0017] Figure 8A and Figure 8B is a diagram showing an example of a training process for adjusting the duty cycle of a multi-phase clock signal according to one or more example embodiments;

[0018] Figures 9 to 11A and Figure 11B is a diagram showing an example of a training process for adjusting the skew of a multi-phase clock signal according to one or more example embodiments;

[0019] Figure 12 is a flowchart showing an operation method for a storage controller to perform data duty cycle training according to one or more example embodiments;

[0020] Figure 13 、 Figure 14A and Figure 14B is a diagram showing an example of performing data duty cycle training according to one or more example embodiments;

[0021] Figure 15 is a block diagram showing an example of a storage controller according to one or more example embodiments; and

[0022] Figure 16A 、 Figure 16B 、 Figure 16C and Figure 17 is a diagram showing an example of setting a skew control code for each data channel according to one or more example embodiments. Detailed Description of the Embodiments

[0023] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

[0024] Figure 1 is a block diagram showing a storage system 10 including a storage controller 100 according to one or more example embodiments.

[0025] Refer to Figure 1, the storage system 10 may include a storage controller 100 and a storage device 200. The storage system 10 may be included in a personal computer (PC), a mobile electronic device, or a data server. The mobile electronic device may include, for example but not limited to, a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a drone, etc.

[0026] The storage controller 100 may be set as an integrated circuit (IC), a system on chip (SoC), an application processor (AP), a mobile AP, a chipset, or a group of chips, or may be included therein. The storage controller 100 may include a semiconductor device that performs a storage control function. For example, when the storage controller 100 corresponds to an AP, the storage controller 100 may include a storage control logic (not shown), a random access memory (RAM), a central processing unit (CPU), a graphics processing unit (GPU), and / or a modem.

[0027] The storage controller 100 may control the storage device 200 to read data DQ (or referred to as read data DQ) stored in the storage device 200 and / or write data DQ (or referred to as write data DQ) on the storage device 200 in response to a write / read request from the host HOST. Specifically, the storage controller 100 may control the write and read operations of the data DQ with respect to the storage device 200 by providing an address and a command to the storage device 200. In addition, the write data DQ and the read data DQ may be sent and received between the storage controller 100 and the storage device 200.

[0028] The storage controller 100 may access the storage device 200 in response to a request from the host HOST and communicate with the host HOST using various protocols. For example, the storage controller 100 may communicate with the host HOST using interface protocols such as Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), and Serial Attached SCSI (SAS). In addition, various other interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE) may be applied to the protocol between the host HOST and the storage controller 100.

[0029] The storage device 200 may include a volatile storage device. The volatile storage device may be formed as a RAM, a dynamic RAM (DRAM), or a static RAM (SRAM), but the embodiments are not limited thereto. For example, the storage device 200 may include a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc. In addition, the storage device 200 may include a high bandwidth memory (HBM). In addition, the storage device 200 may include a non-volatile storage device. For example, the storage device 200 may include a resistive memory, such as a magnetic RAM (MRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), a resistive RAM (ReRAM), etc.

[0030] Reference Figure 1 , the storage controller 100 may include a processor 110, a training circuit 120, a multi-phase clock generator 130, a duty cycle / skew adjuster 140, and a first interface (I / F) circuit 150. The processor 110 may execute all controls related to the storage operation, and the training circuit 120 may perform training operations on various signals and voltages related to the storage operation based on the control of the processor 110. For example, when the storage system 10 is initially driven, the training circuit 120 may perform training on various clock signals used in the storage controller 100, and may also perform training on the data provided to the storage device 200. Additionally or alternatively, the training circuit 120 may perform one or more of skew training between the read data strobe signal and the read data, training of the read reference voltage for distinguishing the read data, skew training between the write data strobe signal and the write data, training of the write reference voltage for distinguishing the write data, etc.

[0031] In addition, the storage device 200 may include a memory cell array 210, a duty cycle monitor 220, a control logic 230, and a second interface circuit 240. When the storage device 200 includes a DRAM, the memory cell array 210 may include a plurality of DRAM cells.

[0032] The multi-phase clock generator 130 of the storage controller 100 may generate a multi-phase clock signal based on a reference clock signal having an arbitrary frequency, and may generate, for example, a 4-phase clock signal having a phase difference of 90 degrees. Various internal operations of the storage controller 100 may be performed synchronously with the multi-phase clock signal and / or other clock signals generated from the multi-phase clock signal. The multi-phase clock signal may have a frequency lower than the data output speed, and the storage controller 100 may transmit and receive data based on the clock signal having a relatively low frequency. Therefore, data can be stably transmitted and received.

[0033] The multi-phase clock signals generated from the multi-phase clock generator 130 can be sent to each circuit block via the lines inside the memory controller 100. However, during the generation and transmission of the multi-phase clock signals, the duty cycle and / or skew of each of the multi-phase clock signals may be distorted due to clock transmission paths, offsets of circuit blocks, etc. In addition, distortion of the duty cycle of data may occur during the process of sending data to the storage device 200. Therefore, correction of the duty cycle and / or skew of the multi-phase clock signals and data is required.

[0034] According to one or more example embodiments, the memory controller 100 can detect and adjust the duty cycle / skew of the multi-phase clock signals during a training process, and can also detect and adjust the duty cycle / skew of data. For example, the training operation can include a training process for setting duty cycle control codes and skew control codes for various clock signals and data, and the training operation can be executed during an initial driving process of supplying power to the memory system 10 and / or can be executed at any time point during operation.

[0035] The training operation according to one or more example embodiments is described below.

[0036] During the training process, the memory controller 100 can generate a first clock to an Nth clock (N is an integer equal to or greater than 2) as multi-phase clock signals, and can also generate a write clock WCK defined in the LPDDRx specification (e.g., LPDDR5 and LPDDR6) or the Graphics DDR (GDDR) specification. For example, the write clock WCK can be generated based on the first clock to the Nth clock, and can include a signal having a frequency twice that of each of the first clock to the Nth clock. For example, assuming that the first clock to the fourth clock I, Q, IB, and QB are 4-phase clock signals, the rising edge of the write clock WCK can be synchronized with the rising edges of the first clock and the third clock, and the falling edge of the write clock WCK can be synchronized with the rising edges of the second clock and the fourth clock. The memory controller 100 can provide the write clock WCK to the storage device 200, and the storage device 200 can receive or send data synchronously with the write clock WCK. In addition, the memory controller 100 can receive the data output from the storage device 200 synchronously with the write clock WCK.

[0037] In an embodiment, the write clock WCK can be used as the monitoring signal Sig_M during the training process, and the monitoring signal Sig_M can have various waveforms according to data patterns with various values. For example, the monitoring signal Sig_M having a waveform formed by sampling bits of the data pattern can be generated at the edge timings of the first clock to the fourth clock I, Q, IB, and QB. Therefore, if there are distortions in the duty cycle or skew of the first clock to the fourth clock I, Q, IB, and QB, the distortion characteristics may be reflected in the waveform of the monitoring signal Sig_M generated based on the first clock to the fourth clock I, Q, IB, and QB.

[0038] In an embodiment, the storage controller 100 can send the monitoring signal Sig_M to the storage device 200 and receive the duty cycle information Info_D according to the result of monitoring the duty cycle of the monitoring signal Sig_M from the storage device 200. The storage controller 100 can adjust the duty cycle and / or skew of each of the first clock to the fourth clock I, Q, IB, and QB based on the received duty cycle information Info_D.

[0039] In an embodiment, the value of the data pattern related to the generation of the monitoring signal Sig_M can be changed in various ways during the training process. Depending on the value of the data pattern, the monitoring signal Sig_M can have a waveform corresponding to one of the first clock to the fourth clock I, Q, IB, and QB, or can have a waveform corresponding to the write clock WCK having a frequency twice that of each of the first clock to the fourth clock I, Q, IB, and QB. For example, the training process related to the duty cycle adjustment of the first clock to the fourth clock I, Q, IB, and QB can include multiple operations. In the first operation, the data pattern has a first value, and based on the first value of the data pattern, the monitoring signal Sig_M can have a waveform corresponding to the first clock I. The storage controller 100 can provide the monitoring signal Sig_M to the storage device 200 and adjust the duty cycle of the first clock I based on the duty cycle information Info_D provided from the storage device 200.

[0040] Similarly, for the duty cycle adjustment of the first to fourth clocks I, Q, IB, and QB, the data pattern in the second operation can have a second value. The monitoring signal Sig_M can have a waveform corresponding to the second clock Q based on the second value of the data pattern, and the duty cycle of the second clock Q can be adjusted based on the duty cycle information Info_D. In addition, the data pattern in the third operation can have a third value. The monitoring signal Sig_M can have a waveform corresponding to the third clock IB based on the third value of the data pattern, and the duty cycle of the third clock IB can be adjusted based on the duty cycle information Info_D. In addition, the data pattern in the fourth operation can have a fourth value. The monitoring signal Sig_M can have a waveform corresponding to the fourth clock QB based on the fourth value of the data pattern, and the duty cycle of the fourth clock QB can be adjusted based on the duty cycle information Info_D.

[0041] In addition, the training process related to the skew adjustment of the first to fourth clocks I, Q, IB, and QB can include multiple operations. In the first operation, a monitoring signal Sig_M having a waveform corresponding to the first clock I and a monitoring signal Sig_M having a waveform corresponding to the third clock IB can be generated. For example, the portion between the edges of the first clock I and the third clock IB in the first operation can correspond to the logic high portion or the logic low portion of the monitoring signal Sig_M, and the skew between the first clock I and the third clock IB can be detected and adjusted based on the duty cycle information Info_D related to the monitoring signal Sig_M.

[0042] In addition, in the second operation, a monitoring signal Sig_M having a waveform corresponding to the second clock Q and a monitoring signal Sig_M having a waveform corresponding to the fourth clock QB can be generated. For example, the portion between the edges of the second clock Q and the fourth clock QB in the second operation can correspond to the logic high portion or the logic low portion of the monitoring signal Sig_M, and the skew between the second clock Q and the fourth clock QB can be detected and adjusted based on the duty cycle information Info_D related to the monitoring signal Sig_M. In addition, in the third operation, a monitoring signal Sig_M having a waveform corresponding to the write clock WCK and a waveform inverted therefrom can be generated. For example, the portion between the edges of the first clock I and the second clock Q in the third operation can correspond to the logic high portion or the logic low portion of the monitoring signal Sig_M, and the skew between the first clock I and the second clock Q can be detected and adjusted based on the duty cycle information Info_D related to the monitoring signal Sig_M. Additionally, in the third operation, the skew between the third clock IB and the fourth clock QB can be detected and adjusted.

[0043] Through the above training process, the duty cycle and skew of each of the first to fourth clocks I, Q, IB, and QB can be adjusted. Additionally, althoughFigure 1 is not shown, but a duty ratio adjuster (not shown) for adjusting the duty ratio of data may be provided in a path for transmitting data in the storage controller 100, and the training process may further include a duty ratio training process of outputting and writing data to the storage device 200 and then adjusting the duty ratio of the data based on an effective window size determined according to data read from the storage device 200. Training related to data is described in detail in the following exemplary embodiments.

[0044] According to one or more exemplary embodiments, during the training process, the duty ratio / skew of a multi-phase clock signal may be adjusted in the storage controller 100, and the duty ratio / skew of data may also be adjusted. Accordingly, a sufficient effective window margin can be ensured, and stability can be improved, particularly in the high-speed operation of the storage device 200.

[0045] In addition, in the above embodiments, the write clock WCK has been described as being used as the monitoring signal Sig_M according to the data pattern. However, the embodiments are not limited thereto. For example, the storage controller 100 may further include a circuit that separately generates the monitoring signal Sig_M from the write clock WCK. Additionally, for a plurality of training processes in the training operation, values of data patterns for generating the monitoring signal Sig_M having various waveforms may be set and stored in the storage controller 100. Further, when describing the following exemplary embodiments, the terms "write clock WCK" and "monitoring signal Sig_M" during the training process may be used interchangeably with the same meaning.

[0046] Figure 2A and Figure 2B is a waveform diagram showing an example of a 4-phase clock signal and a write clock. Figure 2A shows a case where the storage controller generates first through fourth clocks I, Q, IB, and QB and generates the write clock WCK from the first through fourth clocks I, Q, IB, and QB. In addition, Figure 2B shows a case where data is serialized based on the 4-phase clock signal.

[0047] Reference Figure 1 and Figure 2A and Figure 2B, the first to fourth clocks I, Q, IB, and QB may have a phase difference of 90 degrees in sequence therebetween. In addition, a write clock WCK may be generated using the first to fourth clocks I, Q, IB, and QB. For example, the write clock WCK may have a logic high level synchronized with the first clock I and the third clock IB, and may have a logic low level synchronized with the second clock Q and the fourth clock QB. In addition, when the write clock WCK is used as the monitoring signal Sig_M during the training process, the write clock WCK has a logic level corresponding to the value of the data pattern synchronously with the edges of the first to fourth clocks I, Q, IB, and QB. Therefore, a monitoring signal Sig_M with various waveforms can be generated.

[0048] As described above, due to various factors in the storage controller 100, distortion may occur in the duty cycle / skew of the first to fourth clocks I, Q, IB, and QB, and such distortion generated in the duty cycle / skew may be reflected in the monitoring signal Sig_M. For example, the waveform of the monitoring signal Sig_M may be distorted due to the distortion of the duty cycle / skew generated in the first to fourth clocks I, Q, IB, and QB. According to the above embodiments, the duty cycle / skew of the first to fourth clocks I, Q, IB, and QB can be corrected by monitoring the duty cycle of the monitoring signal Sig_M based on data patterns with various values.

[0049] Figure 2B The case where the storage controller 100 serializes and outputs the first to fourth data D1 to D4 is shown. For example, the storage controller 100 may include a serializer 151, and the serializer 151 may be provided in the first interface circuit 150. The serializer 151 may sequentially output the first to fourth data D1 to D4 synchronously with the first to fourth clocks I, Q, IB, and QB.

[0050] In an example operation, the serializer 151 may output the first to fourth data D1 to D4 based on a selection signal generated using the first to fourth clocks I, Q, IB, and QB. For example, a first selection signal SEL0 may be generated using the fourth clock QB and the first clock I, and the rising edge of the first selection signal SEL0 may be synchronized with the first clock I. The serializer 151 may output the first data D1 synchronously with the first selection signal SEL0.

[0051] The second selection signal SEL90 can be generated using the first clock I and the second clock Q, and the serializer 151 can output the second data D2 in synchronization with the second selection signal SEL90. The third selection signal SEL180 can be generated using the second clock Q and the third clock IB, and the serializer 151 can output the third data D3 in synchronization with the third selection signal SEL180. The fourth selection signal SEL270 can be generated using the third clock IB and the fourth clock QB, and the serializer 151 can output the fourth data D4 in synchronization with the fourth selection signal SEL270.

[0052] Figure 3 FIG. 4 is a block diagram illustrating an example of a memory controller 310 and a memory system 300 including the memory controller 310 according to one or more example embodiments.

[0053] Referring Figure 3 , the memory system 300 may include a memory controller 310 and a memory device 330. Further, the memory controller 310 may include a phase-locked loop (PLL) 311, a four-phase clock generator 312, a skew adjuster (SA) 313, a duty cycle adjuster 314, a first multiplexer (4:1 MUX) 315 and a second multiplexer (4:1 MUX) 316, a code controller 317, a data receiver (DQ Rx) 318, a delay line 319, a data duty cycle adjuster 320, a data transmitter (DQ Tx) 321, and a write clock transmitter (WCKTx) 322. Further, a DRAM may be an example of the memory device 330, and the memory device 330 may include a data transmitter 331, a data receiver 332, a write clock receiver (WCK Rx) 333, a frequency divider 334, a driver 335, a serializer (SER) 336, and a duty cycle monitor 337. Although Figure 3 not shown in FIG. 4, various other components related to writing and reading data may also be provided in each of the memory controller 310 and the memory device 330. Further, the duty cycle adjuster may be referred to as a duty cycle adjustor (DCA), and the duty cycle monitor may be referred to as a duty cycle monitor (DCM). In the following embodiments, the terms “duty cycle” and “duty degree” may be used interchangeably with the same meaning.

[0054] The phase-locked loop 311 can generate a reference clock with a specific frequency, and the four-phase clock generator 312 can generate a multi-phase clock signal (e.g., the first clock to the fourth clock I, Q, IB, and QB). The skew regulator 313 and the duty cycle regulator 314 can be arranged corresponding to each of the first clock to the fourth clock I, Q, IB, and QB. The skew regulator 313 can adjust the skew of the clock based on a specific control code (e.g., the skew control code), and the duty cycle regulator 314 can adjust the duty cycle of the clock based on a specific control code (e.g., the duty cycle control code).

[0055] Each of the first multiplexer 315 and the second multiplexer 316 can perform a sampling operation based on the first clock to the fourth clock I, Q, IB, and QB. For example, each of the first multiplexer 315 and the second multiplexer 316 can be synchronized with the first clock to the fourth clock I, Q, IB, and QB, or perform the sampling operation synchronously with a selection signal (not shown) generated using the first clock to the fourth clock I, Q, IB, and QB. In the following embodiments, each of the first multiplexer 315 and the second multiplexer 316 is described as operating synchronously with the first clock to the fourth clock I, Q, IB, and QB. However, the embodiments are not necessarily limited thereto. In addition, the operation synchronized with the first clock to the fourth clock I, Q, IB, and QB and the operation synchronized with the selection signal can be defined as substantially the same concept.

[0056] The first multiplexer 315 can receive the first data D1 to the fourth data D4 in parallel and includes a serializer that serially outputs the first data D1 to the fourth data D4 synchronously with the first clock to the fourth clock I, Q, IB, and QB. In addition, the second multiplexer 316 can operate as a write clock generator that generates a write clock WCK. For example, the second multiplexer 316 can receive a data pattern having a plurality of bits (e.g., four bits D1' to D4') and generate a write clock WCK having a logic level corresponding to the data pattern at the edge timing of the first clock to the fourth clock I, Q, IB, and QB. In addition, during the training process, the write clock WCK can be used as a monitoring signal Sig_M. The write clock transmitter 322 can output the monitoring signal Sig_M to the storage device 330.

[0057] In addition, the delay line 319 can adjust the delay of the first data D1 to the fourth data D4 output from the first multiplexer 315, and the data duty cycle regulator 320 can adjust the duty cycle of the first data D1 to the fourth data D4. In addition, the data transmitter 321 can output the first data D1 to the fourth data D4 to the storage device 330.

[0058] The write clock receiver 333 of the storage device 330 can receive a write clock WCK from the storage controller 310, and can generate a four-phase clock signal from the write clock WCK through a frequency divider 334 and a driver 335. The four-phase clock signal can be provided to the serializer 336 of the storage device 330, and the serializer 336 can serialize data synchronously with the four-phase clock signal to send it to the storage controller 310. The data transmitter 331 can sequentially output a plurality of data provided from the serializer 336 to the storage controller 310. In addition, during the training process, the write clock receiver 333 can receive the write clock WCK as a monitoring signal Sig_M, and provide the monitoring signal Sig_M to the duty cycle monitor 337.

[0059] The duty cycle monitor 337 can monitor the duty cycle of the monitoring signal Sig_M having various waveforms, and generate duty cycle information Info_D including the monitoring result. The duty cycle information Info_D can be provided to the storage controller 310 via various transmission paths. In an embodiment, the duty cycle information Info_D can be sent to the storage controller 310 via the data transmitter 331. However, the embodiment is not necessarily limited thereto, and the duty cycle information Info_D can be sent to the storage controller 310 via various other transmission paths.

[0060] According to an embodiment, the data receiver 318 of the storage controller 310 can receive the data output from the storage device 330, and can also receive the duty cycle information Info_D. The code controller 317 can generate various control codes based on the duty cycle information Info_D during the training process. For example, the code controller 317 can generate a skew control code for controlling the skew regulator 313 and a duty cycle control code for controlling the duty cycle regulator 314. In addition, the code controller 317 can also generate one or more control codes for controlling the delay line 319 and the data duty cycle regulator 320.

[0061] The storage controller 310 and the storage device 330 can transmit data to each other via multiple data channels. Therefore, the first multiplexer 315, the delay line 319, the data duty cycle regulator 320, and the data transmitter 321 can each be provided in multiple numbers and arranged corresponding to the multiple data channels. In addition, Figure 3 The embodiment shows the case where the skew regulator 313 and the duty cycle regulator 314 are commonly arranged for a plurality of first multiplexers 315. However, the skew regulator 313 and the duty cycle regulator 314 can be arranged separately from each other for each of the plurality of first multiplexers 315.

[0062] Figure 4 is a block diagram showing an example of the transmission of duty cycle information according to one or more example embodiments. Figure 4Schematically shows a configuration related to the generation and transmission of duty cycle information in a storage system 400 including a storage controller 410 and a storage device 430.

[0063] The processor 411 of the storage controller 410 may control a training operation according to an embodiment. The multi-phase clock generator 412 may generate first to fourth clocks (not shown) as multi-phase clock signals according to the above embodiment, and a write clock WCK or a monitoring signal Sig_M generated based on the first to fourth clocks may be output to the storage device 430. The write clock receiver 431 of the storage device 430 may receive the monitoring signal Sig_M, and the duty cycle monitor 432 may generate duty cycle information Info_D representing the result of monitoring the duty cycle of the monitoring signal Sig_M.

[0064] Various signals may be transmitted and received between the storage controller 410 and the storage device 430 via various paths. For example, the storage device 430 may send the duty cycle information Info_D to the storage controller 410 using pins defined in the LPDDRx specification (e.g., LPDDR4, LPDDR5, and LPDDR6). For example, the duty cycle information Info_D may be provided to the storage controller 410 via a mode register set (MRS) pin among the multiple pins defined in the LPDDRx specification.

[0065] The duty cycle monitor 432 may generate the duty cycle information Info_D and store the duty cycle information Info_D in the MRS 433. The storage device 430 may include one or more MRS pins for storing information in the MRS 433 or reading information from the MRS 433 by communicating with the storage controller 410, and the duty cycle information Info_D read from the MRS 433 may be provided to the storage controller 410 via the MRS pins. For example, the storage controller 410 may receive the duty cycle information Info_D stored in the MRS 433 via an MRS read command (MRR). Based on the value of the duty cycle information Info_D, the duty cycle regulator 413 may adjust the duty cycle of the first to fourth clocks, and the skew regulator 414 may adjust the skew of the first to fourth clocks.

[0066] The memory controller 410 may also generate a control code Ctrl Code to adjust the duty cycle / skew of various clock signals used in the memory device 430, and the memory controller 410 may store the control code Ctrl Code in the MRS 433 via a MRS write command (MRW). A circuit (not shown) for adjusting the duty cycle / skew of various clock signals may be provided inside the memory device 430, and the duty cycle / skew of the clock signals in the memory device 430 may be adjusted based on the control code Ctrl Code stored in the MRS 433.

[0067] Figure 4 The case where the duty cycle information Info_D is transmitted via the MRS pin is shown. However, as described above, the duty cycle information Info_D may be transmitted via the data (DQ) pins for inputting and outputting data DQ or other types of pins.

[0068] Figure 5 FIG. is a block diagram of a SoC employing a memory controller according to one or more example embodiments. A configuration including the SoC and the memory device 530 may be referred to as a memory system or a data processing system.

[0069] As Figure 5 shown, the memory system 500 may include an AP 510 and a memory device 530, and the AP 510 may be configured as a SoC. The memory device 530 may include a cell array 531, a control logic 532, and an interface circuit 533, and the interface circuit 533 may include a double data rate physical interface (DDR PHY).

[0070] The AP 510 may include various intellectual properties (IPs). For example, the AP 510 may include a processor 511 for controlling all operations of the memory system 500 and a memory 512 for storing instructions executable by the processor 511. According to one or more example embodiments, instructions for controlling a training operation may be stored in the memory 512 as a training module, and the processor 511 may control the training operation according to the embodiment described above by executing the training module. For example, the processor 511 may control the training circuit 514_2 based on the result of executing the training module.

[0071] The AP 510 may further include a memory control module (MCU) 513 configured to control access to the storage device 530 based on the control of the processor 511, and a DDR PHY 514 configured to provide a memory interface. The DDR PHY 514 may include input / output (I / O) circuits 514_1 and training circuits 514_2, and components (not shown) for generating various clock signals according to the above embodiments and adjusting the duty cycle / skew of the clock signals and data based on the training results may also be provided in the DDR PHY 514. For example, the MCU 513 and the DDR PHY 514 may include components of the memory controller in the above embodiments.

[0072] The input / output circuits 514_1 may include transmitters and receivers according to the above embodiments, and may transmit various signals to and receive various signals from the interface circuit 533 of the storage device 530 during the training process according to the embodiments. For example, a write clock WCK generated based on a 4-phase clock signal and / or a monitoring signal Sig_M may be provided to the storage device 530 via the input / output circuits 514_1, and duty cycle information Info_D may be received from the storage device 530 via the input / output circuits 514_1. Additionally, the duty cycle / skew of the 4-phase clock signal and data may be corrected inside the AP 510 based on the duty cycle information Info_D.

[0073] Figure 6 is a flowchart showing a method of operating a memory controller according to one or more example embodiments.

[0074] Reference Figure 6 , the memory controller may perform a plurality of training processes related to the correction of the duty cycle / skew of the N-phase clock signal and data. The training operation including a plurality of training processes according to one or more example embodiments is not necessarily limited to Figure 6 the flow order shown, and the order of the training processes may be changed.

[0075] The storage controller can enter a training mode (S11) and perform training to adjust the duty cycle of each of the N-phase clock signals during a first training process (S12). For example, during the first training process, a monitoring signal corresponding to the waveform of each of the N-phase clock signals can be generated, and an operation of monitoring the duty cycle of the monitoring signal can be performed while changing the duty cycle of each of the N-phase clock signals (or changing the duty cycle control code from a minimum value to a maximum value). In an embodiment, the storage controller can generate a monitoring signal using the N-phase clock signals and send the monitoring signal to the storage device, and the storage device can send duty cycle information according to the duty cycle monitoring result of the monitoring signal to the storage controller. The storage controller can set a duty cycle control code for each of the N-phase clock signals based on the duty cycle information received from the storage device.

[0076] In addition, the storage controller can perform training to adjust the skew of at least one of the N-phase clock signals during a second training process (S13). For example, during the second training process, a monitoring signal corresponding to the waveform of each of the N-phase clock signals can be generated, and an operation of monitoring the duty cycle of the monitoring signal can be performed while changing the skew of at least one of the N-phase clock signals (or changing the skew control code from a minimum value to a maximum value). The storage controller can perform a skew correction operation by setting at least one skew control code of the N-phase clock signals based on the duty cycle information received from the storage device, such that the phase difference between the N-phase clock signals has a constant value.

[0077] The storage controller can perform training to adjust the data duty cycle of each of the multiple data during a third training process (S14). For example, a delay line and a data duty cycle regulator can be arranged in the data transmission path inside the storage controller. During the third training process, an operation of measuring the effective window size of the data can be repeatedly performed while changing the delay and duty cycle of the data. For example, the storage controller can send and write the data to the storage device while changing the delay and duty cycle, and can measure the effective window size of the data by comparing the written data with the data read from the storage device.

[0078] The storage controller can set a data duty cycle control code for optimizing the data duty cycle based on the measured effective window size. If the storage controller sends data to the storage device via multiple data channels, the above data duty cycle control code can be set for the data corresponding to each of the multiple data channels.

[0079] In addition, in the embodiment, the storage controller may include a plurality of serializers that serialize output data, and a separate skew adjuster may be provided corresponding to each of the plurality of serializers. Each of the plurality of serializers may receive an N-phase clock signal, and the skew adjuster may adjust the skew of the N-phase clock signal supplied to the corresponding serializer. During the fourth training process, the storage controller may perform training to measure the effective window size of the data while changing the skew of at least one of the N-phase clock signals for the data output via each serializer, and set the skew control codes of the plurality of skew adjusters corresponding to the plurality of serializers based on the measurement result of the effective window size (S15). Through the above fourth training process, skew control codes that can optimally correct the skew of the N-phase clock signal for each data can be set for multiple data channels having different signal transmission characteristics.

[0080] When the training operation according to the above embodiment and other training operations for various other signals and data are completed, the training mode may be ended (S16).

[0081] Hereinafter, an example of the training operation according to the embodiment is described. In the following embodiment, the first clock to the fourth clocks I, Q, IB, and QB are described as multi-phase clock signals, and a plurality of operations in each training process are described for the first clock to the fourth clocks I, Q, IB, and QB and the data. However, the embodiment is not necessarily limited to the scope described below, and the training order for the clocks and data and the execution order or method for the plurality of operations in each training process may be changed in various ways.

[0082] Figure 7 The waveforms of the first selection signal SEL0 to the fourth selection signal SEL270 are shown when the duty cycles of the first clock to the fourth clocks I, Q, IB, and QB are distorted.

[0083] Figure 7 An example in which the duty cycles of the first clock I and the third clock IB are distorted is shown. Since the duty cycle of at least one of the first clock to the fourth clocks I, Q, IB, and QB is distorted, the pulse widths and edge timings of the first selection signal SEL0 to the fourth selection signal SEL270 are distorted. In this case, the effective window margin is reduced during high-speed data input / output operations, which results in deterioration of the data input / output characteristics.

[0084] Figure 8A and Figure 8BFIG. is a diagram illustrating an example of a training process for adjusting a duty cycle of a multi-phase clock signal. As described above, the operation of correcting the duty cycle of the multi-phase clock signal according to one or more example embodiments may be performed based on monitoring the duty cycle of the write clock WCK corresponding to the monitoring signal. Accordingly, the training process for correcting the duty cycle of the multi-phase clock signal may belong to the training operation for the write clock WCK.

[0085] Reference Figure 8A , regarding the duty cycle adjustment of the multi-phase clock signal, four bits of the data pattern in the first operation may have a value of "1100". Accordingly, the waveform of the write clock WCK generated synchronously with the first clock to the fourth clock I, Q, IB, and QB may have a waveform corresponding to the first clock I. For example, since the first clock I and the third clock IB have inverted waveforms, the falling edge timing of the first clock I may be the same as the rising edge timing of the third clock IB. Therefore, the write clock WCK may change to a logic low level at the timing of the falling edge of the first clock I.

[0086] For example, the memory controller may provide the write clock WCK generated while the duty cycle control code of the duty cycle adjuster that adjusts the duty cycle of the first clock I changes from the minimum value (min) to the maximum value (max) to the memory device, and may compare the size of the logic high part of the first clock I with the size of the logic low part of the first clock I based on the value of the duty cycle information Info_D provided from the memory device. For example, when, as a result of the duty cycle monitoring of the write clock WCK, the logic high part is smaller than the logic low part, the duty cycle information Info_D of the first value (for example, the value is "0") may be provided. On the other hand, when the logic high part is larger than the logic low part, the duty cycle information Info_D of the second value (for example, the value is "1") may be provided. The memory controller may determine the duty cycle control code when the value of the duty cycle information Info_D changes from the first value to the second value, and may set the duty cycle control code determined in the first operation as the duty cycle control code for adjusting the duty cycle of the first clock I.

[0087] In addition, as Figure 8BAs shown, the data pattern may have a value of "0110" in the second operation. Accordingly, the waveform of the write clock WCK may have a waveform corresponding to the second clock Q, and the duty cycle of the second clock Q may be adjusted in the second operation. For example, the value of the duty cycle information Info_D provided from the storage device may be determined while changing the duty cycle control code of the duty cycle adjuster that adjusts the duty cycle of the second clock Q from the minimum value (min) to the maximum value (max). In addition, the storage controller may determine the duty cycle control code when the value of the duty cycle information Info_D changes from the first value to the second value, and may set the determined duty cycle control code as the duty cycle control code for adjusting the duty cycle of the second clock Q.

[0088] Although not shown, similar to the first operation and the second operation described above, the data pattern in the third operation may have a value of "0011". Accordingly, the waveform of the write clock WCK may have a waveform corresponding to the third clock IB, and the duty cycle of the third clock IB may be adjusted in the third operation. In addition, the data pattern in the fourth operation may have a value of "1001". Accordingly, the waveform of the write clock WCK may have a waveform corresponding to the fourth clock QB, and the duty cycle of the fourth clock QB may be adjusted in the fourth operation.

[0089] Based on the above process, the duty cycle of each of the first clock to the fourth clock I, Q, IB, and QB can be corrected. Accordingly, the waveform characteristics of the first selection signal SEL0 to the fourth selection signal SEL270 generated based on this correction can be improved.

[0090] Although the duty cycle of each of the first clock to the fourth clock I, Q, IB, and QB is corrected through the above training process, there may still be skews in the first clock to the fourth clock I, Q, IB, and QB. According to an embodiment, the training process for correcting the skews of the first clock to the fourth clock I, Q, IB, and QB can be performed as follows.

[0091] Figures 9 to 11A and Figure 11B is a diagram showing an example of a training process for adjusting the skew of a multi-phase clock signal according to one or more example embodiments. As described above, the operation of correcting the skew of the multi-phase clock signal can also be performed based on monitoring the duty cycle of the write clock WCK. Accordingly, in the training process for adjusting the skew of the multi-phase clock signal, a write clock WCK having various waveforms can be generated as a monitoring signal.

[0092] As Figure 9As shown, even after correcting the duty cycle of each of the first to fourth clocks I, Q, IB, and QB, skew may still exist in at least one of the first to fourth clocks I, Q, IB, and QB. In this case, distortion occurs in the waveforms of the first selection signal SEL0 to the fourth selection signal SEL270. For example, Figure 9 shows a case where distortion occurs in the waveforms of the third selection signal SEL180 and the fourth selection signal SEL270 when there is skew in the third clock IB. In this case, the effective window margin decreases during high-speed data input / output operations.

[0093] Refer to Figure 10A , regarding skew adjustment of the multi-phase clock signal, in the first operation, the skew between the first clock I and the third clock IB can be corrected by adjusting the skew of at least one of the first clock I and the third clock IB. For example, in the first operation, the data pattern can have a value of "1100" as the non-inverting value and a value of "0011" as the inverting value. Accordingly, a write clock WCK having a waveform corresponding to the first clock I and a waveform corresponding to the third clock IB can be generated as a monitoring signal. Additionally, the duty cycle of the write clock WCK can be monitored while adjusting the skew of at least one of the first to fourth clocks I, Q, IB, and QB. For example, the duty cycle of the write clock WCK generated while changing the skew control code of the third clock IB from the minimum value (min) to the maximum value (max) can be monitored.

[0094] In Figure 10A the case of the write clock WCK shown in the upper part, the waveform of the write clock WCK can change from logic high to logic low synchronously with the third clock IB. When the skew control code for the third clock IB has the minimum value (min), the logic high part of the write clock WCK can be relatively narrow. Additionally, the duty cycle of the write clock WCK can be monitored while increasing the value of the skew control code. As the logic high part of the write clock WCK gradually increases, the skew control code can be determined at the timing when the value of the duty cycle information Info_D changes from the first value to the second value.

[0095] Similarly, in Figure 10A the case of the write clock WCK shown in the lower part, the waveform of the write clock WCK can change from logic low to logic high synchronously with the third clock IB. When the skew control code for the third clock IB has the minimum value (min), the logic high part of the write clock WCK can be relatively wide. Additionally, the duty cycle of the write clock WCK can be monitored while increasing the value of the skew control code. The skew control code can be determined at the timing when the value of the duty cycle information Info_D changes from the second value to the first value.

[0096] In an embodiment, the average value or the median value of two skew control codes determined using a non-inverted value and an inverted value can be applied as the skew control code for the third clock IB. For example, if a skew control code with a value of 0 is determined when using the non-inverted value, and a skew control code with a value of +2 is determined when using the inverted value, the +1 value corresponding to the average value can be set as the skew control code for the third clock IB. Through the first operation of the above training process, the skew between the first clock I and the third clock IB can be corrected.

[0097] Figure 10B Shows the case where the rising edge and the falling edge of the logic level of the third clock IB are delayed due to the skew control operation for Figure 10A the third clock IB. Therefore, the skew between the first clock I and the third clock IB is corrected, and the waveforms of the third selection signal SEL180 and the fourth selection signal SEL270 are also corrected.

[0098] As Figure 11A shown, regarding the skew adjustment of the multi-phase clock signal, the skew between the second clock Q and the fourth clock QB can be corrected in the second operation. For example, in the second operation, the data pattern can have a value of "0110" as the non-inverted value and a value of "1001" as the inverted value. Accordingly, a write clock WCK having a waveform corresponding to the second clock Q and a waveform corresponding to the fourth clock QB can be generated as a monitoring signal. In addition, the duty cycle of the write clock WCK generated while changing the skew control code of the fourth clock QB from the minimum value (min) to the maximum value (max) can be monitored.

[0099] According to the result of monitoring the duty cycle of the write clock WCK while changing the skew control code of the fourth clock QB, a skew control code can be determined using "0110" as the non-inverted value during the monitoring process, and a skew control code can be determined using "1001" as the inverted value during the monitoring process. The average value of two skew control codes determined by using the non-inverted value and the inverted value can be set as the skew control code for the fourth clock QB. Through the second operation of the above training process, the skew between the second clock Q and the fourth clock QB can be corrected.

[0100] As Figure 11BAs shown, regarding the skew adjustment of the multi-phase clock signal, the skew between the first clock I and the second clock Q can be corrected in the third operation, and the skew between the third clock IB and the fourth clock QB can also be corrected. In the third operation, the data pattern can have a "1010" value as the non-inverted value and a "0101" value as the inverted value. Accordingly, a write clock WCK with complementary waveforms and a frequency twice that of the 4-phase clock signal can be generated as a monitoring signal. In addition, the duty cycle of the write clock WCK generated while changing the skew control codes of the second clock Q and the fourth clock QB from the minimum value (min) to the maximum value (max) can be monitored.

[0101] In an embodiment, when the skew control code of the fourth clock QB is preset in a previous operation, the value of the skew control code set for the fourth clock QB can be applied as an offset. For example, when adjusting the skew of the fourth clock QB, if the skew control code calculated in the second operation corresponds to +2, the skew control code of the fourth clock QB in the third operation can gradually increase from one value (min + 2). That is, a skew control code with a value of +2 has been set for the fourth clock QB in the previous second operation, such that the second clock Q and the fourth clock QB have a 180-degree phase difference. In the third operation, an offset of +2 is applied to the skew control code of the fourth clock QB. Accordingly, the monitoring operation can be performed while maintaining the 180-degree phase difference between the second clock Q and the fourth clock QB and adjusting the skew of the second clock Q and the fourth clock QB.

[0102] Regarding the second clock Q, both the skew control code when using the non-inverted value and the skew control code when using the inverted value can be determined based on the result of monitoring the duty cycle of the write clock WCK. The average value of the two determined skew control codes can be set as the skew control code for the second clock Q. In addition, regarding the fourth clock QB, both the skew control code when using the non-inverted value and the skew control code when using the inverted value can be determined based on the result of monitoring the duty cycle of the write clock WCK in the above manner. The average value of the two determined skew control codes can be set as the skew control code for the fourth clock QB. Through the third operation of the above training process, the skew between the first clock I and the second clock Q can be corrected, and the skew between the third clock IB and the fourth clock QB can also be corrected.

[0103] Figure 12 is a flowchart showing an operation method for a storage controller to perform data duty cycle training according to one or more example embodiments.

[0104] Even after correcting the duty cycle and skew of the multi-phase clock signal according to the above embodiments, due to the characteristics of the path for transmitting data, the duty cycle characteristics of the data received by the data receiver of the storage device may not be ideal. To compensate for the distortion of the duty cycle characteristics of the data, the storage controller according to an embodiment may perform data duty cycle training and set a duty cycle control code of a data duty cycle regulator inside the storage controller based on the training result.

[0105] As Figure 12 shown, during the training process of adjusting the duty cycle of the data, the storage controller may perform the following operations: record write data with specific bit values in the storage device, then read the write data from the storage device, and compare the write data with the read data to check whether the write data and the read data are the same as each other. For example, the effective window size of the data may be measured by applying a delay to the data and repeating the operation of comparing the write data with the read data, and the training operation may be performed such that the effective window size of the data is maximized.

[0106] According to one or more example embodiments, during the training process of adjusting the duty cycle of the data, the storage controller may write first data to Nth data to the storage device while changing the duty cycle of the data (S21). Assuming the first data to the fourth data, the first data to the fourth data may have bit values with continuously switching logic levels. For example, the first data and the third data may have a value of "1", and the second data and the fourth data may have a value of "0". The storage controller may generate the above write clock WCK and receive the first data to the fourth data from the storage device synchronously with the write clock WCK (S22).

[0107] As described above, by applying a delay to the first data to the fourth data, the writing and reading of the data are repeatedly performed, and the comparison between the write data and the read data is repeatedly performed. Accordingly, the effective window size for each of the first data to the fourth data may be measured. For example, the effective window size of the data having a logic high level (first size) may be measured (S23), and the effective window size of the data having a logic low level (second size) may be measured (S24). If the first data and the third data are referred to as even data, and the second data and the fourth data are referred to as odd data, then the effective window size of the even data and the effective window size of the odd data may be measured.

[0108] The effective window size of the data having a logic high level may be compared with the effective window size of the data having a logic low level (S25). As the above operation is repeatedly performed while changing the duty cycle of the data, when the portion of the logic high level of the data is shorter than the portion of the logic low level of the data, the first size may be determined to be smaller than the second size.

[0109] As the duty cycle of the data gradually increases, the portion of the data at a logic high level may gradually increase. Based on the result of comparing the first size with the second size, a duty cycle control code at the time point when the first size becomes larger than the second size may be determined. Based on the comparison result of the valid window size, a duty cycle control code for the data may be set (S26).

[0110] Furthermore, according to the above embodiment, the memory controller and the memory device can communicate data with each other via multiple data channels, and a data duty cycle adjuster can be separately arranged corresponding to each data channel. The above data duty cycle adjustment can be performed separately for each data channel, and therefore, different data duty cycle control codes can be set for each data channel.

[0111] Figure 13 、 Figure 14A and Figure 14B is a diagram illustrating an example of performing data duty cycle training according to one or more example embodiments.

[0112] Figure 13 An example of measuring the effective window size is shown, and a case where the first data D1 to the fourth data D4 read from the storage device are received synchronously with the write clock WCK while increasing the delay of the data is shown. As the delay of the first data D1 to the fourth data D4 gradually increases, the point at which the values of the write data and the read data become equal to each other can correspond to the starting point of the effective window size. As the delay of the first data D1 to the fourth data D4 further increases, the point at which the values of the write data and the read data become different from each other can correspond to the end point of the effective window size. The effective window size of each of the first data D1 to the fourth data D4 can be measured based on repeating the writing and reading of the first data D1 to the fourth data D4 while applying the delay as described above.

[0113] For example, the first data D1 and the third data D3 may be sampled at the rising edge of the write clock WCK and referred to as even data. Furthermore, the second data D2 and the fourth data D4 may be sampled at the falling edge of the write clock WCK and referred to as odd data. In an embodiment, a training process for adjusting the duty cycle of data may be performed based on a comparison of the effective window size between the even data and the odd data.

[0114] Figure 14A and Figure 14B An example of a duty ratio control code of setting data according to one or more example embodiments is shown.

[0115] refer to Figure 14A, the process of measuring the above-mentioned effective window size while changing the duty cycle of the data from the minimum value to the maximum value, and the process of comparing the effective window sizes of even data and odd data with each other can be repeatedly executed. In Figure 14A In the first operation of data duty cycle training in

[0116] When the duty cycle of the data has a minimum value, the portion of the logic high level can be shorter than the portion of the logic low level. Accordingly, the effective window size of the odd data can be larger than the effective window size of the even data. Subsequently, in Figure 14A In the waveform shown in the lower part of

[0117] In addition, in Figure 14B In the second operation of data duty cycle training in Figure 14B Even in the second operation of data duty cycle training, the operation of comparing the effective window size of the even data with the effective window size of the odd data while changing the duty cycle of the data can be performed. Additionally, in

[0118] Figure 15 FIG.

[0119] Each of the first serializer 610 and the second serializer 620 can receive the first to fourth clocks I, Q, IB, and QB, and separate skew adjusters can be arranged corresponding to the first serializer 610 and the second serializer 620. Therefore, the memory controller 600 may include a first skew adjuster 611 corresponding to the first serializer 610 and a second skew adjuster 621 corresponding to the second serializer 620. In addition, a separate delay line, a separate data duty cycle adjuster, and a separate data output unit can be arranged corresponding to each serializer, and the output data (DQ[0, 1]) can be output in parallel to the memory device via multiple data channels.

[0120] When taking a 4-phase clock signal as an example, each of the first serializer 610 and the second serializer 620 can sequentially output the first data D1 to the fourth data D4 according to the above embodiment. In addition, the data channels can have different channel characteristics. Therefore, when the first to fourth clocks I, Q, IB and QB having the same waveform are jointly provided to the first serializer 610 and the second serializer 620, the different channel characteristics cannot be reflected. Accordingly, the effective window characteristics of the data can vary for each data channel. According to an embodiment, multiple skew control codes with different values can be set for each data channel through a training process. Therefore, the first skew control code Code_SA1 can be provided to the first skew adjuster 611, and the second skew control code Code_SA2 can be provided to the second skew adjuster 621.

[0121] Figure 16A 、 Figure 16B 、 Figure 16C and Figure 17 is a diagram illustrating an example of setting a skew control code for each data lane according to one or more example embodiments. Figure 16A 、 Figure 16B 、 Figure 16C and Figure 17 The case where the skew control code is set for the skew adjuster arranged corresponding to one serializer is shown, and the skew control code can be set for the skew adjuster arranged corresponding to another serializer by the same method.

[0122] According to one or more example embodiments, a training process for correcting the skew of a multi-phase clock signal for each data channel may be performed, and the training process may be performed based on measuring the effective window size of the data according to the above-described embodiment. For example, as described above, the effective window size may be measured by comparing write data with read data while varying the delay of the data on the transmission path from a minimum value to a maximum value. In an embodiment, the effective window size measurement may be performed while varying the skew of at least one of the multi-phase clock signals.

[0123] In an embodiment, the above training process may include a first operation to a third operation. In Figure 16A the first operation shown, the skew between the first clock I and the third clock IB may be adjusted. For example, the first data D1 to the fourth data D4 are received from the storage device synchronously with the write clock WCK, and the valid window size of each of the first data D1 to the fourth data D4 is measured. Accordingly, the valid window size of each of the first data D1 to the fourth data D4 may be measured while changing the skew control code of the third clock IB from the minimum value (min) to the maximum value (max). In addition, when the skew control code of the third clock IB has the minimum value (min), the valid window size of the second data D2 may be measured to be smaller, but the valid window size of the third data D3 may be measured to be larger. In addition, as the skew control code of the third clock IB gradually increases, the valid window size of the second data D2 may gradually increase, but the valid window size of the third data D3 may gradually decrease.

[0124] In Figure 16A the example, the sum of the valid window sizes of the first data D1 and the second data D2 may be compared with the sum of the valid window sizes of the third data D3 and the fourth data D4. In addition, as the skew control code of the third clock IB gradually increases, the sum of the valid window sizes of the first data D1 and the second data D2 may gradually increase. The skew control code at the time point when the sum of the valid window sizes of the first data D1 and the second data D2 becomes greater than the sum of the valid window sizes of the third data D3 and the fourth data D4 may be set as the skew control code for the third clock IB. Additionally, in Figure 16A the example, the skew between the first clock I and the third clock IB may be corrected by setting the skew control code for the third clock IB.

[0125] Similarly, Figure 16B the second operation shown shows the case of correcting the skew between the second clock Q and the fourth clock QB. The valid window size of each of the first data D1 to the fourth data D4 may be measured while changing the skew control code of the fourth clock QB from the minimum value (min) to the maximum value (max). In Figure 16B the example, the sum of the valid window sizes of the second data D2 and the third data D3 may be compared with the sum of the valid window sizes of the first data D1 and the fourth data D4. In addition, the skew control code at the time point when the sum of the valid window sizes of the second data D2 and the third data D3 becomes greater than the sum of the valid window sizes of the first data D1 and the fourth data D4 may be set as the skew control code for the fourth clock QB.

[0126] Additionally, Figure 16CThe third operation shown corrects the skew between the first clock I and the second clock Q. The effective window size of each of the first data D1 to the fourth data D4 can be measured while changing the skew control codes of the second clock Q and the fourth clock QB from the minimum value (min) to the maximum value (max). In Figure 16C example, the sum of the effective window sizes of the first data D1 and the third data D3 can be compared with the sum of the effective window sizes of the second data D2 and the fourth data D4. Additionally, the skew control codes of the second clock Q and the fourth clock QB at the time point when the sum of the effective window sizes of the first data D1 and the third data D3 becomes greater than the sum of the effective window sizes of the second data D2 and the fourth data D4 can be determined. Furthermore, in Figure 16C the embodiment shown, the skew control code for the fourth clock QB has been set in the second operation. Therefore, similar to the embodiment shown in Figure 11B , when changing the skew control code of the fourth clock QB in the third operation in Figure 16C , the code value of the skew control code set in the second operation in Figure 16B can be applied as an offset to the skew control code of the fourth clock QB. Additionally, due to applying this offset to the skew control code of the fourth clock QB, the skew between the first clock I and the second clock Q can be corrected while maintaining the corrected state of the skew between the second clock Q and the fourth clock QB after performing the third operation.

[0127] Figure 17 shows an Figure 16A example of setting the skew control code for the third clock. For example, in the case of the waveform shown in the upper part of Figure 17 , since the skew control code of the third clock IB has the minimum value, the effective window size of the second data D2 is relatively small, but the effective window size of the third data D3 is relatively large. Accordingly, the sum of the effective window sizes of the first data D1 and the second data D2 is less than the sum of the effective window sizes of the third data D3 and the fourth data D4.

[0128] On the other hand, in the case of the waveform shown in the lower part of Figure 17 , as the skew control code of the third clock IB gradually increases, there is a time point when the sum of the effective window sizes of the first data D1 and the second data D2 becomes greater than the sum of the effective window sizes of the third data D3 and the fourth data D4. This indicates that the code value at this time point corresponds to the optimal skew control code for the third clock IB. Although not shown in Figure 17 , the remaining second operation and third operation of the training process for correcting the skew of the multi-phase clock signal for each data channel can be described in a similar manner to the waveform diagram shown in Figure 17 .

[0129] According to an example embodiment, at least one of the components, elements, modules, or units described herein may be embodied as various numbers of hardware, software, and / or firmware structures that perform the corresponding functions described above. For example, at least one of these components, elements, or units may use a direct circuit structure, such as a memory, a processor, a logic circuit, a lookup table, etc., which may perform the corresponding functions under the control of one or more microprocessors or other control devices. In addition, at least one of these components, elements, or units may be specifically implemented by a module, a program, or a code portion that includes one or more executable instructions for performing a specific logic function and is executed by one or more microprocessors or other control devices. In addition, at least one of these components, elements, or units may also include or be implemented by a processor, such as a central processing unit (CPU), a microprocessor, etc., that performs the corresponding functions. Two or more of these components, elements, or units may be combined into a single component, element, or unit that performs all the operations or functions of the combined two or more components, elements, or units. In addition, at least part of the functions of at least one of these components, elements, or units may be performed by another of these components, elements, or units. In addition, although a bus is not shown in the block diagram, communication between the components, elements, or units may be performed via a bus. The functional aspects of the above example embodiments may be implemented in an algorithm executed on one or more processors. In addition, the components, elements, or units represented by the blocks or the processing operations may employ any number of related technologies for electronic configuration, signal processing and / or control, data processing, etc.

[0130] In addition, the example embodiments have been described as being applied to a storage device, a storage controller communicating with the storage device, or a SoC including the storage controller, but the example embodiments are not necessarily limited thereto. For example, the example embodiments may be applied to other types of semiconductor devices that generate a multi-phase clock signal, perform various signal processing using the multi-phase clock signal, and transmit data.

[0131] Although the present disclosure has been specifically shown and described with reference to example embodiments of the present disclosure, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims and their equivalents.

Claims

1. A storage controller, comprising: A multi-phase clock generator configured to generate a first clock to an Nth clock having N different phases, where N is an integer equal to or greater than 2; A write clock generator configured to receive a data pattern and generate monitoring signals having logical states corresponding to bits of the data pattern synchronously with edges of the first clock to the Nth clock during a training process; A duty cycle regulator configured to regulate the duty cycles of the first clock to the Nth clock based on a plurality of duty cycle control codes set during the training process; A skew regulator configured to regulate the skew of at least one of the first clock to the Nth clock based on a skew control code set during the training process; And A training circuit configured to control a training operation for regulating the duty cycles and at least one skew of the first clock to the Nth clock, the training operation including a plurality of training processes including the training process, Wherein, during a first training process of regulating the duty cycles of the first clock to the Nth clock, first monitoring signals to an Nth monitoring signal having waveforms corresponding to the first clock to the Nth clock are generated using data patterns having different values, and the duty cycles of the first clock to the Nth clock are regulated based on results of monitoring the duty cycles of the first monitoring signal to the Nth monitoring signal.

2. The storage controller according to claim 1, wherein, The storage controller is configured to: send the first monitoring signal to the Nth monitoring signal to a storage device, and receive duty cycle information representing results of detecting the duty cycles of the first monitoring signal to the Nth monitoring signal from the storage device.

3. The storage controller according to claim 1, wherein, The duty cycle regulator includes a first duty cycle regulator to an Nth duty cycle regulator configured to regulate the duty cycles of the first clock to the Nth clock respectively, and Wherein, during the first training process, while changing the duty cycles of the first clock to the Nth clock, the duty cycles of the first monitoring signal to the Nth monitoring signal are monitored, and a plurality of duty cycle control codes are set for the first duty cycle regulator to the Nth duty cycle regulator respectively.

4. The storage controller according to claim 1, wherein, The first clock to the Nth clock include a first clock, a second clock, a third clock, and a fourth clock having a 90-degree phase difference in sequence, and Wherein, the data pattern includes four bits sampled synchronously with edges of the first clock, the second clock, the third clock, and the fourth clock.

5. The storage controller according to claim 4, wherein, The first training process includes a first operation, a second operation, a third operation, and a fourth operation, Wherein, during the first operation, a first monitoring signal has a waveform corresponding to the first clock based on a first data pattern with a value of "1100", Wherein, during the second operation, a second monitoring signal has a waveform corresponding to the second clock based on a second data pattern with a value of "0110", Wherein, during the third operation, a third monitoring signal has a waveform corresponding to the third clock based on a third data pattern with a value of "0011", and During the fourth operation, the fourth monitoring signal has a waveform corresponding to the fourth clock based on a fourth data pattern with a value of "1001".

6. The storage controller according to claim 4, wherein, During a second training process for adjusting at least one skew of the first clock, the second clock, the third clock, and the fourth clock, first, second, third, and fourth monitoring signals having waveforms corresponding to the first clock, the second clock, the third clock, and the fourth clock are generated using data patterns with different values, and the duty cycles of the first, second, third, and fourth monitoring signals are monitored while changing at least one skew of the first clock, the second clock, the third clock, and the fourth clock.

7. The storage controller according to claim 6, wherein, The second training process includes a first operation, a second operation, and a third operation, and during the first operation, the first and third monitoring signals are generated, and the skew between the first clock and the third clock is adjusted based on monitoring the duty cycles of the first and third monitoring signals while changing the skew of any one of the first clock and the third clock.

8. The storage controller according to claim 7, wherein, During the second operation, the second and fourth monitoring signals are generated, and the skew between the second clock and the fourth clock is adjusted based on monitoring the duty cycles of the second and fourth monitoring signals while changing the skew of any one of the second clock and the fourth clock.

9. The storage controller according to claim 8, wherein, During the third operation, a fifth monitoring signal having a frequency twice that of each of the first clock, the second clock, the third clock, and the fourth clock is further generated, and the skew between the first clock and the second clock is adjusted based on monitoring the duty cycle of the fifth monitoring signal while changing the skew of the second clock.

10. The storage controller according to claim 1, further comprising: a serializer configured to sequentially output first data to Nth data synchronously with the first clock to the Nth clock for sending to a storage device; and a data duty cycle adjuster configured to adjust the duty cycles of the first data to the Nth data based on a duty cycle control code set for the data duty cycle adjuster, wherein during a second training process for adjusting the duty cycles of the first data to the Nth data, while changing the duty cycles of the first data to the Nth data, the first data to the Nth data are written into the storage device, and the first data to the Nth data output from the storage device are sampled synchronously with a write clock generated by the write clock generator, and wherein an effective window size of even data synchronized with the rising edge of the write clock and an effective window size of odd data synchronized with the falling edge of the write clock among the sampled first data to the Nth data are determined.

11. The storage controller according to claim 10, wherein, During a first operation in the second training process, the even data has a value corresponding to a logic high level, and the odd data has a value corresponding to a logic low level, and wherein a first duty cycle control code is obtained corresponding to a time point when the effective window size of the even data becomes larger than the effective window size of the odd data.

12. The storage controller according to claim 11, wherein, During a second operation in the second training process, the even data has a value corresponding to a logic low level, and the odd data has a value corresponding to a logic high level, wherein a second duty cycle control code is obtained corresponding to a time point when the effective window size of the odd data becomes larger than the effective window size of the even data, and wherein the duty cycle control code set for the data duty cycle regulator corresponds to an average value of the first duty cycle control code and the second duty cycle control code.

13. A method of operating a storage controller, the method comprising: generating a first clock, a second clock, a third clock, and a fourth clock having a 90-degree phase difference from each other; generating monitoring signals corresponding to waveforms of the first clock, the second clock, the third clock, and the fourth clock by sampling bits of a data pattern synchronously with edges of the first clock, the second clock, the third clock, and the fourth clock; sending the monitoring signals to a storage device; receiving, from the storage device, duty cycle information representing a result of monitoring the duty cycle of the monitoring signals; and adjusting the duty cycles of the first clock, the second clock, the third clock, and the fourth clock based on the duty cycle information.

14. The method according to claim 13, wherein, Adjusting the duty cycles of the first clock, the second clock, the third clock, and the fourth clock includes: performing a training process of adjusting the duty cycles of the first clock, the second clock, the third clock, and the fourth clock, the training process including a first operation, a second operation, a third operation, and a fourth operation, wherein, during the first operation, a first monitoring signal having a waveform corresponding to the first clock is generated based on a data pattern having a first value, and the duty cycle of the first clock is adjusted according to a result of monitoring the duty cycle of the first monitoring signal, wherein, during the second operation, a second monitoring signal having a waveform corresponding to the second clock is generated based on a data pattern having a second value, and the duty cycle of the second clock is adjusted according to a result of monitoring the duty cycle of the second monitoring signal, wherein, during the third operation, a third monitoring signal having a waveform corresponding to the third clock is generated based on a data pattern having a third value, and the duty cycle of the third clock is adjusted according to a result of monitoring the duty cycle of the third monitoring signal, and wherein, during the fourth operation, a fourth monitoring signal having a waveform corresponding to the fourth clock is generated based on a data pattern having a fourth value, and the duty cycle of the fourth clock is adjusted according to a result of monitoring the duty cycle of the fourth monitoring signal.

15. The method according to claim 13, wherein, Adjusting the duty cycles of the first clock, the second clock, the third clock, and the fourth clock includes: performing a training process for adjusting the duty cycles of the first clock, the second clock, the third clock, and the fourth clock, where the training process includes: monitoring the duty cycle of the monitoring signal while changing the duty cycles of the first clock, the second clock, the third clock, and the fourth clock, and wherein, for each of the first clock, the second clock, the third clock, and the fourth clock, the code value at the time point when the value of the duty cycle information of the corresponding clock is changed is set as the duty cycle control code for adjusting the duty cycle of the corresponding clock.

16. The method according to claim 13 further comprises: Performing a training process for adjusting the skew of at least one of the first clock, the second clock, the third clock, and the fourth clock, wherein the first operation in the training process for adjusting the skew includes: monitoring the duty cycles of the first monitoring signal and the third monitoring signal having waveforms corresponding to the first clock and the third clock while changing the skew of the third clock, and includes: setting the skew control code of the third clock based on the result of monitoring the duty cycles of the first monitoring signal and the third monitoring signal, and wherein the second operation in the training process for adjusting the skew includes: monitoring the duty cycles of the second monitoring signal and the fourth monitoring signal having waveforms corresponding to the second clock and the fourth clock while changing the skew of the fourth clock, and includes: setting the skew control code of the fourth clock based on the result of monitoring the duty cycles of the second monitoring signal and the fourth monitoring signal.

17. The method according to claim 16, further comprising: Generating a fifth monitoring signal having a frequency twice that of each of the first clock, the second clock, the third clock, and the fourth clock, wherein the third operation in the training process for adjusting the skew includes: setting the skew control code of the second clock based on the result of monitoring the duty cycle of the fifth monitoring signal while changing the skew of the second clock.

18. The method according to claim 13, further comprising: Performing a training process for adjusting the duty cycle of the data provided to the storage device, wherein the training process for adjusting the duty cycle of the data includes: writing the first data, the second data, the third data, and the fourth data into the storage device while changing the duty cycle of the data, and includes: sampling the first data, the second data, the third data, and the fourth data output from the storage device synchronously with a write clock having a frequency twice that of each of the first clock, the second clock, the third clock, and the fourth clock, and wherein, based on the comparison result between the effective window size of the even data synchronized with the rising edge of the write clock and the effective window size of the odd data synchronized with the falling edge of the write clock among the sampled first data, second data, third data, and fourth data, the duty cycle of the data is adjusted.

19. A method of operating a storage controller, the method comprising: Generating a first clock to an Nth clock having a 90-degree phase difference therebetween, where N is an integer equal to or greater than 2; Generating a first monitoring signal to an Nth monitoring signal corresponding to the waveforms of the first clock to the Nth clock based on the first clock to the Nth clock and a data pattern; Adjusting the duty cycle of each of the first clock to the Nth clock based on the result of monitoring the duty cycle of the first monitoring signal to the Nth monitoring signal while changing the duty cycle of the first clock to the Nth clock during a training process; Adjusting the skew of at least one of the first clock to the Nth clock based on the result of monitoring the duty cycle of the first monitoring signal to the Nth monitoring signal while changing the skew of at least one of the first clock to the Nth clock during the training process; Writing first data to Nth data into a storage device while changing the duty cycle of the data, and receiving the first data to the Nth data from the storage device synchronously with a write clock having a frequency twice that of each of the first clock to the Nth clock; And Adjusting the duty cycle of the data based on a comparison result between an effective window size of data received synchronously with the rising edge of the write clock and an effective window size of data received synchronously with the falling edge of the write clock.

20. The method according to claim 19, wherein The storage controller includes a serializer and a skew adjuster, the serializer is configured to sequentially output the first data to the Nth data synchronously with the first clock to the Nth clock, the skew adjuster is arranged corresponding to the serializer, and is configured to adjust the skew of at least one of the first clock to the Nth clock provided to the serializer, and The method further includes: Writing the first data to the Nth data into the storage device while changing the skew of at least one of the first clock to the Nth clock, and receiving the first data to the Nth data from the storage device synchronously with the write clock; and Setting a skew control code for the skew adjuster based on a comparison result between effective window sizes of the received first data to the Nth data.

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