Test method and test equipment for memory device

Abstract

The invention discloses a test method and test equipment for a memory device. The method comprises the steps that a main control chip responds to a power-on operation of a host end and establishes communication connection with a to-be-tested storage device or establishes communication connection with the to-be-tested storage device and a target storage device; the main control chip obtains the test firmware from the first specified address of the to-be-tested memory device and / or directly obtains the test firmware from the target memory device; and the main control chip tests the to-be-tested memory device by using the test firmware. In this way, the testing efficiency of the storage device testing can be improved.

Description

Technical Field

[0001] This application relates to the field of storage, and particularly to a test method and a test device for a storage device. Background Art

[0002] With the progress of technology, storage technology has been continuously developing and innovating. Due to the popularization of computers and the upgrading of the Internet, storage technology has become increasingly important. In order to meet the needs of users in life and work, storage technology has become more and more efficient, reliable, and secure. In the research and development process of storage devices, testing is an essential and important link. When testing storage devices such as flash memory, ATE devices can be used for testing. However, as the capacity of flash memory increases day by day, the testing time becomes longer and longer, and using ATE devices greatly increases the testing cost. Therefore, in order to reduce costs, a testing method using a host, a main controller plus flash memory is usually adopted. The main testing process is that the host sends a test firmware to the main controller, and the main controller runs the firmware in its own memory and tests the connected flash memory. The information generated during the testing process is then sent back by the main controller to the host. But this method first requires the host to have the ability to send firmware, and secondly, the connection between the host and the main controller has a certain limit on the maximum number of connections due to the need for data transmission, which affects the testing efficiency. Summary of the Invention

[0003] The main purpose of this application is to provide a test method and a test device for a storage device, which can improve the testing efficiency of storage device testing.

[0004] To solve the above technical problems, the first technical solution adopted by this application is: to provide a test method for a storage device. The method includes that the main control chip responds to the power-on operation of the host side, establishes a communication connection with the storage device to be tested or establishes a communication connection with the storage device to be tested and the target storage device; the main control chip obtains a test firmware from a first specified address of the storage device to be tested and / or directly obtains a test firmware from the target storage device; the main control chip uses the test firmware to test the storage device to be tested.

[0005] To solve the above technical problems, the second technical solution adopted by this application is: to provide a test device. The test device includes a main control chip and a test interface, and the main control chip is connected to the storage device to be tested through the test interface to implement the method described in the first technical solution.

[0006] To solve the above technical problems, the third technical solution adopted by this application is: to provide a test device, the test device includes a controller and a test interface, the test interface is used to connect the storage device to be tested, the storage device to be tested includes a main control chip and a storage device to be tested, and the controller is connected to the storage device to be tested through the test interface to perform power-on and power-off operations to implement the method described in the first technical solution.

[0007] The beneficial effects of the present application are as follows: By placing the test firmware in the storage device to be tested or the target storage device, after the main control chip is powered on, a communication connection is established between the main control and the storage device, and the test firmware can be read from the storage device to be tested or directly from the target storage device, and then the test firmware is placed in its own memory for operation. The storage device is tested according to the test firmware. The main control no longer needs the host to send the test firmware, but directly obtains it from the storage device. Only the host needs to control the power-on of the main control chip and the storage device, and the main control chip can complete the subsequent test by itself. Compared with the connection method that requires data transmission, the connection method that only needs to implement the power-on connection is simpler and is no longer limited by the number of connections, which can increase the number of main control chips connected to the host and improve the test efficiency of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0009] Figure 1 is a schematic flowchart of the first embodiment of the test method for the storage device of the present application;

[0010] Figure 2 is a schematic flowchart of the second embodiment of the test method for the storage device of the present application;

[0011] Figure 3 is a schematic flowchart of a specific embodiment of the test method for the storage device of the present application;

[0012] Figure 4 is a schematic structural diagram of the first embodiment of the test device of the present application;

[0013] Figure 5 is a schematic structural diagram of the second embodiment of the test device of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0015] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0016] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0017] Refer to Figure 1 , Figure 1 is a schematic flowchart of the first embodiment of the test method for the storage device of this application. The method includes the following steps:

[0018] S11: In response to the power-on operation of the host side, the main control chip establishes a communication connection with the storage device to be tested or establishes a communication connection with the storage device to be tested and the target storage device.

[0019] The main control chip is connected to the host side, and the host side controls the main control chip and the storage device to power on. The storage device can be powered on through the main control chip or directly controlled by the host side to power on. After both the main control chip and the storage device are powered on, the main control chip will establish a communication connection with the storage device. The storage device can include the storage device to be tested or can include the storage device to be tested and the target storage device. The storage device to be tested and the target storage device can be connected or not connected.

[0020] S12: The main control chip obtains the test firmware from the first specified address of the storage device to be tested and / or directly obtains the test firmware from the target storage device.

[0021] S13: The main control chip uses the test firmware to test the storage device to be tested.

[0022] Based on the established communication connection, the main control chip directly reads the test firmware from the storage device. The first specified address is the address where the user previously writes the test firmware. The read test firmware is loaded into the memory of the main control chip, and then the main control chip runs the test firmware to test the storage device. After the test firmware at the first specified address is read, the first specified address can normally participate in the test.

[0023] The ways for the main control chip to obtain the test firmware from the storage device may include the methods described in the following embodiments.

[0024] In one embodiment, the main control chip establishes a communication connection with the storage device to be tested and can obtain the test firmware from the storage device to be tested. The main control chip directly obtains the test firmware from the first specified address of the storage device to be tested. The first specified address is the storage address in the storage device to be tested that the main control chip defaults to read when powered on. When both the main control chip and the storage device to be tested are powered on, the main control chip immediately obtains the test firmware from the storage device to be tested. Usually, there are at least one storage block in the storage device, and the storage block has a corresponding number, such as block 0, block 1, block 2, and so on. In the main control chip, it is usually set to default to read the address of block 0 after power-on. Therefore, the first specified address in this embodiment can be the address of block 0 in the storage device to be tested.

[0025] In another embodiment, the main control chip establishes communication connections with the storage device to be tested and the target storage device. The test firmware is stored in the target storage device. The address where the test firmware is stored is also the storage address in the target storage device that the main control chip defaults to read when powered on. When both the main control chip and the target storage device are powered on, the main control chip immediately obtains the test firmware directly from the target storage device. In this embodiment, the main control chip directly obtains the test firmware from the target storage device, which is a fetching process without the participation of the controller in the host side. Similar to obtaining the test firmware from the storage device to be tested, after the main control chip establishes a communication connection with the target storage device, it directly obtains the test firmware from the target storage device.

[0026] In another embodiment, the main control chip establishes communication connections with the storage device to be tested and the target storage device. The test firmware is stored in both the storage device to be tested and the target storage device. The test firmware in the target storage device can be public test firmware, and the test firmware in the storage device to be tested can be specific test firmware corresponding to the storage device to be tested. In some scenarios, during the test process, the target storage device can be replaced to replace the public test firmware when testing different types of storage devices to be tested, so as to achieve different tests for different storage devices to be tested. The addresses where the test firmware is stored are all the storage addresses that the main control chip will default to read when powered on.

[0027] Different from the conventional technology in which the controller in the host side sends the test firmware to the main control chip, since the test firmware in this application is directly obtained by the main control chip from the storage device and does not interact with the controller in the host side, the interaction process between the main control chip and the host side is reduced, and the requirements for the host side are lowered.

[0028] In this embodiment, by placing the test firmware in the storage device to be tested or the target storage device, after the main control chip is powered on, the main control establishes a communication connection with the storage device, and can read the test firmware from the storage device to be tested or directly from the target storage device, and then place the test firmware in its own memory to run, and test the storage device according to the test firmware. The main control no longer needs the host to send the test firmware, but directly obtains it from the storage device. Only the host needs to control the main control chip and the storage device to be powered on, and the main control chip can complete the subsequent test by itself. The connection method that only needs to implement the power-on connection is simpler than the connection method that needs to perform data transmission, and is no longer limited by the number of connections, which can increase the number of main control chips connected to the host and improve the test efficiency of the storage device.

[0029] In one embodiment, after the main control chip tests the storage device to be tested using the test firmware, in response to the end of the test, the main control chip sends a test end instruction to the host, so that the host performs a power-down operation based on the test end instruction.

[0030] After the main control chip finishes the test, it automatically sends a test end instruction to the host, so that the host controls the main control chip to power down. The user can take away the storage device to be tested that has completed the test according to the power-down situation and replace it with a new storage device to be tested.

[0031] In one embodiment, the test end instruction is a preset level signal sent through a specified pin. Using the level high or low to indicate whether the test is over, only one connection pin is needed to send the level signal to achieve it. The level values are divided into high level and low level, and the high level or low level can be used to indicate the end of the test.

[0032] In one embodiment, after the main control chip tests the storage device to be tested using the test firmware, it can also be that the host itself ends the test process of the storage device to be tested. In response to reaching the preset test time, the host controls the main control chip to power down to end the test.

[0033] Refer to Figure 2 , Figure 2 is a schematic flowchart of the second embodiment of the test method for the storage device of the present application. This method is a further expansion of the above embodiment, and includes the following steps:

[0034] S21: Send the obtained test result to the second specified address of the storage device to be tested.

[0035] After the main control chip tests the storage device to be tested using the test firmware, a test result will be obtained. However, the main control chip does not perform data interaction with the host, but will send the test result to be stored in the storage device to be tested. The test result can include all information generated during the test.

[0036] In one embodiment, the second designated address may not participate in the test process and serve as a reserved address.

[0037] S22: Set a prohibited call flag for the second designated address to prevent normal calls to the second designated address.

[0038] After the test is completed, the main control chip will set a prohibited call flag for the second designated address, so that the second designated address cannot be used for normal read and write operations, avoiding the normal read and write calls from destroying the test results. When the results are needed later, the test results can be read through other means, such as using a burner to read the test results.

[0039] In the normal test process, the host connects to the main control to test the storage device. When the host is connected to multiple main controls, during the test, the host needs to poll and process the test messages returned by different main controls, which will cause a certain degree of delay. In severe cases, it may affect the test on the main control side, and the test needs to wait for the host to process the returned messages before continuing. Therefore, in this embodiment, the test results generated by the main control chip are also placed in the storage device. In this way, there is no need for data transmission such as test firmware or test results between the main control chip and the host side. Only the host side needs to control the power-on and power-off of the main control chip. The main control chip can obtain the test firmware from the storage device, and the main control chip can store the test results in the storage device, reducing the interaction between the main control chip and the host side, greatly reducing the requirements for the host side in the storage device test and the connection requirements for the link between the host side and the main control chip, enabling a single host side to connect more main control chips, and greatly improving the test efficiency of the storage device.

[0040] The test results stored in the storage device can also be ensured for data accuracy through some means.

[0041] In one embodiment, backup data of the test results is also stored in the second designated address. At least two copies of the test results can be stored in the second designated address to increase the fault tolerance rate when reading the test results. When there is a problem with reading one copy of the test results, the other backup test results can be read.

[0042] In one embodiment, verification information is also stored in the second designated address. The verification information is obtained based on the test results and is used to verify whether the test results are complete and correct. The verification information may include an error correction code or an error detection code, such as a parity check code, a cyclic redundancy code, a Hamming code, etc.

[0043] In this application, the main control chip and the storage device to be tested can be separate and separable individuals, or can be encapsulated in the same storage device.

[0044] Next, a specific embodiment will be given to illustrate the test method of the storage device of the present application in more detail.

[0045] In the usual test method of the host plus the main control plus the storage device, the host needs to have the ability to issue test firmware to the main control. And because data transmission is required, it is limited by the connection method, and the number of main control chips that can be connected at a single host end is limited. There is a certain degree of delay when the host processes the test information returned by the main control chip, which will affect the test process. The communication connection between the host and the main control also requires additional hardware support according to the protocol supported by the main control chip.

[0046] The present application directly loads the test firmware from a specified address of the storage device and writes the test result into a specified address of the storage device to be tested, thus greatly simplifying the functions of the host and the communication between the host and the main control chip, reducing the hardware requirements, improving the test efficiency, and reducing the test cost.

[0047] Refer to Figure 3 , Figure 3 which is a schematic flowchart of a specific embodiment of the test method of the storage device of the present application.

[0048] First, the user writes the compiled test firmware to a specified location of the flash memory (usually the block 0 address of the flash memory). A low-cost solution such as a programmer can be used for writing.

[0049] Then, power on the main control and the flash memory through the host.

[0050] Next, after the main control establishes a communication connection with the flash memory, the main control generally supports automatically reading the content of the specified address of the flash memory (usually the block 0 address of the flash memory) and loading it into its own memory after power on. Here, the test firmware in the flash memory will be loaded. After the test firmware is loaded, the main control will test the flash memory according to the test firmware. Since the test firmware has been loaded, the block in the flash memory that previously saved the test firmware can participate in normal tests (such as erase, write, and read operations).

[0051] The test information generated during the test is written by the main control to a specified block address of the flash memory. This block address is a reserved address and does not participate in the test. After the test, this block address needs to be marked as a bad block and cannot be used normally. The written test information can be ensured the integrity of the information by some means (such as using error correction functions and multiple copies, etc.).

[0052] After the test is completed, the host powers off the main control and the flash memory. The signal indicating the end of the test is sent by the main control, such as pulling up or pulling down the level of a specified pin to indicate. The host checks the level of this pin to determine whether the test is over. In addition, the host can also set a test time limit to interrupt the test in time.

[0053] After the test is completed, the test information in the flash memory can be read out, and operations such as classification can be performed according to the test information. A low-cost solution such as a burner can be used to read it out.

[0054] The above flash memory is the storage device to be tested described in this application. Another flash memory can be additionally set as the target storage device to store the test firmware.

[0055] Such as Figure 4 shown, Figure 4 is a schematic structural diagram of the first embodiment of the test device of this application.

[0056] The electronic device includes a main control chip 110 and a test interface 120. The main control chip 110 is connected to the storage device to be tested through the test interface 120.

[0057] The main control chip 110 controls the operation of the storage device to be tested. The main control chip may be an MCU, also known as a micro control unit. The main control chip may be an integrated circuit chip with the ability to process signal sequences. The main control chip 110 can also be a general-purpose processor, a digital signal sequence processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0058] The main control chip 110 is used to execute instructions to implement the method provided by any one of the foregoing embodiments and possible combinations of the storage device test method of this application.

[0059] Such as Figure 5 shown, Figure 5 is a schematic structural diagram of the second embodiment of the test device of this application.

[0060] The test device includes a controller 210 and a test interface 220. The test interface 220 is used to connect the storage device to be tested. The storage device to be tested includes a main control chip and a storage device to be tested. The main control chip controls the operation of the storage device to be tested. The main control chip may be an MCU, also known as a micro control unit. The main control chip may be an integrated circuit chip with the ability to process signal sequences. The main control chip can also be a general-purpose processor, a digital signal sequence processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0061] The controller 210 may be referred to as a CPU (Central Processing Unit). The controller 210 may be an integrated circuit chip with the ability to process signal sequences. The controller 210 may also be a general-purpose processor, a digital signal sequence processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0062] The controller 210 is connected to the storage device to be tested through the test interface 220 to implement the method provided by any one of the foregoing embodiments and possible combinations of the storage device test method of the present application.

[0063] In summary, by placing the test firmware in the storage device to be tested or the target storage device, after the main control chip is powered on, the main control and the storage device establish a communication connection, and it is possible to read the test firmware from the storage device to be tested or directly from the target storage device, and then place the test firmware in its own memory to run, and test the storage device according to the test firmware. The main control no longer needs the host to send the test firmware, but directly obtains it from the storage device. Only the host needs to control the main control chip and the storage device to be powered on, and the main control chip can complete the subsequent test by itself. Compared with the connection method that requires data transmission, the connection method that only needs to implement power-on is simpler, and is no longer limited by the number of connections, which can increase the number of main control chips connected to the host and improve the test efficiency of the storage device.

[0064] In several embodiments provided by the present application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0065] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0066] In addition, in each embodiment of the present application, each functional unit may be integrated into one processing unit, may exist physically alone for each unit, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0067] If the integrated unit in the above-mentioned other embodiments is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in each embodiment of the present application. The foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disc that can store program codes.

[0068] The above are only the embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A test method for a storage device, characterized in that, The method includes: The main control chip responds to the power-on operation of the host side and establishes a communication connection with the storage device to be tested or establishes a communication connection with the storage device to be tested and the target storage device; The main control chip obtains the test firmware from the first specified address of the storage device to be tested and / or directly obtains the test firmware from the target storage device; The main control chip uses the test firmware to test the storage device to be tested.

2. The method according to claim 1, characterized in that, After the main control chip uses the test firmware to test the storage device to be tested, it includes: The main control chip responds to the end of the test and sends a test end instruction to the host side, so that the host side performs a power-off operation based on the test end instruction.

3. The method according to claim 2, wherein The test end instruction is a preset level signal sent through a specified pin.

4. The method according to claim 1, characterized in that The first specified address is the storage address in the storage device to be tested that the main control chip defaults to read when powered on.

5. The method according to claim 1, wherein After the main control chip uses the test firmware to test the storage device to be tested, it includes: Sending the obtained test result to the second specified address of the storage device to be tested; Setting a prohibit call mark for the second specified address to prevent normal calls to the second specified address.

6. The method according to claim 5, characterized in that, The second specified address also stores backup data of the test result.

7. The method according to claim 5, wherein The second specified address also stores verification information, and the verification information is obtained based on the test result for verifying whether the test result is complete and correct.

8. The method according to any one of claims 1-7, characterized in that, The main control chip and the storage device to be tested are encapsulated in a storage device.

9. A test device, characterized in that, The device includes a main control chip and a test interface. The main control chip is connected to the storage device to be tested through the test interface to implement the test method of the storage device according to any one of claims 1-8.

10. A testing device, characterized in that, The device includes a controller and a test interface. The test interface is used to connect to the storage device to be tested. The storage device to be tested includes a main control chip and a storage device to be tested. The controller is connected to the storage device to be tested through the test interface to perform power-on and power-off operations, implementing the test method of the storage device according to any one of claims 1-8.

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