D2W hybrid bonding chip mounting method

Abstract

The invention relates to the technical field of integrated circuit packaging, in particular to a D2W hybrid bonding chip mounting method, in the D2W chip picking and mounting process, the morphology of a chip and a wafer is adjusted and controlled through an ejector pin or pressure, so that the chip and the wafer are bonded from the center, or the chip is bonded with the wafer at an inclined angle by adjusting the position of a mechanical arm. According to the mounting mode, air in the middle of a bonding interface and water vapor generated by condensation can be discharged from a non-contact area, and gas residues and holes of the interface are reduced; meanwhile, a step-by-step mounting mode is adopted, and the contact range, the contact angle and the fitting rate of the chip can be adjusted through the pressure of a manipulator, a chip suction head and a wafer substrate, an ejector pin and the like, so that residual impurities on the interfaces of the chip and the wafer are reduced to the greatest extent; in addition, the chip mounting mode can significantly reduce the stress of a bonding interface, facilitates diffusion bonding of a metal layer at a high temperature, and improves the interface quality of mixed bonding of the chip and the wafer.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a die-to-wafer (D2W) hybrid bonding chip mounting method. Background Art

[0002] Advanced integrated circuit packaging is developing towards high-density three-dimensional stacking. In order to break through the density limit of copper bump interconnection, hybrid bonding is considered to be the most promising core technology for three-dimensional heterogeneous integration of chips, especially die-to-wafer (D2W) hybrid bonding.

[0003] D2W hybrid bonding is a bonding method that bonds known good chips onto a wafer. This method does not require metal bumps and can directly bond a dielectric layer (such as SiO2, SiN, SiCN, etc.) and a metal layer (Cu) simultaneously. After activation, the dielectric layer forms covalent bonds through dehydration condensation at room temperature, and the metal layer realizes electrical interconnection through diffusion bonding at high temperature.

[0004] However, by-products such as water vapor or hydrogen generated during the bonding process remain at the chip-wafer interface, which may cause voids at the interface and seriously damage the bonding quality. Therefore, selecting a suitable chip mounting method is very important for interface voids and bonding quality.

[0005] In the prior art, the main process of the mounting method for D2W hybrid bonding is as follows: The selected good chips and the bottom wafer are placed in the equipment for bonding after being activated and cleaned by plasma; the manipulator first picks up the chips from the blue film, turns them over so that the bonding surface faces down, and transfers them above the wafer; after the chips above and the wafer below are accurately aligned through a microscope, the chips are placed vertically downward, and the entire surface of the chips contacts the surface of the wafer. The Si-OH bonds of the dielectric layer are bonded at room temperature, and then the metal layer is diffusion-bonded by high-temperature annealing ( Figure 1-2 ).

[0006] The above solution has the following disadvantages: (1) Both the chips and the wafer are horizontal. When mounting, the horizontal chips are directly placed vertically on the horizontal wafer, and the air at the interface cannot be removed in time; (2) The water vapor generated by the dehydration condensation on the surface of the dielectric layer at room temperature will remain at the chip-wafer interface, resulting in bonding voids; (3) When directly mounting, the Si-OH bonds on the chip surface almost simultaneously contact and bond with the wafer, and the chemical reactions and by-products occurring in a short time will cause relatively large interface stress; (4) By-products such as water vapor and residual stress are not conducive to the diffusion bonding of copper atoms during the annealing process, affecting the electrical interconnection of the metal layer.

[0007] In view of this, the present invention is specifically proposed. Summary of the Invention

[0008] The object of the present invention is to provide a D2W hybrid bonding chip mounting method, which improves the interface quality of the chip and the wafer hybrid bonding.

[0009] The present invention provides a D2W hybrid bonding chip mounting method, comprising the following steps:

[0010] During the D2W chip picking and mounting process, the topography of the chip and the wafer is controlled by a thimble or pressure adjustment, so that the chip and the wafer start bonding from the center, or by adjusting the position of the manipulator, the chip is bonded to the wafer at an inclined angle, and the mounted D2W sample is obtained.

[0011] When the chip and the wafer start bonding from the center, the bonding surface of any one or both of the chip and the wafer can be processed by the thimble in the manipulator to be in a convex shape facing outwards, so that the chip and the wafer start to contact from the center position in a point-to-plane or point-to-point contact manner. Subsequently, the chip is placed by the manipulator, and the thimble is retracted, so that the chip and the wafer gradually bond from the center position to the periphery. After complete fitting, the manipulator applies pressure vertically downwards to complete the mounting.

[0012] In this picking and mounting method, the chip suction head and the wafer chuck control the topography of the chip and the wafer by mechanical or pressure means. The mechanical means can use a thimble to raise the bonding area for preferential bonding; the pressure means can change the pressure in the middle and around the chip / wafer to generate a pressure difference between the chip / wafer, presenting a certain bending arc. Therefore, the present invention can control the topography of the chip and the wafer to bulge towards the center position. The center positions of the chip and the wafer are bonded first, and then the edge positions of the chip and the wafer are gradually released while bonding, and finally the bonding of the entire chip and the wafer is realized.

[0013] Among them, when processing the bonding surfaces of the wafer and the chip, the middle position of the chip can be lifted by the thimble in the chip manipulator, presenting a shape with the middle protruding downwards and both sides upturned; similarly, the bonding surface of the lower wafer is also lifted by the lower thimble, so that the wafer presents a shape with the middle protruding upwards and both sides downwards. Specifically, the height of the thimble in the manipulator of the chip is any value between 0.01 - 2 mm, and the height of the thimble in the manipulator of the wafer is any value between 0.1 - 10 mm.

[0014] Preferably, as the technical solution, the contact time at the center positions of the chip and the wafer is any value between 1 - 10 s, the speed of the manipulator placing the chip is any value between 0.1 - 200 mm / s, and the speed of the thimble retracting is any value between 0.1 - 1 mm / s; finally, after complete fitting, the pressure applied by the manipulator downwards is 0.1 - 200 N, and different times are set according to different pressures, and the time can be specifically any value between 1 - 60 s;

[0015] It should be noted that during the entire chip mounting process, the ambient temperature is controlled at 20 - 25°C, the temperature of the pick-up head is controlled at 20 - 300°C, and the temperature fluctuation is less than 1°C.

[0016] When the chip is bonded to the wafer at an inclined angle, the position and inclined angle of the robot arm picking up the chip can be adjusted to make the chip present different adsorption forms. Specifically, by changing the angle of the robot arm, the chip can be made to form an angle of 1 - 90° with the wafer surface, so that one side edge of the chip contacts the wafer first and the other side is suspended. Then, the chip is released from the contacting side, and the chip and the wafer are gradually bonded from one side to the other side. After complete fitting, the robot arm applies pressure vertically downward.

[0017] Specifically, the release speed of the chip on the contacting side is preferably any value between 0.01 - 100 mm / s;

[0018] After complete fitting, the pressure applied downward by the robot arm is preferably 0.1 - 200 N, and the time is preferably 1 - 60 s;

[0019] Similarly, during the entire chip mounting process, the ambient temperature is controlled at 20 - 25°C, the temperature of the pick-up head is controlled at 20 - 300°C, and the temperature fluctuation is less than 1°C.

[0020] Preferably, as the technical solution, before the D2W chip is picked up and mounted, it also includes wafer grinding and polishing, chip dicing, activation, cleaning, and drying.

[0021] Among them, during the wafer grinding and polishing, the surface roughness of the wafer after polishing needs to be controlled to be less than 0.5 nm;

[0022] The chip dicing mainly involves thinning and cutting the wafer through chemical mechanical polishing. The thickness of the diced chip is 25 - 1000 μm, and the size is 1*1 mm 2 - 30*30 mm 2 .

[0023] The activation specifically refers to activating both the chip and the wafer through plasma. Specifically, the power of the plasma is any value between 20 - 600 W, the activation gas is any one or more of nitrogen, argon, and oxygen, the activation time is preferably 1 - 10 min, the gas flow rate is preferably 1 - 60 L / min, and the contact angle of the wafer and the chip surface with deionized water after activation < 5°;

[0024] During the cleaning, the flow rate of deionized water is 10 - 200 L / min, and the cleaning time is 1 - 5 min;

[0025] During the drying, the gas flow rate is 10 - 200 L / min, and the drying time is 1 - 10 min;

[0026] During the cleaning and drying processes, the rotation speeds of the wafer and the chip in the present invention are not strictly limited. Specifically, the rotation speed of the wafer is preferably 10 - 2000 rpm / min, and the rotation speed of the chip is preferably 10 - 1500 rpm / min.

[0027] Preferably, the D2W sample after bonding is annealed at 100 - 400 °C for 1 - 60 h. The annealing atmosphere is one or more of air, nitrogen, or argon atmospheres. The heating rate is 0.2 - 10 °C / min, and the holding time is 1 - 50 h. The cooling atmosphere is cooling in air, nitrogen, or argon atmosphere, and the cooling rate is 0.2 - 10 °C / min to obtain a D2W hybrid bonded chip, which promotes the diffusion bonding of the metal copper on the chip and the wafer, and finally realizes the complete bonding of the metal and the dielectric to obtain a D2W hybrid bonded chip.

[0028] The D2W hybrid bonding chip mounting method of the present invention has at least the following beneficial effects:

[0029] In the D2W hybrid bonding chip mounting method of the present invention, whether the chip and the wafer start bonding from the center or the chip bonds to the wafer at an inclined angle, the chip surface and the wafer are bonded in a step-by-step manner, that is, a part of the chip area first contacts the wafer, and the contacting part of the dielectric layer is bonded at room temperature, and then gradually fits other non-contacted areas until the entire chip and the wafer are fitted. This mounting method can discharge the air and the water vapor generated by condensation in the middle of the bonding interface from the non-contacted areas, reducing the gas residue and voids at the interface; at the same time, by adopting the step-by-step mounting method, the contact range, contact angle, and fitting rate of the chip can be adjusted through the pressure of the manipulator, chip suction head, and wafer substrate and the ejector pin, etc., to minimize the residual impurities at the chip and wafer interface; in addition, this chip mounting method can significantly reduce the stress at the bonding interface, which is beneficial to the diffusion bonding of the metal layer at high temperature, and can reduce the interface voids by suppressing the interface by-products, improving the interface quality of the chip and wafer hybrid bonding. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0031] Figure 1 Schematic diagram of the mounting method of D2W hybrid bonding in the prior art;

[0032] Figure 2Front view of the mounting method of D2W hybrid bonding in the current technology;

[0033] Figure 3 The first mounting method of the D2W hybrid bonding chip of the present invention;

[0034] Figure 4 The second mounting method of the D2W hybrid bonding chip of the present invention;

[0035] Figure 5 CSAM scanning result diagram of the bonded sample obtained by the mounting method of the present invention;

[0036] Figure 6 CSAM scanning result after D2W hybrid bonding by the ordinary mounting method of the comparative example of the present invention.

[0037] Reference numerals

[0038] 1: Manipulator; 2: Suction head; 3: Chip; 4: Wafer. Detailed implementation manners

[0039] It should be noted that the following detailed description is exemplary and is intended to provide further illustration of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs.

[0040] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular forms also include the plural forms. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0041] The technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0042] Example 1

[0043] (1) Wafer grinding and polishing and chip dicing

[0044] A 12-inch wafer with a surface dielectric layer of SiO2, a metal layer of copper, and a wafer thickness of 775 μm. After chemical mechanical polishing (CMP), the surface roughness is less than 0.5 nm;

[0045] Another identical wafer is thinned and diced after CMP to obtain the chips to be bonded. The thickness of the chips is 50μm, and the size of the chips is 5mm * 5mm.

[0046] (2) Activation and cleaning

[0047] The wafer and the chips are activated by plasma respectively. When activating, the power of the plasma is 300W, the activating gas is nitrogen, the activating time is 5min, the gas flow rate is 30L / min. After activation, the contact angles of the surfaces of the wafer and the chips with deionized water are both < 5°;

[0048] After activation, deionized water is used for cleaning. When cleaning, the flow rate of deionized water is controlled at 100L / min, and the cleaning time is 2min; after cleaning, nitrogen or argon is used for drying. Among them, the gas flow rate is 100L / min, and the drying time is 5min. During the cleaning and drying processes, the rotation speed of the wafer is 1000rpm / min, and the rotation speed of the chips is 1000rpm / min.

[0049] (3) D2W chip picking and mounting

[0050] The chip is picked up from the blue film or carrier by a manipulator, and the bonding surface of the chip is turned downward through flipping. The ejector pin inside the chip manipulator is used to lift the center position of the chip, presenting a shape with the middle protruding downward and both sides upturned. The area to be bonded under the wafer below is also lifted by the ejector pin, also making the wafer present a shape with the middle protruding upward and both sides downward. Among them, the height of the chip ejector pin is 1mm, and the height of the wafer ejector pin is 1mm;

[0051] The manipulator makes the middle position of the chip contact the wafer first and stay for 5s, and then slowly places the chip at a speed of 0.1mm / s. At this time, the ejector pins under the chip and the wafer slowly retract at a speed of 0.5mm / s, so that the chip and the wafer are gradually bonded from the middle to the surrounding. After complete fitting, the manipulator vertically applies a pressure of 25N downward and controls the time for 30s. During the entire mounting process, the temperature is controlled at 23 ± 1°C.

[0052] (4) D2W annealing

[0053] The mounted D2W sample is placed in an annealing furnace and annealed at 250°C for 2h to promote the diffusion bonding of the metal copper on the chip and the wafer, and achieve the complete bonding of the metal and the dielectric.

[0054] Example 2

[0055] (1) Wafer grinding and polishing and chip dicing

[0056] A 12-inch wafer with a surface dielectric layer of SiO2 and a metal layer of copper. The thickness of the wafer is 1000μm, and after chemical mechanical polishing (CMP), the surface roughness is less than 0.5nm;

[0057] Another identical wafer is thinned and diced after CMP to obtain the chips to be bonded. The thickness of the chips is 200μm, and the size of the chips is 20mm * 20mm.

[0058] (2) Activation and cleaning

[0059] The wafer and the chips are activated by plasma respectively. When activating, the power of the plasma is 600W, the activating gas is argon, the activating time is 10min, the gas flow rate is 60L / min, and after activation, the contact angles of the wafer and chip surfaces with deionized water are both < 5°;

[0060] After activation, deionized water is used for cleaning. When cleaning, the flow rate of deionized water is controlled at 200L / min, and the cleaning time is 5min; after cleaning is completed, nitrogen or argon is used for drying. Among them, the gas flow rate is 200L / min, and the drying time is 10min. During the cleaning and drying process, the rotation speed of the wafer is 1000rpm / min, and the rotation speed of the chips is 1000rpm / min.

[0061] (3) D2W chip pick-up and bonding

[0062] The chip is picked up from the blue film or carrier by a manipulator, and the bonding surface of the chip is turned downward by flipping. The center position of the chip is lifted by the ejector pin inside the chip manipulator, presenting a shape with the middle protruding downward and both sides warping upward. Among them, the height of the chip ejector pin is 2mm;

[0063] The manipulator makes the middle position of the chip contact the wafer first and stay for 10s, and then the chip is slowly placed at a speed of 0.5mm / s. At this time, the ejector pin of the chip slowly retracts at a speed of 0.5mm / s, so that the chip and the wafer are gradually bonded from the middle to the surrounding. After complete fitting, the manipulator vertically applies a pressure of 50N downward and controls the time for 60s. During the entire bonding process, the temperature is controlled at 23 ± 1°C.

[0064] (4) D2W annealing

[0065] The mounted D2W sample is placed in an annealing furnace and annealed at 400°C for 1h to promote the diffusion bonding of the metal copper on the chip and the wafer, and achieve the complete bonding of the metal and the dielectric.

[0066] Example 3

[0067] (1) Wafer grinding and polishing and chip dicing

[0068] A 12-inch wafer with a surface dielectric layer of SiO2 and a metal layer of copper, the thickness of the wafer is 775μm, and the surface roughness is less than 0.5nm after chemical mechanical polishing (CMP);

[0069] Another identical wafer is thinned and diced after CMP to obtain the chips to be bonded. The thickness of the chips is 25μm, and the side length of the chips is 2mm.

[0070] (2) Activation and cleaning

[0071] The wafer and the chips are activated by plasma respectively. When activating, the power of the plasma is 20W, the activating gas is nitrogen, the activating time is 10min, the gas flow rate is 60L / min. After activation, the contact angles of the wafer and chip surfaces with deionized water are both <5°;

[0072] After activation, deionized water is used for cleaning. When cleaning, control the flow rate of deionized water to be 100L / min and the cleaning time to be 2min; after cleaning, nitrogen or argon is used for drying. Among them, the gas flow rate is 100L / min and the drying time is 2min. During the cleaning and drying process, the rotation speed of the wafer is 500rpm / min, and the rotation speed of the chips is 500rpm / min.

[0073] (3) D2W chip pick-up and placement

[0074] By changing the angle of the manipulator, make the chip form a 45° angle with the wafer surface, make one side edge of the chip contact the wafer first and the other side hang in the air, and then release the chip from the contacting side at a speed of 5mm / s, so that the chip and the wafer are gradually bonded from one side to the other side. After complete fitting, the manipulator applies a vertical downward pressure. After complete fitting, the manipulator applies a vertical downward pressure of 50N and controls the time for 10s. During the whole placement process, control the temperature to be 23±1℃.

[0075] (4) D2W annealing

[0076] Place the mounted D2W sample in an annealing furnace and anneal it at 200℃ for 2h to promote the diffusion bonding of the metal copper on the chip and the wafer, and achieve the complete bonding of the metal and the dielectric.

[0077] Example 4

[0078] (1) Wafer grinding and polishing and chip dicing

[0079] A 12-inch wafer with a surface dielectric layer of SiO2 and a metal layer of copper, the thickness of the wafer is 1000μm, and the surface roughness is less than 0.5nm after chemical mechanical polishing (CMP);

[0080] Another identical wafer is thinned and diced after CMP to obtain the chips to be bonded. The thickness of the chips is 200 μm, and the side length of the chips is 50 mm.

[0081] (2) Activation and cleaning

[0082] The wafer and the chips are activated by plasma respectively. When activating, the power of the plasma is 300 W, the activating gas is one or several of nitrogen, argon, and oxygen, the activating time is 5 min, the gas flow rate is 30 L / min, and the contact angles of the surfaces of the wafer and the chips with deionized water are both < 5° after activation;

[0083] After activation, deionized water is used for cleaning. When cleaning, the flow rate of the deionized water is controlled to be 100 L / min, and the cleaning time is 5 min; after cleaning, nitrogen or argon is used for drying. Among them, the gas flow rate is 200 L / min, and the drying time is 2 min. During the cleaning and drying processes, the rotation speed of the wafer is 1000 rpm / min, and the rotation speed of the chips is 1000 rpm / min.

[0084] (3) D2W chip picking and placement

[0085] By changing the angle of the manipulator, the chip is made to be at 60° with the surface of the wafer, one side edge of the chip is made to contact the wafer first, and the other side is suspended. Then, the chip is released from the contacting side at a speed of 1 mm / s, so that the chip and the wafer are gradually bonded from one side to the other side. After complete fitting, the manipulator vertically applies a pressure downward. After complete fitting, the manipulator vertically applies a pressure of 200 N downward and controls the time to be 20 s. During the entire placement process, the temperature is controlled to be 23 ± 1°C.

[0086] (4) D2W annealing

[0087] The mounted D2W sample is placed in an annealing furnace and annealed at 200°C for 2 h to promote the diffusion bonding of the metal copper on the chip and the wafer, and to achieve the complete bonding of the metal and the dielectric.

[0088] Control example

[0089] The placement method of D2W hybrid bonding in the prior art is as Figure 1-2 shown.

[0090] The present invention conducts ultrasonic scanning testing (CSAM) on the samples that have completed D2W hybrid bonding, and checks the bonding voids at the interface between the chip and the wafer through CSAM testing, so as to evaluate the interface bonding quality of D2W.

[0091] Figure 5The figure shows the CSAM scanning result of the bonding sample obtained by using the bonding method of the present invention. It can be seen from the figure that the bonding interface between the chip and the wafer presents a uniform gray color, and there are no obvious bonding voids at the surface interface, indicating that a good bonding effect has been achieved at the interface. This further demonstrates that the bonding method of the present invention can effectively reduce or avoid the formation of interface voids in D2W hybrid bonding and improve the interface bonding quality.

[0092] Figure 6 The figure shows the CSAM scanning result after D2W hybrid bonding by the ordinary bonding method of the comparative example. It can be seen from the figure that there are obvious voids (the black areas in the figure) at the interface between the chip and the wafer. These voids are caused by the fact that when the chip is directly bonded to the wafer, the air at the interface cannot be exhausted, and the water vapor generated by the dehydration of the dielectric layer remains in the interface and cannot be discharged. These voids will seriously affect the interface bonding quality and reduce the reliability.

[0093] In summary, the bonding method of D2W hybrid bonding of the present invention can significantly improve the interface quality of chip and wafer hybrid bonding compared with the prior art.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features. However, such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A D2W hybrid bonding chip mounting method, characterized in that Including the following steps: During the D2W chip pick-and-place process, control the topography of the chip and the wafer through a thimble or pressure adjustment, so that the chip and the wafer are bonded starting from the center, or adjust the position of the manipulator to bond the chip to the wafer at an inclined angle to obtain a mounted D2W sample.

2. The D2W hybrid bonding chip mounting method according to claim 1, characterized in that When the chip and the wafer are bonded starting from the center, use the thimble inside the manipulator to process the bonding surfaces of the chip and / or the wafer to a convex shape facing outward respectively, so that the chip and the wafer come into contact at the center position. Then place the chip through the manipulator and retract the thimble, so that the chip and the wafer are gradually bonded from the center position to the periphery. After complete fitting, the manipulator applies pressure vertically downward.

3. The D2W hybrid bonding chip mounting method according to claim 2, wherein The height of the thimble inside the manipulator of the chip is 0.01 - 2 mm, and the height of the thimble inside the manipulator of the wafer is 0.1 - 10 mm.

4. The D2W hybrid bonding chip mounting method according to claim 2, characterized in that, The contact time at the center position of the chip and the wafer is 1 - 10 s, the speed of the manipulator placing the chip is 0.1 - 200 mm / s, and the retraction speed of the thimble is 0.1 - 1 mm / s; After complete fitting, the pressure applied downward by the manipulator is 0.1 - 200 N, and the time is 1 - 60 s; During the entire pick-and-place process, the ambient control temperature is 20 - 25 °C, and the temperature of the suction head is controlled at 20 - 300 °C.

5. The D2W hybrid bonding chip mounting method according to claim 1, wherein, When the chip is bonded to the wafer at an inclined angle, change the angle of the manipulator so that the surface of the chip and the wafer forms an angle of 1 - 90 °, so that one side edge of the chip contacts the wafer first and the other side is suspended. Then release the chip from the contacting side, so that the chip and the wafer are gradually bonded from one side to the other side. After complete fitting, the manipulator applies pressure vertically downward.

6. The D2W hybrid bonding chip mounting method according to claim 5, wherein, The release speed of the chip on the contacting side is 0.01 - 100 mm / s; After complete fitting, the pressure applied downward by the manipulator is 0.1 - 200 N, and the time is 1 - 60 s; During the entire pick-and-place process, the ambient control temperature is 20 - 25 °C, and the temperature of the suction head is controlled at 20 - 300 °C.

7. The D2W hybrid bonding chip mounting method according to claim 1, characterized in that Before the D2W chip pick-and-place, it also includes wafer grinding and polishing, chip dicing, activation, cleaning, and drying.

8. The D2W hybrid bonding chip mounting method according to claim 7, wherein When grinding and polishing the wafer, control the surface roughness of the polished wafer to be less than 0.5 nm; The thickness of the diced chip is 5 - 1000 μm, and the size is 1*1 mm 2 - 30*30 mm 2 .

9. The D2W hybrid bonding chip mounting method according to claim 7, wherein When activating, the power of the plasma is 20 - 600 W, the activation gas is any one or more of nitrogen, argon, and oxygen, the activation time is 1 - 10 min, the gas flow rate is 1 - 60 L / min, and the water contact angle on the surfaces of the wafer and the chip after activation < 5 °; When cleaning, the deionized water flow rate is 10 - 200 L / min, and the cleaning time is 1 - 5 min; When drying, the gas flow rate is 10 - 200 L / min, and the drying time is 1 - 10 min; Preferably, when cleaning and drying, the rotation speed of the wafer is 10 - 2000 rpm / min, and the rotation speed of the chip is 10 - 1500 rpm / min.

10. The D2W hybrid bonding chip mounting method according to claim 1, characterized in that, The mounted D2W sample is annealed at 100 - 400 °C for 1 - 60 h. The annealing atmosphere is one or more of air, nitrogen, or argon atmospheres. The heating rate is 0.2 - 10 °C / min, the holding time is 1 - 50 h, the cooling atmosphere is one or more of air, nitrogen, or argon atmospheres, and the cooling rate is 0.2 - 10 °C / min to obtain a D2W hybrid bonded chip.

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