Semiconductor structure and forming method of semiconductor structure
By forming an integral connecting layer between adjacent metal layers and forming a conductive layer thereon, the via manufacturing problem is solved, low-cost and efficient metal layer connection is achieved, and electrical performance is optimized.
Patent Information
- Application Number
- CN202410118452.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-26
- Publication Date
- 2025-07-29
AI Technical Summary
As the size of the digital cell decreases, manufacturing and disassembly of vias inside the cell becomes difficult, and the prior art is difficult to effectively connect the metal layer and the conductive layer, resulting in short circuits, increase in capacitance and resistance, and high design costs.
A first connecting layer is formed between adjacent metal layers. The connecting layer is an integral structure with a size greater than a preset range, reducing the use of the photomask, and forming a conductive layer on the connecting layer, and the spacing between the connecting layer and the conductive layer is smaller than the preset range.
Save mask costs, simplify manufacturing process, reduce resistance, optimize electrical performance, avoid performance losses and increased power consumption.
Smart Images
Figure CN120388937A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Art
[0002] In the process manufacturing, vias are usually used to connect transistors inside digital units and metal lines of various layers, such as Via0, Via1, etc. With the development of Moore's Law, the characteristic dimensions such as the size and pitch of vias have been greatly reduced, and the process challenges have also increased significantly. After entering the advanced process, processes such as multi-mask splitting and self-aligned via (abbreviated as SAV) are introduced to cope with the further reduction of the characteristic scale.
[0003] However, as the size of digital units continues to shrink, the manufacturing and splitting of vias inside the units become more difficult. Summary of the Invention
[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure to optimize the problem of via manufacturing inside the unit.
[0005] To solve the above technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming adjacent first and second metal layers on the substrate, the length directions of the first metal layer and the second metal layer being parallel to a first direction, a first spacing being between the first metal layer and the second metal layer, the first spacing being less than a preset range; forming a first connection layer on the first metal layer, or on the first metal layer and the second metal layer, the first connection layer being electrically connected to the first metal layer and the first connection layer being electrically connected to the second metal layer; forming a first conductive layer on the first connection layer, the length direction of the first conductive layer being parallel to a second direction, the second direction being perpendicular to the first direction.
[0006] Optionally, the preset range is: less than or equal to 100 nanometers.
[0007] Optionally, the length direction of the first connection layer is parallel to the second direction; the first connection layer is formed on the first metal layer and the second metal layer.
[0008] Optionally, it further includes: forming a third metal layer on the substrate, the length direction of the third metal layer being parallel to the first direction, the third metal layer being adjacent to the first metal layer; the first connection layer is further located on the third metal layer, and the first connection layer is electrically connected to the third metal layer.
[0009] Optionally, a second spacing is between the third metal layer and the first metal layer, and the second spacing is less than the preset range.
[0010] Optionally, the first metal layer has a first width, and the second metal layer has a second width; the length of the first connection layer is less than or equal to the sum of the first width, the second width, and the first spacing.
[0011] Optionally, the length direction of the first connection layer is parallel to the first direction; the first connection layer is formed on the first metal layer.
[0012] Optionally, further included is: forming a second conductive layer on the first connection layer, the length direction of the second conductive layer being parallel to that of the first conductive layer, and there being a third spacing between the second conductive layer and the first conductive layer, the third spacing being less than a preset range.
[0013] Optionally, the first conductive layer has a third width, and the second conductive layer has a fourth width; the length of the first connection layer is less than or equal to the sum of the third width, the fourth width, and the third spacing.
[0014] Optionally, the formation method of the first metal layer and the second metal layer includes: forming a first dielectric layer on a substrate; forming a first opening and a second opening in the first dielectric layer, the first opening and the second opening exposing the substrate surface; forming the first metal layer in the first opening and forming the second metal layer in the second opening.
[0015] Optionally, the formation method of the first connection layer includes: forming a second dielectric layer on the first dielectric layer, on the first metal layer, and on the second metal layer; forming a first groove in the second dielectric layer, the first groove exposing part of the surface of the first metal layer and part of the surface of the second metal layer; forming the first connection layer in the first groove.
[0016] Optionally, the substrate includes: a substrate; a device layer located on the substrate, the device layer including an isolation structure and a device structure located within the isolation structure, the device structure including a transistor, a diode, a triode, a capacitor, an inductor, or a conductive structure.
[0017] Optionally, the first metal layer is electrically connected to the device structure.
[0018] Optionally, the second metal layer is electrically connected to the device structure.
[0019] Accordingly, the technical solution of the present invention further provides a semiconductor structure, including: a substrate; adjacent first and second metal layers located on the substrate, the length directions of the first metal layer and the second metal layer being parallel to a first direction, a first spacing being provided between the first metal layer and the second metal layer, the first spacing being less than a preset range; a first connection layer located on the first metal layer, or located on the first metal layer and the second metal layer, the first connection layer being electrically connected to the first metal layer and the first connection layer being electrically connected to the second metal layer; a first conductive layer located on the first connection layer, the length direction of the first conductive layer being parallel to a second direction, the second direction being perpendicular to the first direction.
[0020] Optionally, the preset range is: less than or equal to 100 nanometers.
[0021] Optionally, the length direction of the first connection layer is parallel to the second direction; the first connection layer is located on the first metal layer and the second metal layer.
[0022] Optionally, further included is: a third metal layer located on the substrate, the length direction of the third metal layer being parallel to the first direction, the third metal layer being adjacent to the first metal layer; the first connection layer is further located on the third metal layer, and the first connection layer is electrically connected to the third metal layer.
[0023] Optionally, a second spacing is provided between the third metal layer and the first metal layer, the second spacing being less than the preset range.
[0024] Optionally, the first metal layer has a first width, and the second metal layer has a second width; the length of the first connection layer is less than or equal to the sum of the first width, the second width, and the first spacing.
[0025] Optionally, the length direction of the first connection layer is parallel to the first direction; the first connection layer is located on the first metal layer.
[0026] Optionally, further included is: a second conductive layer located on the first connection layer, the length direction of the second conductive layer being parallel to the first conductive layer, a third spacing being provided between the second conductive layer and the first conductive layer, the third spacing being less than the preset range.
[0027] Optionally, the first conductive layer has a third width, and the second conductive layer has a fourth width; the length of the first connection layer is less than or equal to the sum of the third width, the fourth width, and the third spacing.
[0028] Optionally, the substrate includes: a substrate; a device layer located on the substrate, the device layer including an isolation structure and a device structure located within the isolation structure, the device structure including a transistor, a diode, a triode, a capacitor, an inductor, or a conductive structure.
[0029] Optionally, the first metal layer is electrically connected to the device structure; the second metal layer is electrically connected to the device structure.
[0030] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0031] In the forming method of the present invention, a first connection layer is formed on the first metal layer, or on the first metal layer and the second metal layer. The first spacing between the first metal layer and the second metal layer is less than a preset range, and the first connection layer is an integral body. Thus, the size of the first connection layer becomes larger, saving cost without the need for an additional photomask, and being easy to manufacture with less impact on the architecture and performance of the semiconductor structure; in addition, the size of the first connection layer is larger, so the resistance is reduced and the electrical performance is optimized.
[0032] Further, the first connection layer is also located on a third metal layer, the third metal layer is adjacent to the first metal layer, and the second spacing between the third metal layer and the first metal layer is less than a preset range. The first connection layer connects three adjacent metal layers, further saving the photomask cost and optimizing the manufacturing process.
[0033] Further, the length direction of the first connection layer is parallel to the first direction. A first connection layer is formed on the first metal layer, and a first conductive layer and a second conductive layer are formed on the first connection layer. The third spacing between the second conductive layer and the first conductive layer is less than a preset range. The first connection layer connects two adjacent conductive layers, further saving the photomask cost and optimizing the manufacturing process. Description of the Drawings
[0034] Figure 1 and Figure 2 are schematic diagrams of a semiconductor structure in an embodiment;
[0035] Figure 3 are schematic diagrams of a semiconductor structure in an embodiment;
[0036] Figure 4 are schematic diagrams of a semiconductor structure in an embodiment;
[0037] Figures 5 to 11 is a schematic diagram of the structure in the process of forming a semiconductor structure in an embodiment of the present invention;
[0038] Figure 12 and Figure 13It is a schematic diagram of the structure in the process of forming a semiconductor structure in another embodiment of the present invention;
[0039] Figures 14 to 17 It is a schematic diagram of the structure in the process of forming a semiconductor structure in another embodiment of the present invention. Detailed implementation manners
[0040] As described in the background art, as the digital unit size continues to shrink, the via manufacturing and splitting inside the unit become more difficult. The following is an analysis and description in combination with specific embodiments.
[0041] Figure 1 and Figure 2 is a schematic diagram of a semiconductor structure in an embodiment.
[0042] Please refer to Figure 1 , the semiconductor structure includes: a substrate; a plurality of first metal layers 101 located on the substrate, if the first metal layers 101 are parallel to the first direction; a first conductive layer 102 located on the first metal layers 101, the first conductive layer 102 is parallel to the second direction, and the second direction is perpendicular to the first direction; a first plug 103 and a second plug 104 respectively located on adjacent two first metal layers 101, the first conductive layer 102 is located on the first plug 103 and the second plug 104, and the first conductive layer 102 is electrically connected to the first metal layers 101 through the first plug 103 and the second plug 104.
[0043] In the semiconductor structure, adjacent two first metal layers 101 are connected together through the first plug 103, the second plug 104 and the first conductive layer 102.
[0044] However, since the distance d1 between the first plug 103 and the second plug 104 is too small, there is a certain difficulty in manufacturing.
[0045] Please refer to Figure 2 , the semiconductor structure includes: a substrate; a plurality of first metal layers 101 located on the substrate, if the first metal layers 101 are parallel to the first direction; a plurality of first conductive layers 102 located on the first metal layers 101, the first conductive layer 102 is parallel to the second direction, and the second direction is perpendicular to the first direction; a first plug 120 and a second plug 121 located on one first metal layer 101, adjacent two of the first conductive layers 102 are respectively located on the first plug 103 and the second plug 104, and adjacent two of the first conductive layers 102 are respectively electrically connected to the first metal layer 101 through the first plug 120 and the second plug 121.
[0046] However, since the distance d1 between the first plug 120 and the second plug 121 is too small, there is a certain difficulty in manufacturing.
[0047] To solve the problem that the first plug 103 and the second plug 104 as described in Figure 1 cannot be manufactured, the following method is usually adopted. On the one hand, please refer to Figure 3 , increase the spacing d2 between the first plug 103 and the second plug 104, so that d2 is greater than d1. This makes it easy for the first plug 103 and the second plug 104 to be short-circuited with other adjacent first metal layers 101 (as shown in region A in Figure 3 ). Similarly, if the spacing between the first plug 120 and the second plug 121 as in Figure 2 is increased, the first plug 120 and the second plug 121 will be short-circuited with the adjacent first conductive layer 102.
[0048] On the other hand, please refer to Figure 4 , form an additional second conductive layer 105 on the first metal layer 101 and plugs between the first conductive layer 102 and the first metal layer 101, and use additional metal traces to achieve the purpose of connecting two first metal layers 101 as in Figure 1 . However, introducing additional metal will bring more capacitance and resistance, resulting in performance loss and power consumption increase of the overall chip. Similarly, if additional metal traces are added to achieve the purpose of connecting two first conductive layers 102 as in Figure 2 , more capacitance and resistance will be brought, resulting in performance loss and power consumption increase of the overall chip.
[0049] On the other hand, through design rules, the appearance of such structures as in Figure 1 and Figure 2 is prohibited. However, prohibiting such structures may lead to changing the entire design architecture and increasing the design cost.
[0050] To solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the semiconductor structure. By forming a first connection layer on the first metal layer or on the first metal layer and the second metal layer, the first spacing between the first metal layer and the second metal layer is less than a preset range, and the first connection layer is a whole, so that the size of the first connection layer becomes larger, no additional photomask is required, the cost is saved, and it is easy to manufacture, and has little impact on the architecture and performance of the semiconductor structure; in addition, the size of the first connection layer is larger, so the resistance is reduced and the electrical performance is optimized.
[0051] To make the above objects, features and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.
[0052] Figures 5 to 11It is a schematic structural diagram of the formation process of a semiconductor structure in an embodiment of the present invention.
[0053] Please refer to Figure 5 , a substrate is provided.
[0054] The substrate includes: a substrate 200; a device layer located on the substrate 200, the device layer includes an isolation structure 201 and a device structure 202 located within the isolation structure 201, and the device structure 202 includes a transistor, a diode, a triode, a capacitor, an inductor, or a conductive structure, etc.
[0055] In this embodiment, the material of the substrate 200 is silicon.
[0056] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.
[0057] The material of the isolation structure 201 includes a dielectric material, and the dielectric material includes one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride.
[0058] Please refer to Figure 6 and Figure 7 , Figure 6 is Figure 7 a schematic structural diagram along the direction of the section line AA1, Figure 7 is Figure 6 a top view of, adjacent first metal layer 210 and second metal layer 211 are formed on the substrate, the length directions of the first metal layer 210 and the second metal layer 211 are parallel to the first direction X, and there is a first spacing d1 between the first metal layer 210 and the second metal layer 211, and the first spacing d1 is less than a preset range.
[0059] In this embodiment, the preset range is: less than or equal to 100 nanometers.
[0060] In this embodiment, the first metal layer 210 is electrically connected to the device structure. The second metal layer 211 is electrically connected to the device structure.
[0061] The forming method of the first metal layer 210 and the second metal layer 211 includes: forming a first dielectric layer 203 on a substrate; forming a plurality of openings (not shown) in the first dielectric layer 203, the plurality of openings being parallel to a first direction X, the openings including a first opening and a second opening, and the plurality of openings exposing the substrate surface; forming a metal material layer (not shown) in the plurality of openings and on the first dielectric layer 203; planarizing the metal material layer until the surface of the first dielectric layer 203 is exposed, and forming a plurality of metal layers parallel to the first direction X in the plurality of openings, the metal layers including a first metal layer 210 located in the first opening and a second metal layer 211 located in the second opening.
[0062] The material of the metal material layer includes metal or metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.
[0063] The material of the first dielectric layer 203 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride.
[0064] Please refer to Figure 8 and Figure 9 , Figure 8 is Figure 9 a schematic structural diagram along the direction of section line AA1, Figure 9 is Figure 8 a top view omitting the second dielectric layer. A first connection layer 213 is formed on the first metal layer 210 and the second metal layer 211, and the first connection layer 213 is electrically connected to the first metal layer 210 and the second metal layer 211.
[0065] In this embodiment, the length direction of the first connection layer 213 is parallel to a second direction Y, and the second direction Y is perpendicular to the first direction X.
[0066] In this embodiment, the first metal layer 210 has a first width w1, and the second metal layer 211 has a second width w2 (refer to Figure 7 ); the length L1 of the first connection layer 213 is less than or equal to the sum of the first width w1, the second width w2, and a first spacing d1, that is, L1≤w1 + w2 + d1.
[0067] The length L1 of the first connection layer 213 being less than or equal to the sum of the first width w1, the second width w2, and the first spacing d1 reduces the possibility of the first connection layer 213 being short-circuited with adjacent metal layers.
[0068] The method for forming the first connection layer 213 includes: forming a second dielectric layer 204 on the first dielectric layer 203, on the first metal layer 210, and on the second metal layer 211; forming a first groove (not shown) in the second dielectric layer 204, the first groove exposing part of the surface of the first metal layer 210 and part of the surface of the second metal layer 211; forming a connection material layer (not shown) in the first groove and on the second dielectric layer 204; planarizing the connection material layer to form the first connection layer 213 in the first groove.
[0069] The material of the first connection layer 213 includes metal or metal nitride; the metal includes one or a combination of more than one of: copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes one or a combination of more than one of tantalum nitride and titanium nitride.
[0070] The material of the second dielectric layer 204 includes a dielectric material, the dielectric material including one or a combination of more than one of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride.
[0071] Please refer to Figure 10 and Figure 11 , Figure 10 is Figure 11 a schematic structural view along the sectional line AA1 direction, Figure 11 is Figure 10 a top view omitting the second dielectric layer. A first conductive layer 214 is formed on the first connection layer 213, and the length direction of the first conductive layer 214 is parallel to the second direction Y.
[0072] The method for forming the first conductive layer 214 includes: forming a third dielectric layer (not shown) on the second dielectric layer 204 and on the first connection layer 213; forming a second groove (not shown) in the third dielectric layer, the second groove exposing the surface of the first connection layer 213; forming a metal material layer (not shown) in the second groove and on the third dielectric layer; planarizing the metal material layer to form the first conductive layer 214 in the second groove.
[0073] The material of the first conductive layer 214 includes metal or metal nitride; the metal includes one or a combination of more than one of: copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes one or a combination of more than one of tantalum nitride and titanium nitride.
[0074] The forming method forms a first connection layer 213 on a first metal layer 210 and a second metal layer 211. A first spacing d1 between the first metal layer 210 and the second metal layer 211 is less than a preset range. The first connection layer 213 is an integral body, so that the size of the first connection layer 213 becomes larger, saving cost without an additional photomask and being easy to manufacture, with less impact on the architecture and performance of the semiconductor structure. In addition, the size of the first connection layer 213 is larger, so that the resistance is reduced and the electrical performance is optimized.
[0075] Correspondingly, the technical solution of the present invention further provides a semiconductor structure. Please continue to refer to Figure 10 and Figure 11 , including:
[0076] A substrate;
[0077] Adjacent first and second metal layers 210 and 211 located on the substrate. The length directions of the first metal layer 210 and the second metal layer 211 are parallel to a first direction X. There is a first spacing between the first metal layer 210 and the second metal layer 211, and the first spacing is less than a preset range;
[0078] A first connection layer 213 located on the first metal layer 210 and the second metal layer 211. The first connection layer 213 is electrically connected to the first metal layer 210 and the first connection layer 213 is electrically connected to the second metal layer 211;
[0079] A first conductive layer 214 located on the first connection layer 213. The length direction of the first conductive layer 214 is parallel to a second direction Y, and the second direction Y is perpendicular to the first direction X.
[0080] In this embodiment, the preset range is: less than or equal to 100 nanometers.
[0081] In this embodiment, the length direction of the first connection layer 213 is parallel to the second direction Y.
[0082] Figure 12 and Figure 13 are schematic diagrams of the structure during the formation process of the semiconductor structure in another embodiment of the present invention.
[0083] Please refer to Figure 12 and Figure 13 , Figure 12 is a schematic diagram based on Figure 9 , Figure 12 is a schematic diagram of the structure along the section line AA1 direction of Figure 13 , Figure 13 is Figure 12Top view. When forming adjacent first metal layer 210 and second metal layer 211 on the substrate, a third metal layer 212 is also formed on the substrate. The length direction of the third metal layer 212 is parallel to the first direction X, and the third metal layer 212 is adjacent to the first metal layer 210.
[0084] In this embodiment, the first connection layer 213 is also located on the third metal layer 212, and the first connection layer 213 is also electrically connected to the third metal layer 212.
[0085] In this embodiment, a second spacing d3 exists between the third metal layer 212 and the first metal layer 210, and the second spacing d3 is less than a preset range.
[0086] In this embodiment, the preset range is: less than or equal to 100 nanometers.
[0087] In this embodiment, the third metal layer 212 has a third width w3, and the length L1 of the first connection layer 213 is less than or equal to the sum of the first width w1, second width w2, third width w3, first spacing d1, and second spacing d3, that is, L1 ≤ w1 + w2 + w3 + d1 + d3.
[0088] Subsequently, a first conductive layer is continuously formed on the first connection layer 213. For the process and method of forming the first conductive layer, please refer to Figure 10 and Figure 11 the accompanying drawings and written descriptions therein, which will not be elaborated here.
[0089] In the forming method, the first connection layer 213 is also located on the third metal layer 212. The third metal layer 212 is adjacent to the first metal layer 210, and the second spacing d3 between the third metal layer 212 and the first metal layer 210 is less than the preset range. The first connection layer 213 connects three adjacent metal layers, further saving the photomask cost and optimizing the manufacturing process.
[0090] Correspondingly, the technical solution of the present invention also provides a semiconductor structure. Please continue to refer to Figure 12 and Figure 13 , Figure 12 and Figure 13 The difference between the semiconductor structure in Figure 10 and Figure 11 and the semiconductor structure in this embodiment is that in this embodiment, it further includes: a third metal layer 212 located on the substrate. The length direction of the third metal layer 212 is parallel to the first direction X, and the third metal layer 212 is adjacent to the first metal layer 210; the first connection layer 213 is also located on the third metal layer 212, and the first connection layer 213 is also electrically connected to the third metal layer 212.
[0091] Figures 14 to 17 It is a schematic structural diagram of the semiconductor structure formation process in another embodiment of the present invention.
[0092] Please refer to Figure 14 and Figure 15 , Figure 14 and Figure 15 are schematic diagrams based on Figure 7 , Figure 14 is Figure 15 a schematic structural diagram along the direction of section line BB1, Figure 15 is Figure 14 a top view omitting the second dielectric layer. In this embodiment, a first connection layer 313 is formed on the first metal layer 210, and the length direction of the first connection layer 313 is parallel to the first direction X.
[0093] For the formation process of the first connection layer 313, please refer to Figure 8 and Figure 9 , which will not be elaborated here.
[0094] Please refer to Figure 16 and Figure 17 , Figure 16 is Figure 17 a schematic structural diagram along the direction of section line BB1, Figure 17 is Figure 16 a top view omitting the second dielectric layer. A first conductive layer 314 is formed on the first connection layer 313, and a second conductive layer 315 is formed on the first connection layer 313. The length direction of the second conductive layer 315 is parallel to that of the first conductive layer 314. The second conductive layer 315 and the first conductive layer 314 are parallel to the second direction Y. There is a third spacing d4 between the second conductive layer 315 and the first conductive layer 314, and the third spacing d4 is less than a preset range.
[0095] In this embodiment, the preset range is less than or equal to 100 nanometers.
[0096] The first conductive layer 314 has a third width w4, and the second conductive layer 315 has a fourth width w5; the length L2 of the first connection layer 313 is less than or equal to the sum of the third width w4, the fourth width w5, and the third spacing d4, that is, L2 ≤ w4 + w5 + d4.
[0097] The forming method is as follows. The length direction of the first connection layer 313 is parallel to the first direction X. The first connection layer 313 is formed on the first metal layer 210. The first conductive layer 314 and the second conductive layer 315 are formed on the first connection layer 313. The third spacing d4 between the second conductive layer 315 and the first conductive layer 314 is less than a preset range. The first connection layer 313 connects two adjacent conductive layers, further saving the mask cost and optimizing the manufacturing process.
[0098] Correspondingly, the technical solution of the present invention further provides a semiconductor structure. Please continue to refer to Figure 16 and Figure 17 , Figure 16 and Figure 17 The semiconductor structures in Figure 10 and Figure 11 The difference from the semiconductor structures in
[0099] In this embodiment, the first connection layer 313 is located on the first metal layer 210, and the length direction of the first connection layer 313 is parallel to the first direction X; the first conductive layer 314 and the second conductive layer 315 located on the first connection layer 313 are parallel to the second direction Y.
[0100] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming an adjacent first metal layer and a second metal layer on the substrate, the length directions of the first metal layer and the second metal layer being parallel to a first direction, a first spacing being provided between the first metal layer and the second metal layer, the first spacing being less than a preset range; Forming a first connection layer on the first metal layer, or on the first metal layer and the second metal layer, the first connection layer being electrically connected to the first metal layer and the first connection layer being electrically connected to the second metal layer; Forming a first conductive layer on the first connection layer, the length direction of the first conductive layer being parallel to a second direction, the second direction being perpendicular to the first direction.
2. The method for forming a semiconductor structure according to claim 1, wherein, The preset range is: less than or equal to 100 nanometers.
3. The method for forming a semiconductor structure according to claim 1, wherein The length direction of the first connection layer is parallel to the second direction; the first connection layer is formed on the first metal layer and the second metal layer.
4. The method for forming a semiconductor structure according to claim 3, wherein, Further comprising: Forming a third metal layer on the substrate, the length direction of the third metal layer being parallel to the first direction, the third metal layer being adjacent to the first metal layer; The first connection layer is further located on the third metal layer, and the first connection layer is electrically connected to the third metal layer.
5. The method for forming a semiconductor structure according to claim 4, wherein, A second spacing is provided between the third metal layer and the first metal layer, the second spacing being less than the preset range.
6. The method for forming a semiconductor structure according to claim 3, wherein, The first metal layer has a first width, and the second metal layer has a second width; the length of the first connection layer is less than or equal to the sum of the first width, the second width, and the first spacing.
7. The method for forming a semiconductor structure according to claim 1, wherein, The length direction of the first connection layer is parallel to the first direction; the first connection layer is formed on the first metal layer.
8. The method for forming a semiconductor structure according to claim 7, wherein, Further comprising: Forming a second conductive layer on the first connection layer, the length direction of the second conductive layer being parallel to the first conductive layer, a third spacing being provided between the second conductive layer and the first conductive layer, the third spacing being less than the preset range.
9. The method for forming a semiconductor structure according to claim 8, wherein, The first conductive layer has a third width, and the second conductive layer has a fourth width; the length of the first connection layer is less than or equal to the sum of the third width, the fourth width, and the third spacing.
10. The method for forming a semiconductor structure according to claim 1, wherein The forming method of the first metal layer and the second metal layer includes: forming a first dielectric layer on the substrate; forming a first opening and a second opening in the first dielectric layer, the first opening and the second opening exposing the substrate surface; forming the first metal layer in the first opening and forming the second metal layer in the second opening.
11. The method for forming a semiconductor structure according to claim 10, wherein, The forming method of the first connection layer includes: forming a second dielectric layer on the first dielectric layer, the first metal layer, and the second metal layer; forming a first groove in the second dielectric layer, the first groove exposing a part of the surface of the first metal layer and a part of the surface of the second metal layer; forming the first connection layer in the first groove.
12. The method for forming a semiconductor structure according to claim 1, wherein, The substrate includes: a base; a device layer located on the base, the device layer including an isolation structure and a device structure located in the isolation structure, the device structure including a transistor, a diode, a triode, a capacitor, an inductor, or a conductive structure.
13. The method for forming a semiconductor structure according to claim 12, wherein The first metal layer is electrically connected to the device structure.
14. The method for forming a semiconductor structure according to claim 12, wherein, The second metal layer is electrically connected to the device structure.
15. A semiconductor structure, characterized in that, Comprising: A substrate; An adjacent first metal layer and second metal layer located on a substrate, wherein the length directions of the first metal layer and the second metal layer are parallel to a first direction, and there is a first spacing between the first metal layer and the second metal layer, and the first spacing is less than a preset range; A first connection layer located on the first metal layer, or on the first metal layer and the second metal layer, the first connection layer being electrically connected to the first metal layer and the first connection layer being electrically connected to the second metal layer; A first conductive layer located on the first connection layer, the length direction of the first conductive layer being parallel to a second direction, and the second direction being perpendicular to the first direction.
16. The semiconductor structure according to claim 15, wherein, The preset range is: less than or equal to 100 nanometers.
17. The semiconductor structure according to claim 15, wherein, The length direction of the first connection layer is parallel to the second direction; the first connection layer is located on the first metal layer and the second metal layer.
18. The semiconductor structure according to claim 17, wherein, Further included: A third metal layer located on the substrate, the length direction of the third metal layer being parallel to the first direction, and the third metal layer being adjacent to the first metal layer; The first connection layer is further located on the third metal layer, and the first connection layer is electrically connected to the third metal layer.
19. The semiconductor structure according to claim 18, wherein, There is a second spacing between the third metal layer and the first metal layer, and the second spacing is less than the preset range.
20. The semiconductor structure according to claim 17, wherein The first metal layer has a first width, and the second metal layer has a second width; the length of the first connection layer is less than or equal to the sum of the first width, the second width, and the first spacing.
21. The semiconductor structure according to claim 15, characterized in that, The length direction of the first connection layer is parallel to the first direction; the first connection layer is located on the first metal layer.
22. The semiconductor structure according to claim 21, wherein, Further included: A second conductive layer located on the first connection layer, the length direction of the second conductive layer being parallel to the first conductive layer, and there is a third spacing between the second conductive layer and the first conductive layer, and the third spacing is less than the preset range.
23. The semiconductor structure according to claim 22, wherein The first conductive layer has a third width, and the second conductive layer has a fourth width; the length of the first connection layer is less than or equal to the sum of the third width, the fourth width, and the third spacing.
24. The semiconductor structure according to claim 15, wherein, The substrate includes: a substrate; a device layer located on the substrate, the device layer including an isolation structure and a device structure located within the isolation structure, and the device structure including a transistor, a diode, a triode, a capacitor, an inductor, or a conductive structure.
25. The semiconductor structure according to claim 24, wherein The first metal layer is electrically connected to the device structure; the second metal layer is electrically connected to the device structure.