Clock recovery device and method
By using a phase-locked loop generation calibration signal in the optical transmission network to calibrate the clock frequency points of the serial-parallel converter, the problem that the clock recovery method in the prior art cannot meet the requirements of implementation complexity, accuracy and cost at the same time, and achieves a simple and high-precision clock recovery effect.
Patent Information
- Application Number
- CN202410126435.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-29
- Publication Date
- 2025-07-29
AI Technical Summary
The clock recovery method in the prior art cannot meet the requirements of implementation complexity, accuracy and cost at the same time. Especially in optical transmission networks, the existing methods have problems such as simple implementation but poor accuracy, or complex implementation and high cost.
A clock recovery device is adopted, which includes a first module and a phase-locked loop. The calibration signal is generated by the phase-locked loop, and the clock frequency points of the serial-parallel converter are calibrated based on the calibration signal to achieve simple and high-precision clock recovery.
The clock recovery processing is realized in the optical port transmission direction, which simplifies the implementation method, improves the accuracy of clock recovery, and reduces costs.
Smart Images
Figure CN120389823A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuits, and more particularly, to a clock recovery device and method. Background Art
[0002] With the continuous development of communication technologies, the Optical Transport Network (OTN) has gradually become the mainstream choice for transmission networks. The OTN network not only needs to transmit the service data itself, but also needs to transmit the clock information representing the service data rate, so as to keep the services across the network clock-synchronized. Clock transparent transmission means that the recovery clock frequency used for transmitting service data at the optical transmission port of the local device can follow the clock frequency of the service received at the optical reception port.
[0003] There are three common clock recovery methods. The first is to directly adjust the speed of the recovered clock based on the water level of the last-in, first-out (FIFO) memory. First, the payload data is decoded from the Optical Transport Unit (OTU) and written into the transmit FIFO through the system clock, and then the transmit FIFO is read by the client recovery clock. It should be noted here that the source of the client recovery clock is an external clock chip, and the control module of the external clock chip can control the frequency point of the client recovery clock according to the water line level of the transmit FIFO, so as to achieve the function of following the service clock. The second is to transmit the overhead information containing service bits in the overhead in the mapping direction. In the demapping direction, first, the clock overhead information is decoded from the OTU, and at the same time, the OTU clock is recovered. The extracted overhead information is used to control the division ratio of the frequency division unit, and the OTU clock is directly frequency-divided to recover the client recovery clock, and the clock output after being multiplied by the external clock chip is used as the transmit reference clock of the serializer / deserializer (serdes). The third is to use a digital phase-locked loop with a staircase wave generator in both the mapping and demapping directions to recover the recovery clock in the transmit direction.
[0004] However, the existing clock recovery methods still have the following problems: The first method is simple to implement but has poor accuracy and requires an additional clock chip; the second and third methods have high accuracy but are complex to implement and also require a clock chip.
[0005] In summary, when performing clock recovery in a communication transmission system, factors such as implementation complexity, accuracy, and cost need to be comprehensively considered, and the clock recovery method needs to be reasonably designed and optimized. There is still no good solution to this in the related technologies. Summary of the Invention
[0006] Embodiments of the present application provide a clock recovery device and method, which at least solve the problem that the clock recovery method in the related art cannot simultaneously meet the requirements of implementation complexity, accuracy, and cost.
[0007] According to an embodiment of the present application, a clock recovery device is provided. The device includes a first module and a phase-locked loop. The phase-locked loop includes a serial-to-parallel converter. The output end of the first module is connected to the input end of the phase-locked loop. The first module is configured to receive a system clock and a signal to be recovered in the optical port transmission direction, perform smoothing processing and frequency division processing on the signal to be recovered based on the system clock to obtain a first frequency-divided signal, and input the first frequency-divided signal into the phase-locked loop. The phase-locked loop is configured to generate a calibration signal based on the first frequency-divided signal, and calibrate the clock frequency point of the serial-to-parallel converter based on the calibration signal to obtain a recovered clock output by the serial-to-parallel converter.
[0008] According to another embodiment of the present application, a clock recovery method is provided, which is applied to the clock recovery device in any of the above embodiments. The method includes: receiving a system clock and a signal to be recovered in the optical port transmission direction; performing smoothing processing and frequency division processing on the signal to be recovered based on the system clock to obtain a first frequency-divided signal; generating a calibration signal based on the first frequency-divided signal; calibrating the clock frequency point of the serial-to-parallel converter based on the calibration signal, and outputting a recovered clock through the serial-to-parallel converter.
[0009] According to still another embodiment of the present application, a computer-readable storage medium is further provided. A computer program is stored in the storage medium. When the computer program is run by a processor, the steps in the method embodiment are executed.
[0010] According to still another embodiment of the present application, an electronic device is further provided, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in the method embodiment.
[0011] In the embodiments of the present application, a calibration signal is generated by a phase-locked loop, and the clock frequency point of the serial-to-parallel converter is calibrated based on the calibration signal to obtain a recovered clock output by the serial-to-parallel converter. Clock recovery processing can be directly performed in the optical port transmission direction, and the implementation method is simple and has high accuracy. Furthermore, the problem that the clock recovery method in the related art cannot simultaneously meet the requirements of implementation complexity, accuracy, and cost is solved, and the technical effects of reducing costs and improving clock recovery accuracy are achieved. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 is a networking schematic diagram of an OTN transmission system;
[0013] Figure 2 It is a structural block diagram of the clock recovery device according to an embodiment of the present application;
[0014] Figure 3 It is a schematic structural diagram of a phase-locked loop in an embodiment of the present application;
[0015] Figure 4 It is a schematic structural diagram (I) of a feedforward circuit in an embodiment of the present application;
[0016] Figure 5 It is a schematic structural diagram (I) of a numerically controlled oscillator in an embodiment of the present application;
[0017] Figure 6 It is a schematic structural diagram (II) of a numerically controlled oscillator in an embodiment of the present application;
[0018] Figure 7 It is a schematic structural diagram (II) of a feedforward circuit in an embodiment of the present application;
[0019] Figure 8 It is a schematic structural diagram (III) of a feedforward circuit in an embodiment of the present application;
[0020] Figure 9 It is a schematic structural diagram of a first module in an embodiment of the present application;
[0021] Figure 10 It is a schematic overall structural diagram (I) of the clock recovery device in an embodiment of the present application;
[0022] Figure 11 It is a schematic overall structural diagram (II) of the clock recovery device in an embodiment of the present application;
[0023] Figure 12 It is a flowchart of the clock recovery method in an embodiment of the present application;
[0024] Figure 13 It is a signal schematic diagram in the smoothing process and frequency division process according to an embodiment of the present application. Detailed implementation manners
[0025] In the following, embodiments of the present application will be described in detail with reference to the accompanying drawings and in conjunction with the embodiments.
[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence.
[0027] Figure 1 It is a networking schematic diagram of an OTN transmission system, as Figure 1As shown in the figure, the clock recovery device and method in the embodiments of the present application can be applied to the OTN network scenario. Exemplarily, it can be applied to the sending port of the downstream transmission device.
[0028] In some embodiments, the embodiments of the present application can not only be used to recover service clocks such as Synchronous Digital Hierarchy (SDH) and Gigabit Ethernet (GE) from the OTN network, but also be used in the process of recovering the sending clock of the line port.
[0029] An embodiment of the present application provides a clock recovery device. Figure 2 is the structural block diagram of the clock recovery device in the embodiment of the present application. As Figure 2 shown, the clock recovery device includes the following structures:
[0030] A first module 10 and a phase-locked loop 20.
[0031] The phase-locked loop 20 includes a serial-parallel converter 201, and the output end of the first module 10 is connected to the input end of the phase-locked loop 20.
[0032] The first module 10 is configured to receive a system clock and a signal to be recovered in the optical port sending direction, perform smoothing processing and frequency division processing on the signal to be recovered based on the system clock to obtain a first frequency division signal, and input the first frequency division signal into the phase-locked loop.
[0033] The phase-locked loop 20 is configured to generate a calibration signal based on the first frequency division signal, and calibrate the clock frequency point of the serial-parallel converter based on the calibration signal to obtain the recovered clock output by the serial-parallel converter.
[0034] In the embodiments of the present application, a simple and high-precision clock recovery function is implemented based on a digital phase-locked loop. A calibration signal is generated by the phase-locked loop, and the clock frequency point of the serial-parallel converter is calibrated based on the calibration signal to obtain the recovered clock output by the serial-parallel converter. Clock recovery processing can be directly performed in the optical port sending direction, and the implementation method is simple and the accuracy is high. Furthermore, the problem that the clock recovery method in the related art cannot simultaneously meet the requirements of implementation complexity, accuracy, and cost is solved, and the technical effects of reducing costs and improving the clock recovery accuracy are achieved.
[0035] Figure 3 is the structural schematic diagram of the phase-locked loop in an embodiment of the present application. As Figure 3 shown, the phase-locked loop 20 includes the following structures:
[0036] A feedforward circuit 21 and a first frequency division module 22.
[0037] The feedforward circuit 21 includes the serial-parallel converter 201. The output end of the feedforward circuit 21 is connected to the input end of the first frequency division module 22, and the output end of the first frequency division module 22 is connected to the second input end of the feedforward circuit 21.
[0038] Exemplarily, the first input end of the feedforward circuit 21 may be connected to the output end of the first module 10.
[0039] The feedforward circuit 21 is configured to generate a calibration signal based on the first frequency division signal input at the first input end and the second frequency division signal input at the second input end, and calibrate the clock frequency point of the serial-parallel converter based on the calibration signal, and output the recovered clock through the serial-parallel converter.
[0040] The first frequency division module 22 is configured to perform frequency division processing on the recovered clock to obtain the second frequency division signal, and input the second frequency division signal into the feedforward circuit, wherein the frequency point of the second frequency division signal is the same as that of the first frequency division signal.
[0041] Figure 4 is a schematic structural diagram (one) of a feedforward circuit in an embodiment of the present application, as Figure 4 shown, the feedforward circuit 21 includes the following structure:
[0042] Numerical control oscillator 211.
[0043] The numerical control oscillator 211 includes the serial-parallel converter 201. The output end of the numerical control oscillator 211 is connected to the input end of the first frequency division module 22.
[0044] The feedforward circuit 21 is further configured to generate an intermediate signal based on the first frequency division signal and the second frequency division signal.
[0045] The numerical control oscillator 22 is configured to generate the calibration signal based on the intermediate signal, and calibrate the clock frequency point of the serial-parallel converter based on the calibration signal, and output the recovered clock through the serial-parallel converter.
[0046] In this embodiment, the first input end of the feedforward circuit 21 may be connected to the output end of the first module 10, the second input end of the feedforward circuit 21 is connected to the output end of the first frequency division module 22, and the output end of the feedforward circuit 21 is connected to the input end of the first frequency division module 22.
[0047] Figure 5 is a schematic structural diagram (one) of a numerical control oscillator in an embodiment of the present application, as Figure 5 shown, the numerical control oscillator 211 includes the following structure:
[0048] An integrating difference modulator 2111 and a first serial-to-parallel converter 2112 with a phase interpolation controller.
[0049] The output end of the integrating difference modulator 2111 is connected to the input end of the first serial-to-parallel converter 2112.
[0050] The integrating difference modulator 2111 is configured to generate the calibration signal based on the intermediate signal and input the calibration signal into the first serial-to-parallel converter.
[0051] The first serial-to-parallel converter 2112 is configured to control the phase interpolation controller to generate the recovered clock based on the calibration signal and a second reference signal of a preset frequency point input externally.
[0052] Figure 6 This is a schematic diagram (II) of the structure of a numerically controlled oscillator in an embodiment of the present application, as Figure 6 shown. The numerically controlled oscillator 211 includes the following structure:
[0053] An external clock chip 2113 and a second serial-to-parallel converter 2114 without a phase interpolation controller.
[0054] The output end of the external clock chip 2113 is connected to the input end of the second serial-to-parallel converter 2114.
[0055] The external clock chip 2113 is configured to generate a third reference signal under the control of the intermediate signal and input the third reference signal into the second serial-to-parallel converter.
[0056] The second serial-to-parallel converter 2114 is configured to generate the recovered clock based on the third reference signal.
[0057] Figure 7 This is a schematic diagram (II) of the structure of a feedforward circuit in an embodiment of the present application, as Figure 7 shown. The feedforward circuit 21 includes the following structure:
[0058] A numerically controlled oscillator 211 and a phase change rate limiting module 212.
[0059] The output end of the phase change rate limiting module 212 is connected to the input end of the numerically controlled oscillator 211.
[0060] The phase change rate limiting module 212 is configured to limit the phase change rate of the intermediate signal based on a preset phase limit difference to obtain a digitized intermediate signal and input the digitized intermediate signal into the numerically controlled oscillator.
[0061] In this embodiment, the numerically controlled oscillator 211 may adopt the structure of the numerically controlled oscillator in any of the above embodiments. The numerically controlled oscillator 211 is further configured to generate the calibration signal based on the digitized intermediate signal.
[0062] In some embodiments, the phase change rate limiting module 212 is configured to obtain the current phase value and the previous phase value of the intermediate signal based on the intermediate signal, take the absolute value of the difference between the current phase value and the previous phase value to obtain a phase difference; in the case where the phase difference is greater than the phase limit difference, use the sum or difference of the current phase value and the phase limit difference as the output phase; in the case where the phase difference is less than or equal to the phase limit difference, use the current phase value as the output phase; perform digitization processing on the intermediate signal according to the output phase, and input the digitized intermediate signal into the numerically controlled oscillator.
[0063] Exemplarily, the intermediate signal may be a pulse signal, and the pulse signal can be converted into a digital signal by the phase change rate limiting module 212.
[0064] In this embodiment, the phase change rate limiting module can limit the speed of the phase change of the signal to obtain better jitter performance. Exemplarily, the phase change rate limiting module can set a smaller phase mutation value to obtain better jitter performance.
[0065] In one embodiment, for the first serializer / deserializer with a phase interpolation controller, the numerically controlled oscillator includes an integral differential modulator and the phase interpolation controller of the first serializer / deserializer. The digitized intermediate signal after the phase change rate limiting is output as a calibration signal through the integral differential modulator. The first serializer / deserializer controls the internal phase interpolator to regulate the transmission clock (i.e., the recovered clock) according to the calibration signal output by the integral differential modulator to achieve the function of following the service clock.
[0066] In one embodiment, for a field programmable gate array (FPGA) device of the second serializer / deserializer without a phase interpolation controller, the numerically controlled oscillator includes an external clock chip and the second serializer / deserializer without a phase interpolation controller. The digitized intermediate signal obtained after the phase change rate limiting directly regulates the external numerically controlled oscillator and other clock chips. The numerically controlled oscillator and other clock chips generate the reference clock sent by the second serializer / deserializer to achieve the function of following the service clock.
[0067] Figure 8 is a schematic diagram (III) of the structure of a feedforward circuit in an embodiment of the present application, as Figure 8 shown, the feedforward circuit 21 includes the following structure:
[0068] A frequency discriminator / phase discriminator 213, a filter 214, and a numerically controlled oscillator 211.
[0069] A first input terminal of the frequency discriminator / phase discriminator 213 is connected to an output terminal of the first module 10, a second input terminal of the frequency discriminator / phase discriminator 213 is connected to an output terminal of the first frequency division module 22, an output terminal of the frequency discriminator / phase discriminator 213 is connected to an input terminal of the filter 214, an output terminal of the filter 214 is connected to an input terminal of the numerically controlled oscillator 211 or a phase change rate limiting module 212, and an output terminal of the numerically controlled oscillator 211 is connected to an input terminal of the first frequency division module 22.
[0070] The frequency discriminator / phase discriminator 213 is configured to perform frequency discrimination / phase discrimination processing based on the first frequency division signal and the second frequency division signal to obtain a frequency difference / phase difference signal, and input the frequency difference / phase difference signal into the filter.
[0071] The filter 214 is configured to perform filtering processing on the frequency difference / phase difference signal to obtain the intermediate signal, and input the intermediate signal into the numerically controlled oscillator or the phase change rate limiting module.
[0072] In this embodiment, the numerically controlled oscillator 211 may adopt the structure of the numerically controlled oscillator in any of the above embodiments.
[0073] In some embodiments, the feedforward circuit 21 may further include a phase change rate limiting module 212, and the phase change rate of the intermediate signal is limited by the phase change rate limiting module 212 to obtain a digitized intermediate signal, and the digitized intermediate signal is input into the numerically controlled oscillator.
[0074] In other embodiments, if the phase change rate limiting module 212 is not included in the feedforward circuit 21, the filter 214 directly inputs the intermediate signal obtained by the filtering process into the numerically controlled oscillator.
[0075] In one embodiment, the reference clock and the feedback clock of the frequency discriminator / phase discriminator may be divided into a low-frequency clock first and then compared as needed, and the frequency division coefficient can be flexibly configured, and this application does not limit this.
[0076] In an exemplary embodiment, the filter may be a digital second-order loop filter, and the loop bandwidth is from 0.1 Hz to 1 KHz. A larger loop bandwidth can lock the time, but it will cause an increase in jitter. A smaller loop bandwidth has a longer lock time, but better jitter performance. The loop bandwidth can be flexibly configured as needed, and this application does not limit this.
[0077] Figure 9 It is a schematic structural diagram of the first module in an embodiment of the present application, asFigure 9 As shown, the first module 10 may include the following structure:
[0078] A smoothing module 11 and a second frequency division module 12.
[0079] The output end of the smoothing module 11 is connected to the input end of the second frequency division module 12, and the output end of the second frequency division module 12 is connected to the input end of the phase-locked loop 20.
[0080] The smoothing module 11 is configured to receive the system clock and the signal to be recovered, perform smoothing processing on the signal to be recovered based on the system clock to obtain a first reference signal, and input the first reference signal into the second frequency division module.
[0081] The second frequency division module 12 is configured to perform frequency division processing on the first reference signal to obtain the first frequency division signal, and input the first frequency division signal into the phase-locked loop.
[0082] The first module in the embodiments of the present application can be combined with the phase-locked loop in any of the above embodiments. By performing smoothing processing on the signal to be recovered through the smoothing module before the phase-locked loop, the uneven data packet envelope (i.e., the signal to be recovered) after processes such as demapping and cross-clock can be changed into a relatively uniform reference clock, further reducing the clock jitter.
[0083] In this embodiment, since the duty cycle of the reference clock obtained through the processing of the smoothing module fluctuates greatly, it is necessary to use the second frequency division module to further perform frequency division on the reference clock to smooth the duty cycle.
[0084] In an exemplary embodiment, the first frequency division module and the second frequency division module respectively perform frequency division on the recovered clock output by the serializer / deserializer (serdes) and the first reference signal output by the smoothing module, and divide the two signals to the same frequency point.
[0085] In some embodiments, the smoothing module 11 is configured to count the signal to be recovered within a preset cycle period based on the system clock, latch the count value of the signal to be recovered at the end of the cycle period to obtain a latched value, and perform Sigma-Delta frequency division processing on the signal to be recovered with the cycle period as the denominator and the latched value as the numerator to obtain the first reference signal.
[0086] In an exemplary embodiment, the signal to be recovered may be the write enable signal of a FIFO. The smoothing module performs self-loop counting using the system clock on the sending side, and the cycle period can be set. The write enable signal is counted at the start of each cycle period, and the counted value is latched at the end of the cycle period. The write enable signal is Sigma-Delta divided with the latched value as the numerator and the cycle counting period as the denominator.
[0087] In this embodiment, the statistical period of the smoothing module can be flexibly configured as needed, and the present application places no restrictions on this.
[0088] In some embodiments, the smoothing module 11 is further configured to obtain the memory state of the last-in, first-out memory (FIFO) at the last stage in the sending direction, where the signal to be recovered is the output signal of the first-in, first-out memory, and the memory state includes a nearly full state, a nearly empty state, and a normal state;
[0089] In this embodiment, the smoothing module 11 is further configured to, when the memory state is the nearly full state, add 1 to the latched value and then perform Sigma-Delta division processing on the signal to be recovered; when the memory state is the nearly empty state, subtract 1 from the latched value and then perform Sigma-Delta division processing on the signal to be recovered, and when the memory state is the normal state, directly perform Sigma-Delta division processing on the signal to be recovered according to the latched value.
[0090] In this embodiment, the smoothing module can be calibrated according to the state of the last-stage FIFO in the sending direction, where the FIFO state includes a nearly empty state, a nearly full state, and a normal state. When the FIFO is in the nearly full state, 1 needs to be added to the latched value before performing Sigma-Delta division. When the FIFO is in the nearly empty state, 1 needs to be subtracted from the latched value before performing Sigma-Delta division. When the FIFO is in the normal state, Sigma-Delta division is directly performed on the latched value.
[0091] Through the embodiments of the present application, a simple and high-precision clock recovery function is implemented based on a digital phase-locked loop, which can solve the problem that the clock recovery method in the related art cannot simultaneously meet the requirements of implementation complexity, precision, and cost. Compared with the prior art, the embodiments of the present application do not distinguish between service mapping methods and service types, have a wide range of applications, are simple to implement, and have high precision. For devices supporting phase interpolation serial-to-parallel converters, clock chips can be saved and costs can be reduced. For FPGA devices that do not support phase interpolation serial-to-parallel converters, high-precision clock recovery can also be achieved.
[0092] Figure 10This is a schematic diagram of the overall structure of a clock recovery device in an embodiment of the present application (1), as Figure 10 shown. The clock recovery device includes the following structures:
[0093] A smoothing module, a second frequency division module, a frequency discriminator / phase discriminator, a filter, a phase change rate limiting module, an integral differential modulation module, a first serial-parallel converter supporting phase interpolation, and a first frequency division module.
[0094] In this embodiment, the data packet envelope (i.e., the signal to be recovered mentioned above) and the system clock are input to the smoothing module. The output end of the smoothing module is connected to the input end of the second frequency division module. The output end of the second frequency division module is connected to the first input end of the frequency discriminator / phase discriminator. The output end of the frequency discriminator / phase discriminator is connected to the input end of the filter. The output end of the filter is connected to the input end of the phase change rate limiting module. The output end of the phase change rate limiting module is connected to the input end of the integral differential modulation module. The output end of the integral differential modulation module is connected to one input end of the first serial-parallel converter supporting phase interpolation. The fixed frequency point reference clock is input to the other input end of the first serial-parallel converter. The output end of the first serial-parallel converter is connected to the input end of the first frequency division module. The transmission clock of the first serial-parallel converter (i.e., the recovered clock) is input to the first frequency division module. The output end of the first frequency division module is connected to the second input end of the frequency discriminator / phase discriminator.
[0095] The embodiment of the present application can be applied to an FPGA device supporting a serial-parallel converter with phase interpolation, saving clock chips and reducing costs.
[0096] Figure 11 This is a schematic diagram of the overall structure of a clock recovery device in an embodiment of the present application (2), as Figure 11 shown. The clock recovery device includes the following structures:
[0097] A smoothing module, a second frequency division module, a frequency discriminator / phase discriminator, a filter, a phase change rate limiting module, an external clock chip, a second serial-parallel converter not supporting phase interpolation, and a first frequency division module.
[0098] In this embodiment, the data packet envelope (i.e., the signal to be restored mentioned above) and the system clock are used as the inputs of the smoothing module. The output end of the smoothing module is connected to the input end of the second frequency division module. The output end of the second frequency division module is connected to the first input end of the frequency discriminator / phase discriminator. The output end of the frequency discriminator / phase discriminator is connected to the input end of the filter. The output end of the filter is connected to the input end of the phase change rate limiting module. The output end of the phase change rate limiting module is connected to the input end of the external clock chip. The output end of the external clock chip is connected to the input end of the second serial-parallel converter that does not support phase interpolation. The output end of the second serial-parallel converter is connected to the input end of the first frequency division module. The transmission clock (i.e., the restored clock) of the second serial-parallel converter is input into the first frequency division module. The output end of the first frequency division module is connected to the second input end of the frequency discriminator / phase discriminator.
[0099] The embodiment of the present application can be applied to an FPGA device that does not support phase interpolation serial-parallel converters to achieve high-precision clock recovery.
[0100] In another embodiment of the present application, a clock recovery method is also provided. This method can be implemented by the clock recovery device in any of the above device embodiments.
[0101] Figure 12 is a flowchart of the clock recovery method in an embodiment of the present application. As Figure 12 shown, this process includes the following steps:
[0102] Step S1202: Receive the system clock and the signal to be restored in the optical port transmission direction;
[0103] Step S1204: Perform smoothing processing and frequency division processing on the signal to be restored based on the system clock to obtain a first frequency division signal;
[0104] Step S1206: Generate a calibration signal based on the first frequency division signal;
[0105] Step S1208: Calibrate the clock frequency point of the serial-parallel converter based on the calibration signal, and output the restored clock through the serial-parallel converter.
[0106] In this embodiment, through the above steps S1202 to S1208, clock recovery can be directly performed on the sending side, and the function of following the service clock can be realized based on the serial-parallel converter. The implementation method is simple and the clock accuracy is also higher, thereby solving the problem that the clock recovery method in the related technology cannot simultaneously meet the requirements of implementation complexity, accuracy, and cost.
[0107] In some embodiments, step S1206 may include: generating a calibration signal based on the first frequency division signal and the second frequency division signal. Step S1208 may include: calibrating the clock frequency of the serial-to-parallel converter based on the calibration signal, outputting the recovered clock through the serial-to-parallel converter; performing frequency division processing on the recovered clock to obtain the second frequency division signal, where the frequency point of the second frequency division signal is the same as that of the first frequency division signal.
[0108] In some embodiments, step S1206 may include: generating an intermediate signal based on the first frequency division signal and the second frequency division signal; generating the calibration signal based on the intermediate signal.
[0109] In some embodiments, step S1208 may include: inputting the calibration signal into a first serial-to-parallel converter with a phase interpolation controller; in the first serial-to-parallel converter, controlling the phase interpolation controller to generate the recovered clock based on the calibration signal and a second reference signal with a preset frequency point input externally.
[0110] In other embodiments, step S1208 may include: controlling an external clock chip to generate a third reference signal through the intermediate signal, and inputting the third reference signal into a second serial-to-parallel converter without a phase interpolation controller; controlling the second serial-to-parallel converter to generate the recovered clock based on the third reference signal.
[0111] In some embodiments, step S1206 may include: limiting the phase change rate of the intermediate signal based on a preset phase limit difference to obtain a digitized intermediate signal, and controlling a numerically controlled oscillator to generate the calibration signal based on the digitized intermediate signal.
[0112] In some embodiments, step S1206 may further include: obtaining the current phase value and the previous phase value of the intermediate signal based on the intermediate signal, taking the absolute value of the difference between the current phase value and the previous phase value to obtain a phase difference; in the case where the phase difference is greater than the phase limit difference, using the sum or difference of the current phase value and the phase limit difference as the output phase; in the case where the phase difference is less than or equal to the phase limit difference, using the current phase value as the output phase; performing digitization processing on the intermediate signal according to the output phase to obtain a digitized intermediate signal.
[0113] In some embodiments, step S1206 may further include: performing frequency discrimination / phase discrimination processing on the first frequency division signal and the second frequency division signal to obtain a frequency difference / phase difference signal; performing filtering processing on the frequency difference / phase difference signal to obtain the intermediate signal.
[0114] In some embodiments, step S1204 may include: smoothing the signal to be recovered based on the system clock to obtain a first reference signal; performing frequency division processing on the first reference signal to obtain the first divided-frequency signal.
[0115] In some embodiments, the step of smoothing the signal to be recovered based on the system clock in step S1204 to obtain a first reference signal may specifically include: counting the signal to be recovered based on the system clock within a preset cycle period, latching the count value of the signal to be recovered at the end of the cycle period to obtain a latched value, and performing Sigma-Delta frequency division processing on the signal to be recovered with the cycle period as the denominator and the latched value as the numerator to obtain the first reference signal.
[0116] In an exemplary embodiment, performing Sigma-Delta frequency division processing on the signal to be recovered with the cycle period as the denominator and the latched value as the numerator to obtain the first reference signal may specifically include: obtaining the memory state of the last-in first-out (FIFO) memory at the transmission end, where the signal to be recovered is the output signal of the FIFO memory, and the memory state includes a nearly full state, a nearly empty state, and a normal state; in the case where the memory state is the nearly full state, adding 1 to the latched value and then performing Sigma-Delta frequency division processing on the signal to be recovered; in the case where the memory state is the nearly empty state, subtracting 1 from the latched value and then performing Sigma-Delta frequency division processing on the signal to be recovered; and in the case where the memory state is the normal state, directly performing Sigma-Delta frequency division processing on the signal to be recovered according to the latched value.
[0117] Through the embodiments of the present application, a simple and high-precision clock recovery method can be implemented, which can solve the problem that the clock recovery method in the related art cannot simultaneously meet the requirements of implementation complexity, precision, and cost. Compared with the prior art, the embodiments of the present application do not need to distinguish the service mapping method and service type, and have the beneficial effects of wide application range, simple implementation, high precision, and low cost.
[0118] In an exemplary embodiment, taking the Synchronous Transfer Module-16 (STM16) service in cooperation with a serializer / deserializer (Serdes) supporting phase interpolation as an example, the clock recovery process includes the following steps:
[0119] Step S1, smoothing the write enable signal (also referred to as the clock to be recovered or the packet envelope) of the last-stage FIFO in the optical port transmission direction to obtain a clock that has a multiple relationship with the write enable signal and has good uniformity.
[0120] In some embodiments, a self - cycling counter can be designed under the sending - side system clock, and the cycle period can be set. To obtain better jitter performance, the cycle period can be set to 1,000,000. At the start of the cycle period, the write - enable signal of the FIFO is counted, and the counted value is latched at the end of the cycle period. Using the latched value as the numerator and the cycle - counting period as the denominator, Sigma - Delta frequency division is performed on the write - enable signal.
[0121] Exemplarily, for STM16 service data with a data bit - width of 16 bits, the equivalent frequency point is 155.52 MHz, and the reference clock frequency point after Sigma - Delta frequency division is 77.76 MHz.
[0122] Exemplarily, the smoothing module can be calibrated according to the state of the last - stage FIFO in the sending direction, where the FIFO state includes near - empty state, near - full state, and normal state. When the FIFO is in the near - full state, 1 needs to be added to the latched value before performing Sigma - Delta frequency division. When the FIFO is in the near - empty state, 1 needs to be subtracted from the latched value before performing Sigma - Delta frequency division. When the FIFO is in the normal state, Sigma - Delta frequency division is directly performed on the latched value. After smoothing processing, the originally uneven packet envelope after de - mapping and cross - clock processing becomes a relatively uniform reference clock.
[0123] Step S2: Divide the smoothed clock and the recovered clock of the serial - to - parallel converter by a frequency - division module to a same frequency point.
[0124] In this embodiment, since the duty cycle of the reference clock after smoothing fluctuates greatly, further frequency division is required to smooth the duty cycle. Exemplarily, the reference clock after smoothing can be configured to be divided by 19,440, and the sending clock of the serial - to - parallel converter can be divided by 9,720. After frequency division, the frequency points of the two input clocks of the frequency - discriminator and phase - detector are 8 KHz.
[0125] Figure 13 is a signal schematic diagram in the smoothing processing and frequency - division processing procedures in the embodiments of the present application. As Figure 13 shown, the packet envelope (also known as valid data) on the sending side can be smoothed based on the sending - side system clock to obtain a smoothed reference clock (equivalent to the first reference clock above), and a frequency - divided reference clock (equivalent to the first frequency - divided signal above) can be obtained through further frequency - division processing.
[0126] Exemplarily, the smoothing processing and frequency - division processing can be performed successively according to the above - mentioned Step S1 and Step S2.
[0127] Step S3: The frequency discriminator / phase discriminator performs frequency discrimination and phase discrimination on the divided clock to generate a frequency difference / phase difference signal.
[0128] Step S4: The filter smooths the frequency difference / phase difference signal output by the frequency discriminator / phase discriminator to obtain a first reference signal. Exemplarily, the filter bandwidth can be set to 20 Hz.
[0129] Step S5: The phase change rate limiting module performs phase limiting on the first reference signal obtained in step S4 to obtain a digital signal (i.e., the above-mentioned digitized intermediate signal).
[0130] In this embodiment, the phase change rate limiting module mainly realizes the limitation of the speed of phase change to obtain better jitter performance. The phase change rate limiting module can perform beat delay on the current valid input phase value (i.e., the current phase value) to obtain the previous valid input phase value (i.e., the previous phase value). Take the absolute value of the difference between the current phase value and the previous phase value to obtain a phase difference; in the case where the phase difference is greater than the phase limit difference, use the sum or difference of the current phase value and the phase limit difference as the output phase; in the case where the phase difference is less than or equal to the phase limit difference, use the current phase value as the output phase.
[0131] In an exemplary embodiment, the output phase can be determined in the following manner:
[0132]
[0133] diff = |data_in - data_in_pre|;
[0134] where psl_out is the output phase, data_in is the current phase value, data_in_pre is the previous phase value, diff is the phase difference, and psl_lm_dt is the phase limit difference (which can be set manually).
[0135] Exemplarily, the phase limit difference can be set manually as needed, such as set to 1. A smaller phase limit difference can obtain better jitter performance.
[0136] Step S6: The integral differential modulator performs integral differential modulation on the digital signal obtained in step S5 and outputs a calibration signal.
[0137] In an exemplary embodiment, the current input signed data sdm_in(n) of the integrator-differentiator modulator is added to the remainder operand a(n - 1) of the previous operation sum to obtain the current operation sum sum(n). A quantization operation is performed on the current operation sum. Specifically, the upper 5 bits of sum(n) are taken to obtain the quantized result sdm_out(n). sdm_out(n) directly controls the phase interpolator of the serializer / deserializer. A remainder operation is performed on the current operation sum. Specifically, the number of bits remaining after sum(n) removes the upper 5 bits of the most significant bit (MSB) is assigned to a(n), and a(n) is used for the next operation sum operation with the input.
[0138] Step S7: Control the internal phase interpolator of the serializer / deserializer according to the calibration signal obtained in step S6 to regulate the transmission clock of the serializer / deserializer, so as to achieve the function of following the service clock and obtain the recovered clock.
[0139] The embodiment of the present application can directly calibrate the transmission frequency point of the serializer / deserializer based on the digital phase-locked loop to achieve clock recovery. This method can support any external reference clock frequency point. Exemplarily, a fixed reference clock of 250M can be provided, and the Serdes is configured according to the actual rate. The phase calibration signal directly adjusts the phase of the phase-locked loop (PLL) of the serializer / deserializer.
[0140] In the embodiment of the present application, through the above steps S1 to S7, the problem that the clock recovery method in the related art cannot simultaneously meet the requirements of implementation complexity, accuracy, and cost can be solved. Compared with the prior art, the embodiment of the present application does not need to distinguish the service mapping method and the service type, and has the beneficial effects of wide application range, simple implementation, high accuracy, and low cost.
[0141] The embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is run by a processor, it executes the steps in any one of the above method embodiments.
[0142] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (ROM), random access memory (RAM), mobile hard disk, magnetic disk, or optical disc, and other various media that can store computer programs.
[0143] Embodiments of the present application further provide an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.
[0144] In an exemplary embodiment, the above electronic device may further include a transmission device and an input / output device. The transmission device is connected to the above processor, and the input / output device is connected to the above processor.
[0145] Specific examples in this embodiment may refer to the examples described in the above embodiments and exemplary embodiments, and will not be elaborated here.
[0146] The above are only exemplary embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application shall be included in the protection scope of the present application.
Claims
1. A clock recovery device, characterized in that, The device includes a first module and a phase-locked loop. Among them, the phase-locked loop includes a serial-to-parallel converter. The output end of the first module is connected to the input end of the phase-locked loop. Among them, the first module is configured to receive a system clock and a signal to be recovered in the optical port transmission direction, perform smoothing processing and frequency division processing on the signal to be recovered based on the system clock to obtain a first divided-frequency signal, and input the first divided-frequency signal into the phase-locked loop; the phase-locked loop is configured to generate a calibration signal based on the first divided-frequency signal, and calibrate the clock frequency point of the serial-to-parallel converter based on the calibration signal to obtain a recovered clock output by the serial-to-parallel converter.
2. The device according to claim 1, characterized in that The phase-locked loop includes a feedforward circuit and a first frequency division module. Among them, the feedforward circuit includes the serial-to-parallel converter. The output end of the feedforward circuit is connected to the input end of the first frequency division module. The output end of the first frequency division module is connected to the second input end of the feedforward circuit. The first input end of the feedforward circuit is connected to the output end of the first module. Among them, the feedforward circuit is configured to generate a calibration signal based on the first divided-frequency signal input from the first input end and a second divided-frequency signal input from the second input end, and calibrate the clock frequency point of the serial-to-parallel converter based on the calibration signal, and output the recovered clock through the serial-to-parallel converter; the first frequency division module is configured to perform frequency division processing on the recovered clock to obtain the second divided-frequency signal, and input the second divided-frequency signal into the feedforward circuit, where the frequency point of the second divided-frequency signal is the same as that of the first divided-frequency signal.
3. The device according to claim 2, characterized in that, The feedforward circuit includes a numerically controlled oscillator. Among them, the numerically controlled oscillator includes the serial-to-parallel converter. The output end of the numerically controlled oscillator is connected to the input end of the first frequency division module. Among them, the feedforward circuit is further configured to generate an intermediate signal based on the first divided-frequency signal and the second divided-frequency signal; the numerically controlled oscillator is configured to generate the calibration signal based on the intermediate signal, and calibrate the clock frequency point of the serial-to-parallel converter based on the calibration signal, and output the recovered clock through the serial-to-parallel converter.
4. The device according to claim 3, characterized in that, The numerically controlled oscillator includes: an integrating differential modulator and a first serial-to-parallel converter with a phase interpolation controller. Among them, the output end of the integrating differential modulator is connected to the input end of the first serial-to-parallel converter. Among them, the integrating differential modulator is configured to generate the calibration signal based on the intermediate signal and input the calibration signal into the first serial-to-parallel converter; the first serial-to-parallel converter is configured to control the phase interpolation controller to generate the recovered clock based on the calibration signal and a second reference signal with a preset frequency point input externally.
5. The device according to claim 3, wherein The numerically controlled oscillator includes: an external clock chip and a second serial-to-parallel converter without a phase interpolation controller. Among them, the output end of the external clock chip is connected to the input end of the second serial-to-parallel converter. Among them, the external clock chip is configured to generate a third reference signal under the control of the intermediate signal and input the third reference signal into the second serial-to-parallel converter; The second series-parallel converter is configured to generate the recovered clock based on the third reference signal.
6. The device according to claim 3, characterized in that, The feedforward circuit further includes a phase change rate limiting module. The output end of the phase change rate limiting module is connected to the input end of the numerically controlled oscillator. The phase change rate limiting module is configured to limit the phase change rate of the intermediate signal based on a preset phase limit difference to obtain a digitized intermediate signal, and input the digitized intermediate signal into the numerically controlled oscillator. The numerically controlled oscillator is further configured to generate the calibration signal based on the digitized intermediate signal.
7. The device according to claim 6, wherein the phase change rate limiting module is configured to obtain the current phase value and the previous phase value of the intermediate signal based on the intermediate signal, and take the absolute value of the difference between the current phase value and the previous phase value to obtain a phase difference; when the phase difference is greater than the phase limit difference, use the sum or difference of the current phase value and the phase limit difference as the output phase; when the phase difference is less than or equal to the phase limit difference, use the current phase value as the output phase; digitize the intermediate signal according to the output phase, and input the digitized intermediate signal into the numerically controlled oscillator.
8. The device according to claim 3, characterized in that, The feedforward circuit further includes a frequency discriminator / phase discriminator and a filter. The first input end of the frequency discriminator / phase discriminator is connected to the output end of the first module, the second input end of the frequency discriminator / phase discriminator is connected to the output end of the first frequency division module, the output end of the frequency discriminator / phase discriminator is connected to the input end of the filter, and the output end of the filter is connected to the input end of the numerically controlled oscillator or the phase change rate limiting module. The output end of the numerically controlled oscillator is connected to the input end of the first frequency division module. The frequency discriminator / phase discriminator is configured to perform frequency discrimination / phase discrimination processing based on the first frequency division signal and the second frequency division signal to obtain a frequency difference / phase difference signal, and input the frequency difference / phase difference signal into the filter. The filter is configured to perform filtering processing on the frequency difference / phase difference signal to obtain the intermediate signal, and input the intermediate signal into the numerically controlled oscillator or the phase change rate limiting module.
9. The device according to claim 1, characterized in that, The first module includes a smoothing module and a second frequency division module. The output end of the smoothing module is connected to the input end of the second frequency division module, and the output end of the second frequency division module is connected to the input end of the phase-locked loop. The smoothing module is configured to receive the system clock and the signal to be recovered, perform smoothing processing on the signal to be recovered based on the system clock to obtain a first reference signal, and input the first reference signal into the second frequency division module. The second frequency division module is configured to perform frequency division processing on the first reference signal to obtain the first frequency division signal, and input the first frequency division signal into the phase-locked loop.
10. The device according to claim 9, wherein The smoothing module is configured to count the signal to be restored within a preset cycle period based on the system clock, latch the count value of the signal to be restored at the end of the cycle period to obtain a latched value, and perform Sigma-Delta frequency division processing on the signal to be restored with the cycle period as the denominator and the latched value as the numerator to obtain the first reference signal.
11. The apparatus according to claim 10, wherein the smoothing module is further configured to obtain the memory state of the last-in first-out memory at the transmission direction, where the signal to be restored is the output signal of the first-in first-out memory, and the memory state includes a nearly full state, a nearly empty state, and a normal state; the smoothing module is further configured to, when the memory state is the nearly full state, add 1 to the latched value and then perform Sigma-Delta frequency division processing on the signal to be restored; when the memory state is the nearly empty state, subtract 1 from the latched value and then perform Sigma-Delta frequency division processing on the signal to be restored; and when the memory state is the normal state, directly perform Sigma-Delta frequency division processing on the signal to be restored according to the latched value.
12. A clock recovery method, characterized in that, Applied to the clock recovery apparatus in any one of claims 1 to 11 above, the method includes: Receiving a system clock and a signal to be restored in the optical port transmission direction; Performing smoothing processing and frequency division processing on the signal to be restored based on the system clock to obtain a first frequency-divided signal; Generating a calibration signal based on the first frequency-divided signal; Calibrating the clock frequency point of the serial-to-parallel converter based on the calibration signal, and outputting a recovered clock through the serial-to-parallel converter.
13. A computer-readable storage medium, characterized in that, A computer program is stored in the storage medium, wherein the computer program, when run by a processor, executes the method described in claim 12.
14. An electronic device, comprising a memory and a processor, characterized in that, A computer program is stored in the memory, and the processor is configured to run the computer program to execute the method described in claim 12.