Semiconductor device, manufacturing method thereof and circuit structure

Abstract

The invention relates to the field of semiconductors, and discloses a semiconductor device and a manufacturing method thereof, and a circuit structure, and the method comprises the steps: growing an epitaxial layer on the upper surface of a first substrate; forming a patterned first gate dielectric layer on the surface, deviating from the first substrate, of the epitaxial layer; growing metal on the surface, deviating from the epitaxial layer, of the first gate dielectric layer to form a first gate and a second gate; forming a source electrode and a drain electrode on the surface, deviating from the first substrate, of the epitaxial layer; the first grid is located between the source and the second grid, and the first grid is electrically connected with the source; removing the first substrate, and etching the epitaxial layer to form a third gate groove; the third gate groove is opposite to the second gate; growing a second gate dielectric layer on the surface of the epitaxial layer; growing metal in the third gate groove with the second gate dielectric layer to form a third gate and obtain the semiconductor device; the third gate is short-circuited with the second gate. According to the enhanced device manufactured in the invention, the first grid plays an auxiliary role, and current collapse can be relieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and particularly to a semiconductor device, a manufacturing method thereof, and a circuit structure. Background Art

[0002] The enhancement-mode high electron mobility transistor (HEMT) adopts a heterostructure, and uses the energy band difference between different materials to form a two-dimensional electron gas (2DEG) at the interface. When there is no applied gate voltage, the 2DEG concentration in the channel is low, and the transistor device is in the cut-off state; when a positive gate voltage is applied, the electron concentration in the channel can be effectively enhanced, making the transistor device conduct, thereby realizing the control of the current.

[0003] Currently, the methods for realizing the enhancement mode of high electron mobility transistors include the P-GaN gate technology, the fluoride ion implantation technology, and the storage gate dielectric technology, etc. The P-GaN gate technology introduces a P-GaN layer between the gate electrode and the barrier layer to deplete the 2DEG under the gate. This technology has a complex process, and the high-concentration P-type doping is a technical difficulty; the storage gate dielectric technology uses a material capable of storing electrons as the gate dielectric, and depletes the 2DEG under the gate by capturing electrons. This technology increases the complexity of the gate drive circuit and the process is complex; the fluoride ion implantation technology implants fluoride ions into the barrier layer under the gate to deplete the 2DEG. Ion implantation is likely to cause material damage and easily cause problems such as current collapse and threshold instability. In addition, the existing enhancement-mode high electron mobility transistors are prone to a significant increase in the dynamic on-resistance and a significant decrease in the on-current during the switching process, which is called current collapse.

[0004] Therefore, how to solve the above technical problems should be the focus of attention of those skilled in the art. Summary of the Invention

[0005] The purpose of the present application is to provide a semiconductor device, a manufacturing method thereof, and a circuit structure, so that the method has the characteristics of low damage and easy implementation when manufacturing an enhancement-mode semiconductor device, and at the same time can alleviate current collapse.

[0006] To solve the above technical problems, the present application provides a manufacturing method of a semiconductor device, including:

[0007] Growing an epitaxial layer on the upper surface of a first substrate;

[0008] Forming a patterned first gate dielectric layer on the surface of the epitaxial layer facing away from the first substrate;

[0009] Growing a metal on the surface of the first gate dielectric layer facing away from the epitaxial layer to form a first gate and a second gate;

[0010] Source and drain are formed on the surface of the epitaxial layer facing away from the first substrate; the first gate is located between the source and the second gate, and the first gate is electrically connected to the source;

[0011] The first substrate is removed, and the epitaxial layer is etched to form a third gate groove; the third gate groove is opposite to the second gate;

[0012] A second gate dielectric layer is grown on the surface of the epitaxial layer;

[0013] Metal is grown in the third gate groove having the second gate dielectric layer to form a third gate, obtaining a semiconductor device; the third gate is shorted to the second gate.

[0014] As an implementable manner, after removing the first substrate, it further includes:

[0015] The epitaxial layer is etched to form a fourth gate groove; the fourth gate groove is opposite to the first gate;

[0016] After growing the second gate dielectric layer on the surface of the epitaxial layer, it further includes:

[0017] Metal is grown in the fourth gate groove having the second gate dielectric layer to form a fourth gate; the fourth gate is shorted to the first gate.

[0018] As an implementable manner, after growing metal on the surface of the first gate dielectric layer facing away from the epitaxial layer to form the first gate and the second gate, it further includes:

[0019] A patterned passivation layer is formed on the surface of the epitaxial layer facing away from the first substrate; the passivation layer is located between the source and the first gate, between the first gate and the second gate, and between the second gate and the drain.

[0020] As an implementable manner, removing the first substrate includes:

[0021] A semiconductor layer is grown on the target surface; the target surface is the surface formed by the source, the drain, the first gate, the second gate, and the passivation layer facing away from the epitaxial layer;

[0022] The surface of the semiconductor layer facing away from the epitaxial layer is bonded to a second substrate;

[0023] Chemical mechanical polishing is performed on the lower surface of the first substrate to remove the first substrate.

[0024] As an implementable manner, growing an epitaxial layer on the upper surface of the first substrate includes:

[0025] A buffer layer is grown on the upper surface of the first substrate;

[0026] A channel layer is grown on the surface of the buffer layer facing away from the first substrate;

[0027] A barrier layer is grown on the surface of the channel layer facing away from the buffer layer;

[0028] Wherein, the room temperature resistivity of the buffer layer is greater than 10 6 Ω·cm; and / or, the channel layer is an unintentionally doped channel layer, and the concentration of background impurity carbon is less than 10 16 cm −3 .

[0029] As an implementable manner, a first distance between the source electrode and the first gate is less than a second distance between the second gate and the drain electrode.

[0030] As an implementable manner, etching the epitaxial layer to form a third gate groove includes:

[0031] Rough etching the epitaxial layer by inductively coupled plasma etching; wherein, the etching gas includes chlorine gas, boron trichloride and argon gas, the flow rate range of chlorine gas is 20 standard cubic centimeters per minute to 40 standard cubic centimeters per minute, the flow rate range of boron trichloride is 10 standard cubic centimeters per minute to 20 standard cubic centimeters per minute, the flow rate range of argon gas is 5 standard cubic centimeters per minute to 15 standard cubic centimeters per minute; the temperature range of rough etching is 20 degrees Celsius to 60 degrees Celsius; the etching chamber pressure range is 10 millitorr to 30 millitorr, and the etching power range is 600 watts to 1000 watts;

[0032] Fine etching the epitaxial layer by inductively coupled plasma etching; wherein, the etching gas includes chlorine gas, boron trichloride and hydrogen gas, the flow rate range of chlorine gas is 10 standard cubic centimeters per minute to 20 standard cubic centimeters per minute, the flow rate range of boron trichloride is 5 standard cubic centimeters per minute to 10 standard cubic centimeters per minute, the flow rate range of hydrogen gas is 5 standard cubic centimeters per minute to 10 standard cubic centimeters per minute; the temperature range of fine etching is 20 degrees Celsius to 40 degrees Celsius; the etching chamber pressure range is 5 millitorr to 10 millitorr, and the etching power range is 400 watts to 600 watts.

[0033] As an implementable manner, after removing the first substrate, it further includes:

[0034] Etching the epitaxial layer to form a field plate groove, the field plate groove is located on one side of the third gate close to the drain electrode; the depth of the field plate groove is less than the depth of the third gate groove;

[0035] After growing a second gate dielectric layer on the surface of the epitaxial layer, the following steps are further included:

[0036] Grow metal in the field plate groove having the second gate dielectric layer to form a gate field plate.

[0037] This application also provides a semiconductor device, which is fabricated by using the manufacturing method of any one of the above-mentioned semiconductor devices.

[0038] This application also provides a circuit structure, including the above-mentioned semiconductor device.

[0039] A manufacturing method of a semiconductor device provided by this application includes: growing an epitaxial layer on the upper surface of a first substrate; forming a patterned first gate dielectric layer on the surface of the epitaxial layer facing away from the first substrate; growing metal on the surface of the first gate dielectric layer facing away from the epitaxial layer to form a first gate and a second gate; forming a source electrode and a drain electrode on the surface of the epitaxial layer facing away from the first substrate; the first gate is located between the source electrode and the second gate, and the first gate is electrically connected to the source electrode; removing the first substrate and etching the epitaxial layer to form a third gate groove; the third gate groove is opposite to the second gate; growing a second gate dielectric layer on the surface of the epitaxial layer; growing metal in the third gate groove having the second gate dielectric layer to form a third gate, thereby obtaining a semiconductor device; the third gate is short-circuited with the second gate.

[0040] It can be seen that in the manufacturing method of the present application, an epitaxial layer and a patterned first gate dielectric layer are sequentially grown on a first substrate. A first gate and a second gate are grown on the first gate dielectric layer. Source and drain electrodes are grown on the surface of the epitaxial layer. After removing the first substrate, the epitaxial layer is etched, and a second gate dielectric layer is grown on the surface of the epitaxial layer. Then, a third gate is formed in the third gate groove formed by etching. Since the third gate is short-circuited with the second gate, and the third gate, the second gate dielectric layer, and the epitaxial layer form a MIS (Metal-Insulator-Semiconductor) structure above the two-dimensional electron gas in the epitaxial layer, and the second gate, the first gate dielectric layer, and the epitaxial layer form a MIS structure below the two-dimensional electron gas in the epitaxial layer. That is, two MIS structures are formed in the present application. By the depletion effect of the work function difference of these two MIS structures on the electrons in the channel region of the epitaxial layer, enhancement is achieved, that is, an enhancement-mode semiconductor device is obtained. The semiconductor device of the present application not only has a high electron current density at the two-dimensional electron gas channel, but also introduces a new electron current path in the electron accumulation layer near the third gate. When conducting forward, on the one hand, the two-dimensional electron gas depleted only by the work function difference is restored to a higher concentration due to the high gate potential; on the other hand, the high-concentration electron accumulation layer formed by the MIS structure provides a new conduction channel, both of which can effectively increase the saturation output current and reduce the specific on-resistance.

[0041] The first gate plays an auxiliary role. When the semiconductor device is in the off state, electrons will accumulate in the epitaxial layer above the first gate. Once the semiconductor device conducts, the electrons accumulated in the epitaxial layer above the first gate will quickly move to the epitaxial layer above the second gate structure and the depletion region in the epitaxial layer below the third gate, alleviating current collapse. In addition, the manufacturing method of the present application does not require ion implantation, which can avoid problems such as damage to the semiconductor device caused by ion implantation, and can be completed through conventional semiconductor processes without complex processes such as P-GaN gate technology and storage gate dielectric technology, which can reduce the manufacturing difficulty of the semiconductor device and has the characteristics of being easy to implement.

[0042] In addition, the present application also provides a semiconductor device and a circuit structure having the above advantages. Description of the Drawings

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0044] Figure 1Flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application Figure 1 ;

[0045] Figure 2 Flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application Figure 2 ;

[0046] Figures 3 to 10 Process flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0047] Figure 11 Schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

[0048] In the figure, 1 is the first substrate, 2 is the epitaxial layer, 3 is the first gate dielectric layer, 4 is the first gate, 5 is the second gate, 6 is the passivation layer, 7 is the source electrode, 8 is the drain electrode, 9 is the semiconductor layer, 10 is the second substrate, 11 is the second gate dielectric layer, 13 is the gate field plate, 12 is the third gate, and 14 is the fourth gate. Detailed implementation manners

[0049] In order to enable those skilled in the art to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific implementation manners. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the protection scope of the present application.

[0050] In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0051] As described in the background art section, currently, when implementing an enhancement-mode high electron mobility transistor, P-GaN gate technology, fluoride ion implantation technology, and storage gate dielectric technology can be used, which have problems such as complex manufacturing processes, easy to cause damage, and in the switching process, the dynamic on-resistance is likely to decrease.

[0052] In view of this, the present application provides a method for manufacturing a semiconductor device. Please refer to Figure 1 , and the method may include:

[0053] Step S101: Grow an epitaxial layer on the upper surface of the first substrate.

[0054] The first substrate can be a Si(111) substrate, and the thickness range of the first substrate can be 300 μm to 500 μm, which can be specifically set by oneself and is not specifically limited in this embodiment.

[0055] As an implementable manner, the epitaxial layer can include a buffer layer, a channel layer, and a barrier layer. The buffer layer can be a GaN buffer layer, and the thickness range of the buffer layer can be 1.5 μm to 3.5 μm; the channel layer can be a GaN channel layer, and the thickness range of the channel layer can be 50 nm to 100 nm; the barrier layer can be Al x Ga 1-x GaN barrier layer, where x represents the component ratio of Al, 0 ≤ x ≤ 0.3, and the thickness range of the barrier layer can be 5 nm to 30 nm.

[0056] The growth process of the epitaxial layer can include:

[0057] Growing a buffer layer on the upper surface of the first substrate;

[0058] Growing a channel layer on the surface of the buffer layer facing away from the first substrate;

[0059] Growing a barrier layer on the surface of the channel layer facing away from the buffer layer.

[0060] Step S102: Form a patterned first gate dielectric layer on the surface of the epitaxial layer facing away from the first substrate.

[0061] Grow a first gate dielectric layer on the surface of the epitaxial layer facing away from the first substrate. The growth method of the first gate dielectric layer can be PECVD (Plasma Enhanced Chemical Vaper Deposition), and then perform patterning on the first gate dielectric layer to form a patterned first gate dielectric layer. The position of the patterned first gate dielectric layer corresponds to the positions of the first gate and the second gate.

[0062] It should be noted that in this embodiment, the material of the first gate dielectric layer is not limited and can be selected by oneself.

[0063] The material of the first gate dielectric layer includes but is not limited to Al2O3, SiO2, SiN, AlN, SiNx, etc., and the thickness range of the first gate dielectric layer can be 1 nm to 5 nm.

[0064] Step S103: Grow metal on the surface of the first gate dielectric layer facing away from the epitaxial layer to form the first gate and the second gate.

[0065] Deposit metal on the first gate dielectric layer to form a metal layer, and then use wet etching to strip the metal outside the first gate and second gate regions to form the first gate and the second gate.

[0066] The material of the first gate can be Ni / Au or Pt / Au. Ni / Au means that in the direction away from the first gate dielectric layer, the first layer is Ni and the second layer is Au; Pt / Au means that in the direction away from the first gate dielectric layer, the first layer is Pt and the second layer is Au.

[0067] The thickness of the first gate is 22 nm / 150 nm, and the first gate electrode length can be 1 μm.

[0068] The material of the second gate can be Ni / Au or Pt / Au. Ni / Au means that in the direction away from the first gate dielectric layer, the first layer is Ni and the second layer is Au; Pt / Au means that in the direction away from the first gate dielectric layer, the first layer is Pt and the second layer is Au.

[0069] The thickness of the second gate can be 22 nm / 150 nm, and the second gate electrode length can be 1 μm.

[0070] Step S104: Form a source electrode and a drain electrode on the surface of the epitaxial layer facing away from the first substrate; the first gate is located between the source electrode and the second gate, and the first gate is electrically connected to the source electrode.

[0071] The growth method of the source electrode and the drain electrode can be magnetron sputtering or other methods, which are not limited in this embodiment. After growth, the sample is placed in an annealing furnace for annealing. The annealing temperature range can be 800 °C to 900 °C, and the annealing time can be 30 s.

[0072] The metal material of the source electrode can be Ti / Al / Ni / Au. Ti / Al / Ni / Au means that in the direction away from the epitaxial layer, the first layer is Ti, the second layer is Al, the third layer is Ni, and the fourth layer is Au. The thickness of Ti / Al / Ni / Au can be 22 nm / 60nm / 55 nm / 50 nm.

[0073] The metal material of the drain electrode can be Ti / Al / Ni / Au. Ti / Al / Ni / Au means that in the direction away from the epitaxial layer, the first layer is Ti, the second layer is Al, the third layer is Ni, and the fourth layer is Au. The thickness of Ti / Al / Ni / Au can be 22 nm / 60nm / 55 nm / 50 nm.

[0074] Step S105: Remove the first substrate and etch the epitaxial layer to form a third gate groove; the third gate groove is opposite to the second gate.

[0075] It should be noted that in this embodiment, the correspondence between the third gate groove and the second gate is not limited and can be set by oneself.

[0076] As an implementable manner, the third gate groove is completely aligned with the second gate, that is, the third gate and the second gate are completely aligned to evenly distribute the electric field. In addition, the second gate, the first gate dielectric layer, and the barrier layer in the epitaxial layer form a MIS structure below the two-dimensional electron gas channel, and the third gate, the second gate dielectric layer, and the buffer layer form a MIS structure above the two-dimensional electron gas channel. The enhancement mode is achieved through the depletion effect of the work function difference between the two MIS structures on the electrons in the channel region.

[0077] Not only is there a high concentration of electron current density at the two-dimensional electron gas channel, but also a new electron current path is introduced in the electron accumulation layer near the third gate.

[0078] It should be noted that in this embodiment, the process of etching to form the third gate groove is not limited as long as the third gate groove can be formed.

[0079] As an implementable manner, etching the epitaxial layer to form the third gate groove includes:

[0080] Rough etching the epitaxial layer by inductively coupled plasma etching; wherein, the etching gas includes chlorine gas, boron trichloride, and argon gas. The flow rate range of chlorine gas is 20 standard cubic centimeters per minute to 40 standard cubic centimeters per minute, the flow rate range of boron trichloride is 10 standard cubic centimeters per minute to 20 standard cubic centimeters per minute, and the flow rate range of argon gas is 5 standard cubic centimeters per minute to 15 standard cubic centimeters per minute; the temperature range of rough etching is 20 degrees Celsius to 60 degrees Celsius; the pressure range of the etching chamber is 10 millitorr to 30 millitorr, and the etching power range is 600 watts to 1000 watts;

[0081] Finely etching the epitaxial layer by inductively coupled plasma etching; wherein, the etching gas includes chlorine gas, boron trichloride, and hydrogen gas. The flow rate range of chlorine gas is 10 standard cubic centimeters per minute to 20 standard cubic centimeters per minute, the flow rate range of boron trichloride is 5 standard cubic centimeters per minute to 10 standard cubic centimeters per minute, and the flow rate range of hydrogen gas is 5 standard cubic centimeters per minute to 10 standard cubic centimeters per minute; the temperature range of fine etching is 20 degrees Celsius to 40 degrees Celsius; the pressure range of the etching chamber is 5 millitorr to 10 millitorr, and the etching power range is 400 watts to 600 watts.

[0082] The third gate groove is made by first rough etching and then fine etching, which can improve the etching efficiency and ensure the etching accuracy at the same time.

[0083] Step S106: Grow the second gate dielectric layer on the surface of the epitaxial layer.

[0084] It should be noted that in this embodiment, the growth method of the second gate dielectric layer is not limited and can be set by oneself. For example, the growth method of the second gate dielectric layer can be plasma enhanced chemical vapor deposition method.

[0085] It should also be noted that in this embodiment, the material of the second gate dielectric layer is not limited and can be selected by oneself.

[0086] The material of the second gate dielectric layer includes but is not limited to Al2O3, SiO2, SiN, AlN, SiNx, etc., and the thickness range of the second gate dielectric layer can be 1nm to 5nm.

[0087] Step S107: Grow metal in the third gate groove with the second gate dielectric layer to form a third gate, obtaining a semiconductor device; the third gate is shorted to the second gate.

[0088] In this embodiment, the growth method of the third gate is not limited and can be selected by oneself. For example, magnetron sputtering or other methods can be used.

[0089] The material of the third gate can be Ni / Au, where Ni / Au means that in the direction away from the second gate dielectric layer, the first layer is Ni and the second layer is Au.

[0090] The third gate leads out a pad (bonding pad), and the second gate also leads out a pad (bonding pad). The third gate and the second gate are shorted through the connection of the pads. The third gate and the second gate are shorted, and the third gate and the second gate are at the same potential.

[0091] In the manufacturing method of this embodiment, an epitaxial layer and a patterned first gate dielectric layer are sequentially grown on a first substrate. A first gate and a second gate are grown on the first gate dielectric layer. Source and drain electrodes are grown on the surface of the epitaxial layer. After removing the first substrate, the epitaxial layer is etched, and a second gate dielectric layer is grown on the surface of the epitaxial layer. Then, a third gate is formed in the third gate groove formed by etching. Since the third gate is short-circuited with the second gate, and the third gate, the second gate dielectric layer, and the buffer layer in the epitaxial layer form a MIS (Metal-Insulator-Semiconductor) structure above the two-dimensional electron gas in the epitaxial layer, and the second gate, the first gate dielectric layer, and the barrier layer in the epitaxial layer form a MIS structure below the two-dimensional electron gas in the epitaxial layer. That is, two MIS structures are formed in this application. The enhancement type is achieved through the depletion effect of the work function difference of these two MIS structures on the electrons in the channel region of the epitaxial layer, that is, an enhancement type semiconductor device is obtained. The semiconductor device of this application not only has a high electron current density at the two-dimensional electron gas channel, but also introduces a new electron current path in the electron accumulation layer near the third gate. When conducting forward, on the one hand, the two-dimensional electron gas depleted only by the work function difference is restored to a higher concentration due to the high gate potential; on the other hand, the high-concentration electron accumulation layer formed by the MIS structure provides a new conduction channel, both of which can effectively increase the saturation output current and reduce the specific on-resistance.

[0092] The first gate plays an auxiliary role. When the semiconductor device is in the off state, electrons will accumulate in the channel layer of the epitaxial layer above the first gate. Once the semiconductor device conducts, the electrons accumulated in the epitaxial layer above the first gate will quickly move to the epitaxial layer above the second gate structure and the depletion region in the epitaxial layer below the third gate, alleviating current collapse. In addition, the manufacturing method in this application does not require ion implantation, which can avoid problems such as damage to the semiconductor device caused by ion implantation, and can be completed through conventional semiconductor processes. It does not require complex processes such as P-GaN gate technology and storage gate dielectric technology, which can reduce the manufacturing difficulty of the semiconductor device and has the characteristics of being easy to implement.

[0093] Please refer to Figure 2 , on the basis of the above embodiment, in an embodiment of this application, the manufacturing method of the semiconductor device includes:

[0094] Step S201: Grow an epitaxial layer on the upper surface of the first substrate.

[0095] Step S202: Form a patterned first gate dielectric layer on the surface of the epitaxial layer facing away from the first substrate.

[0096] Step S203: Grow metal on the surface of the first gate dielectric layer facing away from the epitaxial layer to form a first gate and a second gate.

[0097] Step S204: Form a source electrode and a drain electrode on the surface of the epitaxial layer facing away from the first substrate; the first gate electrode is located between the source electrode and the second gate electrode, and the first gate electrode is electrically connected to the source electrode.

[0098] Step S205: Remove the first substrate and etch the epitaxial layer to form a third gate groove and a fourth gate groove; the third gate groove faces the second gate electrode; the fourth gate groove faces the first gate electrode.

[0099] In this embodiment, the third groove and the fourth groove are etched together, which can save the manufacturing process steps.

[0100] It should be noted that in this embodiment, the corresponding degree between the fourth gate groove and the first gate electrode is not limited and can be set by itself.

[0101] As an implementable manner, the fourth gate groove is completely opposite to the first gate electrode, that is, the fourth gate electrode and the first gate electrode are completely opposite to each other to evenly distribute the electric field.

[0102] Step S206: Grow a second gate dielectric layer on the surface of the epitaxial layer.

[0103] Step S207: Grow metal in the third gate groove with the second gate dielectric layer and the fourth gate groove with the second gate dielectric layer to form a third gate electrode and a fourth gate electrode, obtaining a semiconductor device; the third gate electrode is short-circuited with the second gate electrode; the fourth gate electrode is short-circuited with the first gate electrode.

[0104] The fourth gate electrode is electrically connected to the source electrode.

[0105] In this embodiment, the third gate electrode and the fourth gate electrode are formed together, which can save the process steps.

[0106] The material of the fourth gate electrode can be Ni / Au, and Ni / Au means that in the direction away from the second gate dielectric layer, the first layer is Ni and the second layer is Au.

[0107] The fourth gate electrode leads out a pad (bonding pad), and the first gate electrode also leads out a pad (bonding pad). The fourth gate electrode and the first gate electrode are short-circuited through the connection of the pads. The fourth gate electrode and the second gate electrode are short-circuited, and the fourth gate electrode and the first gate electrode are at the same potential.

[0108] In this embodiment, the fabricated semiconductor device has four gates, namely a first gate, a second gate, a third gate, and a fourth gate. The function of the fourth gate is similar to that of the first gate, and the fourth gate also plays an auxiliary role, further increasing the electron concentration in the channel layer below the fourth gate structure. Once the semiconductor device is turned on and a positive voltage is applied to the drain, the electrons accumulated in the channel layer below the fourth gate structure will quickly move to the depletion region of the channel layer below the third gate structure, further alleviating current collapse.

[0109] Based on any of the above embodiments, in an embodiment of the present application, after growing metal on the surface of the first gate dielectric layer facing away from the epitaxial layer to form the first gate and the second gate, the manufacturing method of the semiconductor device may further include:

[0110] Forming a patterned passivation layer on the surface of the epitaxial layer facing away from the first substrate; the passivation layer is located between the source electrode and the first gate, between the first gate and the second gate, and between the second gate and the drain electrode.

[0111] The material of the passivation layer may be SiNx, and the thickness range of the passivation layer may be 10 nm to 50 nm.

[0112] It should be noted that in this embodiment, the manufacturing method of the passivation layer is not limited and can be set by itself.

[0113] For example, the passivation layer can be fabricated by plasma-enhanced chemical vapor deposition or other methods.

[0114] When depositing the passivation layer, the passivation layer is also distributed at the positions of the source electrode and the drain electrode, and then the inductively coupled plasma (ICP) etching technology is used to etch the passivation layer to form a source electrode groove and a drain electrode groove.

[0115] In this embodiment, on the one hand, the function of the passivation layer is to isolate the source electrode from the first gate, isolate the first gate from the second gate, and isolate the second gate from the drain electrode; on the other hand, the passivation layer also has a protective effect, protecting the surface of the barrier layer and the surface of the semiconductor layer.

[0116] Based on the above embodiments, in an embodiment of the present application, the manufacturing method of the semiconductor device includes:

[0117] Step S301: Growing an epitaxial layer on the upper surface of the first substrate.

[0118] Step S302: Forming a patterned first gate dielectric layer on the surface of the epitaxial layer facing away from the first substrate.

[0119] Step S303: Growing metal on the surface of the first gate dielectric layer facing away from the epitaxial layer to form the first gate and the second gate.

[0120] Step S304: Form a passivation layer on the surface of the epitaxial layer facing away from the first substrate.

[0121] Step S305: Etch the passivation layer to form source and drain grooves, obtaining a patterned passivation layer; and deposit metal in the source and drain grooves to form a source and a drain.

[0122] Wherein, the first gate is located between the source and the second gate, the first gate is electrically connected to the source, and the passivation layer is located between the source and the first gate, between the first gate and the second gate, and between the second gate and the drain.

[0123] Step S306: Grow a semiconductor layer on the target surface; the target surface is the surface formed by the source, the drain, the first gate, the second gate, and the passivation layer facing away from the epitaxial layer.

[0124] The target surface is a flat surface, that is, the surfaces of the source, the drain, the first gate, the second gate, and the passivation layer on the side away from the first substrate are flush.

[0125] The semiconductor layer can be a polycrystalline AlN thin film. The growth method of the polycrystalline AlN thin film can be Physical Vapour Deposition (PVD) method or other methods. The thickness range of the polycrystalline AlN thin film can be 50 nm to 300 nm.

[0126] Step S307: Bond the surface of the semiconductor layer facing away from the epitaxial layer to the second substrate.

[0127] The second substrate can be a Si(100) substrate.

[0128] It should be noted that in this embodiment, the bonding process is not specifically limited as long as bonding can be achieved.

[0129] As an implementable manner, a bonding intermediate layer can be uniformly grown on the surface of the second substrate and the surface of the semiconductor layer facing away from the epitaxial layer by using a magnetron sputtering process. The bonding intermediate layer can be Au / In, and the thickness of the Au / In bonding layer is 500 nm to 2 um / 500 nm to 2 um; then the second substrate with the bonding intermediate layer grown and the semiconductor layer are accurately aligned and bonded face to face, and then placed in a bonding machine. During the bonding process, the bonding temperature range can be set to 280 °C to 320 °C, the bonding pressure range can be set to 10 MPa to 30 MPa, and the bonding time range can be 30 min to 90 min. After the bonding is completed, wait for the temperature to cool to room temperature, release the pressure and take out the sample to end the bonding process. At this time, the device completes the flipping process.

[0130] Step S308: Chemically mechanically polish the first substrate from the lower surface of the first substrate to remove the first substrate.

[0131] Step S309: Etch the epitaxial layer to form a third gate groove; the third gate groove is opposite to the second gate.

[0132] Since the first substrate has been removed, the epitaxial layer is exposed, specifically the surface of the buffer layer is exposed. Since the surface of the buffer layer exposed after chemically mechanically polishing the first substrate is rough and not smooth enough. Before forming the third gate groove, the surface of the buffer layer can also be smoothed so that the subsequently grown second gate dielectric layer can be firmly combined with the buffer layer.

[0133] As an implementable manner, when smoothing the buffer layer, an ICP etching method can be used to precisely etch the buffer layer, and the etching depth range can be 1 μm to 1.5 μm.

[0134] Step S310: Grow a second gate dielectric layer on the surface of the epitaxial layer.

[0135] Step S311: Grow metal in the third gate groove with the second gate dielectric layer to form a third gate, obtaining a semiconductor device; the third gate is short-circuited with the second gate.

[0136] In this embodiment, the flipping of the device is realized by bonding with the second substrate, and then the first substrate is removed to realize the fabrication of the third gate, and the process is simple and easy to implement.

[0137] Based on any of the above embodiments, in an embodiment of the present application, growing an epitaxial layer on the upper surface of the first substrate includes:

[0138] Grow a buffer layer on the upper surface of the first substrate;

[0139] Grow a channel layer on the surface of the buffer layer facing away from the first substrate;

[0140] Grow a barrier layer on the surface of the channel layer facing away from the buffer layer;

[0141] Wherein, the room temperature resistivity of the buffer layer is greater than 10 6 Ω·cm; and / or, the channel layer is an unintentionally doped channel layer, and the concentration of background impurity carbon is less than 10 16 cm −3 .

[0142] The room temperature resistivity of the buffer layer is greater than 10 6Ω·cm, the buffer layer is a high-resistance buffer layer. On the one hand, the channel layer is located on the side of the high-resistance buffer layer close to the barrier layer. By improving the quality and thickness of the high-resistance buffer layer, the quality and flatness of the heterojunction interface can be significantly improved, thereby improving the transport performance of the two-dimensional electron gas. On the other hand, the grown buffer layer has a relatively high resistivity to prevent the leakage of electrons from the channel layer to the buffer layer and solve the problem of buffer layer leakage in the device.

[0143] The unintentionally doped channel layer can improve the transport performance of the two-dimensional electron gas in the epitaxial structure.

[0144] The concentration of background impurity carbon is less than 10 16 cm −3 , which can avoid the formation of deep-level traps or scattering centers.

[0145] Compared with the ordinary channel layer, on the one hand, the undoped high-mobility channel layer has higher crystal quality and low dislocation density, which can provide a high-quality transport channel for the two-dimensional electron gas and reduce scattering; on the other hand, it can also effectively release the lattice mismatch and thermal mismatch stress between the first substrate and the channel layer and improve the interface characteristics of the heterojunction.

[0146] Based on any of the above embodiments, in an embodiment of the present application, the first distance between the source electrode and the first gate is less than the second distance between the second gate and the drain electrode.

[0147] In this embodiment, the first distance between the source electrode and the first gate can range from 0.5 μm to 5 μm, the third distance between the first gate and the second gate is 0.5 μm to 5 μm, and the second distance between the second gate and the drain electrode can range from 5 μm to 10 μm.

[0148] The small first distance between the source electrode and the first gate can reduce the on-resistance; the increased second distance between the second gate and the drain electrode can increase the breakdown voltage.

[0149] Based on any of the above embodiments, in an embodiment of the present application, after removing the first substrate, it may further include:

[0150] Etching the epitaxial layer to form a field plate groove, the field plate groove is located on the side of the third gate close to the drain electrode; the depth of the field plate groove is less than the depth of the third gate groove;

[0151] After growing the second gate dielectric layer on the surface of the epitaxial layer, it further includes:

[0152] Growing metal in the field plate groove with the second gate dielectric layer to form a gate field plate.

[0153] The metal material of the gate field plate can be Ni / Au.

[0154] When there is only the third gate groove, the depth of the field plate groove is less than that of the third gate groove, and the field plate groove can be etched together with the third gate groove; when there are the third gate groove and the fourth gate groove, the depth of the field plate groove is less than that of the third gate groove and the fourth gate groove, and the field plate groove can be etched together with the third gate groove and the fourth gate groove.

[0155] Due to the different heights between the gate field plate and the third gate metal, a step is formed. The gate field plate effectively reduces the electric field peak at the gate edge, introduces a new electric field peak at the end of the field plate, makes the electric field distribution in the drift region more uniform, expands the depletion region of the semiconductor device, and increases the average electric field strength in the drift region.

[0156] The gate field plate optimizes the surface electric field distribution in the blocking state, improves the breakdown voltage of the semiconductor device. At the same time, since it is far from the 2DEG channel, it weakens the depletion effect on the 2DEG in the conducting state.

[0157] Based on any of the above embodiments, in an embodiment of the present application, after forming the patterned first gate dielectric layer on the surface of the epitaxial layer facing away from the first substrate, it may further include:

[0158] Growing metal on the surface of the first gate dielectric layer facing away from the epitaxial layer to form a first protection gate; the protection gate is located between the first gate and the source.

[0159] By setting the first protection gate, the current collapse effect of the semiconductor device can be further alleviated.

[0160] Based on any of the above embodiments, in an embodiment of the present application, after forming the patterned first gate dielectric layer on the surface of the epitaxial layer facing away from the first substrate, it may further include:

[0161] Growing metal on the surface of the first gate dielectric layer facing away from the epitaxial layer to form a first protection gate; the protection gate is located between the first gate and the source;

[0162] After removing the first substrate, it may further include: etching the epitaxial layer to form a protection gate groove; the protection gate groove is completely aligned with the first protection gate;

[0163] After growing the second gate dielectric layer on the surface of the epitaxial layer, it may further include: growing metal in the protection gate groove with the second gate dielectric layer to form a second protection gate.

[0164] By setting the first protection gate and the second protection gate, the current collapse effect of the semiconductor device can be further alleviated.

[0165] The manufacturing method in the present application will be introduced below in a specific case.

[0166] Example 1

[0167] Step 1, as Figure 3 shown, a buffer layer, a channel layer, and a barrier layer are epitaxially grown in sequence on the upper surface of the first substrate 1 to form an epitaxial layer 2, wherein the materials of the buffer layer and the channel layer are both GaN;

[0168] Step 2, as Figure 4 shown, a patterned first gate dielectric layer 3 is formed by PECVD;

[0169] Step 3, as Figure 4 shown, metal is grown on the surface of the first gate dielectric layer 3, and the metal outside the first gate and the second gate regions is removed by wet etching to form a first gate 4 and a second gate 5;

[0170] Step 4, as Figure 4 shown, a passivation layer 6 is deposited by PECVD, and the passivation layer is etched to form a source groove and a drain groove;

[0171] Step 5, as Figure 4 shown, metal is grown in the source groove and the drain groove by magnetron sputtering to form a source 7 and a drain 8; the first gate 4 is located between the source 7 and the second gate 5, and the first gate 4 is electrically connected to the source 7;

[0172] Step 6, as Figure 5 shown, a semiconductor layer 9 is grown on the surfaces of the source 7, the drain 8, the first gate 4, the second gate 5, and the passivation layer 6 facing away from the epitaxial layer 2 by PVD;

[0173] Step 7, as Figure 6 shown, a bonding intermediate layer is uniformly grown on the surface of the semiconductor layer 9 and the surface of the second substrate 10 by magnetron sputtering, and then the semiconductor layer 9 and the second substrate 10 on which the bonding intermediate layer has been grown are accurately aligned face to face and bonded;

[0174] Step 8, as Figure 7 shown, the first substrate 1 is removed by chemical mechanical polishing;

[0175] Step 9, the buffer layer is accurately etched by ICP etching technology to smooth the surface of the buffer layer;

[0176] Step 10, as Figure 8 and Figure 9 shown, a third gate groove and a field plate groove are etched by rough etching and fine etching; the depth of the field plate groove is less than the depth of the third gate groove;

[0177] Step 11, as Figure 9 shown, a second gate dielectric layer 11 is deposited by PECVD;

[0178] Step 12: As Figure 10 shown, deposit the third gate metal and the field plate metal to form the third gate 12 and the gate field plate 13; the third gate 12 is shorted to the second gate 5, and the third gate 12 is directly opposite to the second gate 5, that is, directly above the second gate 5.

[0179] Example 2

[0180] The difference between Example 2 and Example 1 is that in Step 10, the third gate groove, the fourth gate groove, and the field plate groove are etched by means of rough etching and fine etching, and in Step 12, the third gate metal, the fourth gate metal, and the field plate metal are deposited to form the third gate 12, the fourth gate 14, and the gate field plate 13; the third gate 12 is shorted to the second gate 5, the fourth gate 14 is shorted to the first gate 4, the third gate 12 is directly opposite to the second gate 5, that is, directly above the second gate 5, and the fourth gate 14 is directly opposite to the first gate 4, that is, directly above the first gate 4. The remaining steps of Example 2 are the same as those of Example 1. The structural schematic diagram of the semiconductor device obtained in Example 2 is as Figure 11 shown.

[0181] The present application also provides a semiconductor device, which is manufactured by using the manufacturing method of the semiconductor device in any of the above embodiments.

[0182] The semiconductor device can be an enhancement-mode HEMT device.

[0183] The present application also provides a circuit structure, including the semiconductor device in the above embodiment.

[0184] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0185] The semiconductor device, its manufacturing method, and the circuit structure provided by the present application are introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. A manufacturing method of a semiconductor device, characterized in that, Including: Growing an epitaxial layer on the upper surface of a first substrate; Forming a patterned first gate dielectric layer on the surface of the epitaxial layer facing away from the first substrate; Growing a metal on the surface of the first gate dielectric layer facing away from the epitaxial layer to form a first gate and a second gate; Forming a source electrode and a drain electrode on the surface of the epitaxial layer facing away from the first substrate; the first gate is located between the source electrode and the second gate, and the first gate is electrically connected to the source electrode; Removing the first substrate and etching the epitaxial layer to form a third gate groove; the third gate groove is opposite to the second gate; Growing a second gate dielectric layer on the surface of the epitaxial layer; Growing a metal in the third gate groove having the second gate dielectric layer to form a third gate, obtaining a semiconductor device; the third gate is short-circuited with the second gate.

2. The manufacturing method of the semiconductor device according to claim 1, wherein After removing the first substrate, it further includes: Etching the epitaxial layer to form a fourth gate groove; the fourth gate groove is opposite to the first gate; After growing the second gate dielectric layer on the surface of the epitaxial layer, it further includes: Growing a metal in the fourth gate groove having the second gate dielectric layer to form a fourth gate; the fourth gate is short-circuited with the first gate.

3. The manufacturing method of the semiconductor device according to claim 1, wherein, After growing a metal on the surface of the first gate dielectric layer facing away from the epitaxial layer to form a first gate and a second gate, it further includes: Forming a patterned passivation layer on the surface of the epitaxial layer facing away from the first substrate; the passivation layer is located between the source electrode and the first gate, between the first gate and the second gate, and between the second gate and the drain electrode.

4. The method for manufacturing a semiconductor device according to claim 3, wherein Removing the first substrate includes: Growing a semiconductor layer on a target surface; the target surface is the surface formed by the source electrode, the drain electrode, the first gate, the second gate, and the passivation layer facing away from the epitaxial layer; Bonding the surface of the semiconductor layer facing away from the epitaxial layer to a second substrate; Chemically mechanically polishing the first substrate from the lower surface of the first substrate to remove the first substrate.

5. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Growing an epitaxial layer on the upper surface of a first substrate includes: Growing a buffer layer on the upper surface of the first substrate; Growing a channel layer on the surface of the buffer layer facing away from the first substrate; Growing a barrier layer on the surface of the channel layer facing away from the buffer layer; Among them, the room-temperature resistivity of the buffer layer is greater than 10 6 Ω·cm; and / or, the channel layer is an unintentionally doped channel layer, and the concentration of background impurity carbon is less than 10 16 cm −3 .

6. The manufacturing method of the semiconductor device according to claim 1, characterized in that, A first distance between the source electrode and the first gate is less than a second distance between the second gate and the drain electrode.

7. The manufacturing method of the semiconductor device according to claim 1, characterized in that Etching the epitaxial layer to form a third gate groove includes: Roughly etching the epitaxial layer by an inductively coupled plasma etching method; wherein, the etching gas includes chlorine gas, boron trichloride, and argon gas, the flow rate range of chlorine gas is 20 standard cubic centimeters per minute to 40 standard cubic centimeters per minute, the flow rate range of boron trichloride is 10 standard cubic centimeters per minute to 20 standard cubic centimeters per minute, the flow rate range of argon gas is 5 standard cubic centimeters per minute to 15 standard cubic centimeters per minute; the temperature range of the rough etching is 20 degrees Celsius to 60 degrees Celsius; the pressure range of the etching chamber is 10 millitorr to 30 millitorr, and the etching power range is 600 watts to 1000 watts; The epitaxial layer is finely etched by inductively coupled plasma etching; wherein, the etching gas includes chlorine gas, boron trichloride and hydrogen gas, the flow rate range of chlorine gas is 10 standard cubic centimeters per minute to 20 standard cubic centimeters per minute, the flow rate range of boron trichloride is 5 standard cubic centimeters per minute to 10 standard cubic centimeters per minute, and the flow rate range of hydrogen gas is 5 standard cubic centimeters per minute to 10 standard cubic centimeters per minute; the temperature range for fine etching is 20 degrees Celsius to 40 degrees Celsius; the pressure range of the etching chamber is 5 millitorr to 10 millitorr, and the etching power range is 400 watts to 600 watts.

8. The manufacturing method of the semiconductor device according to any one of claims 1 to 7, characterized in that, After removing the first substrate, it further includes: Etching the epitaxial layer to form a field plate groove, the field plate groove is located on the side of the third gate close to the drain; the depth of the field plate groove is less than the depth of the third gate groove; After growing a second gate dielectric layer on the surface of the epitaxial layer, it further includes: Growing metal in the field plate groove having the second gate dielectric layer to form a gate field plate.

9. A semiconductor device, characterized in that, The semiconductor device is fabricated by the manufacturing method of the semiconductor device according to any one of claims 1 to 8.

10. A circuit structure, characterized in that, Including the semiconductor device according to claim 9.

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