High electron mobility transistor chip and preparation method thereof
By adopting a composite buffer layer structure in the HEMT chip, the AlN sublayer suppresses dislocation extension and the GaN sublayer maintains high resistance characteristics, the problem of crystal quality decline caused by carbon doping of the buffer layer is solved, and the overall performance of the transistor chip is improved.
Patent Information
- Application Number
- CN202510417298.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2025-07-29
AI Technical Summary
When existing HEMT chips reduce the carbon doping concentration of the buffer layer to avoid dislocations and point defects, the high resistance characteristics of the buffer layer are sacrificed and affect the crystal quality.
A composite buffer layer structure is adopted, including a plurality of AlN sub-layers and GaN sub-layers stacked in sequence, where the GaN sub-layer is doped with carbon elements, the AlN sub-layer suppresses dislocation extension, the GaN sub-layer maintains high resistance characteristics, and optimizes the carbon doping concentration through pulsed doping and other elements co-doping.
On the basis of ensuring the high resistance characteristics of the buffer layer, the crystal quality of the high electron mobility transistor chip is improved, crystal defects and dislocation problems are improved, and device performance is improved.
Smart Images
Figure CN120390423A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a high electron mobility transistor chip and a method for manufacturing the same. Background Art
[0002] HEMT (High Electron Mobility Transistor) is a heterojunction field effect transistor, which is widely used in fields such as aerospace, communication technology, automotive electronics, and switching power supplies. In particular, it has received wide attention in high-power and high-frequency application fields. The HEMT chip is the basis for manufacturing electronic power devices.
[0003] In the related art, the HEMT chip mainly includes a substrate, and a buffer layer and an epitaxial layer grown on the substrate. The buffer layer is doped with carbon elements and has a high-resistance characteristic. However, carbon atoms will form dislocations or point defects during high-temperature epitaxy, resulting in a reduction in crystal quality. To avoid this problem, the carbon doping concentration of the buffer layer is appropriately reduced in the related art.
[0004] However, after reducing the carbon doping concentration of the buffer layer, the high-resistance characteristic of the buffer layer will be sacrificed to a certain extent. Summary of the Invention
[0005] Embodiments of the present disclosure provide a high electron mobility transistor chip and a method for manufacturing the same, which can improve the crystal quality of the high electron mobility transistor chip on the basis of ensuring the high-resistance characteristic of the buffer layer. The technical solutions are as follows:
[0006] On the one hand, embodiments of the present disclosure provide a high electron mobility transistor chip, including a substrate, and a composite buffer layer and an epitaxial layer sequentially stacked on one side of the substrate;
[0007] The composite buffer layer includes a plurality of sub-buffer layers, and the sub-buffer layers are sequentially stacked. The sub-buffer layer includes an AlN sub-layer and a GaN sub-layer. The GaN sub-layer is located on the side of the AlN sub-layer facing away from the substrate, and the GaN sub-layer is doped with carbon elements.
[0008] In an implementation manner of the present disclosure, the thickness of the AlN sub-layer is 2 to 5 nm;
[0009] The thickness of the GaN sub-layer is 50 to 200 nm.
[0010] In an implementation manner of the present disclosure, the carbon doping concentration of the GaN sub-layer is 5E18 cm -3 ~1E19 cm -3 .
[0011] In one implementation of the present disclosure, the carbon doping concentration of each of the GaN sub-layers gradually decreases along the growth direction of the epitaxial layer.
[0012] In one implementation of the present disclosure, the GaN sub-layer is doped with at least one of iron element, magnesium element, and oxygen element.
[0013] In one implementation of the present disclosure, AlN / GaN superlattice layers are periodically inserted into the GaN sub-layer.
[0014] In one implementation of the present disclosure, a part of the sub-buffer layer includes a low-dimensional material layer, and the low-dimensional material layer is a graphene layer or an h-BN layer, and the low-dimensional material layer is used to replace the GaN sub-layer (212).
[0015] On the other hand, the embodiments of the present disclosure provide a method for manufacturing a high electron mobility transistor chip, and the manufacturing method is used to manufacture the high electron mobility transistor chip as described in the above aspect. The manufacturing method includes:
[0016] Provide a substrate;
[0017] On one side of the substrate, an AlN sub-layer and a GaN sub-layer are sequentially prepared periodically, and one AlN sub-layer and one GaN sub-layer form a sub-buffer layer, and a plurality of the sub-buffer layers form a composite buffer layer;
[0018] An epitaxial layer is prepared on the side of the composite buffer layer facing away from the substrate.
[0019] In one implementation of the present disclosure, preparing the GaN sub-layer includes:
[0020] Using pulsed doping, carbon element is doped into the GaN sub-layer, and the pulse period matches the growth rate of the GaN sub-layer.
[0021] In one implementation of the present disclosure, preparing the GaN sub-layer further includes:
[0022] The carbon doping concentration of each of the GaN sub-layers gradually decreases along the growth direction of the epitaxial layer.
[0023] The beneficial effects brought by the technical solutions provided by the embodiments of the present disclosure at least include:
[0024] The high electron mobility transistor chip provided by the embodiments of the present disclosure is provided with a composite buffer layer between the substrate and the epitaxial layer. The composite buffer layer is composed of multiple sub-buffer layers stacked in sequence. Each sub-buffer layer includes an AlN sub-layer and a GaN sub-layer stacked on top of each other. The GaN sub-layer is located on the side of the AlN sub-layer facing away from the substrate. Among them, the GaN sub-layer is doped with carbon elements and can have a high-resistance characteristic, while the AlN sub-layer can play a role in suppressing the extension of dislocations, thereby effectively ensuring the crystal quality of the high electron mobility transistor chip.
[0025] That is to say, in the high electron mobility transistor chip provided by the embodiments of the present disclosure, the composite buffer layer is composed of multiple groups of AlN sub-layers and GaN sub-layers stacked in sequence. Among them, the AlN sub-layer can play a role in suppressing the extension of dislocations, thereby effectively ensuring the crystal quality of the high electron mobility transistor chip. On this basis, the GaN sub-layer is doped with carbon elements, and the carbon doping amount does not need to be reduced due to considering the crystal quality, so the high-resistance characteristic of the GaN sub-layer can be ensured. That is to say, the high electron mobility transistor chip provided by the embodiments of the present disclosure can improve the crystal quality of the high electron mobility transistor chip on the basis of ensuring the high-resistance characteristic of the buffer layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0027] Figure 1 is a schematic structural diagram of a high electron mobility transistor provided by an embodiment of the present disclosure;
[0028] Figure 2 is a schematic structural diagram of a composite buffer layer provided by an embodiment of the present disclosure;
[0029] Figure 3 is a schematic structural diagram of a sub-buffer layer provided by an embodiment of the present disclosure;
[0030] Figure 4 is a schematic structural diagram of a sub-buffer layer provided by an embodiment of the present disclosure;
[0031] Figure 5 is a flowchart of a preparation method of a high electron mobility transistor chip provided by an embodiment of the present disclosure;
[0032] Figure 6 is a flowchart of another preparation method of a high electron mobility transistor chip provided by an embodiment of the present disclosure;
[0033] Figure 7 It is a schematic diagram of Ga source and C source doping of the GaN sublayer provided by an embodiment of the present disclosure.
[0034] Reference numerals in the attached drawings:
[0035] 10. Substrate;
[0036] 20. Composite buffer layer;
[0037] 210. Sub-buffer layer;
[0038] 211. AlN sublayer; 212. GaN sublayer; 213. AlN / GaN superlattice layer; 214. Low-dimensional material layer;
[0039] 30. Epitaxial layer;
[0040] 310. Channel layer; 320. Barrier layer; 330. Cap layer. Specific embodiments
[0041] To make the purpose, technical solutions and advantages of the present disclosure clearer, the following will further describe the embodiments of the present disclosure in detail with reference to the accompanying drawings.
[0042] As a representative of the third-generation semiconductor materials, GaN is an important semiconductor material that emerged after Si and GaAs materials. Due to its excellent properties such as large bandgap, high critical field strength, high carrier saturation velocity, and high temperature and radiation resistance, it has received extensive attention.
[0043] The GaN-based high electron mobility transistor forms a two-dimensional electron gas (2DEG) with high concentration and high mobility at the heterojunction to generate a conductive channel, thereby realizing the conduction of the device. Due to its excellent properties such as high thermal conductivity, low on-resistance, and tolerance to high-frequency and high-voltage conditions, the GaN-based high electron mobility transistor has become a research hotspot in the fields of high-frequency and high-power devices and switching devices in recent years.
[0044] In the related art, the HEMT chip mainly includes a substrate, and a buffer layer and an epitaxial layer grown on the substrate. The buffer layer is doped with carbon elements and has a high-resistance characteristic. However, carbon atoms will form dislocations or point defects during high-temperature epitaxy, resulting in a reduction in crystal quality. To avoid this problem, the carbon doping concentration of the buffer layer is appropriately reduced in the related art.
[0045] However, after reducing the carbon doping concentration of the buffer layer, the high-resistance characteristic of the buffer layer will be sacrificed to a certain extent.
[0046] To solve the above technical problems, an embodiment of the present disclosure provides a high electron mobility transistor, Figure 1is a schematic structural diagram of the high electron mobility transistor. Combining with Figure 1 , in this embodiment, the high electron mobility transistor includes a substrate 10, and a composite buffer layer 20 and an epitaxial layer 30 stacked in sequence on one side of the substrate 10.
[0047] Figure 2 is a schematic structural diagram of the composite buffer layer 20. Combining with Figure 2 , in this embodiment, the composite buffer layer 20 includes a plurality of sub-buffer layers 210, and the sub-buffer layers 210 are stacked in sequence. The sub-buffer layer 210 includes an AlN sub-layer 211 and a GaN sub-layer 212. The GaN sub-layer 212 is located on the side of the AlN sub-layer 211 facing away from the substrate 10, and the GaN sub-layer 212 is doped with carbon elements.
[0048] For the high electron mobility transistor chip provided by the embodiment of the present disclosure, a composite buffer layer 20 is provided between the substrate 10 and the epitaxial layer 30. The composite buffer layer 20 is composed of a plurality of sub-buffer layers 210 stacked in sequence. Each sub-buffer layer 210 includes an AlN sub-layer 211 and a GaN sub-layer 212 stacked thereon. The GaN sub-layer 212 is located on the side of the AlN sub-layer 211 facing away from the substrate 10. Among them, the GaN sub-layer 212 is doped with carbon elements and can have a high-resistance characteristic, while the AlN sub-layer 211 can play a role in suppressing the extension of dislocations, thereby effectively ensuring the crystal quality of the high electron mobility transistor chip.
[0049] That is to say, in the high electron mobility transistor chip provided by the embodiment of the present disclosure, the composite buffer layer 20 is composed of multiple groups of AlN sub-layers 211 and GaN sub-layers 212 stacked in sequence. Among them, the AlN sub-layer 211 can play a role in suppressing the extension of dislocations, thereby effectively ensuring the crystal quality of the high electron mobility transistor chip. On this basis, the GaN sub-layer 212 is doped with carbon elements, and the carbon doping amount does not need to be reduced due to considering the crystal quality, so the high-resistance characteristic of the GaN sub-layer 212 can be ensured. That is to say, the high electron mobility transistor chip provided by the embodiment of the present disclosure can improve the crystal quality of the high electron mobility transistor chip on the basis of ensuring the high-resistance characteristic of the buffer layer.
[0050] Exemplarily, the thickness of the AlN sub-layer 211 is 2-5 nm, and the thickness of the GaN sub-layer 212 is 50-200 nm.
[0051] In the above implementation manner, the thicknesses of the AlN sub-layer 211 and the GaN sub-layer 212 are designed as the above values. On the one hand, it can ensure that the functionality of the two will not be affected due to too small thickness, and on the other hand, it can also ensure that the preparation efficiency of the two will not be affected due to too large thickness.
[0052] Moreover, in the above implementation, the thickness of the GaN sub-layer 212 is much greater than that of the AlN sub-layer 211, which can effectively ensure the high-resistance characteristics of the overall sub-buffer layer 210. That is to say, the high-resistance characteristics of the sub-buffer layer 210 will not be overly affected by the AlN sub-layer 211.
[0053] In this embodiment, the thickness of the AlN sub-layer 211 is 3 nm, and the thickness of the GaN sub-layer 212 is 130 nm.
[0054] Of course, in other embodiments, the thicknesses of the AlN sub-layer 211 and the GaN sub-layer 212 can also be adjusted to other values within the above range according to actual requirements, and the present disclosure does not limit this.
[0055] Exemplarily, the carbon doping concentration of the GaN sub-layer 212 is 5E18 cm -3 ~1E19 cm -3 .
[0056] In the above implementation, designing the carbon doping concentration of the GaN sub-layer 212 to the above value can effectively ensure the high-resistance characteristics of the sub-buffer layer 210.
[0057] It should be noted that, according to actual requirements, the carbon doping concentrations of the GaN sub-layers 212 of each sub-buffer layer 210 can be either the same or different, and the present disclosure does not limit this.
[0058] Designing the carbon doping concentrations of the GaN sub-layers 212 of each sub-buffer layer 210 to be the same can effectively simplify the preparation process and reduce the preparation difficulty.
[0059] In this embodiment, the carbon doping concentration of the GaN sub-layer 212 of each sub-buffer layer 210 gradually decreases along the growth direction of the epitaxial layer 30.
[0060] In the above implementation, the carbon doping concentration of the GaN sub-layer 212 of the sub-buffer layer 210 closest to the substrate 10 is the highest, and the carbon doping concentration of the GaN sub-layer 212 of the sub-buffer layer 210 closest to the epitaxial layer 30 is the lowest. Designed in this way, the interface stress can be effectively reduced.
[0061] It should be noted that for the GaN sub-layer 212 with the lowest carbon doping concentration and the GaN sub-layer 212 with the highest carbon doping concentration, their carbon doping concentrations are still within the range of 5E18 cm -3 ~1E19 cm -3 . Therefore, the change in the carbon doping concentration of the GaN sub-layer 212 will not have an overly large impact on the high-resistance characteristics of the sub-buffer layer 210.
[0062] Exemplarily, the carbon doping concentration of the GaN sublayer 212 of each sub-buffer layer 210 decreases exponentially along the growth direction of the epitaxial layer 30 .
[0063] For example, the carbon doping concentration of the GaN sub-layer 212 of each sub-buffer layer 210 is 1E19cm -3 Reduced to 5E18cm -3 .
[0064] In this embodiment, in addition to being doped with carbon, the GaN sub-layer 212 may also be doped with other elements. For example, the GaN sub-layer 212 may be doped with at least one of iron, magnesium, and oxygen.
[0065] In the above implementation, the above other doping elements are introduced into the GaN sublayer 212 to achieve co-doping with carbon elements. In this way, carbon-induced defects can be suppressed through interatomic interactions.
[0066] In this embodiment, if the GaN sublayer 212 is doped with iron and magnesium, deep energy level traps can be introduced to effectively capture free carriers, thereby increasing the resistivity of the material and making it semi-insulating. The GaN sublayer 212 has the following effects:
[0067] (1) Reduce leakage current and parasitic conduction of the substrate 10, and improve the breakdown voltage and efficiency of the high electron mobility transistor chip.
[0068] (2) Dislocation suppression: Fe / Mg and other metal element doping can pin dislocations or adjust stress distribution, thereby reducing the lattice mismatch between the substrate 10 and the epitaxial layer 30, lowering the dislocation density, and improving the crystal quality.
[0069] (3) Stress relief: Fe / Mg and other metal elements are doped to adjust the thermal stress of the epitaxial material, thereby reducing cracks or even splits in the epitaxial layer 30 caused by thermal mismatch.
[0070] (4) The high-temperature performance of high-electron-mobility transistor chips is improved. The doping of metal elements such as Fe / Mg is stable at high temperatures, which delays thermal degradation and improves the stability of high-electron-mobility transistor chips under high-temperature regulation.
[0071] (5) Optimize the switching characteristics of high electron mobility transistor chips, especially in RF high electron mobility transistor chips. Appropriate doping of metal elements such as Fe / Mg can adjust the carrier convergence rate and optimize the switching characteristics of high electron mobility transistor chips.
[0072] In this embodiment, if the GaN sublayer 212 is doped with oxygen, the oxygen atoms replace the nitrogen and contribute free electrons as shallow donor impurities. The GaN sublayer 212 has the following effects:
[0073] (1) Suppress dislocations. Equivalent oxygen doping can suppress the extension of dislocations by filling nitrogen vacancies and improve the crystal quality.
[0074] (2) Oxygen doping can increase the longitudinal resistivity and suppress current collapse.
[0075] (3) Improve the high-temperature stability of high electron mobility transistor chips. Oxygen doping improves the high-temperature stability by delaying thermal decomposition.
[0076] Figure 3 It is a schematic structural diagram of the sub-buffer layer. Figure 3 and Figure 2 The main difference lies in the structure of the GaN sub-layer 212. Combining Figure 3 , in this embodiment, AlN / GaN superlattice layers 213 are periodically inserted in the GaN sub-layer 212.
[0077] In the above implementation, the AlN / GaN superlattice layer 213 is a low-dimensional material. By periodically inserting the low-dimensional material in the GaN sub-layer 212, the lattice mismatch is relieved through the dispersion of interface stress.
[0078] Figure 4 It is a schematic structural diagram of the sub-buffer layer. Figure 4 and Figure 2 The main difference lies in the different structures of some sub-buffer layers 210. Combining Figure 4 , in this embodiment, some of the sub-buffer layers 210 include a low-dimensional material layer 214. The low-dimensional material layer 214 is a graphene layer or an h-BN layer, and the low-dimensional material layer 214 is used to replace the GaN sub-layer 212.
[0079] In some of the sub-buffer layers 210, the low-dimensional material layer 214 is used to replace the GaN sub-layer 212. Since the low-dimensional material layer 214 is a low-dimensional material such as a graphene layer or an h-BN layer, it can achieve high-resistance characteristics while avoiding bulk defects.
[0080] It should be noted that using the low-dimensional material layer 214 to replace the GaN sub-layer 212 means that the sub-buffer layer 210 does not have the GaN sub-layer 212, but only has the AlN sub-layer 211 and the low-dimensional material layer 214.
[0081] The number of sub-buffer layers 210 in which the GaN sub-layer 212 is replaced by the low-dimensional material layer 214 can be selected according to actual needs. For example, the GaN sub-layer 212 in 30% of the sub-buffer layers 210 is replaced by the low-dimensional material layer 214. The present disclosure does not limit this ratio.
[0082] In addition, the sub-buffer layer 210 of the GaN sub-layer 212 is replaced by the low-dimensional material layer 214, which may be continuously arranged, periodically arranged, or randomly arranged in the composite buffer layer 20. The present disclosure does not limit this.
[0083] Referring again to Figure 1 , in this embodiment, the epitaxial layer 30 includes a channel layer 310, a barrier layer 320, and a cap layer 330 stacked in sequence.
[0084] Among them, the channel layer 310 is a GaN layer, the barrier layer 320 is an AlGaN layer, and the cap layer 330 is a P-type GaN layer.
[0085] In the above implementation, an AlGaN / GaN heterojunction is formed between the channel layer 310 and the barrier layer 320.
[0086] Through X-ray diffraction analysis, for the high electron mobility transistor chip provided by the embodiments of the present disclosure, the full width at half maxima (FWHM) is reduced by 30%, and the dislocation density is not greater than 1E8 cm -2 . The surface roughness is greatly optimized, the electrical performance temperature, the breakdown voltage is increased by 20%, and the dynamic resistance drift rate is decreased by 50%. The high electron mobility transistor chip provided by the embodiments of the present disclosure can be applied to 5G radio frequency devices and high-power power electronics fields, and has high yield and reliability.
[0087] Figure 5 is a flowchart of a preparation method for a high electron mobility transistor chip provided by an embodiment of the present disclosure. Refer to Figure 5 , the preparation method includes:
[0088] Step 501: Provide a substrate 10.
[0089] Step 502: Periodically prepare an AlN sub-layer 211 and a GaN sub-layer 212 on one side of the substrate 10 in sequence.
[0090] In the above implementation, one AlN sub-layer 211 and one GaN sub-layer 212 form a sub-buffer layer 210, and multiple sub-buffer layers 210 form a composite buffer layer 20.
[0091] Step 503: Prepare an epitaxial layer 30 on the side of the composite buffer layer 20 facing away from the substrate 10.
[0092] In the process of fabricating a high electron mobility transistor (HEMT) chip by the fabrication method provided in the embodiments of the present disclosure, a composite buffer layer 20 is grown between a substrate 10 and an epitaxial layer 30. The composite buffer layer 20 is composed of a plurality of sub-buffer layers 210 stacked in sequence. Each sub-buffer layer 210 includes an AlN sub-layer 211 and a GaN sub-layer 212 stacked on top of each other. The GaN sub-layer 212 is doped with carbon elements and can have a high-resistance characteristic. The AlN sub-layer 211 can play a role in suppressing the extension of dislocations, thereby effectively ensuring the crystal quality of the HEMT chip.
[0093] That is to say, the AlN sub-layer 211 can play a role in suppressing the extension of dislocations, thereby effectively ensuring the crystal quality of the HEMT chip. On this basis, the GaN sub-layer 212 is doped with carbon elements, and the carbon doping amount does not need to be reduced due to considering the crystal quality, so the high-resistance characteristic of the GaN sub-layer 21 can be ensured. That is to say, the HEMT chip provided in the embodiments of the present disclosure can improve the crystal quality of the HEMT chip on the basis of ensuring the high-resistance characteristic of the buffer layer.
[0094] Figure 6 The flowchart of another fabrication method of the HEMT chip provided in the embodiments of the present disclosure is shown in Figure 6 and the fabrication method includes:
[0095] Step 601: Provide a substrate 10 and place the substrate 10 into a reaction chamber. <{
[0096] Exemplarily, the material of the substrate 10 is sapphire, SiC, Si, GaN, etc. In this embodiment, the material of the substrate 10 is sapphire.
[0097] In this embodiment, the reaction chamber is a reaction chamber of a MOCVD (Metal Organic Chemical Vapor Deposition) device.
[0098] Step 602: Periodically and sequentially fabricate an AlN sub-layer 211 and a GaN sub-layer 212 on one side of the substrate 10.
[0099] In the above implementation, one AlN sub-layer 211 and one GaN sub-layer 212 form a sub-buffer layer 210, and a plurality of sub-buffer layers 210 form a composite buffer layer 20.
[0100] In step 602, the fabrication steps of the GaN sub-layer 212 include:
[0101] Adopt pulsed doping to dope carbon elements in the GaN sub-layer 212, and the pulse period matches the growth rate of the GaN sub-layer 212.
[0102] Figure 7 Schematic diagram of Ga source and C source doping for GaN sublayer 212, combined with Figure 7 , in this embodiment, carbon element and gallium element are doped in a pulsed manner, and the peaks and valleys in the pulse periods of carbon element and gallium element are staggered, that is, the peak in the pulse period of carbon element corresponds to the valley in the pulse period of gallium element, and vice versa, the valley in the pulse period of carbon element corresponds to the peak in the pulse period of gallium element.
[0103] In the above implementation, to ensure that each carbon-doped sublayer is evenly distributed, carbon atoms are intermittently incorporated with a duty cycle of 10% - 50%, effectively reducing carbon local aggregation.
[0104] In step 602, the preparation steps of GaN sublayer 212 further include:
[0105] The carbon doping concentration of each GaN sublayer 212 gradually decreases along the growth direction of epitaxial layer 30.
[0106] Exemplarily, the carbon doping concentration of GaN sublayer 212 of each sub-buffer layer 210 decreases exponentially along the growth direction of epitaxial layer 30.
[0107] For example, the carbon doping concentration of GaN sublayer 212 of each sub-buffer layer 210 decreases from 1E19 cm -3 to 5E18 cm -3 .
[0108] Step 603: Prepare epitaxial layer 30 on the side of composite buffer layer 20 facing away from substrate 10.
[0109] Exemplarily, step 603 includes:
[0110] Step 6031: Prepare channel layer 310 on the side of composite buffer layer 20 facing away from substrate 10.
[0111] Step 6032: Prepare barrier layer 320 on the side of channel layer 310 facing away from composite buffer layer 20.
[0112] Step 6033: Prepare cap layer 330 on the side of barrier layer 320 facing away from composite buffer layer 20.
[0113] Step 604: Rapid annealing in N2 environment.
[0114] Exemplarily, in step 604, the annealing temperature is 800 - 1000 °C and the annealing time is 30 - 60 s.
[0115] In the above implementation, through rapid annealing, surface dangling bonds can be effectively repaired.
[0116] In the process of manufacturing a high electron mobility transistor (HEMT) chip by the manufacturing method provided in the embodiments of the present disclosure, a composite buffer layer 20 is grown between a substrate 10 and an epitaxial layer 30. The composite buffer layer 20 is composed of a plurality of sub-buffer layers 210 stacked in sequence. Each sub-buffer layer 210 includes an AlN sub-layer 211 and a GaN sub-layer 212 stacked thereon. The GaN sub-layer 212 is doped with carbon elements and can have a high-resistance characteristic. The AlN sub-layer 211 can play a role in suppressing the extension of dislocations, thus effectively ensuring the crystal quality of the HEMT chip.
[0117] That is to say, the AlN sub-layer 211 can play a role in suppressing the extension of dislocations, thus effectively ensuring the crystal quality of the HEMT chip. On this basis, the GaN sub-layer 212 is doped with carbon elements, and the carbon doping amount does not need to be reduced due to considerations of crystal quality, so the high-resistance characteristic of the GaN sub-layer 212 can be ensured. That is to say, the HEMT chip provided by the embodiments of the present disclosure can improve the crystal quality of the HEMT chip on the basis of ensuring the high-resistance characteristic of the buffer layer.
[0118] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", "third" and similar terms used in the specification and claims of the present patent application do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms "a" or "an" and the like do not denote a quantity limitation, but mean that there is at least one. The terms "comprising" or "including" and the like are intended to mean that the elements or items appearing before "comprising" or "including" cover the elements or items listed after "comprising" or "including" and their equivalents, and do not exclude other elements or items. The terms "connected" or "coupled" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationships may also change accordingly.
[0119] The above is not intended to impose any form of limitation on the present disclosure. Although the present disclosure has been disclosed as above through embodiments, it is not intended to limit the present disclosure. Any person skilled in the art can make some modifications or variations equivalent to the equivalent embodiments by using the technical content disclosed above within the scope of the technical solutions of the present disclosure. However, as long as it does not depart from the technical solutions of the present disclosure, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present disclosure still fall within the scope of the technical solutions of the present disclosure.
Claims
1. A high electron mobility transistor chip, characterized in that, It includes a substrate (10), and a composite buffer layer (20) and an epitaxial layer (30) stacked in sequence on one side of the substrate (10). The composite buffer layer (20) includes a plurality of sub-buffer layers (210) stacked in sequence. Each sub-buffer layer (210) includes an AlN sub-layer (211) and a GaN sub-layer (212). The GaN sub-layer (212) is located on the side of the AlN sub-layer (211) facing away from the substrate (10), and the GaN sub-layer (212) is doped with carbon elements.
2. The high electron mobility transistor chip according to claim 1, wherein The thickness of the AlN sub-layer (211) is 2 - 5 nm. The thickness of the GaN sub-layer (212) is 50 - 200 nm.
3. The high electron mobility transistor chip according to claim 1, characterized in that The carbon doping concentration of the GaN sublayer (212) is 5E18 cm -3 ~1E19 cm -3 .
4. The high electron mobility transistor chip according to claim 1, characterized in that, The carbon doping concentration of each GaN sub-layer (212) gradually decreases along the growth direction of the epitaxial layer (30).
5. The high electron mobility transistor chip according to claim 1, wherein The GaN sub-layer (212) is doped with at least one of iron element, magnesium element, and oxygen element.
6. The high electron mobility transistor chip according to claim 1, characterized in that, AlN / GaN superlattice layers (213) are periodically inserted into the GaN sub-layer (212).
7. The high electron mobility transistor chip according to claim 1, characterized in that, Some of the sub-buffer layers (210) include low-dimensional material layers (214). The low-dimensional material layer (214) is a graphene layer or an h-BN layer, and the low-dimensional material layer (214) is used to replace the GaN sub-layer (212).
8. A method for preparing a high electron mobility transistor chip, characterized in that, The preparation method is used to prepare the high electron mobility transistor chip as described in claim 1. The preparation method includes: Providing a substrate (10); Periodically preparing an AlN sub-layer (211) and a GaN sub-layer (212) in sequence on one side of the substrate (10). One AlN sub-layer (211) and one GaN sub-layer (212) form a sub-buffer layer (210), and a plurality of sub-buffer layers (210) form a composite buffer layer (20); Preparing an epitaxial layer (30) on the side of the composite buffer layer (20) facing away from the substrate (10).
9. The preparation method according to claim 8, wherein, Preparing the GaN sub-layer (212) includes: Using pulsed doping to dope carbon elements in the GaN sub-layer (212), and the pulse period matches the growth rate of the GaN sub-layer (212).
10. The preparation method according to claim 8, characterized in that, Preparing the GaN sub-layer (212) further includes: The carbon doping concentration of each GaN sub-layer (212) gradually decreases along the growth direction of the epitaxial layer (30).