Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. According to an embodiment, a semiconductor device may include: a substrate; a dielectric layer on the substrate; a gate electrode layer on the dielectric layer; a gate dielectric layer on the gate electrode layer; the channel layer is arranged on the gate dielectric layer and is opposite to the gate electrode layer; the source / drain electrodes are arranged on the two sides of the channel layer, and the source / drain electrodes comprise metal materials and are in contact with the side walls of the channel layer.

Description

Technical Field

[0001] The present disclosure generally relates to the field of semiconductor technologies, and more particularly, to an inverted semiconductor device and a method for manufacturing the same. Background Art

[0002] With the continuous miniaturization of semiconductor devices, junction leakage has become increasingly serious, and parasitic capacitances such as the parasitic capacitance between the gate and the source / drain or the source / drain contact portions, and contact resistances such as the contact resistance between the source / drain and the source / drain contact portions have become increasingly large. Summary of the Invention

[0003] In view of this, at least part of the purpose of the present disclosure is to provide an inverted semiconductor device and a method for manufacturing the same.

[0004] According to one aspect of the present disclosure, a semiconductor device is provided, including: a substrate; a dielectric layer on the substrate; a gate electrode layer on the dielectric layer; a gate dielectric layer on the gate electrode layer; a channel layer opposite to the gate electrode layer on the gate dielectric layer; source / drain electrodes on both sides of the channel layer, wherein the source / drain electrodes include a metal material and contact the sidewalls of the channel layer.

[0005] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, including: forming a dielectric layer on a substrate; forming a gate electrode layer on the dielectric layer; forming a gate dielectric layer on the gate electrode layer; forming a channel layer opposite to the gate electrode layer on the gate dielectric layer; forming source / drain electrodes on both sides of the channel layer that contact the sidewalls of the channel layer and include a metal material.

[0006] According to an embodiment of the present disclosure, an inverted semiconductor device is provided. According to some embodiments, the gate electrode layer can be disposed below the source / drain electrodes, thereby reducing or avoiding the lateral overlap of the gate electrode layer and the source / drain electrodes (and thus the resulting parasitic capacitance). In addition, the source / drain contact portions on the source / drain electrodes can be further separated from the gate electrode layer, thereby reducing or avoiding the parasitic capacitance between the gate electrode layer and the source / drain contact portions. In addition, the metal source / drain electrodes can form an ohmic contact with the (metal) source / drain contact portions, thereby reducing the contact resistance. The source / drain electrodes can be isolated from the substrate by a dielectric layer, thereby not forming a junction with the substrate and avoiding junction leakage. Brief Description of the Drawings

[0007] According to the following description in conjunction with the drawings, the above and other aspects, features, and advantages of certain embodiments of the present disclosure can be more clearly understood. In the drawings:

[0008] Figure 1(a) and 1(b) A perspective view of a semiconductor device according to an embodiment of the present disclosure is schematically shown;

[0009] Figures 2 to 8(c) Schematically shows the structure of some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0010] Figure 9 Schematically shows a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure; and

[0011] Figures 10 to 23(b) Schematically shows the structure of some stages in the process of manufacturing a semiconductor device according to another embodiment of the present disclosure,

[0012] wherein the cutting positions AA', BB' and CC' of the cross-section involved in Figures 2 to 8(c) are schematically shown in the perspective view of Fig. 1(a), and the cutting positions AA' and DD' of the cross-section involved in Figures 10 to 23(b) are schematically shown in the top view of Fig. 11(a). Detailed implementation manners

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0014] Various schematic structural diagrams according to embodiments of the present disclosure are shown in the drawings. These figures are not drawn to scale, and for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "under" the other layer / element.

[0015] The present disclosure can be presented in various forms, and some examples will be described below. In the following description, various material selections are involved. In addition to considering their functions (for example, semiconductor materials are used to form active regions, and dielectric materials are used to form electrical isolations), the etching selectivity is also considered when selecting materials. In the following description, the required etching selectivity may or may not be indicated. Those skilled in the art should be aware that when etching a certain material layer is mentioned below, if it is not mentioned that other layers are also etched or not shown in the figure that other layers are also etched, then this etching can be selective, and this material layer can have etching selectivity relative to other layers exposed to the same etching recipe.

[0016] Figure 1(a) and 1(b) A perspective view of a semiconductor device 100 according to an embodiment of the present disclosure is schematically shown.

[0017] As Figure 1(a) and 1(b) As shown, the semiconductor device 100 may include a substrate 101, a dielectric layer DIL on the substrate 101, a gate electrode layer G on the dielectric layer DIL, a gate dielectric layer 111 on the gate electrode layer G, a channel layer 113 opposite to the gate electrode layer G on the gate dielectric layer 111, and source / drain electrodes 115_S, 115_D on both sides of the channel layer 113. In FIG. 1(a), to avoid obscuring the main structure of the semiconductor device 100 in the perspective view, the substrate 101 and the dielectric layer DIL are not shown, and they are shown in FIG. 1(b).

[0018] The substrate 101 may include a suitable semiconductor material, and a dielectric layer DIL is provided on its surface. According to an embodiment, the dielectric layer DIL, such as an oxide, can be formed by deposition or thermal oxidation, etc.

[0019] The gate electrode layer G is configured to apply an electric field to the channel layer 113. The gate electrode layer G may include a gate conductor layer 105 and a work function layer 1�7 on the gate conductor layer 105. The gate conductor layer 105 may include a conductive material such as polysilicon, a metal such as tungsten, etc. The work function layer 107 can be used to adjust the equivalent work function of the gate electrode layer G, and may include a metal such as Ti, a conductive metal nitride such as TiN, etc. The gate dielectric layer 111 may be interposed between the gate electrode layer G and the channel layer 113 (and optionally, the source / drain electrodes 115_S, 115_D). The gate dielectric layer 111 may include a high-k gate dielectric material such as HfO2, etc.

[0020] The gate electrode layer G can be surrounded by a dielectric layer DIL, and its top surface can be exposed from the dielectric layer DIL. For example, the dielectric layer DIL can include a first dielectric layer 103 and a second dielectric layer 109 on the first dielectric layer. The gate electrode layer G can be disposed on the first dielectric layer 103, and the second dielectric layer 109 can be disposed on the outer periphery of the gate electrode layer G on the first dielectric layer 103. In this way, a semiconductor-on-insulator (SOI) structure can be obtained, and the SOI structure can suppress leakage current.

[0021] The channel layer 113 can include a semiconductor material, such as undoped (intrinsic) silicon. The channel layer 113 can be formed on the gate dielectric layer 111 by deposition. In the channel length direction (the direction from the source electrode 115_S to the drain electrode 115_D, or vice versa; for example, the x direction in FIGS. 1(a) and 1(b)), the width of the channel layer 113 can be smaller than the width of the gate electrode layer G, so that the channel layer 113 can completely face the gate electrode layer (through the gate dielectric layer 111). More specifically, in a top view, the channel layer 113 can be located within the region defined by the gate electrode layer G, so that the gate electrode layer G can better control the channel formed in the channel layer 113.

[0022] The source / drain electrodes can include a source electrode 115_S and a drain electrode 115_D, which are respectively disposed on opposite sides of the channel layer 113. In Figure 1(a) and 1(b) although the source electrode 115_S is shown on the left side of the channel layer 113 and the drain electrode 115_D is on the right side of the channel layer 113, the present disclosure is not limited thereto. The source electrode 115_S and the drain electrode 115_D can have the same configuration, and hereinafter can be collectively referred to as the source / drain electrodes 115_S, 115_D. Due to the SOI structure as described above, no junction is formed between the source / drain electrodes 115_S, 115_D and the substrate.

[0023] According to an embodiment of the present disclosure, the source / drain electrodes 115_S, 115_D can include a metal material that contacts the sidewalls of the channel layer 113. If the semiconductor device 100 is of n-type, the source / drain electrodes 115_S, 115_D can include an n-type metal material, such as a metal material whose Fermi level is close to the bottom of the conduction band of silicon, such as Al, Ti, Ta, Cr, etc. On the other hand, if the semiconductor device 100 is of p-type, the source / drain electrodes 115_S, 115_D can include a p-type metal material, such as a metal material whose Fermi level is close to the top of the valence band of silicon, such as Pt, Pd, Ni, or their metal silicides. The height of the top surface of the source / drain electrodes 115_S, 115_D can be lower than the height of the top surface of the channel layer 113.

[0024] According to an embodiment of the present disclosure, on both sides of the channel layer 113, instead of providing a heavily doped semiconductor, such as a source / drain region, source / drain electrodes 115_S and 115_D made of, for example, a metal material are in direct contact with the channel layer 113.

[0025] According to an embodiment of the present disclosure, the gate electrode layer G may be located below the source / drain electrodes 115_S and 115_D. More specifically, the height of the top surface of the gate electrode layer G may be lower than the height of the bottom surface of the source / drain electrodes 115_S and 115_D. Therefore, the overlap (and thus the parasitic capacitance) between the gate electrode layer G and the source / drain electrodes 115_S and 115_D in the lateral direction (e.g., the x direction) can be reduced or avoided.

[0026] The semiconductor device 100 may include an interlayer dielectric layer (see 1017 in the following figures) covering the channel layer 113 and the source / drain electrodes 115_S and 115_D. Various contact portions may be formed in the interlayer dielectric layer, such as source / drain contact portions 119_S and 119_D respectively connected to the source / drain electrodes 115_S and 115_D, a gate contact portion 119_G connected to the gate electrode layer G, and a body contact portion 119_B connected to the channel layer 113. These contact portions may be formed by etching contact holes in the interlayer dielectric layer and filling the contact holes with a conductive material such as metal. Therefore, in the source / drain region of the semiconductor device 100, there is no contact between, for example, a metal and a semiconductor (such as a metal contact portion and a heavily doped semiconductor serving as a source / drain region in the related art), but an ohmic contact between the metal materials (of the source / drain electrodes 115_S and 115_D) and the metal materials (of the source / drain contact portions 119_S and 119_D), and thus the contact resistance can be reduced.

[0027] Moreover, the source / drain contact portions 119_S and 119_D connected to the source / drain electrodes 115_S and 115_D are further away from the gate electrode layer G. More specifically, the height of the bottom surface of the source / drain contact portions 119_S and 119_D may be higher than the height of the top surface of the gate electrode layer G. In this example, the source / drain contact portions 119_S and 119_D may extend upward (e.g., along the +z direction) relative to the top surface of the source / drain electrodes 115_S and 115_D, while the gate electrode layer G may extend downward (e.g., along the -z direction) relative to the bottom surface of the source / drain electrodes 115_S and 115_D. Therefore, the overlap (and thus the parasitic capacitance) between the gate electrode layer G and the source / drain contact portions 119_S and 119_D in the lateral direction (e.g., the x direction) can be reduced or avoided.

[0028] In Figure 1(a) and 1(b)In the example, it is also shown that the gate electrode layer G, the channel layer 113, and the source / drain electrodes 115_S, 115_D have different extension lengths in the channel width direction (e.g., the y direction), mainly to make it easier to fabricate each contact portion (e.g., to avoid them being adjacent to each other in the x direction, thus causing problems such as short circuits). However, the present disclosure is not limited thereto. For example, the gate contact portion 119_G can be connected to the gate electrode layer G from below (along the z direction). Additionally, in some embodiments, the body contact portion 119_B can also be omitted. In this case, at least one of the gate electrode layer G and the channel layer 113 does not necessarily have an extension length greater than that of the source / drain electrodes 115_S, 115_D in the y direction.

[0029] According to an embodiment of the present disclosure, the height of the channel layer 113 (in the vertical direction, e.g., the z direction) can be flexibly adjusted. Based on different heights, fully depleted (FD) devices (e.g., when the height is relatively small) or partially depleted (PD) devices (e.g., when the height is relatively large) can be realized.

[0030] Figures 2 to 8(c) Schematically shows the structures of some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0031] As Figure 2 shown, a substrate 1001 is provided. The substrate 1001 can include a semiconductor material, such as an elemental semiconductor material like silicon or germanium, a compound semiconductor material like silicon germanium, etc. Here, taking a silicon wafer as an example, the substrate 1001 is described. On the substrate 1001, a buried oxide layer (BOX) 1003 can be formed by deposition such as chemical vapor deposition (CVD) or thermal oxidation. The buried oxide layer 1003 can also be referred to as a field oxide layer (FOX).

[0032] As Figure 3 shown, on the buried oxide layer 1003, a gate electrode layer can be formed. For example, by deposition such as CVD, a gate conductor material layer such as tungsten and a work function material layer such as TiN are sequentially formed, and the deposited gate conductor material layer and work function material layer are patterned (e.g., patterned into the rectangle shown in Figure 1(a) and 1(b) ; but the specific shape is not limited thereto) through, for example, photolithography and etching such as reactive ion etching (RIE), thereby forming a gate conductor layer 1005 and a work function layer 1007 (which can be collectively referred to as the gate electrode layer as described above).

[0033] As Figure 4As shown, an oxide layer 1009 can be formed on the buried oxide layer 1003 at the outer periphery of the gate electrode layer. For example, the oxide layer 1009 is formed by depositing an oxide through CVD and planarizing the deposited oxide, such as by chemical mechanical polishing (CMP), to expose the upper surface of the work function layer 1007. Thus, the top surface of the oxide layer 1009 can be substantially coplanar with the upper surface of the work function layer 1007.

[0034] Here, the oxide layer 1009 can support the structure to be formed above, particularly the source / drain electrodes, such that the bottom surface of the source / drain electrodes can be higher than the top surface of the gate electrode layer (i.e., the upper surface of the work function layer 1007). The oxide layer 1009 and the buried oxide layer 1003 can together constitute a dielectric layer on the substrate 1001, which can surround the gate electrode layer (gate conductor layer 1005, work function layer 1007), for example, surrounding the bottom surface and sidewalls of the gate electrode layer, but exposing the top surface of the gate electrode layer. Additionally, this dielectric layer provides electrical isolation between the structures to be formed above, such as the channel layer and the source / drain electrodes, and the substrate 1001, and thus forms a SOI structure.

[0035] In this example, an example of the buried oxide layer 1003 and the oxide layer 1009 is shown, but the present disclosure is not limited thereto. Such a dielectric layer can also be formed by other dielectric materials, such as nitrides or oxynitrides. Moreover, the buried oxide layer 1003 and the oxide layer 1009 can be implemented by different dielectric materials from each other.

[0036] As Figure 5 shown, on the dielectric layer (1003, 1009), a gate dielectric layer 1011, such as HfO2, can be formed by deposition, such as CVD. In this example, the gate dielectric layer 1011 can extend substantially flatly and contact the upper surface of the work function layer 1007.

[0037] An active region can be provided on the gate dielectric layer 1011.

[0038] As Figure 6 shown, a channel layer 1013 opposite to the gate electrode layer can be formed on the gate dielectric layer 1011. For example, a semiconductor material layer can be formed on the gate dielectric layer 1011 by deposition, such as CVD, and the deposited semiconductor material layer can be patterned, such as by lithography and etching, such as RIE (for example, patterned as Figure 1(a) and 1(b)the rectangle shown in; however, the specific shape is not limited thereto), thereby forming the channel layer 1013. As described above, the channel layer 1013 may include various suitable semiconductor materials. The channel layer 1013 may be an intrinsic semiconductor that is not intentionally doped, or it may also be lightly doped. The channel layer 1013 may include amorphous or polycrystalline semiconductor materials, or it may also include single-crystalline semiconductor materials through heat treatment after deposition. The height (in the z direction) of the channel layer 1013 can be adjusted, for example, by adjusting the thickness of the deposited semiconductor material layer, to implement an FD device or a PD device. Additionally, as described above, the width of the channel layer 1013 in the x direction may be less than the width of the gate electrode layer, and thus the channel layer 1013 may face the gate electrode layer as a whole.

[0039] Additionally, as Figure 7 shown, source / drain electrodes 1015_S, 1015_D that are in contact with the sidewalls of the channel layer 1013 can be formed on both sides of the channel layer 1013. For example, a metal material layer can be formed on the gate dielectric layer 1011 by deposition such as CVD, and the height of the top surface of the deposited metal material layer can exceed the height of the top surface of the channel layer 1013. The deposited metal material layer can be planarized such as by CMP and etched back so that the height of its top surface drops below the height of the top surface of the channel layer 1013. Thereafter, the metal material layer can be patterned (e.g., patterned into Figure 1(a) and 1(b) the rectangle shown in; however, the specific shape is not limited thereto), thereby forming the source / drain electrodes 1015_S, 1015_D.

[0040] In this example, the gate dielectric layer 1011 is not further patterned, so that it can extend over the entire upper surface of the dielectric layers (1003, 1009) and the gate electrode layer. However, the present disclosure is not limited thereto. For example, the gate dielectric layer 1011 can also be patterned to remove it from certain regions, especially the regions where the channel layer and the source / drain electrodes are not formed. For example, referring to FIG. 8(c) below, the gate dielectric layer 1011 (and even the underlying work function layer 1007) can be removed from the region where the gate contact portion 1019_G is to be formed.

[0041] Additionally, as Figure 8(a) 、 8(b)As shown in FIGS. 8(c), an interlayer dielectric layer 1017 can be formed on the substrate to cover various components formed on the substrate. For example, an oxide layer can be formed by deposition such as CVD, and the deposited oxide layer can be planarized by processes such as CMP to form the interlayer dielectric layer 1017. The height of the top surface of the interlayer dielectric layer 1017 can be higher than the height of the top surfaces of the channel layer 1013 and the source / drain electrodes 1015_S, 1015_D. Contact holes extending vertically (in the z direction) can be formed in the interlayer dielectric layer 1017 by etching. In a top view, the contact holes can be circular, elliptical, square, etc. By filling the contact holes with a conductive material such as metal, various contact portions can be formed, such as source / drain contact portions 1019_S, 1019_D connected to the source / drain electrodes 1015_S, 1015_D respectively, a gate contact portion 1019_G connected to the gate electrode layer (e.g., the gate conductor layer 1005 of the gate electrode layer), and a body contact portion 1019_B connected to the channel layer 1013. Before filling the contact holes with metal, a diffusion barrier layer such as a conductive metal nitride can also be formed along the bottom and sidewalls of the contact holes. As described above, the source / drain contact portions 1019_S, 1019_D thus formed and the source / drain electrodes 1015_S, 1015_D can form an ohmic contact to reduce the contact resistance. In addition, there can be no overlap in the x direction between the source / drain contact portions 1019_S, 1019_D and the gate electrode layer (1003, 1005), thereby reducing the parasitic capacitance.

[0042] Next, the backend-of-line (BEOL) process can be continued, for example, by forming an interconnect structure on the interlayer dielectric layer 1017.

[0043] Figure 9 A cross-sectional view of a semiconductor device according to another embodiment of the present disclosure is schematically shown.

[0044] As Figure 9As shown, the semiconductor device 200 according to this embodiment may include channel layers 2013-1, 2013-2, and 2013-3 that are stacked on a substrate 2001 with spaces therebetween, and these channel layers may be formed in the form of nanosheets. Although three nanosheets are shown here, the present disclosure is not limited thereto, but may include more or fewer nanosheets. Gate electrode layers may be formed between adjacent channel layers among these channel layers, under the lowermost channel layer 2013-1, and above the uppermost channel layer 2013, and corresponding gate dielectric layers 2011 are provided between each channel layer and the adjacent gate electrode layer. The gate electrode layer may include a gate conductor layer 2005 and a work function layer 2007. The gate conductor layers 2005 in the gate electrode layer may be connected to each other (which will be described in further detail below), and thus a gate-all-around (GAA) configuration may be formed. Source / drain electrodes 2015_S and 2015_D may be formed on opposite sides of the channel layers 2013-1, 2013-2, and 2013-3 in a first direction (e.g., the x direction). Source / drain contact portions 2019_S and 2019_D that penetrate the interlayer insulating layer 2017 may be formed on the source / drain electrodes 2015_S and 2015_D, respectively. Additionally, a gate contact portion 2019_G may be connected to the gate electrode layer (more specifically, the gate conductor layer 2005). In this example, the gate contact portion 2019_G may be formed in a backside structure, that is, extending from the backside of the substrate 2001 to the gate conductor layer 2005. However, the present disclosure is not limited thereto. The gate contact portion 2019_G may also be formed on the front side.

[0045] A buried oxide layer (BOX) or a field oxide layer (FOX) 2003 may be formed on the substrate 2001, and the active region of the semiconductor device 200 may be disposed thereon, thereby forming a silicon-on-insulator (SOI) structure.

[0046] Regarding the substrate 2001, the buried oxide layer 2003, the gate conductor layer 2005, the work function layer 2007, the gate dielectric layer 2011, the channel layers 2013-1, 2013-2, 2013-3, the source / drain electrodes 2015_S, 2015_D, the interlayer dielectric layer 2017, the gate contact 2019_G, and the source / drain contacts 2019_S, 2019_D, reference may be made to the above specific descriptions for the substrate 1001, the buried oxide layer 1003, the gate conductor layer 1005, the work function layer 1007, the gate dielectric layer 1011, the channel layer 1013, the source / drain electrodes 1015_S, 1015_D, the interlayer dielectric layer 1017, the gate contact 1019_G, and the source / drain contacts 1019_S, 1019_D, except that their shapes are different (for example, the channel layers 2013-1, 2013-2, 2013-3 are formed in the form of nanosheets, and accordingly, the sizes of the respective components may be different, but their respective materials and the electrical relationships between them may be substantially the same). The device size parameters of a conventional GAA nanosheet FET also apply to the semiconductor device 200 according to this embodiment.

[0047] In the semiconductor device 200, the source / drain contacts 2019_S, 2019_D (the bottom surfaces thereof are connected to the top surfaces of the source / drain electrodes 2015_S, 2015_D) and the gate electrode layer (the top surface of the uppermost gate electrode layer may be substantially coplanar with the top surfaces of the source / drain electrodes 2015_S, 2015_D) may not overlap with each other laterally, and thus the parasitic capacitance caused thereby can be avoided.

[0048] Figures 10 to 23(b) Schematically shows the structures of some stages in the process of manufacturing a semiconductor device according to another embodiment of the present disclosure. Hereinafter, the differences from the above embodiment will be mainly described.

[0049] As Figure 10 shown, a substrate 2001 is provided, and a buried oxide layer 2003 is formed on the substrate 2001. In this regard, reference may be made to the above description in combination with Figure 2 this.

[0050] As Figure 11(a) and 11(b) shown, on the buried oxide layer 1003, a gate electrode layer may be formed. The gate electrode layer may include a gate conductor layer 2005 and a work function layer 2007. A gate dielectric layer 2011 may be formed on the gate electrode layer. Regarding the materials and formation processes of these layers, reference may be made to the above description in combination with Figure 3 and 5 this. In this embodiment, the gate conductor layer 2005, the work function layer 2007, and the gate dielectric layer 2011 may be patterned together into a strip extending in a second direction (for example, the y direction) intersecting (for example, perpendicular) to the first direction, as shown in FIG. 11(a).

[0051] As Figure 12 shown, on the buried oxide layer 2003, a nitride layer 2009 can be formed on the outer periphery of the gate electrode layer and the gate dielectric layer 2011. For example, the nitride is deposited by CVD, and the deposited nitride is planarized such as by CMP to expose the upper surface of the gate dielectric layer 2011, thereby forming the nitride layer 2009. Thus, the top surface of the nitride layer 2009 can be substantially coplanar with the upper surface of the gate dielectric layer 2011.

[0052] In addition, on the gate dielectric layer 2011 (and the nitride layer 2009), a channel layer 2013-1 can be formed by deposition such as CVD. Regarding the channel layer, reference can be made to the relevant description of the channel layer 1013 above. In this embodiment, the channel layer 2013-1 can be formed as a substantially flat and extending layer.

[0053] Through such a process, a stack of a gate electrode layer - gate dielectric layer - channel layer can be formed, wherein the gate electrode layer - gate dielectric layer together are patterned into a bar shape extending in the second direction, and nitride layers 2009 are formed on both sides in the first direction (e.g., the x direction).

[0054] Such a process can be repeated to obtain a structure in which multiple such stacks are stacked on top of each other, as Figure 13 shown. Figure 13 The structure shown includes three channel layers 2013-1, 2013-2, 2013-3, but the present disclosure is not limited thereto, and more or fewer channel layers can be obtained according to the number of times the process is repeated. In addition, the formation order of the gate dielectric layer, the work function layer, and the gate conductor layer can be designed in the process such that a gate dielectric layer is provided between each channel layer and the adjacent gate electrode layer; a work function layer is provided between the gate conductor layer and the adjacent gate dielectric layer. When patterning each gate electrode layer and gate dielectric layer, the same photolithography mask can be used.

[0055] For example, due to the planarization process, the uppermost gate conductor layer 2005 and the nitride layer 2009 can have substantially coplanar upper surfaces.

[0056] The size of the channel layer in the second direction (e.g., the y direction) can be defined.

[0057] For example, as Figure 14(a) 、 14(b) and 14(c) shown, a photoresist 2021 can be formed on the structure shown in Figure 13 shown, and it is patterned into a bar shape extending in the first direction (e.g., the x direction). The photoresist 2021 can have a certain width in the second direction, which is used to define the width of the channel layer in the second direction. As Figure 15As shown, a photoresist that can be configured in this way is used as an etching mask to anisotropically etch the underlying layer, such as RIE in the vertical direction, and the etching can stop at the buried oxide layer 2003. After that, the photoresist 2021 can be removed. Thus, each gate electrode layer and gate dielectric layer can be configured in a substantially rectangular form (see FIG. 17(a)). Currently, the sidewalls of each channel layer in the second direction are exposed.

[0058] In this embodiment, a GAA configuration will be formed. To this end, a gate dielectric layer can be formed on the sidewalls of the channel layer in the second direction.

[0059] For example, as Figure 16 shown, the channel layers 2013-1, 2013-2, 2013-3 can be selectively etched to be recessed laterally, so as to release space at their ends. As Figure 17(a) and 17(b) shown, the gate dielectric layers 2011s and work function layers 2007s can be formed at the ends of the channel layers 2013-1, 2013-2, 2013-3 by, for example, conformally depositing a corresponding material layer and performing RIE in the vertical direction on the deposited material layer.

[0060] It should be noted here that for convenience in FIG. 17(b), both the gate dielectric layer 2011s and the work function layer 2007s are shown in a vertically extending form. However, the present disclosure is not limited thereto. For example, according to the manufacturing process, the gate dielectric layer 2011s can extend on the top and bottom surfaces of the work function layer 2007s (so that the gate dielectric layer 2011s can surround the work function layer 2007s).

[0061] Currently, each gate electrode layer is disposed above or below the corresponding channel layer. As described above, a GAA configuration can be formed.

[0062] For example, as Figure 18(a) 、 18(b) and FIG. 18(c) shown, by depositing a nitride and planarizing the deposited nitride, such as CMP, to expose the uppermost gate conductor layer 2005, a nitride layer 2023 is formed on the buried oxide layer 2003 (together with the previous nitride 2009). On the nitride layer 2023, a photoresist 2025 can be formed and patterned to expose the regions on the opposite sides of each gate conductor layer 2005 in the second direction. In the example shown, the photoresist 2025 can be patterned to have a strip-shaped opening extending in the second direction by, for example, using a photomask that is the same as or corresponding to the patterning described in combination with Figure 11(a) and 11(b) described.

[0063] As Figure 19(a) 、 19(b)As shown in FIGS. 19(c), the photoresist 2025 can be used as an etching mask to anisotropically etch the nitride layer 2023, such as vertical RIE, and the etching can stop at the buried oxide layer 2003. Thus, space is released in the nitride layer 2023, and a gate conductor layer can be further formed in this space. As shown in the figure, the released space is located on the opposite sides in the second direction of the previously formed gate electrode layers. After that, the photoresist 2025 can be removed.

[0064] As Figure 20(a) and 20(b) shown, in the space released in the nitride layer 2023, an additional gate conductor layer 2005a can be formed by depositing a conductive material and planarizing the deposited conductive material, such as CMP, to expose the nitride layer 2023. The thus formed gate conductor layer 2005a can be connected or in contact with the previously formed gate conductor layer 2005, so as to form a GAA configuration surrounding the outer periphery of each channel layer.

[0065] Similarly, space can be released in the nitride layer 2023 for forming source / drain electrodes.

[0066] For example, as Figure 21(a) and 21(b) shown, on the nitride layer 2023, a photoresist 2027 can be formed and patterned to expose the regions on the opposite sides in the first direction of each gate conductor layer 2005. Here, the exposed regions are spaced apart from each gate conductor layer 2005 by a certain distance in the first direction.

[0067] As Figure 22(a) and 22(b) shown, the photoresist 2027 can be used as an etching mask to anisotropically etch the nitride layer 2023 and each channel layer 2013-1, 2013-2, 2013-3, such as vertical RIE, and the etching can stop at the buried oxide layer 2003. Thus, space is released in the nitride layer 2023, and source / drain electrodes can be formed in this space. As shown in the figure, the released space is located on the opposite sides in the first direction of the previously formed gate conductor layers 2005 and exposes the sidewalls of the channel layers 2013-1, 2013-2, 2013-3. After that, the photoresist 2027 can be removed.

[0068] As Figure 23(a) and 23(b) shown, in the space released in the nitride layer 2023, source / drain electrodes 2015_S, 2015_D can be formed by depositing a conductive material and planarizing the deposited conductive material, such as CMP, to expose the nitride layer 2023. The source / drain electrodes 2015_S, 2015_D can be connected or in contact with each channel layer 2013-1, 2013-2, 2013-3.

[0069] Return reference Figure 9 , an interlayer dielectric layer 2017 can be formed, and various contact portions can be formed.

[0070] The semiconductor device according to an embodiment of the present disclosure can be applied to various electronic devices. For example, an integrated circuit (IC) can be formed based on such a semiconductor device, and an electronic device can be constructed therefrom. Such an electronic device may also include components such as a display screen cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit. Such electronic devices include, for example, smart phones, computers, tablet computers, wearable smart devices, artificial intelligence devices, mobile power supplies, and the like.

[0071] In the above description, technical details such as the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the desired shape. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0072] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes and not for limiting the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a substrate; a dielectric layer on the substrate; a gate electrode layer on the dielectric layer; a gate dielectric layer on the gate electrode layer; a channel layer on the gate dielectric layer opposite to the gate electrode layer; source / drain electrodes on both sides of the channel layer, wherein the source / drain electrodes include a metal material and contact the sidewalls of the channel layer.

2. The semiconductor device according to claim 1, wherein, The height of the top surface of the gate electrode layer is lower than the height of the bottom surface of the source / drain electrodes.

3. The semiconductor device according to claim 2, wherein the gate electrode layer is surrounded by the dielectric layer, and the top surface of the gate electrode layer is exposed from the dielectric layer, the gate dielectric layer extends on the top surface of the gate electrode layer and the top surface of the dielectric layer, and the source / drain electrodes are disposed on the gate dielectric layer.

4. The semiconductor device according to claim 3, wherein, The top surface of the gate electrode layer is substantially coplanar with the top surface of the dielectric layer.

5. The semiconductor device according to claim 3 or 4, wherein, The dielectric layer includes: a buried oxide layer on the substrate, wherein the gate electrode layer is disposed on the buried oxide layer; and an oxide layer on the buried oxide layer and outside the periphery of the gate electrode.

6. The semiconductor device according to claim 1, wherein, In the direction from one source / drain electrode to the other source / drain electrode, the width of the channel layer is smaller than the width of the gate electrode layer.

7. The semiconductor device according to claim 1, further comprising: source / drain contact portions on the source / drain electrodes, wherein the height of the bottom surface of the source / drain contact portions is higher than the height of the top surface of the gate electrode layer.

8. The semiconductor device according to claim 1 further comprises: a body contact portion on the channel layer.

9. The semiconductor device according to claim 1 further comprises: a gate contact portion on the gate electrode layer.

10. The semiconductor device according to claim 1, wherein the gate electrode layer includes a gate conductor layer and a work function layer on the gate conductor layer, the channel layer includes silicon, the source / drain electrodes include: for an n-type semiconductor device, a metal material with a Fermi level close to the bottom of the conduction band of silicon; for a p-type semiconductor device, a metal material with a Fermi level close to the top of the valence band of silicon.

11. The semiconductor device according to claim 1, wherein, The channel layer has a predetermined thickness to implement a fully depleted device or a partially depleted device.

12. The semiconductor device according to claim 1, wherein, The height of the top surface of the source / drain electrodes is lower than the height of the top surface of the channel layer.

13. The semiconductor device according to claim 1, further comprising: one or more other channel layers on the channel layer; and one or more gate electrode layers respectively between the channel layer and the one or more other channel layers and a gate electrode layer on the uppermost channel layer among the one or more other channel layers, wherein a corresponding gate dielectric layer is disposed between each channel layer and the adjacent gate electrode layer, wherein the source / drain electrodes are disposed on the sidewalls of the channel layer and the one or more other channel layers.

14. The semiconductor device according to claim 13, further comprising: source / drain contact portions on the source / drain electrodes, wherein the source / drain contact portions do not overlap with the uppermost gate electrode layer laterally.

15. A method of manufacturing a semiconductor device, comprising: forming a dielectric layer on a substrate; forming a gate electrode layer on the dielectric layer; forming a gate dielectric layer on the gate electrode layer; forming a channel layer on the gate dielectric layer opposite to the gate electrode layer; Source / drain electrodes including a metallic material are formed on both sides of the channel layer and in contact with sidewalls of the channel layer.

16. The method according to claim 15, wherein, Forming the dielectric layer includes: forming a buried oxide layer on the substrate; and after forming the gate electrode layer on the buried oxide layer, forming an oxide layer on the outer periphery of the gate electrode layer, the oxide layer exposing a top surface of the gate electrode layer.

17. The method according to claim 16, wherein, The oxide layer is planarized to expose the top surface of the gate electrode layer, wherein the gate dielectric layer is formed on the planarized oxide layer and the top surface of the gate electrode layer.

18. The method according to claim 15, wherein forming the channel layer includes: depositing a semiconductor material layer; patterning the deposited semiconductor material layer to form the channel layer opposite to the gate electrode.

19. The method according to claim 15, wherein forming the source / drain electrodes includes: depositing a metallic material; and patterning the deposited metallic material such that a height of a top surface thereof is lower than a height of a top surface of the channel layer.

20. The method according to claim 15, further comprising: forming an interlayer dielectric layer on the substrate; forming source / drain contact portions passing through the interlayer dielectric layer and connected to the source / drain electrodes, wherein a height of a bottom surface of the source / drain contact portions is higher than a height of a top surface of the gate electrode layer.

21. The method according to claim 20, further comprising: forming gate contact portions passing through the interlayer dielectric layer and connected to the gate electrode layer; and forming body contact portions passing through the interlayer dielectric layer and connected to the channel layer.

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