Memory device, system and decoding circuit

Abstract

The embodiment of the invention provides a memory device, a memory system and a decoding circuit, and the memory device comprises a memory unit array and a peripheral circuit coupled with the memory unit array. Wherein the memory cell array comprises at least one memory block, and the memory block is provided with a plurality of rows of word lines, a plurality of columns of bit lines and memory cells coupled between the word lines and the bit lines; the peripheral circuit comprises a column decoding circuit; a column decoding circuit is coupled to a plurality of columns of bit lines, the column decoding circuit configured to receive a column address signal, perform multi-stage decoding of the column address signal, and output a column selection signal indicating that a corresponding bit line in the memory block is enabled.

Description

Memory device, system and decoding circuit Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and more particularly to a memory device, system, and decoding circuit. Background Art

[0002] Memory devices and their systems are storage devices used to store information in modern information technology. As people's requirements for storage devices continue to increase, there is much room for improvement in memory devices and their systems.

[0003] Application Contents

[0004] Embodiments of the present application provide a memory device, system, and decoding circuit.

[0005] In a first aspect, an embodiment of the present application provides a memory device comprising: a memory cell array and a peripheral circuit coupled to the memory cell array; wherein:

[0006] The memory cell array includes at least one memory block, wherein the memory block is provided with multiple rows of word lines and multiple columns of bit lines, and memory cells coupled between the word lines and the bit lines;

[0007] The peripheral circuit includes a column decoding circuit; the column decoding circuit is coupled to the multiple column bit lines, and the column decoding circuit is configured to receive a column address signal, perform multi-stage decoding on the column address signal, and output a column selection signal, wherein the column selection signal indicates to enable the corresponding bit line in the storage block.

[0008] In some embodiments, the column decoding circuit includes: a first-stage column decoding circuit including a first input interface and a first output interface; the first input interface at least receives a column address signal, and the first output interface outputs a preliminary column decoding signal; the number of transmission lines corresponding to the column address signal is less than the number of transmission lines corresponding to the preliminary column decoding signal;

[0009] The second-stage column decoding circuit includes a second input interface and a second output interface; the second input interface is coupled to the first-stage column decoding circuit to receive the preliminary column decoding signal; the second output interface is coupled to multiple bit lines in the storage block to output a column decoding signal, wherein the column decoding signal indicates that one bit line among the multiple bit lines of the storage block is enabled, and the number of transmission lines corresponding to the preliminary column decoding signal is less than the number of transmission lines corresponding to the column decoding signal.

[0010] In some embodiments, the memory cell array includes a plurality of memory banks, each of the memory banks includes a plurality of row memory blocks and a plurality of column memory blocks;

[0011] Each of the memory banks corresponds to a plurality of the first-stage column decoding circuits and a plurality of the second-stage column decoding circuits, each of the first-stage column decoding circuits corresponds to a column of memory blocks, and each of the second-stage column decoding circuits corresponds to a memory block in a column of memory blocks;

[0012] The second input interface of each second-stage column decoding circuit is coupled to the first-stage column decoding circuit, and the second output interface is coupled to multiple bit lines of one of the memory blocks. The column decoding signal indicates that the corresponding bit line in the selected memory block is enabled.

[0013] In some embodiments, the column address signal includes multi-bit data; the first-stage column decoding circuit includes:

[0014] A first decoding circuit is configured to decode a plurality of consecutive low-bit data in the column address signal to obtain a first decoding signal;

[0015] The second decoding circuit is configured to decode the remaining multiple consecutive high-bit data in the column address signal to obtain a second decoding signal; the first decoding signal and the second decoding signal are configured to jointly form the preliminary column decoding signal.

[0016] In some embodiments, the first-stage column decoding circuit further includes: a synchronization control signal generating circuit configured to generate a synchronization control signal, wherein a clock period corresponding to the synchronization control signal is smaller than a clock period corresponding to the first decoding signal and the second decoding signal;

[0017] The second input interface of the second-stage column decoding circuit further receives the synchronization control signal. The second-stage column decoding circuit is configured to output the column decoding signal in response to the enable state of the synchronization control signal and the normal output of the first decoding signal and the second decoding signal.

[0018] In some embodiments, the second-stage column decoding circuit is specifically configured to receive the synchronization control signal and the semiconductor element enable signal, and when both the synchronization control signal and the storage block enable signal are enabled, the output column decoding signal will enable the bit line corresponding to the enabled data bit of the preliminary column decoding signal in the selected storage block; when the storage block enable signal is enabled, it indicates that the storage block is selected.

[0019] In some embodiments, the first-stage column decoding circuit further includes: a driving circuit, the driving circuit including a plurality of drivers;

[0020] Each driver is connected to one of the plurality of transmission lines corresponding to the first decoded signal and the second decoded signal respectively, and is configured to perform power amplification processing on the decoded signal on the corresponding transmission line.

[0021] In some embodiments, the memory block includes a first region and a second region, and the number of bit lines arranged in the first region and the second region are the same;

[0022] The first-stage column decoding circuit further includes: a third decoding circuit, a first region selection circuit, and a second region selection circuit;

[0023] a third decoding circuit configured to decode the remaining plurality of consecutive high-bit data in the column address signal to obtain a third decoding signal; the third decoding signal is the same as the second decoding signal;

[0024] The first region selection circuit is connected to the second decoding circuit and is configured to output the second decoding signal when the first region enable signal is enabled;

[0025] The second region selection circuit is connected to the third decoding circuit and is configured to output the third decoding signal when the second region enable signal is enabled; the first region enable signal / the second region enable signal being enabled indicates that the first region / the second region of the storage block is selected.

[0026] In some embodiments, the first-stage column decoding circuit further includes: a buffer;

[0027] The buffer is connected to the first decoding circuit and is configured to adjust the timing of the first decoding signal to be synchronized with the output signals of the first area selection circuit and the second area selection circuit.

[0028] In some embodiments, the column address signal is 6-bit binary data, the preliminary column decoding signal corresponds to 24 transmission lines, the first area of ​​the memory block includes 64 bit lines, and the second area of ​​the memory block includes 64 bit lines.

[0029] In some embodiments, the memory includes a plurality of address transmission lines and a plurality of data transmission lines;

[0030] The first-stage column decoding circuit corresponding to a column of storage blocks is connected to the second-stage column decoding circuit corresponding to each storage block in the column of storage blocks through the plurality of address transmission lines;

[0031] Each memory block in the column of memory blocks is connected to the data transmission line;

[0032] The plurality of address transmission lines and the plurality of data transmission lines are arranged on the same metal layer.

[0033] In some embodiments, the memory cell array is disposed on a first semiconductor structure, and the peripheral circuit is disposed on a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked and electrically connected by bonding;

[0034] Each of the first-stage column decoding circuits is disposed on one side of a corresponding column storage block;

[0035] Each second-stage column decoding circuit and the sensing amplifier circuit and word line driving circuit corresponding to each memory block are located at the position of the orthographic projection of a corresponding memory block on the plane where the second semiconductor structure is located.

[0036] In some embodiments, the memory device includes dynamic random access memory.

[0037] In a second aspect, an embodiment of the present application provides a memory system, including the memory device in the above solution; and

[0038] A memory controller is coupled to the memory device and controls the memory device.

[0039] In a second aspect, an embodiment of the present application provides a decoding circuit, including:

[0040] The first-stage decoding circuit includes a first input interface and a first output interface; the first input interface receives at least a signal to be decoded, and the first output interface outputs a preliminary decoded signal; the number of transmission lines corresponding to the signal to be decoded is less than the number of transmission lines corresponding to the preliminary decoded signal;

[0041] The second-stage decoding circuit includes a second input interface and a second output interface; the second input interface is coupled to the first-stage decoding circuit to receive the preliminary decoding signal; the second output interface is coupled to multiple structures to be selected in the semiconductor element to output a decoding signal, wherein the decoding signal indicates that one of the structures to be selected in the semiconductor element is enabled, and the number of transmission lines corresponding to the preliminary decoding signal is less than the number of transmission lines corresponding to the decoding signal.

[0042] In some embodiments, the number of the second-stage decoding circuits includes a plurality, and each second-stage decoding circuit corresponds to a semiconductor element;

[0043] The second input interface of each second-stage decoding circuit is coupled to the first-stage decoding circuit, and the second output interface is coupled to multiple structures to be decoded of one semiconductor element. The decoding signal indicates that the corresponding structure to be decoded in the selected semiconductor element is enabled.

[0044] In some embodiments, the signal to be decoded includes multi-bit data; the first-stage decoding circuit includes:

[0045] A first decoding circuit is configured to decode a plurality of consecutive low-bit data in the signal to be decoded to obtain a first decoded signal;

[0046] The second decoding circuit is configured to decode the remaining multiple consecutive high-bit data in the signal to be decoded to obtain a second decoded signal; the first decoded signal and the second decoded signal are configured to jointly form the preliminary decoded signal.

[0047] In some embodiments, the first-stage decoding circuit further includes: a synchronization control signal generating circuit configured to generate a synchronization control signal, wherein a clock period corresponding to the synchronization control signal is smaller than a clock period corresponding to the first decoding signal and the second decoding signal;

[0048] The second input interface of the second-level decoding circuit also receives the synchronization control signal, and the second-level decoding circuit is configured to output the decoding signal in response to the enable state of the synchronization control signal and the normal output of the first decoding signal and the second decoding signal.

[0049] In some embodiments, the second-stage decoding circuit is specifically configured to receive the synchronization control signal and the semiconductor element enable signal, and when both the synchronization control signal and the semiconductor element enable signal are enabled, the output decoding signal will select and enable the to-be-selected structure in the semiconductor element corresponding to the enabled data bit of the preliminary decoding signal; when the semiconductor element enable signal is enabled, it indicates that the semiconductor element is selected.

[0050] In some embodiments, the first stage decoding circuit further includes: a driving circuit, the driving circuit including a plurality of drivers;

[0051] Each driver is connected to one of the plurality of transmission lines corresponding to the first decoded signal and the second decoded signal respectively, and is configured to perform power amplification processing on the decoded signal on the corresponding transmission line.

[0052] In some embodiments, the first stage decoding circuit further includes: a third decoding circuit, a first region selection circuit, and a second region selection circuit;

[0053] a third decoding circuit configured to decode the remaining plurality of consecutive high-bit data in the signal to be decoded to obtain a third decoded signal; the third decoded signal is the same as the second decoded signal;

[0054] The first region selection circuit is connected to the second decoding circuit and is configured to output the second decoding signal when the first region enable signal is enabled;

[0055] The second region selection circuit is connected to the third decoding circuit and is configured to output the third decoding signal when the second region enable signal is enabled; the first region enable signal / the second region enable signal being enabled indicates that the first region / the second region of the semiconductor element is selected.

[0056] In some embodiments, the first stage decoding circuit further comprises: a buffer;

[0057] The buffer is connected to the first decoding circuit and is configured to perform timing adjustment on the first decoding signal so as to be synchronized with output signals of the first region selection circuit and the second region selection circuit.

[0058] In some embodiments, the first region selection circuit / the second region selection circuit includes: a first NAND gate, a second NAND gate;

[0059] One input end of the first NAND gate is connected to the output of the second decoding circuit / the third decoding circuit, and the other input end is used to receive a partition enable signal; when the partition enable signal is enabled, it indicates that the semiconductor element supports selection by region;

[0060] One input end of the second NAND gate is connected to the output end of the first NAND gate, the other input end is used to receive the first region enable signal / the second region enable signal, and the output end is connected to the first output interface.

[0061] In some embodiments, the signal to be decoded includes a column address signal; the transmission line includes an address transmission line; the semiconductor element includes a memory block, the plurality of structures to be selected include a plurality of bit lines; and the decoding signal indicates selection of one of the plurality of bit lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present application and should not be regarded as limiting the scope of the present application.

[0063] FIG1 is a block diagram of an exemplary electronic device according to an embodiment of the present application;

[0064] FIG2A is a block diagram illustrating the composition of an exemplary solid-state drive (SSD) or a flash memory (UFS) according to an embodiment of the present application;

[0065] FIG2B is a block diagram illustrating the composition of an exemplary memory according to an embodiment of the present application;

[0066] FIG3 is a schematic diagram of the structure of an exemplary dynamic random access memory according to an embodiment of the present application;

[0067] 4 is a schematic diagram illustrating the connection relationship between word lines, bit lines, and memory cells of an exemplary dynamic random access memory according to an embodiment of the present application;

[0068] 5A is a schematic diagram illustrating the distribution of a memory cell array and peripheral circuits in an exemplary memory device according to an embodiment of the present application;

[0069] 5B is a top view schematically illustrating the distribution of a memory cell array and peripheral circuits in an exemplary memory device according to an embodiment of the present application;

[0070] 5C is a top view schematically illustrating the distribution of memory blocks and column decoding circuits in an exemplary memory bank according to an embodiment of the present application;

[0071] 6A is a top view schematically illustrating the distribution of memory blocks and column decoding circuits in an exemplary memory bank according to another embodiment of the present application;

[0072] 6B is a top view schematically illustrating the distribution of memory blocks and column decoding circuits in an exemplary memory bank according to yet another embodiment of the present application;

[0073] 7A is a schematic diagram illustrating the distribution of a memory cell array and peripheral circuits in an exemplary memory device according to another embodiment of the present application;

[0074] 7B is a top view schematically illustrating the distribution of a memory cell array and peripheral circuits in an exemplary memory device according to another embodiment of the present application;

[0075] FIG8A is a block diagram of an exemplary column decoding circuit according to an embodiment of the present application;

[0076] FIG8B is a schematic diagram of a specific implementation circuit of an exemplary column decoding circuit according to an embodiment of the present application;

[0077] FIG8C is a schematic diagram of voltage timing sequences of some signals in an exemplary column decoding circuit according to an embodiment of the present application;

[0078] FIG9A is a block diagram of an exemplary column decoding circuit according to another embodiment of the present application;

[0079] FIG9B is a schematic diagram of a specific implementation circuit of an exemplary column decoding circuit according to another embodiment of the present application. DETAILED DESCRIPTION

[0080] The following describes exemplary embodiments of the present application in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0081] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0082] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0083] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0084] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0085] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an" and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items. The units "root", "bar" or "piece" for transmission lines all have the same meaning.

[0086] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0087] FIG1 shows a block diagram of an exemplary electronic device according to an embodiment of the present application. The electronic device 1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG1 , the electronic device 1 may include a host HOST and a memory system 30, the memory system 30 including a memory controller 10 and one or more memory devices 20. The host HOST may be a processor of the electronic device (e.g., a central processing unit (CPU) or a graphic processing unit (GPU)). The host HOST may be configured to send data to the memory device 20 or receive data from the memory device 20. The memory controller 10 is coupled to the memory device 20 and the host HOST and is configured to control the memory device 20. The memory controller 10 may manage the data stored in the memory device 20 and communicate with the host HOST.

[0088] The memory controller 10 may be configured to control operations of the memory device 20, such as read, erase, write, and refresh operations. In some embodiments, the memory controller 10 may also be configured to process error correction codes (ECC) on data read from or written to the memory device 20. The memory controller 10 may also perform any other suitable functions, such as formatting the memory device 20.

[0089] In some specific embodiments, the memory controller 10 and one or more memory devices 20 can be integrated into various types of electronic devices. For example, the memory controller 10 can be integrated into the north bridge of a computer motherboard or directly integrated into the computer CPU, and multiple memory devices 20 can be integrated into a memory module. In other words, the memory system 30 can be implemented and packaged into various types of terminal electronic products.

[0090] The memory controller 10 can send and receive data to and from the host HOST and can send commands CMD and addresses ADDR to the memory device 20. The memory controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 receives commands CMD and addresses ADDR from the host HOST. The command generator 110 can decode the commands CMD received from the host HOST to generate access commands, row hammer refresh commands, and the like, and can provide the access commands and row hammer refresh commands to the memory device 20 via the device interface 130. The access command may be a signal instructing the memory device 20 to write or read data by accessing a row of the memory cell array 220 corresponding to the address ADDR. The row hammer refresh command may be a signal instructing the memory device 20 to perform an additional refresh operation on word lines adjacent to word lines that have been frequently accessed within a short period of time. In other words, the additional refresh operation may be performed on word lines adjacent to word lines that have been accessed multiple times within a short period of time.

[0091] The address generator 120 in the memory controller 10 can generate a row address and a column address to be accessed in the memory cell array 220 by decoding the address ADDR received from the host interface 140. In addition, the memory device 20 can generate an address of a memory bank to be accessed when the memory cell array 220 includes a plurality of memory banks.

[0092] In addition, the memory controller 10 may control memory operations such as writing and reading by providing various signals to the memory device 20 via the device interface 130. For example, the memory controller 10 may provide a write command to the memory device 20. The write command is used to instruct the memory device 20 to perform a write operation to store data in the memory device 20.

[0093] In some embodiments, the memory device 20 includes a memory cell array 220 and a peripheral circuit 210. The memory cell array 220 includes a plurality of memory banks, each memory bank includes a plurality of memory blocks, each memory block includes a plurality of memory cell rows and a plurality of memory cell columns, each memory cell row is coupled to a corresponding word line, and each memory cell column is coupled to a corresponding bit line. The peripheral circuit 210 can write data to or read data from the memory cell array 220 based on a command CMD and an address ADDR received from the memory controller 10, or can provide a control signal CTRL for refreshing memory cells included in the memory cell array 220 to a row decoding circuit and a column decoding circuit. In other words, the peripheral circuit 210 can perform all operations to process the data in the memory cell array 220. The peripheral circuit 210 may include: a control circuit corresponding to each memory block, such as a sensing amplifier (SA) and a word-line driver (WLD), a control circuit corresponding to each memory bank, such as a row decoding circuit and a column decoding circuit, and a control circuit corresponding to all memory banks, such as a command buffer, a command decoder, an address buffer, a data input / output buffer, a mode register, etc.

[0094] The memory device 20 may be a random access memory (RAM), such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc. The following description only uses DRAM as an example.

[0095] Figure 2A is a block diagram of an exemplary SSD / UFS according to an embodiment of the present application. Here, the SSD / UFS can be understood as a type of memory system in Figure 1 . In this example, DRAM can be used as a buffer memory.

[0096] As shown in FIG2A , the SSD / UFS 30′ may include an SSD / UFS controller 10′, a buffer memory 20′, and a non-volatile memory 40. The SSD / UFS controller 10′ may provide a physical connection between the host HOST and the SSD / UFS 30′. Specifically, the SSD / UFS controller 10′ may provide an interface between the host HOST and the SSD / UFS 30′ according to the host's bus format. The SSD controller 10′ may decode commands provided by the host HOST. Based on the decoded results, the SSD / UFS controller 10′ may access the non-volatile memory 40. The buffer memory 20′ may temporarily store write data provided by the host HOST or data read from the non-volatile memory 40. When the host HOST issues a read request, if data in the non-volatile memory 40 is cached, the buffer memory 20′ may support a caching function for directly providing the cached data to the host HOST. The data transfer rate via the host's bus format (e.g., SATA or SAS) is much higher than the data transfer rate of the memory channel of the SSD / UFS 30′. That is, when the host's interface speed is significantly higher, performance degradation due to the speed difference can be minimized by providing a high-capacity buffer memory 20'. Furthermore, the buffer memory 20' can store an address mapping table for the non-volatile memory 40. The buffer memory 20' can include, but is not limited to, DRAM. The non-volatile memory 40 can be provided as a storage medium for the SSD / UFS 30'. The non-volatile memory 40 can include, but is not limited to, a NAND memory.

[0097] FIG2B is a block diagram illustrating the composition of an exemplary memory according to an embodiment of the present application; here, the memory can be understood as a type of memory system in FIG1 , and in this example, DRAM can be used as a storage medium.

[0098] As shown in FIG2B , the memory 30 ′′ can be easily attached or installed to the electronic device or removed from the electronic device 1 through the interface shown. The memory 30 ′′ may include a plurality of volatile memories 20 ′′ (e.g., DRAM) and a memory controller 10 ′′. The memory module memory 30 ′′ can be used to write data, store data, retrieve (or read) data, and / or erase data under the control of the computer's processor. In some embodiments, the controller memory controller 10 ′′ can communicate with the DRAM using at least one communication protocol or technical standard typically associated with, for example, a dual in-line memory module (DIMM), a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), an unregistered DIMM (UDIMM), or the like.

[0099] It should be noted that the buffer memory 20 ′ in FIG. 2A and the volatile memory 20 ″ in FIG. 2B are both an application scenario of the memory device 20 in FIG. 1 , and may also be applicable to other application scenarios, which are not limited here.

[0100] FIG3 is a schematic diagram of the composition structure of an exemplary dynamic random access memory according to an embodiment of the present application; FIG4 is a schematic diagram of the connection relationship between word lines, bit lines and memory cells of an exemplary dynamic random access memory according to an embodiment of the present application.

[0101] The right side of Figure 3 shows the circuit of the memory cell in the DRAM. DRAM includes at least one DRAM chip (die). Each DRAM chip includes a memory cell array. The memory cell array includes multiple memory cells 201 arranged in an array. Each memory cell 201 includes a transistor T (Tran sistor) and a capacitor C (Capacitor). The main working principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array and can be regarded as a typical mesh structure. The mesh structure can be specifically referred to in Figure 4. The memory cell array uses rows (Row) and columns (Column) to specify addresses. By specifying the intersection of rows and columns (by specifying the row address and column address of the DRAM), the memory controller can independently access each memory cell in the DRAM chip and read, write, or refresh the data stored therein.

[0102] The left side of Figure 3 shows the memory cell array and some peripheral circuits in a DRAM. It should be noted that the row decoder circuit selects a word line to select the row of memory cells to be accessed in response to the address input to the row decoder circuit. The row decoder circuit decodes the input address and enables (activates) the word line corresponding to the decoded address. The column decoder circuit selects one or more bit lines to input the user's output data to the portion of the row of memory cells corresponding to the selected word line.

[0103] Figure 5A is a diagram illustrating the layout of a memory cell array and peripheral circuits in an exemplary memory device according to an embodiment of the present application; Figure 5B is a top-down schematic diagram illustrating the layout of a memory cell array and peripheral circuits in an exemplary memory device according to an embodiment of the present application; and Figure 5C is a top-down schematic diagram illustrating the layout of memory blocks and column decoding circuits in an exemplary memory bank according to an embodiment of the present application.

[0104] As shown in FIG5A , the memory cell array 220 and the peripheral circuit 210 are arranged in parallel. More specifically, the memory cell array includes M memory banks, each memory bank includes N memory blocks, and at least one side of each memory block is provided with a control circuit corresponding to the memory block. At least one side of each memory bank is provided with a control circuit corresponding to the memory bank. Every K memory banks in the M memory banks form a memory bank row, and the M memory banks form M / K memory bank rows. Peripheral circuits corresponding to all memory banks are provided between the middle two memory bank rows. It should be noted that M, N, and K are all positive integers, and M is an integer multiple of K.

[0105] For example, as shown in FIG5B , the memory cell array 220 includes 16 memory banks Bank0-Bank15, each of which includes multiple memory blocks Block. Each memory block Block is surrounded by corresponding memory blocks SA and WLD. Column decoding circuits and row decoding circuits corresponding to the memory bank are provided on both sides of each memory bank. Every four memory banks form a memory bank row, and 16 memory banks form four memory bank rows. Control circuits corresponding to all memory banks are provided between the two middle memory bank rows. It should be noted that the number of memory banks and the positional relationship of the circuits in FIG5B are for illustrative purposes only and are not intended to limit the number of memory banks and the positional relationship of the circuits in the memory of this application.

[0106] As shown in Figure 5C, each storage body Bank includes multiple rows of storage blocks Block and multiple columns of storage blocks Block. Each column of storage blocks corresponds to a column decoding circuit (corresponding to YDEC in Figure 5C). The column decoding circuit is configured to receive a column address signal, directly decode the column address signal or perform a first-level decoding, and output a column selection signal. The column selection signal indicates that the corresponding bit line in the selected storage block is enabled. The column decoding circuit is arranged on one side of the corresponding column memory block, and the column decoding circuit is connected to each memory block in the corresponding column through the column address transmission line. For example, if a column includes multiple memory blocks, each memory block is selected as a whole, and each memory block includes 64 bit lines, then the column decoding circuit needs to be coupled to the 64 bit lines of each memory block in the corresponding column through 64 column address transmission lines; if a column includes multiple memory blocks, each memory block is selected in a block manner (such as two blocks on the left and right), and each block includes 64 bit lines, then the column decoding circuit needs to be coupled to the 64 bit lines of each of the left and right blocks of each memory block in the corresponding column through 128 column address transmission lines (Y128:0> in Figure 5C shows the case of 128 column address lines). Since the column address transmission line here spans the entire column memory block, the span length is relatively long, so it is also called a long column address transmission line.

[0107] Furthermore, data also needs to be connected to each memory block in a column via a data transmission line. As shown in FIG5C , data is connected to each memory block in a column via a data transmission line pair DL<31:0> / DL_n<31:0>, i.e., 64 data transmission lines. It is understandable that, with the current increasingly high storage density requirements, the area of ​​the memory cell array is relatively small, and the area of ​​each column of memory blocks is also very small. If each column of memory blocks needs to be connected to a large number of address transmission and data transmission lines, such as 128 column address transmission lines and 64 data transmission lines for each column of memory blocks as shown in FIG5C , and a structure is required to prevent transmission line crosstalk, then it is difficult to layout the column address transmission lines and the data transmission lines on the same metal layer (or wiring layer), such as the column address transmission lines being arranged on the fourth metal layer and the data transmission lines being arranged on the fifth metal layer (FIG5C uses solid and dashed lines to indicate that the column address transmission lines and the data transmission lines are not on the same metal layer). Not locating the column address and data transmission lines on the same metal layer can lead to delay mismatches between the column address and data signals, as well as large variations in PVT (Process Voltage Temperature). This can be improved in some embodiments by adding trimming bits, such as compensation circuits, but mismatches between circuit and routing delays still exist.

[0108] Based on this, in each embodiment of the present application, the total number of column address transmission lines is reduced by improving the column decoding circuit from single-stage decoding to multi-stage decoding, and area savings are achieved by reasonably setting the positions of decoders at each stage.

[0109] An embodiment of the present application provides a memory device, comprising: a memory cell array and a peripheral circuit coupled to the memory cell array; wherein,

[0110] The memory cell array includes at least one memory block, wherein the memory block is provided with multiple rows of word lines and multiple columns of bit lines, and memory cells coupled between the word lines and the bit lines;

[0111] The peripheral circuit includes a column decoding circuit coupled to the plurality of column bit lines. The column decoding circuit is configured to receive a column address signal, perform multi-stage decoding on the column address signal, and output a column selection signal indicating that a corresponding bit line in the storage block is enabled.

[0112] Here, the memory device can be understood with reference to the memory device in FIG. 1 . In some specific embodiments, the memory device 20 is a dynamic random access memory. The following description uses a DRAM as an example. The specific structure of the DRAM can be understood with reference to the DRAM structure shown in FIG. 3 .

[0113] In some implementations, a column decoding circuit (also referred to as a column decoder) is coupled to the bit lines in the memory cell array via a sense amplifier circuit (also referred to as a sense amplifier). The column decoding circuit may include multiple stages of decoding circuits that together decode the column address signal, i.e., instruct the corresponding bit lines in the memory block to be enabled. The multiple stages may include two, three, or more stages. In some specific embodiments, the column decoding circuit includes two stages of decoding circuits.

[0114] It is understandable that the two-stage decoding circuit can reduce the number of column address transmission lines without adding too many circuits and causing too much burden of increased area.

[0115] In some embodiments, the column decoding circuit includes: a first-stage column decoding circuit including a first input interface and a first output interface; the first input interface at least receives a column address signal, and the first output interface outputs a preliminary column decoding signal; the number of transmission lines corresponding to the column address signal is less than the number of transmission lines corresponding to the preliminary column decoding signal;

[0116] The second-stage column decoding circuit includes a second input interface and a second output interface; the second input interface is coupled to the first-stage column decoding circuit to receive the preliminary column decoding signal; the second output interface is coupled to multiple bit lines in the storage block to output a column decoding signal, wherein the column decoding signal indicates that one bit line among the multiple bit lines of the storage block is enabled, and the number of transmission lines corresponding to the preliminary column decoding signal is less than the number of transmission lines corresponding to the column decoding signal.

[0117] Here, the first-stage column decoding circuit and the second-stage column decoding circuit are cascaded in series, the first output interface of the first-stage column decoding circuit is coupled to the second input interface of the second-stage column decoding circuit, and the second output interface of the second-stage column decoding circuit is coupled to multiple bit lines in the memory block. Each column of memory blocks in each memory bank in the memory device corresponds to a column decoding circuit, and each column decoding circuit includes a first-stage decoding circuit and one or more second-stage column decoding circuits. In some embodiments, the number of second-stage column decoding circuits included in each column decoding circuit is the same as the number of memory blocks included in a column of memory blocks in the memory bank. Exemplarily, the number of memory blocks included in a column of memory blocks in the memory bank is 64, and the number of second-stage column decoding circuits included in each column decoding circuit is also 64, and each second-stage column decoding circuit corresponds one-to-one to one memory block in a column of memory blocks.

[0118] In some embodiments, the memory cell array includes a plurality of memory banks, each of the memory banks includes a plurality of row memory blocks and a plurality of column memory blocks;

[0119] Each of the memory banks corresponds to a plurality of the first-stage column decoding circuits and a plurality of the second-stage column decoding circuits, each of the first-stage column decoding circuits corresponds to a column of memory blocks, and each of the second-stage column decoding circuits corresponds to a memory block in a column of memory blocks;

[0120] The second input interface of each second-stage column decoding circuit is coupled to the first-stage column decoding circuit, and the second output interface is coupled to multiple bit lines of one of the memory blocks. The column decoding signal indicates that the corresponding bit line in the selected memory block is enabled.

[0121] Here, the first output interface of the first-stage column decoding circuit needs to be coupled to the second input interfaces of all second-stage column decoding circuits. The second-stage column decoding circuits are arranged corresponding to the memory blocks and are arranged next to the second-stage column decoding circuits. Therefore, the first address transmission line between the first output interface of the first-stage column decoding circuit and the second input interfaces of all second-stage column decoding circuits spans the entire column of memory blocks. The span is relatively long, similar to the length of the long column address transmission line mentioned above.

[0122] It should be noted that the number of the first address transmission lines needs to be represented to each bit line in the memory block. If the number of bit lines in each memory block is M, and the address signal on each address transmission line can be a high logic level "1" or a low logic level "0", then 2 N =M, it can be seen that at least M bit lines can be represented by N address transmission lines, where M and N are both positive integers. For example, if each memory block is selected as a whole, each memory block includes 64 bit lines, and the number of first address transmission lines is 16; if each memory block is selected separately in a block manner (such as two left and right blocks), each block includes 64 bit lines, and the number of first address transmission lines is 24. It can be seen that compared with the aforementioned 64 and 128 long column address transmission lines, the 16 and 24 first address transmission lines in this embodiment have greatly reduced the number of lines, which will be beneficial to saving area, so that all column address transmission lines and data transmission lines corresponding to a column of memory blocks are arranged on the same metal layer.

[0123] Here, the second output interface of the second-stage column decoding circuit needs to be coupled to all bit lines in a memory block. Therefore, the number of second address transmission lines between the second output interface of each second-stage column decoding circuit and each bit line in the memory block is related to the number of bit lines in each memory block. For example, if each memory block is selected as a whole and each memory block includes 64 bit lines, the number of second address transmission lines is 64; if each memory block is selected separately in blocks (such as left and right blocks), and each block includes 64 bit lines, the number of second address transmission lines is 128.

[0124] It should be noted that since the second-stage column decoding circuit is arranged corresponding to the memory block and is arranged next to the second-stage column decoding circuit, the length spanned by the second address transmission line is not long. The second address transmission line here is not the same as the aforementioned long address transmission line.

[0125] In some embodiments, each first-stage column decoding circuit is disposed on one side of a corresponding column storage block. The first-stage column decoding circuit may be disposed on one side of the corresponding column storage block along a direction in which the column storage blocks extend.

[0126] The second-stage column decoding circuit needs to be arranged near the corresponding memory block. There are multiple ways to arrange the position of the second-stage column decoding circuit. Two examples are given below.

[0127] In some embodiments, as shown in FIG6A , the first-stage column decoding circuit (corresponding to YDEC_1st in FIG6A ) of each column memory block is disposed on one side of the corresponding column memory block, and the second-stage column decoding circuit (corresponding to YDEC_2nd in FIG6A ) is disposed in parallel on one side of the corresponding memory block. For ease of wiring, the second-stage column decoding circuit can be disposed on the side of the memory block where the sense amplifier circuit SA is disposed. Considering that, for example, the SA may be disposed on both sides of a memory block as shown in FIG5B , when disposing the second-stage column decoding circuit, each second-stage column decoding circuit can also be designed to be split into two to accommodate the SA (this scenario is not shown in FIG6A ).

[0128] In the case where the second-stage column decoding circuit and the corresponding memory block are arranged in parallel, the overall structure of the corresponding memory device can refer to the structures shown in the aforementioned FIG. 5A and FIG. 5B .

[0129] In other embodiments, as shown in FIG6B , the first-level column decoding circuit (corresponding to YDEC_1st in FIG6B ) of each column storage block is disposed on one side of the corresponding column storage block, and the second-level column decoding circuit (corresponding to YDEC_2nd in FIG6B ) and the corresponding storage block are stacked. Specifically, the second-level column decoding circuit may be located above the corresponding storage block, or the storage block may be located above the corresponding second-level column decoding circuit.

[0130] It should be noted that FIG. 6A and FIG. 6B are merely schematic diagrams of the relative positions of the second-stage column decoding circuit and the corresponding memory block, and are not intended to limit the specific location of the second-stage column decoding circuit.

[0131] In some embodiments, the memory includes a plurality of address transmission lines and a plurality of data transmission lines;

[0132] The first-stage column decoding circuit corresponding to a column of storage blocks is connected to the second-stage column decoding circuit corresponding to each storage block in the column of storage blocks through the plurality of address transmission lines;

[0133] Each memory block in the column of memory blocks is connected to the data transmission line;

[0134] The plurality of address transmission lines and the plurality of data transmission lines are arranged on the same metal layer.

[0135] As previously mentioned, the first address transmission lines between the first output interface of each first-stage column decoder circuit and the second input interfaces of all second-stage column decoder circuits significantly reduce the length of the previously mentioned long column address transmission. As shown in FIG6A or FIG6B , the first address transmission lines between the first output interface of each first-stage column decoder circuit and the second input interfaces of all second-stage column decoder circuits are reduced from 128 as shown in FIG5C to 24 AY<23:0> lines. These lines can be arranged on the same metal layer as the 64 data transmission lines DL<31:0> / DL_n<31:0>. For example, the first address transmission lines and the data transmission lines are both arranged on the fifth metal layer. In FIG6A and FIG6B , AY<23:0> and DL<31:0> / DL_n<31:0> are both illustrated with solid lines to indicate that they are located on the same metal layer. It can be understood that when the address transmission lines and the data transmission lines are arranged on the same metal layer, the problem of column address and data signal asynchrony within the block can be improved, and the impact of PVT can be reduced by adding a compensation circuit.

[0136] In the case where the second-stage column decoding circuit and the corresponding memory block are arranged in a stacked manner, the overall structural layout of the memory device needs to be adjusted accordingly.

[0137] In some embodiments, the memory cell array is disposed on a first semiconductor structure, and the peripheral circuit is disposed on a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked and electrically connected by bonding;

[0138] Each of the first-stage column decoding circuits is disposed on one side of a corresponding column storage block;

[0139] Each second-stage column decoding circuit and the sensing amplifier circuit and word line driving circuit corresponding to each memory block are located at the position of the orthographic projection of a corresponding memory block on the plane where the second semiconductor structure is located.

[0140] 7A is a schematic diagram showing the distribution of a memory cell array and peripheral circuits in an exemplary memory according to another embodiment of the present application; FIG. 7B is a top-down schematic diagram showing the distribution of a memory cell array and peripheral circuits in an exemplary memory according to another embodiment of the present application.

[0141] 7A , the first semiconductor structure 100 is located above the second semiconductor structure 200 . The first semiconductor structure 100 includes a memory cell array 220 , and the second semiconductor structure 200 includes a peripheral circuit 210 .

[0142] It should be noted that the first semiconductor structure corresponding to FIG. 7A in FIG. 7B is located above the second semiconductor structure, and the structure corresponding to the solid line in FIG. 7B is located within the first semiconductor structure, while the structure corresponding to the dashed line is located within the second semiconductor structure. For ease of understanding, the structure within the second semiconductor structure is shown in perspective. That is, in the enlarged view corresponding to each memory block in FIG. 7B , the solid line represents the enlarged portion of the memory block, while the dashed line represents the structure within the second semiconductor structure directly below the memory block.

[0143] For example, as shown in FIG7B , memory cell array 220 includes 16 memory banks, Bank0-Bank15, each of which includes multiple memory blocks, Block. A sense amplifier circuit SA, a second-stage column decoder circuit YDEC_2nd, and a connection circuit, Conjunction, between the sense amplifier circuit SA and the second-stage column decoder circuit YDEC_2nd are disposed directly below each memory block, and a word line driver is disposed directly below the gap between two adjacent memory blocks along the direction in which a row of memory blocks extends. In some embodiments, the word line driver may include an odd word line driver Odd WLD and an even word line driver Even WLD, with the odd word line driver Odd WLD and the even word line driver Even WLD respectively disposed on either side of the memory block.

[0144] It should be noted that the positions of the sense amplifier circuit SA, the second-stage column decoder circuit YDEC_2nd, the connection circuit Conjunction, the odd word line driver Odd WLD, and the even word line driver Even WLD in FIG. 7B are for illustration only and are not intended to limit the positions of the corresponding circuits in the memory of this application.

[0145] In some specific embodiments, the bonding methods of the memory cell array 220 and the peripheral circuit 210 include but are not limited to hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, etc.

[0146] When the memory device is stacked in a bonded manner, the newly added circuits in the embodiments of the present application, such as the secondary address decoding circuit and SA, WLD, and other related circuits, can be placed under the memory cell array. Due to the stacked configuration, the newly added circuits do not incur additional area costs.

[0147] The specific circuit implementation of each decoding circuit in the two-stage decoding circuit will be introduced in detail below.

[0148] In some embodiments, the column address signal includes multi-bit data; the first-stage column decoding circuit 231 includes:

[0149] The first decoding circuit 2311 is configured to decode a plurality of consecutive low-bit data in the column address signal to obtain a first decoding signal;

[0150] The second decoding circuit 2312 is configured to decode the remaining multiple consecutive high-bit data in the column address signal to obtain a second decoding signal; the first decoding signal and the second decoding signal are configured to jointly form the preliminary column decoding signal.

[0151] Here, the column address signal is a signal representing the column address information. In some specific embodiments, the column address signal is multi-bit binary data, and the number of bits of the column address signal is related to the number of bit lines included in the memory block. If the number of bit lines in each memory block is M and the column address signal is N-bit binary data, then 2 N = M. For example, if each memory block includes 64 bit lines, the column address signal may be 6-bit binary data.

[0152] Considering the generally large number of bit lines, a single decoding circuit may not be sufficient. Therefore, a first decoding circuit 2311 and a second decoding circuit 2312 are used to decode different portions of consecutive data bits in the column address signal, respectively. These two decoded signals then form the output of the first-stage decoding circuit 231. In one specific embodiment, the first decoding circuit 2311 and the second decoding circuit 2312 are responsible for decoding the same data bits. For example, as shown in FIG8A , the column address signal AY_9_4_<9:4> is 6-bit binary data. The first decoding circuit 2311 decodes the lower three bits AY_9_4_<6:4> of the column address signal, while the second decoding circuit 2312 decodes the upper three bits AY_9_4_<9:7> of the column address signal.

[0153] In some embodiments, the first decoding circuit 2311 and the second decoding circuit 2312 may each include one or more decoders, such as a 2-4 decoder or a 3-8 decoder. In some specific embodiments, the first decoding circuit 2311 and the second decoding circuit 2312 may each include one or more 3-8 decoders. Using different combinations of 3-8 decoders can achieve decoding of different data bits.

[0154] For example, as shown in FIG8B , the column address signal is 6-bit binary data, and the first decoding circuit 2311 and the second decoding circuit 2312 are both 3-8 decoders. The two 3-8 decoders can implement 6-16 bit decoding.

[0155] Exemplarily, the column address signal is 12-bit binary data, the first decoding circuit 2311 and the second decoding circuit 2312 are both two 3-8 decoders, each two 3-8 decoders can achieve 6-16 bit decoding, and four 3-8 decoders can achieve 12-32 bit decoding.

[0156] For example, the column address signal is 4-bit binary data. The first decoding circuit 2311 and the second decoding circuit 2312 are each a 3-8 decoder. The two 3-8 decoders each decode 2 of the 4 bits into 4 bits (discarding some bits), thereby implementing 4-8-bit decoding. Alternatively, the first decoding circuit 2311 and the second decoding circuit 2312 can each be a 2-4 decoder. The two 2-4 decoders can implement 4-8-bit decoding.

[0157] In some embodiments, the first-stage column decoding circuit 231 further includes: a synchronization control signal generating circuit 2314 configured to generate a synchronization control signal, wherein a clock period corresponding to the synchronization control signal is smaller than a clock period corresponding to the first decoding signal and the second decoding signal;

[0158] The second input interface of the second-stage column decoding circuit 232 also receives the synchronization control signal. The second-stage column decoding circuit 232 is configured to output the column decoding signal in response to the enable state of the synchronization control signal and the normal output of the first decoding signal and the second decoding signal.

[0159] To synchronize the timing of the first-stage column decoding circuit 231 and the second-stage decoding circuit, a synchronization control signal generating circuit 2314 is provided to enforce timing constraints, as shown in FIG8A . The clock period corresponding to the synchronization control signal is shorter than the clock periods corresponding to the first decoding signal and the second decoding signal. In some specific embodiments, the clock period corresponding to the synchronization control signal is half the clock period corresponding to the first decoding signal and the second decoding signal.

[0160] For example, as shown in FIG8B , the synchronization control signal generating circuit 2314 can be a square wave signal generating circuit. The waveform diagram of the synchronization control signal can refer to Ypulse shown in FIG8C . FIG8B also shows a schematic diagram of a synchronization control signal generating circuit 2341. As shown in FIG8B , the synchronization control signal generating circuit 2341 can include an inverter, a delay circuit, and an XOR gate. The input of the inverter receives a clock signal AY_CLK, where the clock period of the clock signal can be the same as the clock period corresponding to the first decoding signal and the second decoding signal. The output of the inverter is connected to the input of the delay circuit, and the delay circuit is configured to delay the clock signal, for example, by half a period. The first input of the XOR gate is connected to the output of the delay circuit, the second input of the XOR gate receives the clock signal, and the output of the XOR gate outputs the synchronization control signal.

[0161] As shown in FIG8C , the period of the preliminary column decoding signals AY_6_4_BUF<7:0> and AY_9_7_BUF<7:0> is narrowed under the action of the synchronization control signal Ypulse. This is manifested as the period of the column decoding signal AY_Y<63:0> is narrowed to half the period of the preliminary column decoding signals AY_6_4_BUF<7:0> and AY_9_7_BUF<7:0>, which means that the synchronization control signal plays a role in timing constraint.

[0162] It should be noted that FIG8B only provides an example of a synchronous control signal generating circuit, and is not intended to limit the specific circuit of the synchronous control signal generating circuit in the embodiment of the present application.

[0163] It is understood that the column decoding circuit includes a first-stage column decoding circuit and a second-stage column decoding circuit. The second-stage column decoding circuit adds synchronization control operations. The consistency of column address and data timing in the memory block facilitates timing coordination for high-speed operation.

[0164] In some embodiments, the second-stage column decoding circuit 232 is specifically configured to receive the synchronization control signal and the semiconductor element enable signal, and when both the synchronization control signal and the storage block enable signal are enabled, the output column decoding signal will select and enable the bit line corresponding to the enabled data bit of the preliminary column decoding signal in the storage block; when the storage block enable signal is enabled, it indicates that the storage block is selected.

[0165] Here, the second-stage column decoding circuit 232 is configured to receive the first decoding signal, the second decoding signal, the synchronization control signal, and the storage block enable signal, and perform operations on the first decoding signal, the second decoding signal, the synchronization control signal, and the storage block enable signal to obtain a decoding signal. For a bit line in a storage block, when the signal corresponding to the corresponding bit of the first decoding signal and the signal corresponding to the corresponding bit of the second decoding signal are both in an enabled state, and the synchronization control signal and the storage block enable signal are also in an enabled state, the decoding signal corresponding to the bit line is in an enabled state. In this case, the decoding signals corresponding to the remaining bit lines are in a disabled state. It should be noted that the enabled state and disabled state of the decoding signal referred to here can be understood as the signal being at a certain logic level to indicate whether a bit line is activated or deactivated.

[0166] The specific circuit components of the second-stage column decoding circuit 232 can be seen in FIG8B . It should be noted that FIG8B only shows one second-stage column decoding circuit 232. As previously described, there is a corresponding second-stage column decoding circuit 232 for each memory block, and each second-stage column decoding circuit is connected to the output of the first-stage column decoding circuit. Different memory blocks have different corresponding memory block enable signals. For example, for a selected memory block, its corresponding memory block enable signal is a high logic level "1," while for an unselected memory block, its corresponding memory block enable signal is a ground logic level "0."

[0167] As shown in FIG8B , the second-stage column decoding circuit 232 includes circuits shown in dashed boxes, which have the same number as the bit lines. The circuits shown in the dashed boxes include one NOR gate and two NAND gates, wherein a first input of one NAND gate receives a storage block enable signal, and a second input receives a signal on a data bit of a first decoded signal in a preliminary column decoding signal corresponding to the bit line; a first input of another NAND gate receives a synchronous control operation signal lypulse corresponding to the synchronous control signal (here, the synchronous control operation signal lypulse is obtained by an AND logic operation of the synchronous control signal Ypulse and the storage block enable signal Blk_en), and a second input receives a signal on a data bit of a second decoded signal in the preliminary column decoding signal corresponding to the bit line; the outputs of the two NAND gates are connected to the input of the NOR gate, and the output of the NOR gate outputs a column decoding signal, wherein each data bit of the column decoding signal corresponds to a bit line.

[0168] It should be noted that in the embodiment of the present application, the number of circuits shown in the dashed boxes included in each second-stage column decoding circuit 232 is the same as the number of bit lines, and the input ends of the circuits shown in the dashed boxes respectively receive a combination signal of any data bit included in the first decoding signal and any data bit included in the second decoding signal. For example, if the first decoding signal includes 8 bits of data and the second decoding signal includes 8 bits of data, there are 64 circuits shown in the dashed boxes, and the input of each circuit shown in the dashed boxes is a combination of any data bit in the 8 bits of data included in the first decoding signal and any data bit in the 8 bits of data included in the second decoding signal.

[0169] It should be noted that FIG8B only provides an example of the second-stage column decoding circuit 232 , and is not intended to limit the specific circuit of the second-stage column decoding circuit 232 in the embodiment of the present application.

[0170] In some embodiments, the first-stage column decoding circuit 231 further includes: a driving circuit 2315 , the driving circuit 2315 including a plurality of drivers;

[0171] Each driver is connected to one of the plurality of transmission lines corresponding to the first decoded signal and the second decoded signal respectively, and is configured to perform power amplification processing on the decoded signal on the corresponding transmission line.

[0172] Here, as shown in Figure 8A, a driver can be set on each transmission line. Each transmission line can include a first address transmission line between the first output interface of each first-level column decoding circuit 231 and the second input interface of all second-level column decoding circuits, and can also include a transmission line for the synchronization control signal generated by the synchronization control signal generating circuit 2314.

[0173] In some specific embodiments, as shown in 8B, the driver may include an even number of inverters cascaded in series, and the specific number may be two, four or more. The driver can be used to increase the transmission power to avoid or improve the problem of transmission failure caused by too long a transmission line or excessive power loss.

[0174] It can be understood that since the driver 2315 is provided corresponding to each transmission line, when the address transmission lines are reduced in the embodiment of the present application, the number of drivers can also be reduced, thereby reducing the overall circuit area.

[0175] The memory blocks in the aforementioned column decoding circuit 230 are selected or unselected as a whole. In some embodiments, the memory blocks can also be selected by region, or called block selection. The following describes the specific implementation of the column decoding circuit 230 for the memory blocks selected by region.

[0176] In some embodiments, the memory block includes a first region and a second region, and the number of bit lines arranged in the first region and the second region are the same;

[0177] The first-stage column decoding circuit 231 further includes: a third decoding circuit 2313 , a first region selection circuit 2316 , and a second region selection circuit 2317 ;

[0178] A third decoding circuit 2313 is configured to decode the remaining plurality of consecutive high-bit data in the column address signal to obtain a third decoding signal; the third decoding signal is the same as the second decoding signal;

[0179] The first region selection circuit 2316 is connected to the second decoding circuit 2312 and is configured to output the second decoding signal when the first region enable signal is enabled;

[0180] The second region selection circuit 2317 is connected to the third decoding circuit 2313 and is configured to output the third decoding signal when the second region enable signal is enabled; the first region enable signal / second region enable signal being enabled indicates that the first region / second region of the storage block is selected.

[0181] In some embodiments, the first-stage column decoding circuit 231 further includes: a buffer 2318;

[0182] The buffer 2318 is connected to the first decoding circuit and is configured to adjust the timing of the first decoding signal to synchronize with the output signals of the first region selection circuit and the second region selection circuit.

[0183] As shown in FIG9A , the first-stage column decoding circuit 231 may further include a third decoding circuit 2313, a first region selection circuit 2316, and a second region selection circuit 2317. The third decoding circuit 2313 may replicate the second decoding circuit 2312, specifically decoding the upper three bits AY_9_4_<9:7> of the column address signal. The specific implementation of the third decoding circuit 2313 can also be understood with reference to the aforementioned second decoding circuit 2312.

[0184] The first region selection circuit 2316 and the second region selection circuit 2317 are respectively used to select a storage block region. The first region selection circuit 2316 is connected to the second decoding circuit 2312 and is configured such that when the first region enable signal is in the enabled state, the second decoding signal is continuously transmitted through the first region selection circuit 2316; when the first region enable signal is in the disabled state, the second decoding signal transmits a fixed logic level, such as a signal with all data bits being "0". The second region selection circuit 2317 is connected to the third decoding circuit 2313 and is configured such that when the second region enable signal is in the enabled state, the third decoding signal is continuously transmitted through the second region selection circuit 2317; when the second region enable signal is in the disabled state, the third decoding signal transmits a fixed logic level, such as a signal with all data bits being "0".

[0185] In some specific embodiments, as shown in Figure 9B, the first region selection circuit 2316 and the second region selection circuit 2317 may each include two NAND gates in a cascade relationship in series, wherein a first input terminal of one NAND gate is connected to the output terminal of the second decoding circuit 2312 or the output terminal of the third decoding circuit 2313, and a second input terminal receives a partition enable signal, which indicates that the storage block supports selection of partitioned regions when the partition enable signal is enabled; a first input terminal of the other NAND gate is connected to the output terminal of the previous NAND gate, and a second input terminal receives the partition enable signal, which indicates that the storage block supports selection of partitioned regions when the partition enable signal is enabled, and an output terminal of the other NAND gate outputs a second decoding signal or a third decoding signal.

[0186] After adding the first region selection circuit 2316 and the second region selection circuit 2317, in order to match the timing of the branch circuit where the first decoding circuit 2311 is located with the second decoding circuit 2312 and the third decoding circuit 2313, it is necessary to add a buffer 2318 as shown in Figure 9A to the branch circuit where the first decoding circuit 2311 is located.

[0187] In some specific embodiments, as shown in FIG9B , the buffer 2318 may include a NAND gate and an inverter in a cascade relationship, wherein a first input terminal of the NAND gate is connected to an output terminal of the first decoding circuit 2311, a second input terminal receives a fixed logic level signal, such as VDD2H, i.e., a high logic level "1", and an output terminal is connected to an input terminal of the inverter, and the input terminal of the inverter normally outputs the first decoding signal.

[0188] It should be noted that the output terminals of the buffer 2318 , the first region selection circuit 2316 , and the second region selection circuit 2317 may be connected to the input terminals of the aforementioned driving circuit for power amplification.

[0189] It should be noted that the second-stage column decoding circuit 232 also requires corresponding adjustments. As shown in FIG9B , the circuit in the dashed box in FIG8B needs to be replicated for each partition of the memory block, and the corresponding input signals are different for different partitions. Specifically, the input ends of the circuit shown in the dashed box corresponding to the first region receive a combination signal of any data bit included in the first decoded signal and any data bit included in the second decoded signal; the input ends of the circuit shown in the dashed box corresponding to the second region receive a combination signal of any data bit included in the first decoded signal and any data bit included in the third decoded signal.

[0190] Exemplarily, the first area of ​​the storage block includes 64 bit lines, and the second area of ​​the storage block includes 64 bit lines; the column address signal is 6-bit binary data, and the preliminary column decoding signal corresponds to 24 transmission lines, wherein the first decoding signal includes 8-bit data, the second decoding signal includes 8-bit data, and the third decoding signal also includes 8-bit data; then there are 128 circuits shown in the dotted boxes, and the input of the circuit shown in each dotted box corresponding to the first area is a combination of any data bit in the 8-bit data included in the first decoding signal and any data bit in the 8-bit data included in the second decoding signal; the input of the circuit shown in each dotted box corresponding to the second area is a combination of any data bit in the 8-bit data included in the first decoding signal and any data bit in the 8-bit data included in the third decoding signal.

[0191] In the embodiment of the present application, the column decoding circuit includes a first-level column decoding circuit and a second-level column decoding circuit, with an additional post-column address decoding circuit (second-level column decoding circuit) that transmits the last decoded column address (second-level column decoding circuit) to each block. Synchronization control is also added to the second-level column decoding circuit. As such, the decoding circuit provided in the embodiment of the present application can significantly reduce the number of long column address lines and can use the same metal layer to transmit column addresses and data. Furthermore, column addresses and data are synchronized within the memory block, reducing the impact of PVT and facilitating timing coordination for high-speed operation.

[0192] Furthermore, when the memory device is stacked using a bonding method, the newly added circuits in the embodiments of the present application, such as the secondary address decoding circuit and SA, WLD, and other related circuits, can be placed below the memory cell array. Because the memory cells and peripheral circuits are stacked, the column address and data match more closely, and the newly added circuits do not incur additional area costs.

[0193] An embodiment of the present application further provides a memory system, including:

[0194] One or more memory devices as provided in the embodiments of the present application; and

[0195] A memory controller is coupled to the memory device and controls the memory device.

[0196] Here, the internal composition of the memory system can be understood by referring to the aforementioned FIG. 1 , and some application scenarios of the memory system can be understood by referring to the aforementioned FIG. 2A and FIG. 2B , which will not be repeated here.

[0197] The embodiment of the present application further provides a decoding circuit, comprising:

[0198] The first-stage decoding circuit includes a first input interface and a first output interface; the first input interface receives at least a signal to be decoded, and the first output interface outputs a preliminary decoded signal; the number of transmission lines corresponding to the signal to be decoded is less than the number of transmission lines corresponding to the preliminary decoded signal;

[0199] The second-stage decoding circuit includes a second input interface and a second output interface; the second input interface is coupled to the first-stage decoding circuit to receive the preliminary decoding signal; the second output interface is coupled to multiple structures to be selected in the semiconductor element to output a decoding signal, wherein the decoding signal indicates that one of the structures to be selected in the semiconductor element is enabled, and the number of transmission lines corresponding to the preliminary decoding signal is less than the number of transmission lines corresponding to the decoding signal.

[0200] Here, the decoding circuit is not limited to the column decoding circuit of the aforementioned memory, and may be a decoding circuit of other electronic devices, which is used to perform decoding processing to indicate a structure to be selected in a semiconductor element included in the electronic device.

[0201] It should be noted that the first-level decoding circuit here can be understood with reference to the aforementioned first-level column decoding circuit, the second-level decoding circuit here can be understood with reference to the aforementioned second-level column decoding circuit, and the signal to be decoded can be understood with reference to the aforementioned column address signal; the semiconductor element can be understood with reference to the aforementioned storage block, and the structure to be selected can be understood with reference to the aforementioned bit line.

[0202] In some embodiments, the number of the second-stage decoding circuits includes a plurality, and each second-stage decoding circuit corresponds to a semiconductor element;

[0203] The second input interface of each second-stage decoding circuit is coupled to the first-stage decoding circuit, and the second output interface is coupled to multiple structures to be decoded of one semiconductor element. The decoding signal indicates that the corresponding structure to be decoded in the selected semiconductor element is enabled.

[0204] In some embodiments, the signal to be decoded includes multi-bit data; the first-stage decoding circuit includes:

[0205] A first decoding circuit is configured to decode a plurality of consecutive low-bit data in the signal to be decoded to obtain a first decoded signal;

[0206] The second decoding circuit is configured to decode the remaining multiple consecutive high-bit data in the signal to be decoded to obtain a second decoded signal; the first decoded signal and the second decoded signal are configured to jointly form the preliminary decoded signal.

[0207] In some embodiments, the first-stage decoding circuit further includes: a synchronization control signal generating circuit configured to generate a synchronization control signal, wherein a clock period corresponding to the synchronization control signal is smaller than a clock period corresponding to the first decoding signal and the second decoding signal;

[0208] The second input interface of the second-level decoding circuit also receives the synchronization control signal, and the second-level decoding circuit is configured to output the decoding signal in response to the enable state of the synchronization control signal and the normal output of the first decoding signal and the second decoding signal.

[0209] In some embodiments, the second-stage decoding circuit is specifically configured to receive the synchronization control signal and the semiconductor element enable signal, and when both the synchronization control signal and the semiconductor element enable signal are enabled, the output decoding signal will select and enable the to-be-selected structure in the semiconductor element corresponding to the enabled data bit of the preliminary decoding signal; when the semiconductor element enable signal is enabled, it indicates that the semiconductor element is selected.

[0210] In some embodiments, the first stage decoding circuit further includes: a driving circuit, the driving circuit including a plurality of drivers;

[0211] Each driver is connected to one of the plurality of transmission lines corresponding to the first decoded signal and the second decoded signal respectively, and is configured to perform power amplification processing on the decoded signal on the corresponding transmission line.

[0212] In some embodiments, the first stage decoding circuit further includes: a third decoding circuit, a first region selection circuit, and a second region selection circuit;

[0213] a third decoding circuit configured to decode the remaining plurality of consecutive high-bit data in the signal to be decoded to obtain a third decoded signal; the third decoded signal is the same as the second decoded signal;

[0214] The first region selection circuit is connected to the second decoding circuit and is configured to output the second decoding signal when the first region enable signal is enabled;

[0215] The second region selection circuit is connected to the third decoding circuit and is configured to output the third decoding signal when the second region enable signal is enabled; the first region enable signal / the second region enable signal being enabled indicates that the first region / the second region of the semiconductor element is selected.

[0216] In some embodiments, the first stage decoding circuit further comprises: a buffer;

[0217] The buffer is connected to the first decoding circuit and is configured to perform timing adjustment on the first decoding signal so as to be synchronized with output signals of the first region selection circuit and the second region selection circuit.

[0218] In some embodiments, the first region selection circuit / the second region selection circuit includes: a first NAND gate, a second NAND gate;

[0219] One input end of the first NAND gate is connected to the output of the second decoding circuit / the third decoding circuit, and the other input end is used to receive a partition enable signal; when the partition enable signal is enabled, it indicates that the semiconductor element supports selection by region;

[0220] One input end of the second NAND gate is connected to the output end of the first NAND gate, the other input end is used to receive the first region enable signal / the second region enable signal, and the output end is connected to the first output interface.

[0221] The specific components of the first-stage decoding circuit here can be understood by referring to the specific components of the first-stage column decoding circuit mentioned above. The specific components of the second-stage decoding circuit here can be understood by referring to the specific components of the second-stage column decoding circuit mentioned above.

[0222] In some embodiments, the signal to be decoded includes a column address signal; the transmission line includes an address transmission line; the semiconductor element includes a memory block, the plurality of structures to be selected include a plurality of bit lines; and the decoding signal indicates selection of one of the plurality of bit lines.

[0223] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0224] The above description is only a preferred embodiment of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made using the contents of the present application description and drawings under the inventive concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A memory device, comprising: a memory cell array and a peripheral circuit coupled to the memory cell array; wherein, the memory cell array includes at least one memory block, the memory block is provided with multiple rows of word lines and multiple columns of bit lines, and memory cells coupled between the word lines and the bit lines; the peripheral circuit includes a column decoding circuit; the column decoding circuit is coupled to the multiple columns of bit lines, and the column decoding circuit is configured to receive a column address signal, perform multi-stage decoding on the column address signal, and output a column selection signal, the column selection signal indicating enabling a corresponding bit line in the memory block.

2. The memory device according to claim 1, wherein, the column decoding circuit includes: a first-stage column decoding circuit, including a first input interface and a first output interface; the first input interface receives at least the column address signal, and the first output interface outputs a preliminary column decoding signal; the number of transmission lines corresponding to the column address signal is less than the number of transmission lines corresponding to the preliminary column decoding signal; a second-stage column decoding circuit, including a second input interface and a second output interface; the second input interface is coupled to the first-stage column decoding circuit and receives the preliminary column decoding signal; the second output interface is coupled to multiple bit lines in the memory block and outputs a column decoding signal, the column decoding signal indicating enabling one of the multiple bit lines in the memory block, and the number of transmission lines corresponding to the preliminary column decoding signal is less than the number of transmission lines corresponding to the column decoding signal.

3. The memory device according to claim 2, the memory cell array includes multiple memory banks, each memory bank includes a plurality of rows of memory blocks and a plurality of columns of memory blocks; each memory bank corresponds to multiple first-stage column decoding circuits and multiple second-stage column decoding circuits, each first-stage column decoding circuit corresponds to a column of memory blocks, and each second-stage column decoding circuit corresponds to one memory block in a column of memory blocks; the second input interface of each second-stage column decoding circuit is coupled to the first-stage column decoding circuit, and the second output interface is coupled to multiple bit lines of one memory block, and the column decoding signal indicates enabling the corresponding bit line in the selected memory block.

4. The memory device according to claim 2 or 3, wherein, the column address signal includes multiple bits of data; the first-stage column decoding circuit includes: a first decoding circuit configured to perform decoding processing on multiple consecutive low-order bits of data in the column address signal to obtain a first decoding signal; a second decoding circuit configured to perform decoding processing on the remaining multiple consecutive high-order bits of data in the column address signal to obtain a second decoding signal; the first decoding signal and the second decoding signal are configured to jointly form the preliminary column decoding signal.

5. The memory device according to claim 4, wherein, the first-stage column decoding circuit further includes: a synchronous control signal generation circuit configured to generate a synchronous control signal, and the clock period corresponding to the synchronous control signal is less than the clock periods corresponding to the first decoding signal and the second decoding signal; The second input interface of the second - stage column decoding circuit also receives the synchronization control signal, and the second - stage column decoding circuit is configured to output the column decoding signal in response to the enabling state of the synchronization control signal and the normal output of the first decoding signal and the second decoding signal.

6. The memory device according to claim 5, wherein, the second - stage column decoding circuit is specifically configured to receive the synchronization control signal and the semiconductor element enabling signal, and when both the synchronization control signal and the memory block enabling signal are enabled, the output column decoding signal will enable the bit lines corresponding to the enabled data bits in the selected memory block in the preliminary column decoding signal; when the memory block enabling signal is enabled, it indicates that the memory block is selected.

7. The memory device according to claim 4, wherein, the first - stage column decoding circuit further includes: a driving circuit, and the driving circuit includes a plurality of drivers; each driver is connected to one of the plurality of transmission lines corresponding to the first decoding signal and the second decoding signal respectively, and is configured to perform power amplification processing on the decoding signal on the corresponding transmission line.

8. The memory device according to claim 4, wherein, the memory block includes a first area and a second area, and the number of bit lines provided in the first area and the second area is the same; the first - stage column decoding circuit further includes: a third decoding circuit, a first area selection circuit, and a second area selection circuit; the third decoding circuit is configured to perform decoding processing on the remaining multiple consecutive high - order data in the column address signal to obtain a third decoding signal; the third decoding signal is the same as the second decoding signal; the first area selection circuit is connected to the second decoding circuit and is configured to output the second decoding signal when the first area enabling signal is enabled; the second area selection circuit is connected to the third decoding circuit and is configured to output the third decoding signal when the second area enabling signal is enabled; when the first area enabling signal / second area enabling signal is enabled, it indicates that the first area / second area of the memory block is selected.

9. The memory device according to claim 8, wherein, the first - stage column decoding circuit further includes: a buffer; the buffer is connected to the first decoding circuit and is configured to adjust the timing of the first decoding signal to be synchronized with the output signals of both the first area selection circuit and the second area selection circuit.

10. The memory device according to claim 8, wherein, the column address signal is 6 - bit binary data, the preliminary column decoding signal corresponds to 24 transmission lines, the first area of the memory block includes 64 bit lines, and the second area of the memory block includes 64 bit lines.

11. The memory device according to claim 3, wherein, the memory includes a plurality of address transmission lines and a plurality of data transmission lines; the first - stage column decoding circuit corresponding to a column of memory blocks is connected to the second - stage column decoding circuit corresponding to each memory block in the column of memory blocks through the plurality of address transmission lines; each memory block in the column of memory blocks is connected to the data transmission lines; The multiple address transmission lines and the multiple data transmission lines are disposed in the same metal layer.

12. The memory device according to claim 3, wherein, the memory cell array is disposed on a first semiconductor structure, and the peripheral circuit is disposed on a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked and electrically connected by bonding; each of the first-stage column decoding circuits is disposed on one side of a corresponding column memory block; each of the second-stage column decoding circuits, the sense amplifier circuit corresponding to each memory block, and the word line driver circuit are all located at a position of a positive projection of a corresponding memory block on the plane where the second semiconductor structure is located.

13. The memory device according to any one of claims 1 to 12, wherein, the memory device includes a dynamic random access memory.

14. A memory system, comprising: one or more memory devices according to any one of claims 1 to 13; and a memory controller coupled to the memory device and controlling the memory device.

15. A decoding circuit, comprising: a first-stage decoding circuit including a first input interface and a first output interface; the first input interface receives at least a signal to be decoded, and the first output interface outputs a preliminary decoded signal; the number of transmission lines corresponding to the signal to be decoded is less than the number of transmission lines corresponding to the preliminary decoded signal; a second-stage decoding circuit including a second input interface and a second output interface; the second input interface is coupled to the first-stage decoding circuit and receives the preliminary decoded signal; the second output interface is coupled to a plurality of structures to be selected in a semiconductor element and outputs a decoded signal, the decoded signal indicating enabling one of the structures to be selected in the semiconductor element, and the number of transmission lines corresponding to the preliminary decoded signal is less than the number of transmission lines corresponding to the decoded signal.

16. The decoding circuit according to claim 15, wherein, the number of the second-stage decoding circuits includes a plurality, and each second-stage decoding circuit corresponds to a semiconductor element; the second input interface of each second-stage decoding circuit is coupled to the first-stage decoding circuit, and the second output interface is coupled to a plurality of structures to be decoded in a semiconductor element, and the decoded signal indicates enabling the corresponding structure to be decoded in the selected semiconductor element.

17. The decoding circuit according to claim 15 or 16, wherein, the signal to be decoded includes multiple-bit data; the first-stage decoding circuit includes: a first decoding circuit configured to perform decoding processing on multiple consecutive low-order data in the signal to be decoded to obtain a first decoded signal; a second decoding circuit configured to perform decoding processing on the remaining multiple consecutive high-order data in the signal to be decoded to obtain a second decoded signal; the first decoded signal and the second decoded signal are configured to jointly form the preliminary decoded signal.

18. The decoding circuit according to claim 17, wherein, ​ The first - stage decoding circuit further includes: a synchronization control signal generation circuit configured to generate a synchronization control signal, and a clock period corresponding to the synchronization control signal is less than clock periods corresponding to the first decoding signal and the second decoding signal; A second input interface of the second - stage decoding circuit further receives the synchronization control signal, and the second - stage decoding circuit is configured to output the decoding signal in response to an enabling state of the synchronization control signal and normal outputs of the first decoding signal and the second decoding signal.

19. The decoding circuit according to claim 18, wherein, The second - stage decoding circuit is specifically configured to receive the synchronization control signal and a semiconductor element enabling signal, and when both the synchronization control signal and the semiconductor element enabling signal are enabled, the output decoding signal will enable a to - be - selected structure corresponding to an enabled data bit of the preliminary decoding signal in the selected semiconductor element; when the semiconductor element enabling signal is enabled, it indicates that the semiconductor element is selected.

20. The decoding circuit according to claim 17, wherein, The first - stage decoding circuit further includes: a driving circuit, and the driving circuit includes a plurality of drivers; Each driver is connected to one transmission line among a plurality of transmission lines respectively corresponding to the first decoding signal and the second decoding signal, and is configured to perform power amplification processing on the decoding signal on the corresponding transmission line. amplification.

21. The decoding circuit according to claim 17, wherein, The first - stage decoding circuit further includes: a third decoding circuit, a first area selection circuit, and a second area selection circuit; The third decoding circuit is configured to perform decoding processing on the remaining plurality of consecutive high - order data in the to - be - decoded signal to obtain a third decoding signal; the third decoding signal is the same as the second decoding signal; The first area selection circuit is connected to the second decoding circuit and is configured to output the second decoding signal when a first area enabling signal is enabled; The second area selection circuit is connected to the third decoding circuit and is configured to output the third decoding signal when a second area enabling signal is enabled; when the first area enabling signal / second area enabling signal is enabled, it indicates that the first area / second area of the semiconductor element is selected.

22. The decoding circuit according to claim 21, wherein, The first - stage decoding circuit further includes: a buffer; The buffer is connected to the first decoding circuit and is configured to perform timing adjustment on the first decoding signal to be synchronized with output signals of both the first area selection circuit and the second area selection circuit.

23. The decoding circuit according to claim 21, wherein, The first area selection circuit / second area selection circuit includes: a first NAND gate and a second NAND gate; One input terminal of the first NAND gate is connected to an output of the second decoding circuit / the third decoding circuit, and the other input terminal is used to receive a partition enabling signal; when the partition enabling signal is enabled, it indicates that the semiconductor element supports being selected by regions. One input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, and the other input terminal is used to receive the first region enable signal / the second region enable signal, and the output terminal is connected to the first output interface.

24. The decoding circuit according to claim 15, wherein, the signal to be decoded includes a column address signal; the transmission line includes an address transmission line; the semiconductor element includes a memory block, and the plurality of the to-be-selected structures include a plurality of bit lines; the decoding signal indicates to select one bit line from the plurality of bit lines.

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