Chip testing equipment and control method thereof

Abstract

The invention relates to the technical field of semiconductors, provides chip test equipment and a control method thereof, and is used for solving the technical problems of low cleaning efficiency of a test socket and long waiting time of a machine table. The chip testing equipment comprises a sorting device which comprises a first chamber used for accommodating a first carrying disc, and cleaning particles are arranged on the first carrying disc; the testing device comprises a second cavity and a testing socket, the second cavity is used for accommodating the second carrying disc, and the testing device is used for being electrically connected with a to-be-tested chip located on the second carrying disc through the testing socket and executing testing operation on the to-be-tested chip; the transmission part is used for transmitting the first carrying disc; and the control part is used for controlling the transmission part to move the first carrying disc from the first cavity to the second cavity where the test socket is located and controlling the first carrying disc to perform cleaning operation on the test socket when the test socket reaches a preset cleaning condition. Therefore, the cleaning efficiency of the test socket can be effectively improved, the waiting time of a machine table is shortened, and the productivity of the machine table is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a chip testing device and a control method thereof. Background Art

[0002] Before a chip is produced and shipped, various testing operations need to be carried out to ensure the quality and reliability of the chip. In the testing process of semiconductor manufacturing technology, the test socket, as a key interface connecting the testing device and the chip under test, is crucial for the accuracy and efficiency of the testing operation. However, after a certain number of tests, the test socket will be contaminated with foreign substances, and the main components of the foreign substances include tin slag, adhesive on the bumps or solder balls of integrated circuit products, and dust and fibers in the air. If not cleaned in time, these foreign substances will affect the testing operation of the chip, and further affect the accuracy of the testing parameters.

[0003] Currently, the cleaning operation of the test socket mostly relies on manual operation. The manual cleaning method not only consumes a large amount of manpower and time, has low cleaning efficiency, but also prolongs the waiting time of the machine tool, seriously affecting the overall production capacity of the machine tool. Therefore, how to improve the cleaning efficiency of the test socket, shorten the waiting time of the machine tool and improve the production capacity of the machine tool has become a technical problem to be solved urgently. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a chip testing device and a control method thereof.

[0005] To achieve the above object, the technical solution of the present disclosure is realized as follows: On the one hand, an embodiment of the present disclosure provides a chip testing device, including: a sorting device, including a first chamber for accommodating a first carrier, and cleaning particles are arranged on the first carrier; a testing device, including a second chamber and a test socket, the test socket is located in the second chamber, and the second chamber is used for accommodating a second carrier, and the testing device is used to electrically connect with the chip under test located on the second carrier through the test socket and perform a testing operation on the chip under test; a transmission component for transmitting the first carrier between the first chamber and the second chamber; a control unit for controlling the transmission component to move the first carrier from the first chamber to the second chamber and controlling the first carrier to perform a cleaning operation on the test socket when the test socket reaches a preset cleaning condition.

[0006] In some embodiments, the sorting device further includes a third chamber, which is arranged in sequence with the first chamber in the vertical direction, and an isolation door is arranged between the third chamber and the first chamber; specifically, the control unit is configured to control the isolation door to open and control the transfer component to transfer the first carrier from the first chamber to the second chamber via the isolation door and the third chamber when the test socket reaches the preset cleaning condition, and control the cleaning particles on the first carrier to perform the cleaning operation on the test socket.

[0007] In some embodiments, the third chamber is configured to perform a first heating operation on the second carrier where the chip that has completed the test operation at a first preset temperature, so as to raise the temperature of the second carrier and the chip to a second preset temperature; the first preset temperature is lower than -20°C, and the second preset temperature is higher than 0°C.

[0008] In some embodiments, the control unit is further configured to control the transfer component to transfer the first carrier from the second chamber to the first chamber via the third chamber and the isolation door and control the isolation door to close after the cleaning operation; a heating component is arranged in the first chamber, which is configured to perform a second heating operation on the first carrier that has completed the cleaning operation at a third preset temperature, so as to raise the temperature of the first carrier to a fourth preset temperature, wherein the third preset temperature is lower than -20°C, and the fourth preset temperature is higher than 0°C.

[0009] In some embodiments, the size of the cleaning particles matches the size of the chip to be tested; the arrangement of the cleaning particles on the first carrier is the same as the arrangement of the chips to be tested on the second carrier.

[0010] In some embodiments, the chip testing device further includes a pressing head; specifically, the control unit is configured to control the pressing head to descend to press the cleaning particles arranged on the first carrier against the test socket, so as to perform the cleaning operation on the test socket.

[0011] In some embodiments, the control unit is specifically configured to control the pressing head to rise to separate the cleaning particles arranged on the first carrier from the test socket after the cleaning operation.

[0012] In some embodiments, the transfer component includes a fixing plate, a lifting cylinder located below the fixing plate in the vertical direction and connected to the fixing plate, and a jaw component; the lifting cylinder is connected to the jaw component, and the lifting cylinder is configured to drive the opening and closing of the jaw component to grab or release the first carrier and lift and lower along the vertical direction.

[0013] In some embodiments, the transmission component further includes: a cam mechanism; sliders located on opposite sides of the cam mechanism in the horizontal direction; springs located between the sliders and the cam mechanism; the jaw component is connected to the fixed plate through the springs, the sliders and the cam mechanism; the cam mechanism is configured to control the jaw component to expand and contract relative to the fixed plate under the action of the springs and the sliders.

[0014] In some embodiments, the volume of the first chamber is smaller than the volume of the third chamber, and the sum of the volumes of the first chamber and the third chamber is equal to or substantially equal to the volume of the second chamber.

[0015] In some embodiments, the sorting device further includes a manipulator, and the manipulator is configured to sort the chips that pass the test and the chips that fail the test.

[0016] On the other hand, embodiments of the present disclosure also provide a control method for a chip testing device, and the control method includes: providing a sorting device, a testing device, and a transmission component; wherein, the sorting device includes a first chamber for accommodating a first carrier tray on which cleaning particles are provided; the testing device includes a second chamber and a testing socket located in the second chamber, and the second chamber is configured to accommodate a second carrier tray, and the testing device is configured to electrically connect to a chip to be tested located on the second carrier tray through the testing socket and perform a testing operation on the chip to be tested; the transmission component is configured to transfer the first carrier tray between the first chamber and the second chamber; controlling the testing socket in the testing device to perform a testing operation on the chip to be tested; when the testing socket reaches a preset cleaning condition, controlling the transmission component to move the first carrier tray from the first chamber to the second chamber and controlling the first carrier tray to perform a cleaning operation on the testing socket.

[0017] In some embodiments, the sorting device further includes a third chamber, the third chamber and the first chamber are arranged in sequence in the vertical direction and an isolation door is provided between the third chamber and the first chamber; the control method further includes: when the testing socket reaches the preset cleaning condition, controlling the isolation door to open and controlling the transmission component to move the first carrier tray from the first chamber through the isolation door and the third chamber to the second chamber, and controlling the cleaning particles on the first carrier tray to perform the cleaning operation on the testing socket.

[0018] In some embodiments, the control method further includes: when the isolation door is closed, performing a first heating operation on the second carrier on which the chip that has completed the test operation at a first preset temperature is located, so as to raise the temperature of the second carrier and the chip to a second preset temperature; wherein, the first preset temperature is lower than -20°C, and the second preset temperature is higher than 0°C.

[0019] In some embodiments, the control method further includes: after the cleaning operation, controlling the transfer component to transfer the first carrier from the second chamber to the first chamber via the third chamber and the isolation door and controlling the isolation door to close; performing a second heating operation on the first carrier that has completed the cleaning operation at a third preset temperature, so as to raise the temperature of the first carrier to a fourth preset temperature, wherein, the third preset temperature is lower than -20°C, and the fourth preset temperature is higher than 0°C.

[0020] Embodiments of the present disclosure provide a chip testing device and its control method. In the embodiments of the present disclosure, by providing a first chamber in the sorting device and using the first chamber to accommodate a first carrier, and cleaning particles are provided on the first carrier. When the test socket reaches the preset cleaning condition, the control unit of the chip testing device can automatically control the transfer component to move the first carrier from the first chamber to the second chamber, and control the first carrier to perform a cleaning operation on the test socket. On the one hand, online automatic cleaning of the test socket is realized, which not only significantly saves manpower and time, but also effectively shortens the waiting time of the machine, thereby greatly improving the production capacity of the machine. On the other hand, it effectively avoids the adverse impact of foreign matter contamination on the test socket on the chip testing operation, and further improves the accuracy and efficiency of the testing operation. On the third hand, it ensures that the conditions of each cleaning operation are consistent, thereby avoiding the problem of unstable cleaning effect caused by differences in manual cleaning techniques. Description of the Drawings

[0021] In the drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed according to the present disclosure, and should not be regarded as a limitation on the scope of the present disclosure.

[0022] Figure 1A One of the schematic diagrams of the manual cleaning operation process of the test socket provided for an exemplary embodiment; Figure 1B Two of the schematic diagrams of the manual cleaning operation process of the test socket provided for an exemplary embodiment; Figure 1C Three of the schematic diagrams of the manual cleaning operation process of the test socket provided for an exemplary embodiment; Figure 2 Schematic structural diagram of a chip testing device provided by an embodiment of the present disclosure; Figure 3 One of the process schematic diagrams of a control method for a chip testing device provided by an embodiment of the present disclosure; Figure 4 Another one of the process schematic diagrams of a control method for a chip testing device provided by an embodiment of the present disclosure; Figure 5 Another one of the process schematic diagrams of a control method for a chip testing device provided by an embodiment of the present disclosure; Figure 6 Another one of the process schematic diagrams of a control method for a chip testing device provided by an embodiment of the present disclosure; Figure 7 One of the process schematic diagrams of a control method for a chip testing device provided by another embodiment of the present disclosure; Figure 8 Another one of the process schematic diagrams of a control method for a chip testing device provided by another embodiment of the present disclosure; Figure 9 Process schematic diagram of a control method for a chip testing device provided by another embodiment of the present disclosure; Figure 10 Process schematic diagram of a cleaning operation provided by an embodiment of the present disclosure; Figure 11 For Figure 10 Enlarged schematic diagram of the structure within the dashed circular frame in Figure 12 Flow schematic diagram of a control method for a chip testing device provided by an embodiment of the present disclosure. Detailed implementation manners

[0023] Next, in combination with the embodiments of the present disclosure and the accompanying drawings, the technical solutions in the embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0024] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some well-known technical features are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0025] In the drawings, for the sake of clarity, the dimensions of layers, regions, elements and their relative dimensions may be exaggerated. Throughout the drawings, the same reference numerals indicate the same elements.

[0026] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer or portion discussed below may be referred to as the second element, component, region, layer or portion. And when discussing the second element, component, region, layer or portion, it does not imply that a first element, component, region, layer or portion necessarily exists in the present disclosure.

[0027] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0028] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0029] To thoroughly understand the present disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other embodiments.

[0030] In the manual cleaning operation of the test socket, the staff usually uses tape and, by pressing with the thumb or with the assistance of a manual tool, adheres the tape to the surface of the test socket to remove foreign objects. Figures 1A to 1C FIG. is a schematic diagram of the manual cleaning operation process of the test socket provided for an exemplary embodiment. The following will be described by way of example in conjunction with Figures 1A to 1C for illustrative purposes.

[0031] As Figure 1A shown, the test socket 102 includes a first insulating layer 104 and a plurality of conductive particles 106. Exemplarily, the material of the first insulating layer 104 includes, but is not limited to, silicone resin, and the conductive particles 106 can be implemented by a single conductive metal material such as iron, copper, zinc, chromium, nickel, silver, cobalt, aluminum, or an alloy of two or more of these metal materials. In the test operation of the chip, the test socket 102 contacts the printed circuit board (PCB) 100 of the test device and the chip to be tested (not shown) respectively through the plurality of conductive particles 106.

[0032] As Figure 1A and Figure 1B shown, when performing a manual cleaning operation on the test operation, the staff usually uses the tape 110 and, by pressing with the thumb or with the assistance of a manual tool, adheres the tape 110 to the surface of the test socket 102 so that the tape 110 adheres to the foreign objects 108 on the surface of the test socket 102.

[0033] As Figure 1C shown, the tape 110 is separated from the test socket 102 so that the foreign objects 108 on the surface of the test socket 102 are removed by the tape 110.

[0034] The above-mentioned manual cleaning operation has many problems. First of all, the manual cleaning method results in too long downtime of the test device. When performing a cleaning operation on the test socket, the downtime of the test device is as long as 4 to 5 hours, which greatly reduces the Overall Equipment Effectiveness (OEE) of a single device and seriously affects the production capacity and production efficiency of the equipment. Secondly, the instability of the manual cleaning operation has a negative impact on the performance of the test socket and the accuracy of the test. During the cleaning operation, it is difficult to quantify the techniques of manually attaching and peeling the tape, and manual deviation is likely to occur. This inconsistency leads to the cleaning effect not meeting the expectations, further affecting the performance of the test socket and the accuracy of the test, and increasing the uncertainty of the test results. Finally, in order to avoid the rapid aging of the performance of the test socket caused by rapid temperature changes, complex temperature control operations are required. For example, when switching from the test operation to the cleaning operation, in order to avoid the rapid aging of the performance of the test socket caused by the temperature change value being greater than 150°C and the change rate exceeding 1°C / min, it is necessary to forcibly turn off the temperature control system of the sorting device to reduce the temperature of the test socket area from the working temperature to room temperature. In addition, when the temperature of the test socket area is relatively low (such as -30°C), it is also necessary to first heat it up to a preset temperature (such as 105°C) and maintain it for a certain period of time (such as 40 min - 60 min) to eliminate moisture, and then cool it down to room temperature. These temperature control operations not only consume time, but also increase the maintenance cost and operation complexity of the equipment, further reducing the production efficiency.

[0035] Based on one or more of the above technical problems, the embodiments of the present disclosure provide a chip testing device and a control method therefor.

[0036] It should be noted that, for the convenience of description, the directions that may be used in the following description are defined first. In the plane perpendicular to the carrier plate (the first carrier plate or the second carrier plate), the vertical direction (Z direction) is defined, and in the plane parallel to the tray, the horizontal directions (such as the intersecting X direction and Y direction) are defined. The X direction, Y direction, and Z direction can be perpendicular to each other in pairs.

[0037] Figure 2 is a schematic structural diagram of a chip testing device provided by an embodiment of the present disclosure, as Figure 2As shown in the figure, the chip testing device includes: a sorting device 208, including a first chamber 210 for accommodating a first carrier plate on which cleaning particles are provided; a testing device 202, including a second chamber 204 and a testing socket 206 located in the second chamber 204, and the second chamber 204 is for accommodating a second carrier plate, and the testing device 202 is used to electrically connect to a chip to be tested located on the second carrier plate through the testing socket 206 and perform a testing operation on the chip to be tested; a transmission component 214 for transmitting the first carrier plate between the first chamber 210 and the second chamber 204; a control unit 216 for controlling the transmission component 214 to move the first carrier plate from the first chamber 210 to the second chamber 204 and controlling the first carrier plate to perform a cleaning operation on the testing socket 206 when the testing socket 206 reaches a preset cleaning condition.

[0038] In some embodiments, the preset cleaning condition may be when a preset time interval (such as two weeks) is reached, or when the test result of the testing device 202 performing a test on the chip to be tested is lower than a preset test yield rate. The preset cleaning condition can be selected according to actual needs, and the embodiments of the present disclosure do not make specific limitations.

[0039] It should be noted that, in this embodiment, the control unit may include, but is not limited to, one of a Programmable Logic Controller (PLC), a Microcontroller Unit (MCU), or a Central Processing Unit (CPU), which can be selected according to actual needs.

[0040] In the embodiments of the present disclosure, by providing a first chamber in the sorting device and using the first chamber to accommodate a first carrier plate on which cleaning particles are provided. When the testing socket reaches the preset cleaning condition, the control unit of the chip testing device can automatically control the transmission component to move the first carrier plate from the first chamber to the second chamber and control the first carrier plate to perform a cleaning operation on the testing socket. On the one hand, on-line automatic cleaning of the testing socket is realized, which not only significantly saves manpower and time, but also effectively shortens the waiting time of the machine, thereby greatly improving the production capacity of the machine. On the second hand, it effectively avoids the adverse effect of foreign matter contamination on the testing socket on the chip testing operation, and further improves the accuracy and efficiency of the testing operation. On the third hand, it ensures that the conditions of each cleaning operation are consistent, thereby avoiding the problem of unstable cleaning effect caused by differences in manual cleaning techniques.

[0041] In some embodiments, such as Figure 2As shown, the sorting device 208 further includes a third chamber 212. The third chamber 212 and the first chamber 210 are arranged in sequence in the vertical direction, and an isolation door 218 is provided between the third chamber 212 and the first chamber 210. Specifically, the control unit 216 is configured to control the isolation door 218 to open and control the transfer component 214 to transfer the first carrier from the first chamber 210 to the second chamber 204 via the isolation door 218 and the third chamber 212 when the test socket 206 reaches the preset cleaning condition, and control the cleaning particles on the first carrier to perform a cleaning operation on the test socket 206.

[0042] In some embodiments, the control unit 216 is coupled to the isolation door 218. Exemplarily, the control unit 216 realizes the opening and closing of the isolation door 218 by controlling the valve on the isolation door 218.

[0043] In some embodiments, the duration of the cleaning operation is 5 min - 10 min. More specifically, the duration of each cleaning operation can be 5 min, 6 min, 7 min, 8 min, 9 min, or 10 min.

[0044] In some embodiments, as Figure 2 shown, the chip testing device further includes a fourth chamber 220. Exemplarily, the fourth chamber 220 serves as a preheating chamber, which can preheat the chips to be tested to a temperature close to the test temperature in advance, reduce the temperature fluctuation in the second chamber, shorten the test preparation time, and improve the test efficiency and accuracy.

[0045] In some embodiments, the first carrier and the second carrier are compatible. In other words, the first carrier and the second carrier can share the same device interface, transfer system, and operation process. Specifically, the first carrier and the second carrier can be used in different chambers of the chip testing device without major modification or adjustment of the device. In this way, seamless switching between the first carrier and the second carrier in different operation stages (such as cleaning operation and testing operation) can be ensured, which can effectively improve the equipment utilization rate, simplify the operation process, reduce the equipment cost, improve the production efficiency, and enhance the flexibility.

[0046] In some embodiments, the sorting device further includes a manipulator, which is used to sort the chips that pass the test and the chips that fail the test.

[0047] In some embodiments, during the execution of the test operation, the path of the second carrier is the virtual path (a) and the virtual path (b). During the execution of the cleaning operation, the path of the first carrier is also the virtual path (a) and the virtual path (b).

[0048] In some embodiments, as Figure 2 and Figure 9As shown, during the execution of the test operation, the control unit 216 controls the transfer component 214 to move the idle second carrier tray out of the third chamber 212 to the loading / unloading area 213, the control unit 216 controls the manipulator to load the chip to be tested onto the second carrier tray and controls the transfer component 214 to move the second carrier tray loaded with the chip to be tested into the second chamber 204 via the fourth chamber 220. After the test operation, the control unit 216 controls the transfer component 214 to transfer the second carrier tray loaded with the chip to be tested into the third chamber 212, and controls the manipulator to sort the qualified chips and unqualified chips in the loading / unloading area 213.

[0049] In some embodiments, during the period other than the execution of the cleaning operation, the first carrier tray provided with cleaning particles is arranged in the first chamber. When the test socket reaches the preset cleaning condition, the control unit 216 controls the isolation door 218 to open and controls the transfer component 214 to transfer the first carrier tray from the first chamber 210 to the second chamber 204 via the isolation door 218, the third chamber 212 and the fourth chamber 220, and controls the cleaning particles on the first carrier tray to perform a cleaning operation on the test socket 206. After the cleaning operation, the control unit 216 controls the transfer component 214 to return the first carrier tray to the first chamber 210 via the third chamber 212 and the isolation door 218.

[0050] It should be noted that when the cleaning operation is performed, the first carrier tray passes through the loading / unloading area 213, but no loading or unloading operation is performed on the first carrier tray. In some embodiments, the type of the carrier tray can be detected as the first carrier tray or the second carrier tray provided with cleaning particles by setting a weight sensor in the loading / unloading area 213, so as to quickly identify and classify different types of carrier trays, avoid unnecessary loading or unloading operations on the first carrier tray and contamination of the chips to be tested, and improve the operation efficiency and reliability of the equipment.

[0051] In some embodiments, the third chamber 212 is used to perform a first heating operation on the second carrier tray where the chips that have completed the test operation at the first preset temperature are located when the isolation door 218 is closed, so as to raise the temperature of the second carrier tray and the chips to the second preset temperature; the first preset temperature is lower than -2℃, and the second preset temperature is higher than 0℃.

[0052] In some embodiments, when the temperature of the test operation is a low-temperature test at the first preset temperature, after the test operation, a first heating operation needs to be performed on the second carrier tray and the chips in the third chamber to protect the second carrier tray and the chips from the influence of thermal stress, avoid damaging the chips and extend the service life of the second carrier tray. Exemplarily, the first preset temperature can be -25℃, -30℃, -35℃ or -40℃, and the second preset temperature can be 10℃, 15℃, 20℃ or 25℃.

[0053] Exemplarily, the test operation can be a low temperature operating life (LTOL) test, which is used to verify the performance of the chip at extremely low temperatures (such as -40°C) and ensure its stability and reliability under extreme low temperature conditions. The first preset temperature is -40°C.

[0054] It should be noted that the selection of the second preset temperature needs to comprehensively consider the material characteristics of the chip, test requirements, and equipment compatibility. The specific second preset temperature needs to be adjusted according to the actual application.

[0055] In some embodiments, the control unit 216 is further configured to, after the cleaning operation, control the transfer component 214 to transfer the first carrier from the second chamber 204 to the first chamber 210 via the third chamber 212 and the isolation door 218 and control the isolation door 218 to close; a heating component is provided in the first chamber 210 for performing a second heating operation on the first carrier that has completed the cleaning operation at the third preset temperature to raise the temperature of the first carrier to the fourth preset temperature, where the third preset temperature is lower than -20°C and the fourth preset temperature is higher than 0°C.

[0056] In some embodiments, when the temperature of the cleaning operation is a low temperature test at the third preset temperature, a second heating operation needs to be performed on the first carrier in the first chamber after the cleaning operation to protect the first carrier from the influence of thermal stress and extend the service life of the first carrier. Exemplarily, the third preset temperature can be -25°C, -30°C, -35°C, or -40°C, and the fourth preset temperature can be 10°C, 15°C, 20°C, or 25°C.

[0057] In some embodiments, in order to reduce the thermal stress and energy consumption of the equipment, the ambient temperatures of the test operation and the cleaning operation are close to or equal to avoid too large a temperature difference between the cleaning operation and the test operation, so that the equipment needs to frequently adjust the temperature when switching.

[0058] Exemplarily, the first preset temperature is equal to the third preset temperature, and the second preset temperature is equal to the fourth preset temperature.

[0059] In some embodiments, the size of the cleaning particles matches the size of the chip to be tested; the arrangement pattern of the cleaning particles on the first carrier is the same as the arrangement pattern of the chip to be tested on the second carrier. In this way, the corresponding positions of the test socket and the chip to be tested in the test operation can be accurately positioned, thereby improving the cleaning operation efficiency, effectively improving the cleaning operation effect on the test socket, and ensuring the accuracy and reliability of the subsequent test operation.

[0060] In some embodiments, such as Figure 3 , Figure 4 ,Figure 5 and Figure 6 As shown in Figure 6 , the volume of the first chamber 210 is smaller than that of the third chamber 212. Exemplarily, the first chamber 210 is used to accommodate the first carrier 228, and the third chamber is used to accommodate the first carrier 228 and / or the second carrier 230. There are 4 carrier tracks 232 in 2 groups provided in the first chamber 210 for carrying the first carrier 228. There are 8 carrier tracks 234 in 4 groups provided in the third chamber 212 for carrying the first carrier 228 and / or the second carrier 230.

[0061] Setting the volume of the first chamber 210 to be smaller and specifically used to accommodate the first carrier 228 can save space and improve the overall compactness of the device. Setting the volume of the third chamber 212 to be larger can accommodate both the first carrier 228 and the second carrier 230 simultaneously, increasing the flexibility of the device, enabling adjustment of the use of the carriers as needed, and improving the flexibility and efficiency of the device.

[0062] In some embodiments, as Figure 2 shown, the sum of the volumes of the first chamber 210 and the third chamber 212 is equal to or substantially equal to the volume of the second chamber 204. In this way, an increase in the overall size of the chip testing device is avoided, ensuring the compactness and space utilization rate of the chip testing device.

[0063] It should be noted that the terms "equal" or "substantially equal" in this article should be understood as being equal within the allowable process error range. For example, the sum of the volumes of the first chamber 210 and the third chamber 212 being "equal" or "substantially equal" to the volume of the second chamber 204 should be understood as the sum of the volumes of the first chamber 210 and the third chamber 212 being equal in size to the volume of the second chamber 204, or, when there is a deviation within the allowable process error range between the sum of the volumes of the first chamber 210 and the third chamber 212 and the volume of the second chamber 204, it is also considered that the sum of the volumes of the first chamber 210 and the third chamber 212 is equal in size to the volume of the second chamber 204.

[0064] In some embodiments, as Figure 10 and Figure 11 shown, the chip testing device further includes a press head 236; the control unit 216 is specifically configured to control the press head 236 to descend to press a cleaning particle 240 provided on a first carrier (not shown) against the test socket 206, so that the cleaning particle 240 adheres to a foreign object 242 on the surface of the test socket 206 to perform a cleaning operation on the test socket 206.

[0065] In some embodiments, as Figure 10 and Figure 11 shown, the test socket 206 includes a second insulating layer 2061 and a plurality of probes 2062.

[0066] In some embodiments, the control unit 216 is specifically configured to, after the cleaning operation, control the ram 236 to rise to separate the cleaning particles 240 provided on the first carrier (not shown) from the test socket 206, so that the cleaning particles 240 carry away the foreign matter 242 on the surface of the test socket 206.

[0067] Here, the main components of the foreign matter 242 include solder dross, adhesive on the bumps or solder balls of integrated circuit products, as well as dust and fibers in the air, etc.

[0068] In some embodiments, the cleaning particles 240 adhere to the first surface of the adhesion layer 239 in the vertical direction, and the second surface of the adhesion layer 239 opposite to the first surface in the vertical direction adheres to the first carrier.

[0069] In some embodiments, as Figure 3 , Figure 4 , Figure 5 and Figure 6 shown, the transfer component 214 includes a fixed plate 222, a lifting cylinder 224 located below the fixed plate 222 in the vertical direction and connected to the fixed plate 222, and a jaw component 226; the lifting cylinder 224 is connected to the jaw component 226, and the lifting cylinder 224 is configured to drive the opening and closing of the jaw component 226 to grasp or release the first carrier and lift and lower in the vertical direction.

[0070] In some embodiments, the lifting cylinder 224 is a double-stroke cylinder.

[0071] As Figure 3 and Figure 4 shown, the first stroke of the lifting cylinder 224 is to descend in the vertical direction to the height of the first carrier 228 in the first chamber 210, the jaw component 226 closes to grasp the first carrier 228, and the control unit controls the isolation door 218 to open.

[0072] In some embodiments, the carrier track 232 in the first chamber 210 moves in the horizontal direction to disengage from the first carrier 228.

[0073] As Figure 4 and Figure 5 shown, the second stroke of the lifting cylinder 224 is to descend in the vertical direction to the top layer height in the third chamber 212, the jaw component 226 opens to release the first carrier 228 onto the carrier track 234.

[0074] As Figure 5 and Figure 6 shown, the jaw component 226 returns to the top layer height in the first chamber 210 along with the lifting cylinder 224 in the vertical direction, and the control unit controls the isolation door 218 to close.

[0075] In some embodiments, such as Figure 7 and Figure 8 shown, the transmission component 214 further includes: a cam mechanism 238; sliders 235 located on opposite sides of the cam mechanism 238 in the horizontal direction; a spring 237 located between the sliders 235 and the cam mechanism 238; the jaw component 226 is connected to the fixed plate 222 through the spring 237, the sliders 235 and the cam mechanism 238; the cam mechanism 238 is configured to control the telescopic movement of the jaw component 226 relative to the fixed plate 222 under the action of the spring 237 and the sliders 235.

[0076] Exemplarily, as Figure 8 shown, when the jaw component 226 needs to be closed, the cam mechanism 238 rotates to push the jaw component 226 to extend relative to the fixed plate 222 in the vertical direction, and at the same time, the elastic force after the spring 237 is stretched fixes the jaw component 226 to the cam mechanism 238.

[0077] Exemplarily, as Figure 7 shown, when the jaw component 226 needs to be opened to release the grasped carrier (such as the first carrier 228), the cam mechanism 238 rotates back to its original position, and the elastic force of the spring 237 pulls the jaw component 226 back to its original position.

[0078] It should be noted that the connection manner between the lifting cylinder and the fixed plate in the embodiments of the present disclosure is not limited to only Figure 7 and Figure 8 the connection manner between the lifting cylinder 224 and the fixed plate 222, nor is it limited to the connection manner shown in Figures 3 to 6 In fact, other connection manners that are not shown and can achieve the functions of the transmission component can also be adopted to ensure that in different application scenarios, the most suitable connection manner can be selected according to specific requirements, thereby improving the applicability and reliability of the device.

[0079] Figure 12 is a schematic flowchart of a control method for a chip testing device provided by an embodiment of the present disclosure. Referring to Figure 12 , the control method includes the following steps: Step S121: Provide a sorting device, a testing device, and a transmission component; Among them, the sorting device includes a first chamber for accommodating a first carrier on which cleaning particles are provided; the testing device includes a second chamber and a testing socket located in the second chamber, and the second chamber is for accommodating a second carrier, and the testing device is configured to electrically connect to a chip to be tested located on the second carrier through the testing socket and perform a testing operation on the chip to be tested; the transmission component is for transmitting the first carrier between the first chamber and the second chamber.

[0080] Step S122: Control the test socket in the test device to perform a test operation on the chip to be tested; Step S123: When the test socket reaches the preset cleaning condition, control the transfer component to move the first carrier from the first chamber to the second chamber and control the first carrier to perform a cleaning operation on the test socket.

[0081] For the structure and composition of the sorting device, test device, and transfer component of the chip testing equipment, reference can be made to the detailed introduction in the foregoing embodiments. For the sake of brevity, it will not be elaborated here. Figures 2 to 11 For the sake of brevity, it will not be elaborated here.

[0082] In some embodiments, as Figure 2 shown, the sorting device 208 further includes a third chamber 212. The third chamber 212 and the first chamber 210 are arranged in sequence along the vertical direction, and an isolation door 218 is provided between the third chamber 212 and the first chamber 210. The control method of the chip testing equipment further includes: when the test socket 206 reaches the preset cleaning condition, control the isolation door 218 to open and control the transfer component 214 to move the first carrier from the first chamber 210 through the isolation door 218 and the third chamber 212 to the second chamber 204, and control the cleaning particles on the first carrier to perform a cleaning operation on the test socket 206.

[0083] In some embodiments, during the execution of the test operation, the path of the second carrier is the virtual path (a) and the virtual path (b). During the execution of the cleaning operation, the path of the first carrier is also the virtual path (a) and the virtual path (b).

[0084] In some embodiments, as Figure 2 and Figure 9 shown, during the execution of the test operation, control the transfer component to move the idle second carrier out of the third chamber 212 to the loading / unloading area 213, control the manipulator to load the chip to be tested onto the second carrier, and control the transfer component to move the second carrier loaded with the chip to be tested into the second chamber 204 through the fourth chamber 220; control the test socket in the test device to perform a test operation on the chip to be tested; after the test operation, control the transfer component to transfer the second carrier loaded with the chip to be tested into the third chamber 212, and control the manipulator to sort the qualified chips and unqualified chips in the loading / unloading area 213.

[0085] In some embodiments, during periods other than the cleaning operation, a first carrier plate provided with cleaning particles is disposed in a first chamber. When the test socket reaches a preset cleaning condition, the isolation door 218 is controlled to open and the transfer component 214 is controlled to transfer the first carrier plate from the first chamber 210 to the second chamber 204 via the isolation door 218, the third chamber 212, and the fourth chamber 220, and the cleaning particles on the first carrier plate are controlled to perform a cleaning operation on the test socket 206. After the cleaning operation, the transfer component 214 is controlled to return the first carrier plate to the first chamber 210 via the third chamber 212 and the isolation door 218.

[0086] In some embodiments, the control method of the chip testing device further includes: when the isolation door 218 is closed, performing a first heating operation on a second carrier plate where a chip that has completed a test operation at a first preset temperature is located, so that the temperature of the second carrier plate and the chip rises to a second preset temperature; wherein, the first preset temperature is lower than -20°C and the second preset temperature is higher than 0°C.

[0087] In some embodiments, when the temperature of the test operation is a low-temperature test at the first preset temperature, after the test operation, a first heating operation needs to be performed on the second carrier plate and the chip in the third chamber to protect the second carrier plate and the chip from the influence of thermal stress, avoid damaging the chip, and extend the service life of the second carrier plate. Exemplarily, the first preset temperature can be -25°C, -30°C, -35°C, or -40°C, and the second preset temperature can be 10°C, 15°C, 20°C, or 25°C.

[0088] Exemplarily, the test operation can be a low-temperature aging test (LTOL) for verifying the performance of the chip at extremely low temperatures (such as -40°C) and ensuring its stability and reliability under extreme low-temperature conditions. The first preset temperature is -40°C.

[0089] In some embodiments, the control method of the chip testing device further includes: after the cleaning operation, controlling the transfer component to transfer the first carrier plate from the second chamber to the first chamber via the third chamber and the isolation door and controlling the isolation door to close; performing a second heating operation on the first carrier plate that has completed the cleaning operation at a third preset temperature, so that the temperature of the first carrier plate rises to a fourth preset temperature, wherein, the third preset temperature is lower than -20°C and the fourth preset temperature is higher than 0°C.

[0090] In some embodiments, when performing a low-temperature test at a third preset temperature during the cleaning operation, a second heating operation needs to be performed on the first carrier in the first chamber after the cleaning operation to protect the first carrier from thermal stress and extend its service life. Exemplarily, the third preset temperature can be -25°C, -30°C, -35°C or -40°C, and the fourth preset temperature can be 10°C, 15°C, 20°C or 25°C.

[0091] In some embodiments, to reduce the thermal stress and energy consumption of the equipment, the ambient temperature of the test operation and the cleaning operation is close to or equal to avoid excessive temperature differences between the cleaning operation and the test operation, and the equipment needs to frequently adjust the temperature when switching.

[0092] Exemplarily, the first preset temperature is equal to the third preset temperature, and the second preset temperature is equal to the fourth preset temperature.

[0093] In some embodiments, the duration of the cleaning operation is 5 min - 10 min. More specifically, the duration of each cleaning operation can be 5 min, 6 min, 7 min, 8 min, 9 min or 10 min.

[0094] The chip testing device used in the control method of the chip testing device provided by the embodiments of the present disclosure is the same as or similar to the chip testing devices in the foregoing embodiments. For the technical features not disclosed in detail in the embodiments of the present disclosure, please refer to the chip testing devices in the foregoing embodiments for understanding, and details are not described herein again.

[0095] The control method of the chip testing device provided by the embodiments of the present disclosure, on the one hand, realizes the on-line automatic cleaning of the test socket, which not only significantly saves manpower and time, but also effectively shortens the waiting time of the machine, thereby greatly improving the production capacity of the machine. On the other hand, it effectively avoids the adverse effects of foreign matter contamination on the test socket on the chip test operation, and further improves the accuracy and efficiency of the test operation. On the third hand, it ensures that the conditions of each cleaning operation are consistent, thereby avoiding the problem of unstable cleaning effect caused by differences in manual cleaning techniques.

[0096] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the "in one embodiment" or "in an embodiment" that appears throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitudes of the sequence numbers of the above processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The sequence numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0097] The above is only the preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. Any equivalent structural transformation made by using the content of the specification and drawings of the present disclosure under the inventive concept of the present disclosure, or directly / indirectly applied to other related technical fields, is included in the patent protection scope of the present disclosure.

Claims

1. A chip testing device, characterized in that, Comprising: A sorting device, including a first chamber for accommodating a first carrier tray, and cleaning particles are provided on the first carrier tray; A testing device, including a second chamber and a test socket located within the second chamber, and the second chamber is for accommodating a second carrier tray. The testing device is used to electrically connect to a chip under test located on the second carrier tray through the test socket and perform a testing operation on the chip under test; A transmission component for transmitting the first carrier tray between the first chamber and the second chamber; A control unit for controlling the transmission component to move the first carrier tray from the first chamber to the second chamber and controlling the first carrier tray to perform a cleaning operation on the test socket when the test socket reaches a preset cleaning condition.

2. The chip testing device according to claim 1, characterized in that The sorting device further includes a third chamber, the third chamber and the first chamber are arranged in sequence in the vertical direction, and an isolation door is provided between the third chamber and the first chamber; The control unit is specifically configured to control the isolation door to open and control the transmission component to transfer the first carrier tray from the first chamber to the second chamber via the isolation door and the third chamber when the test socket reaches the preset cleaning condition, and control the cleaning particles on the first carrier tray to perform the cleaning operation on the test socket.

3. The chip testing device according to claim 2, characterized in that, The third chamber is for performing a first heating operation on the second carrier tray where the chip that has completed the testing operation at a first preset temperature is located when the isolation door is closed, so as to raise the temperature of the second carrier tray and the chip to a second preset temperature; the first preset temperature is lower than -20°C, and the second preset temperature is higher than 0°C.

4. The chip testing device according to claim 2 or 3, characterized in that, The control unit is further used to control the transmission component to transfer the first carrier tray from the second chamber to the first chamber via the third chamber and the isolation door and control the isolation door to close after the cleaning operation; A heating component is provided in the first chamber for performing a second heating operation on the first carrier tray that has completed the cleaning operation at a third preset temperature, so as to raise the temperature of the first carrier tray to a fourth preset temperature, wherein the third preset temperature is lower than -20°C, and the fourth preset temperature is higher than 0°C.

5. The chip testing device according to any one of claims 1-3, characterized in that, The size of the cleaning particles matches the size of the chip under test; the arrangement pattern of the cleaning particles on the first carrier tray is the same as the arrangement pattern of the chips under test on the second carrier tray.

6. The chip testing device according to any one of claims 1-3, characterized in that, The chip testing device further includes a press head; The control unit is specifically configured to control the press head to descend to press the cleaning particles provided on the first carrier tray against the test socket to perform the cleaning operation on the test socket.

7. The chip testing device according to claim 6, wherein The control unit is specifically configured to control the press head to rise to separate the cleaning particles provided on the first carrier tray from the test socket after the cleaning operation.

8. The chip testing device according to any one of claims 1-3, characterized in that, The transmission component includes a fixed plate, a lifting cylinder located vertically below the fixed plate and connected to the fixed plate, and a gripper component; The lifting cylinder is connected to the jaw component, and the lifting cylinder is used to drive the opening and closing of the jaw component to grasp or release the first carrier tray and lift it along the vertical direction.

9. The chip testing device according to claim 8, wherein, The transfer component further includes: a cam mechanism; sliders located on opposite sides of the cam mechanism in the horizontal direction; springs located between the sliders and the cam mechanism; the jaw component is connected to the fixed plate through the springs, the sliders and the cam mechanism; The cam mechanism is used to control the telescopic movement of the jaw component relative to the fixed plate under the action of the springs and the sliders.

10. The chip testing device according to claim 2 or 3, characterized in that, The volume of the first chamber is smaller than the volume of the third chamber, and the sum of the volumes of the first chamber and the third chamber is equal to or substantially equal to the volume of the second chamber.

11. The chip testing device according to any one of claims 1-3, characterized in that, The sorting device further includes a manipulator, and the manipulator is used to sort the qualified chips and unqualified chips after testing.

12. A control method for a chip testing device, characterized in that, The control method includes: providing a sorting device, a testing device and a transfer component; wherein, the sorting device includes a first chamber for accommodating a first carrier tray on which cleaning particles are provided; the testing device includes a second chamber and a testing socket located in the second chamber, and the second chamber is used to accommodate a second carrier tray, and the testing device is used to electrically connect to a chip to be tested located on the second carrier tray through the testing socket and perform a testing operation on the chip to be tested; the transfer component is used to transfer the first carrier tray between the first chamber and the second chamber; controlling the testing socket in the testing device to perform a testing operation on the chip to be tested; when the testing socket reaches a preset cleaning condition, controlling the transfer component to move the first carrier tray from the first chamber to the second chamber and controlling the first carrier tray to perform a cleaning operation on the testing socket.

13. The control method of the chip testing device according to claim 12, characterized in that, The sorting device further includes a third chamber, the third chamber and the first chamber are arranged in sequence along the vertical direction and an isolation door is arranged between the third chamber and the first chamber; the control method further includes: when the testing socket reaches the preset cleaning condition, controlling the isolation door to open and controlling the transfer component to move the first carrier tray from the first chamber through the isolation door and the third chamber to the second chamber, and controlling the cleaning particles on the first carrier tray to perform the cleaning operation on the testing socket.

14. The control method of the chip testing device according to claim 13, wherein The control method further includes: when the isolation door is closed, performing a first heating operation on the second carrier tray where the chip that has completed the testing operation at a first preset temperature, so that the temperature of the second carrier tray and the chip rises to a second preset temperature; wherein, the first preset temperature is lower than -20°C and the second preset temperature is higher than 0°C.

15. The control method of the chip testing device according to claim 13, characterized in that, The control method further includes: after the cleaning operation, controlling the transfer component to transfer the first carrier tray from the second chamber through the third chamber and the isolation door to the first chamber and controlling the isolation door to close; Perform a second heating operation on the first carrier tray that has completed the cleaning operation at a third preset temperature to raise the temperature of the first carrier tray to a fourth preset temperature, where the third preset temperature is lower than -20°C and the fourth preset temperature is higher than 0°C.

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