Wafer cutting path adjusting method, wafer cutting method and application

By adjusting the wafer cutting path, the end of the cutting line is retracted to the invalid area, the problem of scraps flying materials in traditional blade cutting is solved, the tool life and product yield are improved, and the wafer edge cracking is avoided.

CN120397983APending Publication Date: 2025-08-01SUZHOU SUNA PHOTOELECTRIC
View PDF 6 Cites 0 Cited by

Patent Information

Application Number
CN202510566607.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-04-30
Publication Date
2025-08-01

AI Technical Summary

Technical Problem

Traditional blade cutting is prone to scraps falling off and flying materials during wafer-level products, resulting in damage to the blade and a decrease in product yield.

Method used

By adjusting the wafer cutting path, the end of the cutting line is retracted to the invalid area, increasing the adhesion area of the scraps, reducing the probability of flying materials, and avoiding stress and separation difficulties caused by large-scale adjustment of the cutting line.

Benefits of technology

It significantly reduces the frequency of flying material problems, improves tool service life and product yield, and avoids the risk of cracking of grains and wafer edges.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN120397983A_ABST
    Figure CN120397983A_ABST
Patent Text Reader

Abstract

The invention discloses a wafer cutting path adjusting method, a wafer cutting method and application. The adjusting method comprises the following steps: providing a wafer to be cut, and dividing the wafer into an effective area and an invalid area; a cutter is adopted for cutting, and the extending direction of the first cutting direction and the extending direction of the second cutting direction intersect; and enabling the tail ends of the first cutting line and / or the second cutting line connected with the fallen corner to retract into the invalid area towards the center direction of the wafer at the selected position where the corner of the wafer is fallen. According to the wafer cutting path adjusting method provided by the invention, the length of the cutting line at the material flying position is adjusted based on positioning of the cutting material flying condition, so that the tail end of the cutting line retracts into the invalid area, the occurrence frequency of the material flying problem can be remarkably reduced, and the cutting efficiency is improved. And the problem that the edges of the crystal grains and the wafer are difficult to separate or generate concentrated stress to cause cracking and the like due to the fact that a large number of cutting lines on the edges are adjusted can be avoided, the service life of the cutter is greatly prolonged, and the product yield is greatly increased.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The present invention relates to the field of micro-nano processing technology, and particularly relates to a method for adjusting a wafer cutting path, a wafer cutting method and an application thereof. Background Art

[0002] With the continuous development of Moore's Law, both optical and semiconductor devices have put forward higher requirements for integration, precision and stability. At the same time, microlenses have become an indispensable part of fields such as optical communication and photovoltaic.

[0003] With the trend of miniaturization of the size of microlens chip products, in the process of wafer-level products, traditional blade cutting will have a relatively high probability of problems such as corner scrap chipping and flying, resulting in blade damage, angle exceeding the standard and other abnormalities, directly affecting the cutting quality and production efficiency.

[0004] Specifically, in the current market, the cutting method of conventional silicon lens wafers is to perform complete cutting according to the actual size of the wafer. However, this will inevitably generate tiny corner scraps at the junction of the edge knife marks. The adhesion of the corner scraps is poor, and the probability of flying scraps (refers to the abnormal phenomenon that because the size of the corner scraps is small, the adhesion area with the adhesive film is small, and after being separated from the whole wafer, there is a certain probability of falling off and flying out with the movement of the blade and the impact of the cutting water) increases, which will cause damage to the blade and directly affect the product yield. Therefore, a new cutting method is needed to prevent the problem of flying corner scraps. Summary of the Invention

[0005] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a method for adjusting a wafer cutting path, a wafer cutting method and an application thereof.

[0006] To achieve the foregoing invention purpose, the technical solutions adopted by the present invention include:

[0007] In a first aspect, the present invention provides a method for adjusting a wafer cutting path, which includes:

[0008] Providing a wafer to be cut, the plane of the wafer to be cut is divided into a valid area and an invalid area which are coaxially arranged, and the valid area is surrounded by the invalid area;

[0009] Cutting the wafer to be cut along a first cutting direction and a second cutting direction by using a tool, the extending directions of the first cutting direction and the second cutting direction intersect, the first cutting direction includes a plurality of first cutting lines arranged in parallel, and the second cutting direction includes a plurality of second cutting lines arranged in parallel;

[0010] At a selected position where wafer corner chipping occurs, retract the ends of the first cutting line and / or the second cutting line connected to the chipped corner towards the center direction of the wafer into the invalid area.

[0011] In a second aspect, the present invention also provides a wafer cutting method, which includes:

[0012] Determining the wafer cutting path by using the above adjustment method;

[0013] Cutting the wafer to be cut along the wafer cutting path.

[0014] In a third aspect, the present invention also provides an application of the above wafer cutting method in the fields of micro-nano processing, optical communication, and AI.

[0015] Based on the above technical solutions, compared with the prior art, the beneficial effects of the present invention at least include:

[0016] The adjustment method of the wafer cutting path provided by the present invention adjusts the length of the cutting line for the flying material position based on the positioning of the flying material during cutting, so that the end of the cutting line retracts into the invalid area. This can not only significantly reduce the occurrence frequency of the flying material problem, but also avoid problems such as difficult separation of the grains and the wafer edge or cracking caused by concentrated stress due to a large number of adjustments to the cutting lines at the edge, greatly improving the tool service life and product yield.

[0017] The above description is only an overview of the technical solution of the present invention. In order to enable those skilled in the art to more clearly understand the technical means of the present application and implement it in accordance with the content of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the detailed drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is an example diagram of the original cutting path and abnormal phenomena provided by a typical embodiment of the present invention;

[0019] Figure 2 is a schematic diagram of the calculation method of the adjustment method of the wafer cutting path provided by a typical embodiment of the present invention;

[0020] Figure 3 is an example diagram of the adjusted cutting path and corner states provided by a typical embodiment of the present invention;

[0021] Figure 4 is a statistical chart of cutting batch anomalies before and after adjustment provided by a typical embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] In view of the deficiencies in the prior art, the inventors of this case have proposed the technical solution of the present invention through long-term research and a large number of practices. The following will further explain the technical solution, its implementation process, principles, etc.

[0023] In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, the present invention may be practiced in other ways than those described herein, and thus, the scope of protection of the present invention is not limited by the specific embodiments disclosed below.

[0024] Moreover, relative terms such as "first" and "second" are only used to distinguish one component or method step with the same name from another, and do not necessarily require or imply any actual relationship or order between these components or method steps.

[0025] The present invention proposes to use the method of cutting and remaining waste in the invalid area without affecting quality and efficiency, increasing the adhesion area of the waste after wafer cutting, reducing the probability of waste flying, and maintaining the stability of the wafer cutting process. This method can be widely applied to the manufacturing processes of various imaging sensors, displays, and photovoltaic devices.

[0026] Based on the above technical idea, an embodiment of the present invention provides a method for adjusting a wafer cutting path, which includes the following steps:

[0027] Provide a wafer to be cut, the plane of the wafer to be cut is divided into a valid area and an invalid area arranged coaxially, and the valid area is surrounded by the invalid area;

[0028] Use a tool to cut the wafer to be cut along a first cutting direction and a second cutting direction, the extending directions of the first cutting direction and the second cutting direction intersect, the first cutting direction includes a plurality of first cutting lines arranged in parallel, and the second cutting direction includes a plurality of second cutting lines arranged in parallel;

[0029] At a selected position where the wafer corner breaks, retract the ends of the first cutting line and / or the second cutting line adjacent to the broken corner towards the center of the wafer into the invalid area.

[0030] In some embodiments, the wafer to be cut includes a plurality of grains arranged in an array, and there are cutting channels between the grains, and both the first cutting line and the second cutting line are in the cutting channels.

[0031] The key technical means of the present invention is that for wafers to be cut in the same batch, first count the positions where the corner breaks and waste flies, and retract the cutting lines for this position, without changing or minimally changing the cutting routes of other normal positions; such technical means can maximize the avoidance of the problem of waste flying from the corners while also avoiding large adjustments to the overall cutting grid. Especially in the case of blade cutting, it prevents the stress risk brought by large adjustments to the cutting grid and the risk that the grains at the edge are not easily separated after cutting.

[0032] Some of the prior arts relate to the retraction of cutting paths. For example, in the Chinese invention patent with the publication number CN119601461A, laser cutting is used to ensure that the cutting line does not exceed the edge position, thus avoiding the generation of multiple pieces of scrap around the edge, reducing the difficulty of scrap collection, and improving efficiency. However, this technical solution is significantly different from the technical concept of the present invention. First, their application scenarios are different. This technical solution uses laser cutting, while the present invention uses blade cutting, and the technical problems faced and various adverse reactions caused by cutting are completely different. Second, their functions are different. The function of the laser cutting path planning is to facilitate the collection of scrap, while the function of the blade cutting in the present invention is to prevent edge flying materials and blade damage, and such risks do not exist in laser cutting. Finally, the technical effects produced are also different. In the laser cutting solution, it is to reduce the loss of ineffective actions, while the effect of blade cutting is to improve the yield by preventing abnormal occurrences.

[0033] In addition, since blade cutting is wire cutting and laser is point cutting (multiple points are continuously formed into a line), the retraction method applicable to laser cutting will cause other problems when used for blade cutting. For example, different from laser cutting, it is not easy to directly start cutting with a blade in the non-edge area of the wafer, which will directly lead to a sharp increase in the probability of blade damage. Therefore, when planning the cutting path, the starting end of the cutting line adjusted in the present invention should be kept as unchanged as possible, and mainly the position of the end point of the finishing cut is changed to avoid the problem of corner chipping and flying materials. Of course, unless both ends of a cutting line have the phenomenon of corner chipping and flying materials, but the incidence of this situation is very small.

[0034] Therefore, although the present invention only makes fine adjustments to the cutting route, the obtained technical effects are very obvious and are fully supported by data in the long-term practice of the inventor.

[0035] Regarding some technical details in the specific implementation of the present invention, in some embodiments, the first cutting direction and the second cutting direction intersect with each other. This intersection is generally perpendicular to each other, but is not limited to this situation, and the situation where the two cutting directions (usually referring to the directions of the cutting channels in the wafer) form a regular included angle is also possible.

[0036] In some embodiments, the grains are divided into intact grains and defective grains. The effective area refers to the circular area that encompasses all the intact grains, and the ineffective area refers to the annular area that surrounds the circular area in the wafer to be cut.

[0037] In addition, in some embodiments, the adjustment method may specifically include the following process:

[0038] Multiple wafers to be cut are successively cut, and the corner chipping states of the cut wafers are counted to determine the selected positions where wafer corner chipping occurs.

[0039] The above technical solution describes how to qualitatively adjust the cutting path. The preferred embodiments of the present invention also provide a way to quantitatively adjust the cutting path. That is, in some embodiments, the endpoints of the first cutting line and the second cutting line retract to a distance from the edge of the effective area equal to the remaining value, and the calculation method of the remaining value is expressed as:

[0040] C = (L - W1) / 2 + W 2×α

[0041] Where C represents the remaining value, L represents the total length of the first cutting line or the second cutting line, W1 represents the width occupied by the effective area on the first cutting line or the second cutting line, W2 represents the width occupied by a section of the invalid area on the first cutting line or the second cutting line, and α represents a proportionality coefficient greater than 0 and less than 1.

[0042] In some embodiments, the value range of the proportionality coefficient is 30 - 50%. The general recommended value is 40%, and fine-tuning can be performed nearby according to the cutting situation to find the optimal proportionality coefficient.

[0043] Of course, this proportionality coefficient is the best range summarized by the inventors of the present invention through long-term practice, but it does not mean that the feasible range of the present invention is limited to this. This value may vary to a certain extent depending on the material and thickness of the wafers to be cut, as well as the width and spacing of the cutting lines.

[0044] In addition, some key differences between the present invention and many prior arts of cutting line retraction are also reflected in: in some embodiments, at non-selected positions where wafer corner chipping does not occur, the starting positions of the first cutting line and the second cutting line remain unchanged.

[0045] The second aspect of the embodiments of the present invention also provides a wafer cutting method, which includes the following steps:

[0046] Determine the wafer cutting path by using the adjustment method provided in any of the above embodiments;

[0047] Cut the wafer to be cut along the wafer cutting path.

[0048] The third aspect of the embodiments of the present invention also provides the application of the above wafer cutting method in the fields of micro-nano processing, optical communication, and AI.

[0049] The technical solutions of the present invention will be further described in detail below through several embodiments in conjunction with the accompanying drawings. However, the selected embodiments are only used to illustrate the present invention and do not limit the scope of the present invention.

[0050] Embodiment 1

[0051] In this embodiment, through the algorithm for the effective area of the wafer and the precise control of the moving position of the cutting axis, local semi-cutting is performed in the ineffective area of the wafer to increase the sticking area of the scrap and improve the adhesion force, thereby preventing the scrap from flying. The specific steps are as follows:

[0052] 1. According to the requirements of the product design drawing, accurately check the effective area and ineffective area of the wafer.

[0053] 2. Cut one or more wafer products in a conventional manner, and measure and record the distance between the actual end position of the cutting mark and the effective area as shown, and calculate the cutting allowance according to this distance as shown. Figure 1 as shown Figure 2 Calculate the cutting allowance according to this distance.

[0054] 3. Finally, set the cutting allowance in the cutting program, perform wafer cutting, and observe the effect of the cutting mark after cutting. If the allowance is too large, it cannot prevent the scrap from flying; if the allowance is too small, it will cause the effective area to be missed. Adjust the allowance parameter according to the actual situation.

[0055] Based on the above improvement plan, the inventor of the present invention implemented this new cutting allowance method for product 043 on November 1, 2024. By December 31, a total of about 150 wafers (70 million finished products) were cut. As shown, Figure 4 the abnormal incidence rate caused by flying materials decreased from 12.7% to 0%.

[0056] Based on the above embodiments, it can be clearly seen that the method for adjusting the wafer cutting path provided by the present invention adjusts the length of the cutting line for the flying material position based on the positioning of the flying material situation, so that the end of the cutting line retracts into the ineffective area, which can not only significantly reduce the occurrence frequency of the flying material problem, but also avoid problems such as the difficulty in separating the edge of the die and the wafer or the generation of concentrated stress leading to cracking caused by a large amount of adjustment of the cutting line at the edge, greatly improving the tool service life and product yield.

[0057] It should be understood that the above embodiments are only used to illustrate the technical concept and features of the present invention, and their purpose is to enable those familiar with this technology to understand the content of the present invention and implement it accordingly, and cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for adjusting a wafer cutting path, characterized in that, Including: Providing a wafer to be cut, the plane of the wafer to be cut is divided into an effective area and an ineffective area which are coaxially arranged, and the effective area is surrounded by the ineffective area; Using a cutting tool to cut the wafer to be cut along a first cutting direction and a second cutting direction, the extending directions of the first cutting direction and the second cutting direction intersect, the first cutting direction includes a plurality of first cutting lines arranged in parallel, and the second cutting direction includes a plurality of second cutting lines arranged in parallel; At a selected position where the corner of the wafer breaks off, the ends of the first cutting line and / or the second cutting line connected to the broken corner are retracted towards the center of the wafer into the ineffective area.

2. The adjustment method according to claim 1, wherein The wafer to be cut includes a plurality of grains arranged in an array, and there are cutting channels between the grains, and both the first cutting line and the second cutting line are located in the cutting channels.

3. The adjustment method according to claim 2, wherein The first cutting direction and the second cutting direction intersect each other.

4. The adjustment method according to claim 2, characterized in that, The grains are divided into intact grains and defective grains. The effective area is a circular area encompassing all the intact grains, and the ineffective area is an annular area surrounding the circular area in the wafer to be cut.

5. The adjustment method according to claim 1, characterized in that, Specifically including: Cutting a plurality of the wafers to be cut successively, and counting the corner breakage states of the cut wafers to determine the selected positions where the corners of the wafers break off.

6. The adjustment method according to claim 1, wherein The endpoints of the first cutting line and the second cutting line are retracted to a distance from the edge of the effective area equal to a remaining value, and the calculation method of the remaining value is expressed as: C = (L - W1) / 2 + W2×α Wherein, C represents the remaining value, L represents the total length of the first cutting line or the second cutting line, W1 represents the width occupied by the effective area on the first cutting line or the second cutting line, W2 represents the width occupied by a section of the ineffective area on the first cutting line or the second cutting line, and α represents a proportionality coefficient greater than 0 and less than 1.

7. The adjustment method according to claim 6, wherein The value range of the proportionality coefficient is 30 - 50%.

8. The adjustment method according to claim 1, characterized in that At non-selected positions where the corners of the wafers do not break off, the starting positions of the first cutting line and the second cutting line remain unchanged.

9. A wafer cutting method, characterized in that, Including: Determining the wafer cutting path by using the adjustment method described in any one of claims 1 - 8; Cutting the wafer to be cut along the wafer cutting path.

10. Application of the wafer cutting method according to claim 9 in the fields of micro-nano processing, optical communication, and AI.

Citation Information

Patent Citations

  • Automatic production process of flash memory wafer

    CN119601461A

  • Wafer cutting method possessing test pattern

    CN105336685A

  • Cutting method

    CN111599752A

  • Semiconductor wafer segmentation method

    CN118197995A

  • Manufacture of semiconductor device

    JP1992000740A