Forming method of inertial sensor, inertial sensor and electronic equipment

Abstract

The invention relates to a forming method of an inertial sensor, the inertial sensor and electronic equipment. The forming method of the inertial sensor comprises the following steps: forming a structure wafer with a first insulating layer and bonding the structure wafer with a device wafer; patterning a device structure and a conductive structure independent of the device structure on the device wafer; bonding an electric connection wafer on one side, deviating from the structure wafer, of the device wafer; etching the structural wafer to form a first through hole, wherein the first insulating layer is exposed in the first through hole; the projection of the first through hole is overlapped with the projection of the conductive structure; etching the first insulating layer exposed in the first through hole until the conductive structure is exposed; and depositing a conductive material on the inner wall of the first through hole and the surface of the conductive structure to form a conductive layer. According to the invention, the necessity of forming a large-aperture silicon through hole in the electric connection wafer is omitted, and the first through hole only needs to penetrate through the structure wafer, so that the hole depth is greatly reduced, the aperture of the first through hole is reduced, and the miniaturization of the inertial sensor is facilitated.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductors, and in particular to a method for forming an inertial sensor, an inertial sensor, and an electronic device. Background Art

[0002] As microelectromechanical systems (MEMS) and inertial sensors (such as accelerometers and gyroscopes) develop toward smaller packages and higher integration, wafer-level packaging (WLP) has gradually become the mainstream packaging method for inertial sensor chips due to its advantages such as a short process flow, low cost, and small package size. In a typical inertial sensor wafer-level packaging structure, in order to lead the weak electrical signals inside the chip to external pads, a through-silicon via (TSV) structure must be fabricated on the silicon substrate. The electrical signals are then routed from the chip to the external pads through the TSV.

[0003] In the wafer-level packaging process of inertial sensors, when preparing through-silicon vias, opening the through-silicon via on the electrical connection wafer side will reduce the structural strength of the electrical connection wafer and affect the reliability of the formed inertial sensor chip. Opening the through-silicon via on the structural wafer side will cause the through-silicon via to occupy more area of the inertial sensor chip, limiting the miniaturization of the inertial sensor chip. Summary of the Invention

[0004] The embodiments of the present application provide a method for forming an inertial sensor, an inertial sensor, and an electronic device, which aim to solve the problems caused by the opening of through-silicon vias (TSVs) during wafer-level packaging of the inertial sensor.

[0005] To achieve the above objectives, according to a first aspect of the present application, a method for forming an inertial sensor is provided, comprising: forming a structural wafer, wherein one side surface of the structural wafer has a first insulating layer; Providing a device wafer, and bonding the device wafer to a side of the structure wafer having the first insulating layer; Patterning the device wafer to form a device structure and a conductive structure; the conductive structure and the device structure are independent of each other; bonding an electrical connection wafer on a side of the device wafer facing away from the structure wafer; Etching the structural wafer to form a first through hole on the structural wafer, wherein the first insulating layer is exposed in the first through hole; in a thickness direction of the structural wafer, a projection of the first through hole overlaps with a projection of the conductive structure; Etching the first insulating layer exposed in the first through hole until the conductive structure is exposed in the first through hole; A conductive material is deposited at least on the inner wall of the first through hole and the surface of the conductive structure exposed in the first through hole to form a conductive layer.

[0006] Optionally, before the conductive structure is exposed in the first through hole by etching the first insulating layer exposed in the first through hole, the method for forming the inertial sensor further includes: Forming a second insulating layer; the second insulating layer covers the surface of the structure wafer facing away from the device wafer, the inner wall of the first through hole, and the first insulating layer exposed in the first through hole; Wherein, the first insulating layer and the second insulating layer covering the surface of the conductive structure facing away from the electrical connection wafer together constitute a first sacrificial structure.

[0007] Optionally, etching the first insulating layer exposed in the first through hole until the conductive structure is exposed in the first through hole includes: Etching the first sacrificial structure until the first insulating layer covering the surface of the conductive structure facing away from the electrical connection wafer is exposed, and the thickness of the first insulating layer is less than the thickness of the second insulating layer covering the inner wall of the first through hole; Etching the second insulating layer covering the surface of the structure wafer facing away from the device wafer and the inner wall of the first through hole and the first insulating layer covering the surface of the conductive structure facing away from the electrical connection wafer until the conductive structure is exposed in the first through hole.

[0008] Optionally, depositing a conductive material on at least the inner wall of the first through hole and the surface of the conductive structure exposed in the first through hole to form a conductive layer includes: Depositing a conductive material on the second insulating layer covering the surface of the structure wafer facing away from the device wafer and the inner wall of the first through hole and on the surface of the conductive structure exposed in the first through hole to form a conductive layer.

[0009] Optionally, the conductive layer covers the surface of the structure wafer facing away from the device wafer, the inner wall of the first through hole, and the surface of the conductive structure exposed in the first through hole; the method for forming the inertial sensor further includes: forming an electrical connection structure on the conductive layer; The forming of the electrical connection structure on the conductive layer includes: Forming an insulating dielectric layer; the insulating dielectric layer fills the first through hole and covers the surface of the conductive layer facing away from the structure wafer; Etching the insulating dielectric layer to form a plurality of notches on the insulating dielectric layer; the conductive layer covering the surface of the structure wafer facing away from the device wafer is exposed in the notches; Forming the electrical connection structure on the conductive layer exposed in each of the notches.

[0010] Optionally, the formed structural wafer includes: Providing a first wafer; Etching a plurality of grooves on one side surface of the first wafer; Forming a first insulating layer on one side surface of the first wafer having a plurality of grooves and on the inner walls of the respective grooves to form the structural wafer; Wherein, the grooves correspond to the device structures, and in the thickness direction of the structural wafer, the projection of the grooves overlaps with the projection of the corresponding device structures.

[0011] Optionally, before patterning the device wafer to form device structures and conductive structures, the method for forming the inertial sensor further includes: Etching one side surface of the device wafer facing away from the structural wafer to form a plurality of electrical connection bumps; Depositing a metal layer on one side surface of each of the electrical connection bumps facing away from the structural wafer.

[0012] According to a second aspect of the present application, there is provided an inertial sensor, including: A structural wafer, one side surface of the structural wafer has a first insulating layer, and a first through hole penetrating the structural wafer and the first insulating layer is provided on the structural wafer; A device wafer, bonded to one side surface of the structural wafer having the first insulating layer, the device wafer includes independent device structures and conductive structures, the device structures and the conductive structures are made of the same material, and in the thickness direction of the structural wafer, the first through hole overlaps with the projection of the conductive structure; An electrical connection wafer, bonded to the side of the device structure facing away from the structural wafer; A conductive layer, covering the inner wall of the first through hole and the surface of the conductive structure exposed in the first through hole, and an electrical connection structure is provided on the conductive layer.

[0013] Optionally, it further includes a second insulating layer, and the second insulating layer covers the inner wall of the first through hole and the side surface of the structural wafer facing away from the device structure; The conductive layer covering the inner wall of the first through hole is located on the second insulating layer.

[0014] Optionally, there is also a conductive layer on the second insulating layer covering the side surface of the structural wafer facing away from the device structure; The inertial sensor further includes: An insulating dielectric layer, filling the first through hole and covering the side surface of the conductive layer facing away from the structural wafer, and a plurality of notches are provided on the insulating dielectric layer covering the side surface of the conductive layer facing away from the structural wafer; Among them, the electrical connection structure is located in each of the gaps and is connected to the conductive layer exposed in each of the gaps.

[0015] According to a third aspect of the present application, there is also provided an electronic device including the inertial sensor as described above.

[0016] In the method for forming the inertial sensor disclosed in the present application, by first depositing a first insulating layer on the surface of the structural wafer on the side for bonding with the device wafer, when etching the structural wafer to form the first through hole, this first insulating layer can be used as an accurate etching stop layer to effectively prevent damage to the underlying device wafer during the etching process; at the same time, a conductive structure independent of the device structure and dedicated to signal extraction is patterned on the device wafer, so that after the structural wafer, the device wafer, and the electrical connection wafer are bonded, the first through hole can be directly docked with the metal interconnect layer of the electrical connection wafer through this conductive structure.

[0017] The present application not only eliminates the need to open large-aperture through-silicon vias on the electrical connection wafer, but also since the first through hole only needs to penetrate the structural wafer, the hole depth is significantly reduced, the aperture of the first through hole is reduced, which helps to miniaturize the inertial sensor, and significantly reduces the processing difficulty and stress risk of the structural wafer, while ensuring the reliability of the signal path and the mechanical strength of the inertial sensor.

[0018] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. Description of the Drawings In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application, and those skilled in the art can obtain other drawings without creative efforts based on these drawings.

[0019] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, where the same reference numerals represent the same parts in the following description.

[0020] Figure 1 is a flowchart of the method for forming the inertial sensor provided by the embodiment of the present application; Figures 2 to 14 is a cross-sectional view during the formation process of the inertial sensor provided by the embodiment of the present application.

[0021] Description of the Reference Numerals: 10. Structural wafer; 11. First through hole; 12. Groove; 20. Device wafer; 21. Device structure; 22. Conductive structure; 23. Electrical connection bump; 30. Electrically connect the wafer; 40. First insulating layer; 41. Second insulating layer; 42. Conductive layer; 43. Insulating dielectric layer; 431. Notch; 44. Electrical connection structure; 45. Metal layer; 50. First sacrificial structure. Detailed implementation manners

[0022] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0023] As described in the background art, wafer-level packaging (WLP) has gradually become the mainstream packaging method for inertial sensor chips due to its advantages such as short process flow, low cost, and small packaging size. Specifically, an inertial sensor generally includes a packaging layer, a sensitive structure layer, and an integrated circuit layer. In some embodiments, by sequentially depositing multiple layers of thin films (such as polysilicon, silicon nitride, silicon oxide, and metal interconnection layers, etc.) on a substrate, and directly forming the sensitive structure and the packaging layer of the inertial sensor on the same wafer using a micromachining process. Although this "deposition-etching-packaging" integrated method seems to simplify the process, due to the inevitable generation of large residual stresses during the deposition of multiple layers of thin films, as the thickness and number of layers of the thin films increase, the residual stresses may cause local or overall warping of the wafer or the packaging structure, affecting the flatness of the inertial sensor chip.

[0024] The change in mechanical stress may also cause drift in the zero offset and sensitivity of the inertial sensor chip, affecting the measurement accuracy. In contrast, the wafer bonding process not only effectively reduces the risk of warping and failure caused by stress, but also provides a better technical path for the miniaturization and performance stability of the inertial sensor chip by utilizing the high precision and high reliability advantages of wafer-level packaging.

[0025] When forming an inertial sensor chip through wafer-level packaging, in some embodiments, through-silicon vias are opened on the electrically connected wafer to lead out electrical signals. The electrically connected wafer has an integrated circuit layer on which multiple functional circuits are integrated. The electrically connected wafer needs to have sufficient area to accommodate the circuit layout and maintain mechanical strength to ensure the reliability of the inertial sensor chip. Opening through-silicon vias on the electrically connected wafer not only seriously occupies the circuit layout space, but also significantly weakens the mechanical strength of the electrically connected wafer due to the thinning and opening of the electrically connected wafer, thereby significantly reducing the reliability of the inertial sensor.

[0026] To improve the reliability of inertial sensors, in some embodiments, through-silicon vias are opened on a structural wafer to lead out electrical signals. However, when forming through-silicon vias on the structural wafer, the through-silicon vias need to penetrate both the structural wafer and the device wafer. To obtain sufficient hole depth, the aperture of the through-silicon vias often needs to be enlarged to dozens or even hundreds of micrometers. This not only reduces the impact resistance of the structural wafer, but also occupies the precious layout space of the structural wafer and increases the process difficulty of deep silicon etching and re-planarization, thereby significantly increasing the manufacturing cost and reducing the yield.

[0027] To solve the problems caused by the formation of through-silicon vias during the wafer-level packaging process of inertial sensors, an embodiment of the present application discloses a method for forming an inertial sensor, which includes: S100: Form a structural wafer, one side surface of the structural wafer has a first insulating layer; S200: Provide a device wafer, and bond the device wafer to the side of the structural wafer with the first insulating layer; S300: Pattern the device wafer to form a device structure and a conductive structure; the conductive structure is independent of the device structure; S400: Bond an electrically connected wafer to the side of the device wafer facing away from the structural wafer; S500: Etch the structural wafer to form a first through-hole on the structural wafer, and the first insulating layer is exposed in the first through-hole; in the thickness direction of the structural wafer, the projection of the first through-hole overlaps with the projection of the conductive structure; S600: Etch the first insulating layer exposed in the first through-hole until the conductive structure is exposed in the first through-hole; S700: Deposit a conductive material at least on the inner wall of the first through-hole and on the surface of the conductive structure exposed in the first through-hole to form a conductive layer.

[0028] Referring to Figure 2 , in step S100, a structural wafer 10 is formed, and one side surface of the structural wafer 10 has a first insulating layer 40.

[0029] In the embodiment disclosed in the present application, forming the structural wafer 10 includes the following steps: providing a first wafer; etching a plurality of grooves 12 on one side surface of the first wafer; forming a first insulating layer 40 on one side surface of the first wafer having a plurality of grooves 12 and on the inner walls of the respective grooves 12 to form the structural wafer 10; wherein, the grooves 12 correspond to the device structure 21, and in the thickness direction of the structural wafer 10, the projection of the groove 12 overlaps with the projection of the corresponding device structure 21.

[0030] Specifically, in the embodiments of the present application, the materials of the first wafer and the device wafer 20 are both silicon. Preferably, the device wafer 20 uses a low-resistance silicon material to enhance the conductivity of the conductive structure 22. The material of the first insulating layer 40 is silicon oxide, and the first insulating layer 40 can be formed by thermal oxidation (TEOS) or by plasma-enhanced chemical vapor deposition (PECVD).

[0031] Referring to Figure 3 , in step S200, the device wafer 20 is provided, and the device wafer 20 is bonded to the side of the structural wafer 10 having the first insulating layer 40.

[0032] The bonding method between the device wafer 20 and the structural wafer 10 includes but is not limited to anodic bonding. It is worth mentioning that in some embodiments, before the device wafer 20 is patterned, the device wafer 20 is also ground to thin the device wafer 20 to 10 μm to 70 μm. The device structure 21 is the sensitive mass layer of the final inertial sensor.

[0033] Referring to Figure 6 , in step S300, the device wafer 20 is patterned to form the device structure 21 and the conductive structure 22; the conductive structure 22 is independent of the device structure 21.

[0034] It should be noted that after the device structure 21 is patterned, a plurality of device regions are formed. The conductive structure 22 and the device structure 21 in each device region are independent of each other and are both made of low-resistance silicon material. The present application discloses Figures 2 to 14 Only one device region is taken as an example, and in some other embodiments, multiple device regions can also be taken as examples.

[0035] In some embodiments, referring to Figure 4 and Figure 5 , before step S300, the method for forming the inertial sensor further includes: etching the surface of the device wafer 20 facing away from the structural wafer 10 to form a plurality of electrical connection bumps 23; depositing a metal layer 45 on the surface of each electrical connection bump 23 facing away from the structural wafer 10. It should be noted that at least one electrical connection bump 23 is located on the side of the conductive structure 22 facing away from the structural wafer 10.

[0036] In some embodiments, the surface of the electrical connection bump 23 facing away from the structural wafer 10 protrudes 1.5 μm to 3 μm compared to the surface of the device wafer 20 facing away from the structural wafer 10. The material of the metal layer 45 includes but is not limited to germanium.

[0037] Referring to Figure 7 , in step S400, an electrical connection wafer 30 is bonded to the side of the device wafer 20 facing away from the structural wafer 10.

[0038] One side of the electrical connection wafer 30 for bonding with the device wafer 20 has a metal interconnect layer, and the electrical connection bumps 23 of the device wafer 20 are connected to the electrical connection wafer 30 by means of metal eutectic bonding.

[0039] Referring to Figure 8 , in step S500, the structural wafer 10 is etched to form a first through hole 11 on the structural wafer 10, and the first insulating layer 40 is exposed in the first through hole 11; in the thickness direction of the structural wafer 10, the projection of the first through hole 11 overlaps with the projection of the conductive structure 22.

[0040] It should be noted that since the attached drawings disclosed in the embodiments of the present application only show the formation method of the inertial sensor by taking one device area of the device wafer 20 as an example, Figure 8 only one first through hole 11 is shown in . In the actual manufacturing process, the device wafer 20 has multiple device areas. For each device area, the structural wafer 10 needs to open the first through hole 11 based on the number of conductive structures 22. The first through holes 11 corresponding to multiple device areas can be completed simultaneously through one process, or can be completed separately through multiple processes. Each first through hole 11 overlaps with the projection of the conductive structure 22 of the device wafer 20 in the corresponding device area. If there are multiple conductive structures 22 in one device area of the device wafer 20, the structural wafer 10 needs to open the corresponding number of first through holes 11.

[0041] The material of the first insulating layer 40 is different from that of the structural wafer 10, so it can be used as a stop etching layer for the first through hole 11 to effectively prevent damage to the underlying device wafer 20 during the etching process. Before etching the first through hole 11, in order to effectively reduce the hole depth of the first through hole 11, the structural wafer 10 can also be thinned.

[0042] In the embodiments of the present application, the first through hole 11 only penetrates the structural wafer 10, reducing the hole depth of the first through hole 11. The aperture and hole depth of the first through hole 11 are proportional. When the hole depth is reduced, the aperture can also be significantly reduced, reducing the space occupied by the first through hole 11, which helps to miniaturize the inertial sensor. By setting the conductive structure 22 independent of the device structure 21, the electrical signal of the electrical connection wafer 30 can be led out without the later conductive layer 42 contacting the electrical connection wafer 30.

[0043] Referring to Figure 10 and Figure 11 , in step S600, the first insulating layer 40 exposed in the first through hole 11 is etched until the conductive structure 22 is exposed in the first through hole 11.

[0044] Referring to Figure 9, in some embodiments, before step S600, the method for forming the inertial sensor further includes: forming a second insulating layer 41; the second insulating layer 41 covers the surface of the structural wafer 10 facing away from the device wafer 20, the inner wall of the first through hole 11, and the first insulating layer 40 exposed in the first through hole 11; wherein, the first insulating layer 40 covering the surface of the conductive structure 22 facing away from the electrical connection wafer 30 and the second insulating layer 41 together constitute the first sacrificial structure 50.

[0045] The material of the second insulating layer 41 is silicon oxide, and the second insulating layer 41 can be formed by thermal oxidation (TEOS) or by plasma enhanced chemical vapor deposition (PECVD).

[0046] Covering the first insulating layer 40 and the second insulating layer 41 on the surface of the conductive structure 22 facing away from the electrical connection wafer 30 can make the thickness of the formed first sacrificial structure 50 greater than the thickness of the second insulating layer 41 covering the inner wall of the first through hole 11, which helps to selectively and stepwise remove the silicon oxide layer at the bottom of the first through hole 11 and the silicon oxide layer on the inner wall during the subsequent etching process, and provides a process window for accurately exposing the conductive structure 22 and ensuring the integrity of the silicon oxide layer on the inner wall.

[0047] In some embodiments, step S600 includes the following steps: etching the first sacrificial structure 50 until the first insulating layer 40 covering the surface of the conductive structure 22 facing away from the electrical connection wafer 30 is exposed, and the thickness of the first insulating layer 40 is less than the thickness of the second insulating layer 41 covering the inner wall of the first through hole 11; etching the second insulating layer 41 covering the surface of the structural wafer 10 facing away from the device wafer 20 and the inner wall of the first through hole 11 and the first insulating layer 40 covering the surface of the conductive structure 22 facing away from the electrical connection wafer 30 until the conductive structure 22 is exposed in the first through hole 11.

[0048] By first etching the first sacrificial structure 50 to make its thickness less than the thickness of the second insulating layer 41 covering the inner wall of the first through hole 11, and then etching the first insulating layer 40 and the second insulating layer 41 as a whole, the integrity of the second insulating layer 41 on the inner wall of the first through hole 11 can be maintained when the conductive structure 22 is completely exposed in the first through hole 11.

[0049] Referring to Figure 12 , in step S700, deposit a conductive material on at least the inner wall of the first through hole 11 and the surface of the conductive structure 22 exposed in the first through hole 11 to form a conductive layer 42.

[0050] Specifically, in some embodiments, step S700 includes the following steps: depositing a conductive material on the second insulating layer 41 covering the surface of the structural wafer 10 facing away from the device wafer 20 and the inner wall of the first through hole 11 and on the surface of the conductive structure 22 exposed in the first through hole 11 to form a conductive layer 42.

[0051] The material of the conductive layer 42 includes, but is not limited to, any one material or combination of copper, nickel, gold, tungsten, etc. The formation process of the conductive layer 42 includes, but is not limited to, electroplating, physical or chemical vapor deposition, atomic layer deposition, etc.

[0052] By depositing a conductive material on the second insulating layer 41 covering the surface of the structural wafer 10 facing away from the device wafer 20 and the inner wall of the first through hole 11 and on the surface of the conductive structure 22 exposed in the first through hole 11, a continuous conductive layer 42 is formed, which helps to release the position of the electrical connection structure 44 from the narrow first through hole 11, and a larger area of redistribution wiring (RDL) or pads can be flexibly arranged on one side of the structural wafer 10. In this way, not only the available soldering area is significantly expanded, but also the layout freedom and signal integrity of the package design are enhanced.

[0053] Refer to Figures 13 to 14 , in some embodiments, after step S700, the method for forming an inertial sensor further includes: forming an electrical connection structure 44 on the conductive layer 42.

[0054] Specifically, forming the electrical connection structure 44 on the conductive layer 42 includes: forming an insulating dielectric layer 43; the insulating dielectric layer 43 fills the first through hole 11 and covers the surface of the conductive layer 42 facing away from the structural wafer 10; etching the insulating dielectric layer 43 to form a plurality of notches 431 on the insulating dielectric layer 43; the conductive layer 42 covering the surface of the structural wafer 10 facing away from the device wafer 20 is exposed in the notches 431; and forming an electrical connection structure 44 on the conductive layer 42 exposed in each notch 431.

[0055] In the embodiments of the present application, the material of the insulating dielectric layer 43 includes, but is not limited to, silicon oxide, silicon nitride, polyimide. The formation process of the insulating dielectric layer 43 includes, but is not limited to, atmospheric pressure chemical vapor deposition (Atmospheric Pressure CVD), low pressure chemical vapor deposition (Low Pressure CVD), plasma enhanced chemical vapor deposition (PECVD), thermal oxidation (Thermal Oxidation), magnetron sputtering. The material of the electrical connection structure 44 includes, but is not limited to, aluminum, copper, titanium. The formation process of the electrical connection structure 44 includes, but is not limited to, physical vapor deposition processes such as sputtering and evaporation.

[0056] The first through-hole 11 is filled with an insulating dielectric layer 43, and the conductive layer 42 is entirely covered by the insulating dielectric layer 43, completely enclosing all of the conductive layer 42 except for the notch 431. This can effectively isolate leakage, crosstalk, and short circuits between adjacent electrical connection structures 44, and also prevent electrical failures caused by contact between the inertial sensor and external conductors during application, thereby significantly improving the electrical reliability of the inertial sensor.

[0057] An embodiment of the present application also discloses an inertial sensor, which is formed by the method for forming an inertial sensor disclosed above. Referring to Figure 14 , the inertial sensor includes a structural wafer 10, a device wafer 20, an electrical connection wafer 30, and a conductive layer 42. One side surface of the structural wafer 10 has a first insulating layer 40, and a first through-hole 11 penetrating through the structural wafer 10 and the first insulating layer 40 is formed on the structural wafer 10. The device wafer 20 is bonded to the side surface of the structural wafer 10 having the first insulating layer 40. The device wafer 20 includes independent device structures 21 and conductive structures 22. The device structures 21 and the conductive structures 22 are made of the same material. In the thickness direction of the structural wafer 10, the projection of the first through-hole 11 overlaps with the conductive structure 22. The electrical connection wafer 30 is bonded to the side of the device structure 21 facing away from the structural wafer 10. The conductive layer 42 covers the inner wall of the first through-hole 11 and the surface of the conductive structure 22 exposed in the first through-hole 11. Electrical connection structures 44 are provided on the conductive layer 42.

[0058] In the embodiment of the present application, the materials of the structural wafer 10 and the device wafer 20 are both silicon. Preferably, the device wafer 20 uses a low-resistance silicon material to enhance the conductivity of the conductive structure 22. In some embodiments, the inertial sensor further includes a second insulating layer 41. The second insulating layer 41 covers the inner wall of the first through-hole 11 and the side surface of the structural wafer 10 facing away from the device structure 21. The conductive layer 42 covering the inner wall of the first through-hole 11 is located on the second insulating layer 41.

[0059] In some embodiments, the inertial sensor further includes a conductive layer 42 on the second insulating layer 41 covering the side surface of the structural wafer 10 facing away from the device structure 21. The inertial sensor further includes an insulating dielectric layer 43. The insulating dielectric layer 43 is filled in the first through-hole 11 and covers the side surface of the conductive layer 42 facing away from the structural wafer 10. A plurality of notches 431 are formed on the insulating dielectric layer 43 covering the side surface of the conductive layer 42 facing away from the structural wafer 10. Among them, the electrical connection structures 44 are located in the respective notches 431 and are connected to the conductive layer 42 exposed in the respective notches 431.

[0060] An embodiment of the present application also discloses an electronic device, including any one of the inertial sensors disclosed above.

[0061] In the description of the present application, the terms "first" and "second" are used only for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0062] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0063] Among the embodiments, implementation manners and related technical features of the present application, they can be combined and replaced with each other without conflict.

[0064] The above are only the preferred embodiments of the present application and do not impose any form of limitation on the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A method for forming an inertial sensor, characterized in that, Including: Forming a structural wafer, one side surface of the structural wafer having a first insulating layer; Providing a device wafer, bonding the device wafer to the side of the structural wafer having the first insulating layer; Patterning the device wafer to form a device structure and a conductive structure; The conductive structure is independent of the device structure; Bonding an electrically connected wafer to the side of the device wafer facing away from the structural wafer; Etching the structural wafer to form a first through hole in the structural wafer, the first insulating layer being exposed in the first through hole; in the thickness direction of the structural wafer, the projection of the first through hole overlaps with the projection of the conductive structure; Etching the first insulating layer exposed in the first through hole until the conductive structure is exposed in the first through hole; Depositing a conductive material at least on the inner wall of the first through hole and on the surface of the conductive structure exposed in the first through hole to form a conductive layer.

2. The method for forming an inertial sensor according to claim 1, wherein Before etching the first insulating layer exposed in the first through hole until the conductive structure is exposed in the first through hole, the method for forming the inertial sensor further includes: Forming a second insulating layer; the second insulating layer covers the side surface of the structural wafer facing away from the device wafer, the inner wall of the first through hole, and the first insulating layer exposed in the first through hole; Wherein, the first insulating layer covering the side surface of the conductive structure facing away from the electrically connected wafer and the second insulating layer together constitute a first sacrificial structure.

3. The method for forming an inertial sensor according to claim 2, wherein The etching the first insulating layer exposed in the first through hole until the conductive structure is exposed in the first through hole includes: Etching the first sacrificial structure until the first insulating layer covering the side surface of the conductive structure facing away from the electrically connected wafer is exposed, and the thickness of the first insulating layer is less than the thickness of the second insulating layer covering the inner wall of the first through hole; Etching the second insulating layer covering the side surface of the structural wafer facing away from the device wafer and the inner wall of the first through hole and the first insulating layer covering the side surface of the conductive structure facing away from the electrically connected wafer until the conductive structure is exposed in the first through hole.

4. The method for forming an inertial sensor according to claim 3, wherein, The depositing a conductive material at least on the inner wall of the first through hole and on the surface of the conductive structure exposed in the first through hole to form a conductive layer includes: Depositing a conductive material on the second insulating layer covering the side surface of the structural wafer facing away from the device wafer and the inner wall of the first through hole and on the surface of the conductive structure exposed in the first through hole to form a conductive layer.

5. The method for forming an inertial sensor according to claim 1, wherein, The conductive layer covers the side surface of the structural wafer facing away from the device wafer, the inner wall of the first through hole, and the surface of the conductive structure exposed in the first through hole; The method for forming the inertial sensor further includes: forming an electrical connection structure on the conductive layer; The forming an electrical connection structure on the conductive layer includes: Forming an insulating dielectric layer; the insulating dielectric layer fills the first through hole and covers the side surface of the conductive layer facing away from the structural wafer; Etch the insulating dielectric layer to form a plurality of notches on the insulating dielectric layer; expose the conductive layer covering the surface of the structural wafer facing away from the device wafer in the notches; Form the electrical connection structure on the conductive layer exposed in each of the notches.

6. The method for forming an inertial sensor according to claim 1, wherein The forming of the structural wafer includes: Provide a first wafer; Etch a plurality of grooves on one surface of the first wafer; Form a first insulating layer on one surface of the first wafer having a plurality of grooves and the inner walls of each of the grooves to constitute the structural wafer; Wherein, the grooves correspond to the device structures, and in the thickness direction of the structural wafer, the projection of the grooves overlaps with the projection of the corresponding device structures.

7. The method for forming an inertial sensor according to claim 1, wherein Before patterning the device wafer to form device structures and conductive structures, the forming method of the inertial sensor further includes: Etch the surface of the device wafer facing away from the structural wafer to form a plurality of electrical connection bumps; Deposit a metal layer on the surface of each of the electrical connection bumps facing away from the structural wafer.

8. An inertial sensor, characterized in that, Comprising: A structural wafer (10), one surface of the structural wafer (10) has a first insulating layer (40), and a first through hole (11) penetrating the structural wafer (10) and the first insulating layer (40) is formed on the structural wafer (10); A device wafer (20), bonded to the surface of the structural wafer (10) having the first insulating layer (40), the device wafer (20) includes independent device structures (21) and conductive structures (22), the device structures (21) and the conductive structures (22) are made of the same material, and in the thickness direction of the structural wafer (10), the projection of the first through hole (11) overlaps with the projection of the conductive structure (22); An electrical connection wafer (30), bonded to the side of the device structure (21) facing away from the structural wafer (10); A conductive layer (42), covering the inner wall of the first through hole (11) and the surface of the conductive structure (22) exposed in the first through hole (11), and an electrical connection structure (44) is provided on the conductive layer (42).

9. The inertial sensor according to claim 8, characterized in that, It further includes a second insulating layer (41), and the second insulating layer (41) covers the inner wall of the first through hole (11) and the surface of the structural wafer (10) facing away from the device structure (21); The conductive layer (42) covering the inner wall of the first through hole (11) is located on the second insulating layer (41).

10. The inertial sensor according to claim 9, characterized in that, There is also a conductive layer (42) on the second insulating layer (41) covering the surface of the structural wafer (10) facing away from the device structure (21); The inertial sensor further includes: An insulating dielectric layer (43), filled in the first through hole (11) and covering the surface of the conductive layer (42) facing away from the structural wafer (10), and a plurality of notches (431) are formed on the insulating dielectric layer (43) covering the surface of the conductive layer (42) facing away from the structural wafer (10); Wherein, the electrical connection structure (44) is located in each of the notches (431) and is connected to the conductive layer (42) exposed in each of the notches (431).

11. An electronic device, characterized in that, Comprising an inertial sensor according to any one of claims 8-10.

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