Manufacturing method of semiconductor structure, waveguide and photon integrated circuit chip

Abstract

The invention relates to the field of semiconductors, and provides a manufacturing method of a semiconductor structure, a waveguide and a photon integrated circuit chip. The manufacturing method of the semiconductor structure comprises the following steps: forming a waveguide structure; depositing an oxide layer above and around the waveguide structure; the relative height between the top surface of the oxide layer and the top surface of the waveguide structure is adjusted such that the waveguide structure is higher than the oxide layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and more specifically, to a method for manufacturing a semiconductor structure, a waveguide, and a photonic integrated circuit chip. Background Art

[0002] With the rapid development of technologies such as optical communication, optical interconnection, and optical computing, the application fields of photonic integrated circuit chips are becoming increasingly wide. In a photonic integrated circuit chip, the transmission loss of a waveguide is one of the key indicators for evaluating its performance, which directly relates to the efficiency and distance of optical signal transmission in the waveguide. Summary of the Invention

[0003] According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor structure, including the following steps: forming a waveguide structure; depositing an oxide layer above and around the waveguide structure; adjusting the relative height between the top surface of the oxide layer and the top surface of the waveguide structure such that the waveguide structure is higher than the oxide layer.

[0004] In some embodiments, the step of forming the waveguide structure includes: forming a mask layer on a silicon layer; transferring the pattern of a mask plate to the mask layer through photolithography and etching processes to form a patterned mask layer; etching the silicon layer through the patterned mask layer to define the waveguide structure.

[0005] In some embodiments, the mask layer is a silicon nitride layer.

[0006] In some embodiments, the step of depositing the oxide layer includes depositing silicon oxide by at least one of high density plasma chemical vapor deposition and high aspect ratio process filling.

[0007] In some embodiments, adjusting the relative height between the top surface of the oxide layer and the top surface of the waveguide structure includes: performing chemical mechanical polishing on the deposited oxide layer.

[0008] In some embodiments, adjusting the relative height between the top surface of the oxide layer and the top surface of the waveguide structure includes: after the chemical mechanical polishing, etching the oxide layer such that the waveguide structure is higher than the oxide layer.

[0009] In some embodiments, etching the oxide layer includes using high selectivity etching to have a higher etching rate for etching the oxide layer material.

[0010] In some embodiments, after adjusting the relative height between the top surface of the oxide layer and the top surface of the waveguide structure, the residue of the silicon nitride layer is removed by a wet process.

[0011] In some embodiments, it includes: etching the top silicon in the SOI structure to form the waveguide structure.

[0012] According to one aspect of the present invention, a waveguide is provided, which is manufactured by using the manufacturing method of the above semiconductor structure.

[0013] According to one aspect of the present invention, a photonic integrated circuit chip is provided, including the waveguide.

[0014] Aspects, features, advantages, etc. of the embodiments of the present invention will be specifically described below in conjunction with the accompanying drawings. According to the following specific description in conjunction with the accompanying drawings, the above aspects, features, advantages, etc. of the present invention will become clearer. Description of the Drawings

[0015] Figure 1 is a cross-sectional schematic diagram after forming a mask layer during the manufacturing process of a semiconductor structure according to an embodiment of the present invention.

[0016] Figure 2 is Figure 1 a cross-sectional schematic diagram of the structure shown after lithography and etching to form a waveguide structure.

[0017] Figure 3 is Figure 2 a cross-sectional schematic diagram of the structure shown after depositing an oxide layer.

[0018] Figure 4 is Figure 3 a cross-sectional schematic diagram of the structure shown after chemical mechanical polishing (CMP).

[0019] Figure 5 is Figure 4 a cross-sectional schematic diagram of the structure shown after selective etching of the oxide layer to adjust the relative height, showing that the waveguide structure is higher than the oxide layer.

[0020] Figure 6 is Figure 5 a cross-sectional schematic diagram of the final structure after removing the residual silicon nitride mask of the structure shown. Detailed Embodiments

[0021] In order to facilitate understanding of various aspects, features, and advantages of the technical solution of the present invention, the present invention will be specifically described below in conjunction with the accompanying drawings. It should be understood that the following various embodiments are only for illustrative purposes and are not used to limit the protection scope of the present invention. Unless otherwise specified, silicon oxide and silicon nitride in the present invention include non-stoichiometric cases.

[0022] The terms used in this disclosure are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" refers to only A, only B, or both A and B. As used herein, a substrate may refer to an uncut substrate, such as an uncut wafer, or a cut substrate. As used herein, a chip may include a die.

[0023] In a photonic integrated circuit chip, the transmission loss of a waveguide is one of the key indicators for evaluating its performance, which directly relates to the efficiency and distance of optical signal transmission in the waveguide. The factors affecting the loss of the waveguide include the material, shape, surface topography of the waveguide, and even the manufacturing process of specific steps.

[0024] According to one aspect of an embodiment of the present invention, a method for manufacturing a semiconductor structure is provided, including the following main steps:

[0025] Step S110, forming a waveguide structure.

[0026] This step aims to form a waveguide structure for guiding optical transmission on a substrate. Specifically, it may include the following sub-steps:

[0027] (1) Providing a substrate and forming a mask layer: Select a suitable substrate, such as a substrate having a silicon-on-insulator (SOI) structure. A typical SOI structure includes a substrate layer 101, a buried oxide layer 102, and a top silicon layer 103. Above the top silicon layer 103 of the SOI structure, a mask layer 104 is deposited, such as a silicon nitride (Si x N y ) layer. This silicon nitride layer will be used as a hard mask for subsequent etching of the top silicon, and the top silicon layer 103 serves as the silicon layer to be etched for forming the waveguide structure. As Figure 1 shown, from bottom to top, it is the substrate layer 101, the buried oxide layer 102, the top silicon layer 103, and the silicon nitride mask layer 104.

[0028] (2) Forming the waveguide through patterning and etching: Using photolithography and etching processes, transfer the preset waveguide pattern from the mask to the mask layer 104 and the underlying top silicon layer 103. First, form a photoresist pattern on the silicon nitride mask layer 104 through photolithography. Then, using the photoresist as a mask, etch the silicon nitride mask layer 104 to transfer the pattern to the mask layer 104. After removing the photoresist, use the patterned mask layer 104a as a hard mask to etch the top silicon layer 103. For example, by etching the top silicon in the SOI structure until reaching the buried oxide layer 102 (for a fully etched waveguide), thereby defining the waveguide structure 103a. As Figure 2 shown, the formation of the waveguide structure 103a is completed at this time.

[0029] S120 Deposit an oxide layer above and around the waveguide structure.

[0030] The purpose of this step is to deposit an oxide layer to cover the waveguide structure and fill the gaps around it after the waveguide structure is formed, serving as an optical cladding and / or isolation layer. Specifically, it may include depositing an oxide: Above and around the formed waveguide structure 103a (which may still have the patterned mask layer 104a on its top), deposit an oxide layer 105 using chemical vapor deposition method, for example, silicon oxide (Si x O y ). The deposition method may include at least one of high-density plasma chemical vapor deposition (HDP-CVD) and high aspect ratio process (HARP) filling. The deposited oxide layer 105 needs to be thick enough to completely cover the waveguide structure and the patterned mask layer 104a on it. As Figure 3 shown, the oxide layer 105 covers above and around the waveguide structure 103a.

[0031] S130 Adjust the relative height between the top surface of the oxide layer and the top surface of the waveguide structure so that the waveguide structure is higher than the oxide layer.

[0032] By precisely controlling the height relationship between the top of the waveguide and the top of the surrounding oxide, the optical characteristics (such as loss) of the waveguide are adjusted. In some embodiments, it may include the following sub-steps:

[0033] (1) Planarize the oxide layer: Perform chemical mechanical polishing (CMP) on the deposited oxide layer 105. The purpose of the CMP process is to globally planarize the top surface of the oxide layer, remove the surface topography that may be generated during the deposition process, and provide a flat reference surface for the subsequent precise height adjustment step. After CMP, a planarized oxide layer 105 is obtained, as Figure 4 shown (schematically showing an ideal flat state).

[0034] (2) Selectively etching the oxide layer to adjust the relative height: After the chemical mechanical polishing, the oxide layer 105 is etched to reduce the height of its top surface, so that the top surface of the waveguide structure 103a is finally higher than the top surface of the oxide layer 105. For example, a highly selective etching process is used for this step, such as dry etching or wet etching that has a much higher etching rate for silicon dioxide than for silicon nitride and silicon. By precisely controlling the depth (etching amount) of this etching, the relative height difference between the top surface of the oxide layer 105 and the top surface of the finally exposed waveguide structure 103a can be precisely adjusted, making the waveguide structure 103a higher than the oxide layer 105. For example, a specific thickness of silicon dioxide is etched away to achieve a target height difference, such as 5 nm (or other values such as 4 nm, 6 nm, 7 nm). This results in a stepped structure as shown in Figure 5 shown.

[0035] (3) Removing the mask residue: If a silicon nitride mask layer is used in forming the waveguide structure and the mask layer still exists on top of the silicon waveguide after adjusting the relative height, then after adjusting the relative height, the remaining patterned mask layer 104a can be removed. For example, through a wet process, hot phosphoric acid with high selectivity for silicon nitride is used for cleaning. After removing the mask, the top surface of the waveguide structure 103a is directly exposed and is higher than the surrounding oxide layer 105. As shown in Figure 6 shown, a schematic diagram after removing the patterned mask layer is presented.

[0036] In addition, in some embodiments, after removing the patterned mask layer 104a, a step of depositing a covering layer is included. The covering layer covers the waveguide structure 103a and the oxide layer 105. The method of depositing the covering layer can use PECVD, which is different from the method of depositing the oxide mentioned above.

[0037] According to one aspect of the present invention, a waveguide is proposed, which is manufactured by the manufacturing method of the above semiconductor structure.

[0038] According to one aspect of the present invention, a photonic integrated circuit chip is proposed, including the waveguide. In some embodiments, the photonic integrated circuit chip may further include optical devices such as modulators, photodetectors, beam splitters, and grating couplers.

[0039] The manufacturing method according to the embodiments of the present invention reduces the loss of the waveguide. It may be that during manufacturing, the waveguide structure is made higher than the oxide layer in the relevant steps, which brings about a change in the characteristics near the interface of the waveguide structure, or changes the boundary position between the oxide layer and the subsequently deposited material, thereby changing the material environment or mechanical properties of the waveguide structure and reducing the loss of the waveguide. Those skilled in the art should understand that what is disclosed above is only the embodiments of the present invention, and of course, it cannot be used to limit the scope of the rights claimed by the present invention. Equivalent changes made according to the embodiments of the present invention still fall within the scope covered by the claims of the present invention.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, Including the following steps: Forming a waveguide structure; Depositing an oxide layer above and around the waveguide structure; Adjusting the relative height between the top surface of the oxide layer and the top surface of the waveguide structure so that the waveguide structure is higher than the oxide layer.

2. The method according to claim 1, wherein The step of forming the waveguide structure includes: Forming a mask layer on a silicon layer; Transferring the pattern of the mask plate to the mask layer through photolithography and etching processes to form a patterned mask layer; Etching the silicon layer through the patterned mask layer to define the waveguide structure.

3. The method according to claim 2, wherein The mask layer is a silicon nitride layer.

4. The method according to claim 1, wherein The step of depositing the oxide layer includes depositing silicon oxide by at least one of high-density plasma chemical vapor deposition and deep aspect ratio process filling.

5. The method according to claim 1, characterized in that, The adjusting the relative height between the top surface of the oxide layer and the top surface of the waveguide structure includes: Performing chemical mechanical polishing on the deposited oxide layer.

6. The method according to claim 5, characterized in that The adjusting the relative height between the top surface of the oxide layer and the top surface of the waveguide structure includes: After the chemical mechanical polishing, etching the oxide layer so that the waveguide structure is higher than the oxide layer.

7. The method according to claim 6, characterized in that, The etching of the oxide layer includes using high-selectivity etching to have a higher etching rate for etching the oxide layer material.

8. The method according to claim 3, wherein After adjusting the relative height between the top surface of the oxide layer and the top surface of the waveguide structure, removing the residue of the silicon nitride layer through a wet process.

9. The method according to claim 1, wherein Including: Forming the waveguide structure by etching the top silicon in the SOI structure.

10. A waveguide, characterized in that, It is manufactured by the method described in any one of claims 1-9.

11. A photonic integrated circuit chip, characterized in that, Including the waveguide described in claim 10.

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