Low-power-consumption phased array ultrasonic transceiving switch control system

Abstract

The invention relates to the technical field of transceiving switch circuit design, in particular to a low-power-consumption phased array ultrasonic transceiving switch control system which comprises a control circuit, a transmitting circuit and a T / R chip set. The control circuit is used for receiving an input clock signal CLK, outputting a high-voltage trigger signal to the transmitting circuit and outputting a Latch signal and an SPI communication signal to the T / R chipset; the transmitting circuit is used for receiving the high-voltage trigger signal and generating a high-voltage pulse signal synchronized with the high-voltage trigger signal to the T / R chip set; and the T / R chipset is used for receiving the Latch signal, the SPI communication signal and the high-voltage pulse signal of the SPI communication signal, outputting a low-voltage echo signal to the amplifying circuit and outputting a signal to the phased array ultrasonic transducer. According to the invention, the T / R switch is turned off in a high-voltage transmitting period and turned on in a normal receiving state in a ping-pong mode by utilizing a pre-storing and latching mechanism.

Description

Technical Field

[0001] The present invention relates to the technical field of transceiver switch circuit design, and particularly to a low-power phased array ultrasonic transceiver switch control system. Background Art

[0002] In the field of phased array ultrasonic testing, especially for portable instruments, power consumption is relatively sensitive. Ultrasonic testing generally involves two processes: ultrasonic transmission and ultrasonic reception. For a transceiver integrated device, high voltage to low voltage impact is often achieved through a TR transceiver switch or a clamping diode circuit. However, since the ultrasonic transmission generally has a voltage of up to hundreds of volts, during the transmission stage, part of the transmitted energy will be coupled into the transceiver circuit, resulting in energy loss. Taking a 64-element phased array as an example, according to a 10 mA current of the TR transceiver switch, for a 100 ns pulse width and a 10 KHz pulse repetition frequency (PRF), the energy loss is about 0.5 W.

[0003] Specifically, in the field of phased array ultrasonic testing, the isolation between high-voltage transmission pulses and low-voltage received signals is generally achieved through a T / R transceiver switch chip. The T / R switch uses a constant current source isolation bridge, and utilizes the characteristics of the diode to be reverse cutoff and forward conduction to effectively block the high-voltage transmission pulses of ultrasonic waves and provide a path for low-voltage signals. However, for a transceiver integrated ultrasonic application, in order to save energy or completely isolate the T / R circuit during the retransmission pulse, appropriate means are needed to control the circuit so that the circuit is completely isolated during transmission and weak echo signals can pass through during reception. If not controlled, several problems will arise: 1) power consumption waste; 2) the clamping circuit of high-voltage pulses causes full-amplitude sharp pulses to pour into the subsequent amplification circuit, which has an impact on reliability; 3) precise timing control is required for the channel T / R to turn off and on. The ultrasonic signal generally has a high voltage of dozens to hundreds of volts, and the echo signal is generally between μV and mV. However, for a phased array, the time delay of each wafer is different during each transmission, and the dynamic transformation of whether to transmit or not requires dynamic adjustment means. At the same time, due to the large number of channels in the phased array circuit, such as 32 - 256, the channel configuration is often serial, resulting in a long configuration time and unable to meet the precise switching time.

[0004] In view of this, the present invention provides a low-power phased array ultrasonic transceiver switch control system. Summary of the Invention

[0005] The purpose of the present invention is to provide a low-power phased array ultrasonic transceiver switch control system in view of the deficiencies of the prior art.

[0006] To solve the above technical problems, the following technical solutions are adopted: A low-power phased array ultrasonic transceiver switch control system includes a control circuit, a transmission circuit, and a T / R chip set; Control circuit: It is used to receive the input clock signal CLK, output a high-voltage trigger signal to the transmitting circuit, and output a Latch signal and an SPI communication signal to the T / R chipset; Transmitting circuit: It is used to receive the high-voltage trigger signal and generate a high-voltage pulse signal synchronized with the high-voltage trigger signal to the T / R chipset; T / R chipset: It is used to receive the Latch signal, SPI communication signal and its high-voltage pulse signal, output a low-voltage echo signal to the amplifying circuit, and output a signal to the phased array ultrasonic transducer.

[0007] Based on the above technical solution, a further improvement is that the control circuit includes a control register group, a T / R control circuit and a transmitting pulse generating circuit, The control register group includes a delay window register, a T / R switch register, a control register CTRL, a PRF register and a pulse width register Width; The delay window register is used to output delay parameters to the T / R control circuit; The T / R control circuit is used to output a T / R switch EN signal to the T / R control circuit; The control register CTRL is used to output a transmission enable signal TxEn to the transmitting pulse generating circuit; The PRF register is used to output a pulse repetition frequency to the transmitting pulse generating circuit; The pulse width register Width outputs a pulse width Width to the transmitting pulse generating circuit.

[0008] Based on the above technical solution, a further improvement is that the transmitting pulse generating circuit includes a transmitting pulse delay counter and a pulse width counter, The transmitting pulse delay counter is used to receive the input clock signal, receive the enable signal TxEn of the control register CTRL and receive the pulse repetition frequency of the PRF register; and the transmitting pulse delay counter is used to output a delay trigger signal to the pulse width counter; The pulse width counter is used to receive the input clock signal, receive the delay trigger signal and receive the pulse width Width of the pulse width register Width; and the pulse width counter is used to output a high-voltage trigger signal to the transmitting circuit.

[0009] Based on the above technical solution, a further improvement is that the T / R control circuit includes a T / R delay counter, a control state machine, a data selector and an SPI configuration controller, The T / R delay counter is used to receive the input clock signal, the delay parameter of the delay window register, the enable signal TxEn of the control register CTRL, and the high-voltage trigger signal of the transmit pulse generation circuit; The control state machine is used to receive the input clock signal, the Delay_Finis signal of the T / R delay counter, the enable signal TxEn of the control register CTRL, the high-voltage trigger signal of the transmit pulse generation circuit, and the Cfg_Finis signal of the SPI configuration controller; and its output SEL signal to the data selector, output start signal to the SPI configuration controller, and output Latch signal to the T / R chipset; The data selector is used to receive the SEL signal of the control state machine, receive the DataA signal and the DataB signal; and its output Data signal to the SPI configuration controller; The SPI configuration controller is used for the input clock signal, receive the start signal of the control state machine and the Data signal of the data selector; and its output Cfg_Finis signal to the control state machine and SPI communication signal to the T / R chipset.

[0010] Based on the above technical solution, a further improvement is that the SPI communication input by the T / R chipset can adopt a parallel mode or a cascaded mode.

[0011] Based on the above technical solution, a further improvement is that the control circuit includes a communication interface for reading and writing the register group, the transmit pulse generation circuit, and the transmit pulse generation circuit. The communication interface includes an internal communication bus, an external Uart communication interface, an I2C communication interface, or an SPI communication interface.

[0012] Based on the above technical solution, a further improvement is that the amplifier circuit is used to perform analog amplification on the low-voltage echo signal output by the T / R chipset.

[0013] Due to the above technical solution, the following beneficial effects are achieved: The present invention provides a novel phased array ultrasonic transceiver switch (T / R) control circuit, which realizes the timing coordination of the high-voltage pulse trigger signal, T / R configuration communication, and latching, so as to turn off the T / R switch during high-voltage transmission and turn on the T / R switch during reception, in order to achieve the purpose of reducing power consumption.

[0014] The present invention uses a sequential circuit to implement the transceiver timing of a T / R switch chip, which can be turned off during transmission and turned on during the echo signal period. At the same time, a pre-store - latch (Load-Latch) mechanism is proposed to separate the configuration and activation times, giving the chip more time for configuration, so that the phased array pulse repetition frequency setting is not affected by the communication time of the configured T / R chip.

[0015] The present invention mainly uses a timing control circuit to control the software configuration of a phased array ultrasonic transceiver chip, such as the MAX4936 chip, so that during the high-voltage pulse transmitter period, the TR transceiver is turned off, and after the high-voltage pulse, the transceiver switch is turned on to ensure normal reception of echo signals, which reduces energy loss during transmission in a transceiver integrated application.

[0016] The present invention proposes a pre-store - latch mechanism. Using timing control, the TR chip can first store when idle, and during pulse transmission, load and latch the stored information and lock the output. This mechanism guarantees the communication time and can also output immediately when needed. This method not only ensures that the T / R transceiver is turned off during the high-voltage pulse transmission time interval but also reserves communication time for configuring the transceiver switch chip. Brief Description of the Drawings

[0017] The present invention will be further described below with reference to the accompanying drawings: Figure 1 It is a three-dimensional structural schematic diagram of a low-power phased array ultrasonic transceiver switch control system according to an embodiment of the present invention.

[0018] Figure 2 It is a structural schematic diagram of a control circuit according to an embodiment of the present invention.

[0019] Figure 3 It is a structural schematic diagram of a transmit pulse generation circuit according to an embodiment of the present invention.

[0020] Figure 4 It is a timing diagram of a transmit pulse generation circuit according to an embodiment of the present invention.

[0021] Figure 5 It is a structural schematic diagram of a T / R control circuit according to an embodiment of the present invention.

[0022] Figure 6 It is a timing diagram of a T / R control circuit according to an embodiment of the present invention.

[0023] Figure 7 It is a working principle diagram of a control state machine of a T / R control circuit according to an embodiment of the present invention.

[0024] In the figure: 101 - control circuit; 102 - transmit circuit; 103 - T / R chip group; 104 - amplifier circuit; 105 - phased array ultrasonic transducer. Detailed Embodiments

[0025] To make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below through the accompanying drawings and embodiments as a further explanation of the present invention. However, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the scope of the present invention. In addition, in the following description, the descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention.

[0026] Refer to Figure 1 , a low-power phased array ultrasonic transceiver switch control system, including a control circuit, a transmitting circuit, a T / R chip set, an amplifying circuit and a phased array ultrasonic transducer.

[0027] Control circuit: used to receive the input clock signal CLK, output a high-voltage trigger signal to the transmitting circuit and output a Latch signal and an SPI communication signal to the T / R chip set.

[0028] Transmitting circuit: used to receive the high-voltage trigger signal and generate a high-voltage pulse signal synchronized with the high-voltage trigger signal to the T / R chip set. The high-voltage pulse signal can be a negative pulse, a positive and negative pulse or a pulse train high-voltage pulse signal. The transmitting circuit is generally a high-voltage transmitting pulse integrated chip, such as MAX4940 of Maxim Corporation, etc.

[0029] T / R chip set: used to receive the Latch signal, the SPI communication signal and its high-voltage pulse signal, output a low-voltage echo signal to the amplifying circuit and output a signal to the phased array ultrasonic transducer.

[0030] Specifically, the T / R chip set is a multi-channel transceiver (T / R) switch chip, which can be composed of one or more chips in cascade. Multiple chips can be independently controlled by the control circuit or controlled in a daisy chain manner, such as the MAX4936 chip of Maxim Corporation.

[0031] The amplifying circuit is used to perform analog amplification on the low-voltage echo signal output by the T / R chip set.

[0032] The amplifying circuit is an echo circuit, generally composed of several amplifiers, which can be built with discrete amplifiers or can use an integrated analog front-end chip AFE, such as AFE5816 of TI, etc.

[0033] The phased array ultrasonic transducer is a 64-line array transducer, etc.

[0034] The present invention provides a novel phased array ultrasonic transceiver switch (T / R) control circuit. By coordinating the timing of high-voltage pulse trigger signals, T / R configuration communication, and latching, the T / R switch is turned off during high-voltage transmission and turned on during reception, so as to achieve the purpose of reducing power consumption.

[0035] As a further description of this embodiment, the schematic diagram of the control circuit is as Figure 2 shown. The control circuit includes a control register group inside the FPGA or CPLD, a T / R control circuit, and a transmit pulse generation circuit.

[0036] The control register group includes a delay window register, a T / R switch register, a control register CTRL, a PRF register, and a pulse width register Width.

[0037] The delay window register is used to output delay parameters to the T / R control circuit.

[0038] The T / R control circuit is used to output the T / R switch EN signal to the T / R control circuit.

[0039] The control register CTRL is used to output the transmit enable signal TxEn to the transmit pulse generation circuit.

[0040] The PRF register is used to output the pulse repetition frequency to the transmit pulse generation circuit.

[0041] The pulse width register Width outputs the pulse width Width to the transmit pulse generation circuit.

[0042] As a further description of this embodiment, the control circuit further includes a communication interface for reading and writing the register group, the transmit pulse generation circuit, and the transmit pulse generation circuit inside the FPGA or CPLD. The communication interface includes an internal communication bus, an external Uart communication interface, an I2C communication interface, or an SPI communication interface.

[0043] Referring to Figure 2 , the trigger signal Trig is Figure 1 the Trig signal of the transmit circuit in

[0044] Latch and SPI communication serve as Figure 1 the inputs of the T / R chip group in

[0045] for configuring the T / R chip group and inputting the Latch signal of the T / R chip group. The SPI communication input to the T / R chip group can be in parallel or cascade mode. This invention only illustrates with 1 T / R chip.

[0046] The control circuit includes a control register group and its functional circuits (T / R control circuit and transmit pulse generation circuit) inside the FPGA or CPLD. Among them, there is a high-voltage trigger signal, and the pulse repetition frequency (PRF register) and pulse width (pulse width register Width) of the high-voltage trigger signal can be set. For example, a PRF of 2KHz and a pulse width of 100ns. The T / R control circuit takes the value of the delay window register, the T / R switch enable register, and the switch enable signal as inputs, and generates a timing circuit based on the Trig signal as a reference to complete the timing configuration of the T / R chipset, and turns off the T / R function during the high-voltage pulse emission to achieve the purpose of low-power design.

[0047] As a further description of this embodiment, the transmit pulse generation circuit includes a transmit pulse delay counter and a pulse width counter. The transmit pulse delay counter is used to receive the input clock signal, the enable signal TxEn of the control register CTRL, and the pulse repetition frequency of the PRF register; and the transmit pulse delay counter is used to output a delay trigger signal to the pulse width counter. The pulse width counter is used to receive the input clock signal, the delay trigger signal, and the pulse width Width of the pulse width register Width; and the pulse width counter is used to output a high-voltage trigger signal to the transmit circuit.

[0048] See Figure 3 For the structural block diagram of the transmit pulse generation circuit. After the transmit enable TxEn is valid, the delay counter counts according to the clock counting period obtained by the reciprocal conversion of the PRF register. After the counting is completed, a single-cycle delay trigger signal is generated. The pulse width counter starts counting at the rising edge of the delay trigger signal according to the pulse width value and outputs a high level until the pulse width counter finishes counting and outputs a low level. Its timing diagram is as Figure 4 shown.

[0049] As a further description of this embodiment, see Figure 5 For the structural block diagram of the T / R control circuit. The T / R control circuit includes a T / R delay counter, a control state machine, a data selector, and an SPI configuration controller. The T / R delay counter starts counting at the rising edge of the Trig signal (high-voltage trigger signal) when EN is at a high level, and the counted value is the number of clock cycles of Delay[15:0]. Assuming the PRF is 1KHz, the trigger period is 1ms, then the Delay value is the value of 1ms - ta time ( Figure 6 ta in

[0050] The T / R delay counter is used to receive the input clock signal, the delay parameter of the delay window register, the enable signal TxEn of the control register CTRL, and the high-voltage trigger signal of the transmit pulse generation circuit; The control state machine is used to receive the input clock signal, the Delay_Finis signal of the T / R delay counter, the enable signal TxEn of the control register CTRL, the high-voltage trigger signal of the transmit pulse generation circuit, and the Cfg_Finis signal of the SPI configuration controller; and output the SEL signal to the data selector, output the start signal to the SPI configuration controller, and output the Latch signal to the T / R chipset; The data selector is used to receive the SEL signal of the control state machine, receive the DataA signal and the DataB signal; and output the Data signal to the SPI configuration controller; The SPI configuration controller is used for the input clock signal, receive the start signal of the control state machine and the Data signal of the data selector; and output the Cfg_Finis signal to the control state machine and the SPI communication signal to the T / R chipset.

[0051] As a further description of this embodiment, the SPI communication input by the T / R chipset can adopt a parallel mode or a cascade mode.

[0052] The control state machine is as Figure 7 shown, and the behavior of this control state machine can be established as: IDLE: Idle state.

[0053] S0: When EN is high-level effective and the rising edge of the Trig signal occurs, it enters the high-voltage trigger state, and at this moment the high-voltage pulse is effective. When the falling edge of the Trig signal appears, it enters the S1 state.

[0054] S1: The S1 state is Figure 6 the Latch_after state in

[0055] S2: S2 is in the waiting state, counting with its value being the count value Delay[15:0] of the delay window register. When the count reaches 0, the Delay_Finis signal is generated. When the Delay_Finis signal is generated, the state machine enters state 3. Assuming the PRF is 1KHz and the trigger period is 1ms. Then the delay corresponding to Delay[15:0] is the value of 1ms - ta. The SPI configuration communication time should be less than the sum of ta and the pulse width time.

[0056] S3: The S1 state is Figure 6 the Latch_pre state in, and the Latch latch signal will be output. At this time, the T / R chip will obtain the T / R switch state control signal of DataB. Under normal circumstances, the T / R switch state of DataB is in the OFF state. The state machine directly enters the S4 state in the next beat.

[0057] S4: The S state is the waiting state. If the EN signal is invalid (low level), it enters the IDLE state. If the rising edge of Trig arrives, it enters the S0 state.

[0058] Looping in this way, the states of DataA and DataB are configured in a ping-pong manner. DataA is the T / R channel switch state of the T / R chip during the high-voltage trigger period, and DataB is the T / R channel switch state of the T / R chip during the echo reception period.

[0059] As a further description of this embodiment, for the two states of DataA and DataB, the number of states can be increased or decreased, and the control state machine can be adjusted.

[0060] The present invention utilizes the pre-storage and latch mechanisms to achieve turning off the T / R switch during the high-voltage transmission period and turning on the T / R switch during the normal reception state in a ping-pong manner.

[0061] The above are only specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent replacements, or modifications made based on the present invention to solve substantially the same technical problems and achieve substantially the same technical effects are all covered by the protection scope of the present invention.

Claims

1. A low-power phased array ultrasonic transceiver switch control system, characterized in that It includes a control circuit, a transmitting circuit, and a T / R chipset; The control circuit: is used to receive an input clock signal CLK, output a high-voltage trigger signal to the transmitting circuit, and output a Latch signal and an SPI communication signal to the T / R chipset; The transmitting circuit: is used to receive the high-voltage trigger signal and generate a high-voltage pulse signal synchronized with the high-voltage trigger signal to the T / R chipset; The T / R chipset: is used to receive the Latch signal, the SPI communication signal, and its high-voltage pulse signal, output a low-voltage echo signal to an amplifier circuit, and output a signal to a phased array ultrasonic transducer.

2. The low-power phased array ultrasonic transceiver switch control system according to claim 1, wherein: The control circuit includes a control register group, a T / R control circuit, and a transmitting pulse generation circuit. The control register group includes a delay window register, a T / R switch register, a control register CTRL, a PRF register, and a pulse width register Width; The delay window register is used to output a delay parameter to the T / R control circuit; The T / R control circuit is used to output a T / R switch EN signal to the T / R control circuit; The control register CTRL is used to output a transmit enable signal TxEn to the transmitting pulse generation circuit; The PRF register is used to output a pulse repetition frequency to the transmitting pulse generation circuit; The pulse width register Width outputs a pulse width Width to the transmitting pulse generation circuit.

3. A low-power phased array ultrasonic transceiver switch control system according to claim 2, characterized in that: The transmitting pulse generation circuit includes a transmitting pulse delay counter and a pulse width counter. The transmitting pulse delay counter is used to receive the input clock signal, receive the enable signal TxEn of the control register CTRL, and receive the pulse repetition frequency of the PRF register; and the transmitting pulse delay counter is used to output a delay trigger signal to the pulse width counter; The pulse width counter is used to receive the input clock signal, receive the delay trigger signal, and receive the pulse width Width of the pulse width register Width; and the pulse width counter is used to output a high-voltage trigger signal to the transmitting circuit.

4. The low-power phased array ultrasonic transceiver switch control system according to claim 2, characterized in that: The T / R control circuit includes a T / R delay counter, a control state machine, a data selector, and an SPI configuration controller. The T / R delay counter is used to receive the input clock signal, receive the delay parameter of the delay window register, receive the enable signal TxEn of the control register CTRL, and receive the high-voltage trigger signal of the transmitting pulse generation circuit; The control state machine is used to receive the input clock signal, receive the Delay_Finis signal of the T / R delay counter, receive the enable signal TxEn of the control register CTRL, receive the high-voltage trigger signal of the transmitting pulse generation circuit, and the Cfg_Finis signal of the SPI configuration controller; and output a SEL signal to the data selector, output a start signal to the SPI configuration controller, and output a Latch signal to the T / R chipset; The data selector is used to receive the SEL signal of the control state machine, receive DataA signal and DataB signal; and output a Data signal to the SPI configuration controller; The SPI configuration controller is used for the input clock signal, receives the start signal of the control state machine and the Data signal of the data selector; and outputs the Cfg_Finis signal to the control state machine and the SPI communication signal to the T / R chipset.

5. A low-power phased array ultrasonic transceiver switch control system according to claim 1 or 2, characterized in that: The SPI communication input by the T / R chipset can adopt a parallel mode or a cascade mode.

6. A low-power phased array ultrasonic transceiver switch control system according to claim 2, characterized in that: The control circuit includes a communication interface for reading and writing the register bank, the transmit pulse generation circuit and the transmit pulse generation circuit. The communication interface includes an internal communication bus, an external Uart communication interface, an I2C communication interface or an SPI communication interface.

7. A low-power phased array ultrasonic transceiver switch control system according to claim 2, characterized in that: The amplifier circuit is used for analog amplification of the low-voltage echo signal output by the T / R chipset.

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