Memory scheduling device and memory scheduling method

Abstract

The memory scheduling device comprises a preprocessing storage device, a selector, a current storage device and an arbiter. The pre-processing storage device provides a plurality of primary commands and a plurality of secondary commands. The selector selects the plurality of primary commands and / or the plurality of secondary commands according to a selection signal. The current storage device receives the plurality of primary commands and / or the plurality of secondary commands transmitted by the selector. The arbiter calculates predicted burst lengths corresponding to the plurality of main commands expected to be received by the current storage device in advance according to the polling sequence, and if the predicted burst lengths corresponding to the plurality of main commands are smaller than a threshold burst length, the arbiter transmits a selection signal to the selector. The pre-processing storage device transmits a part of the plurality of primary commands and at least one secondary command of the plurality of secondary commands to the current storage device through the selector.

Description

Technical Field

[0001] The present invention relates to a memory scheduling device and a memory scheduling method, and more particularly to a memory scheduling device and a memory scheduling method for determining whether to transmit a primary command and / or a secondary command based on a predicted burst length. Background Art

[0002] In dynamic random-access memory (DRAM), the Four Active Window (tFAW) is a DRAM timing parameter that represents the window period for accessing the four memory banks. DRAM efficiency may be affected by restrictions related to tFAW. Summary of the Invention

[0003] In view of the deficiencies of the prior art, one of the objectives of this application is (but not limited to) to provide a memory scheduling device and a memory scheduling method to improve the deficiencies of the prior art.

[0004] In some embodiments, the memory scheduling device includes a pre-processing storage device, a selector, a current storage device, and an arbiter. The pre-processing storage device is used to provide a plurality of primary commands and a plurality of secondary commands. The selector is coupled to the pre-processing storage device and is used to select the plurality of primary commands and / or the plurality of secondary commands according to a selection signal. The current storage device is coupled to the selector and receives the plurality of primary commands and / or the plurality of secondary commands transmitted by the selector. The arbiter is used to pre-calculate the predicted burst length corresponding to the plurality of primary commands that the current storage device is expected to receive according to a polling order. If the predicted burst length corresponding to the plurality of primary commands is less than a threshold burst length, the arbiter transmits a selection signal to the selector so that the pre-processing storage device transmits part of the plurality of primary commands and at least one secondary command of the plurality of secondary commands to the current storage device through the selector.

[0005] In some embodiments, a memory scheduling method includes: precalculating, via an arbiter, predicted burst lengths corresponding to a plurality of primary commands that a current storage device is expected to receive based on a polling order; transmitting, via the arbiter, a selection signal to a selector if the predicted burst lengths corresponding to the plurality of primary commands are less than a threshold burst length; and transmitting, via a pre-processing storage device, a portion of the plurality of primary commands and at least one secondary command from a plurality of secondary commands to the current storage device via the selector.

[0006] The technical means embodied in the embodiments of this case can improve at least one of the disadvantages of the prior art. The memory scheduling device and memory scheduling method of this case can know in advance which main commands the current storage device has received according to the polling order, and calculate the predicted burst lengths corresponding to these main commands. If the predicted burst length is less than the threshold burst length, it may cause the memory access to be affected by the tFAW limit in terms of utilization rate (DRAM Utilization). At this time, this case can transmit a selection signal to the selector, so that the preprocessing storage device transmits a secondary command through the selector to replace one of the original main commands to be transmitted. In this way, the predicted burst lengths corresponding to all commands (including main and secondary commands) will be greater than or equal to the threshold burst length, thereby avoiding the situation of decreased memory utilization rate.

[0007] Regarding the features, implementation and effects of this case, the following provides a detailed description of the preferred embodiments in conjunction with the accompanying drawings. Description of the Drawings

[0008] Figure 1 It is a schematic diagram of a memory scheduling device drawn according to some embodiments of this case;

[0009] Figure 2 It is a flowchart of a memory scheduling method drawn according to some embodiments of this case;

[0010] Figure 3 It is an operation schematic diagram of a memory scheduling device drawn according to some embodiments of this case;

[0011] Figure 4 It is an operation schematic diagram of a memory scheduling device drawn according to some embodiments of this case;

[0012] Figure 5 It is an operation schematic diagram of a memory scheduling device drawn according to some embodiments of this case;

[0013] Figure 6 It is an operation schematic diagram of a memory scheduling device drawn according to some embodiments of this case;

[0014] Figure 7 It is an operation schematic diagram of a memory scheduling device drawn according to some embodiments of this case; and

[0015] Figure 8 It is a partial structural schematic diagram of a memory scheduling device drawn according to some embodiments of this case. Detailed Description of the Specific Embodiments

[0016] All the terms used in this document have their ordinary meanings. The definitions of the above terms in commonly used dictionaries, including examples of the use of any of the terms discussed herein, are for illustration only and should not limit the scope and meaning of this case. Similarly, this case is not limited to the various embodiments shown in this specification.

[0017] Regarding the use of "coupled" or "connected" in this document, it can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, and can also refer to two or more components operating or acting on each other. As used herein, the term "circuit" can be a device that processes signals by connecting at least one transistor and / or at least one active or passive component in a certain manner.

[0018] As used herein, the term "and / or" includes any combination of one or more of the listed related items. In this document, the use of terms such as first, second, and third, etc. is used to describe and distinguish each component. Therefore, the first component in this document can also be called the second component without departing from the intention of this case. For ease of understanding, similar components in each figure will be designated with the same reference numerals.

[0019] To improve the problem that the efficiency of dynamic random-access memory (DRAM) is affected due to the relevant regulations of the Four Active Window (tFAW) in the prior art, this case proposes a memory scheduling device and a memory scheduling method, which are described in detail as follows.

[0020] Figure 1 To draw a schematic diagram of a memory scheduling device 100 according to some embodiments of this case. As shown in the figure, the memory scheduling device 100 includes a preprocessing storage device 110, a selector 120, a current storage device 130, an arbiter 140, a multiplexer 150, and a scheduler 160.

[0021] In some embodiments, the selector 120 is coupled to the preprocessing storage device 110, the current storage device 130 is coupled to the selector 120, the arbiter 140, and the multiplexer 150, and the multiplexer 150 is coupled to the arbiter 140 and the scheduler 160. The preprocessing storage device 110 is configured to provide a plurality of primary commands Am1-Am n and a plurality of secondary commands As1-As n. The selector 120 is configured to select the primary commands Am1-Am n and / or the secondary commands As1-As n according to the selection signal Ssel. The current storage device 130 is configured to receive the primary commands Am1-Am n and / or the secondary commands As1-As n transmitted by the selector 120. The multiplexer 150 transmits the primary commands Am1-Am n and / or the secondary commands As1-As n received by the current storage device 130 to the scheduler 160 according to the selection signal Ssel for the scheduler 160 to execute.

[0022] To facilitate understanding of the operation of the memory scheduling device 100 of this case, please also refer to Figure 2 , Figure 2 FIG. is a flowchart of a memory scheduling method 200 according to some embodiments of this case. In step 210, the arbiter 140 pre-computes the predicted burst lengths corresponding to a plurality of primary commands Am1-Am4 that the current storage device 130 is expected to receive according to the polling order. For example, the arbiter 140 can pre-know, according to the round-robin order, a plurality of primary commands Am1-Am4 that the preprocessing storage device 110 will transmit to the current storage device 130. Therefore, the arbiter 140 can pre-compute the predicted burst lengths corresponding to the plurality of primary commands Am1-Am4 that the current storage device 130 is expected to receive.

[0023] The following is combined with Figures 3 to 7 to illustrate the operation of the memory scheduling device 100. Figures 3 to 7 FIG. is a schematic diagram of the operation of a memory scheduling device 100 according to some embodiments of this case. As Figure 3 shown, this is a schematic diagram of four active windows (tFAW) executed by the current storage device 130. There is a tFAW window between commands A1-A5, which corresponds to the total burst length. In this embodiment, the total burst length is greater than or equal to the threshold burst length. Therefore, although the subsequent command A5 will be delayed (and the data corresponding to A5 will also be delayed), since there is still a large amount of data to be processed for accessing the DRAM, the high utilization rate of the DRAM Data Bus can continue until the data access corresponding to A5. The calculation formula of the above threshold burst length is as follows:

[0024] 〖BS〗_th = RU(tFAW / tCK)×2×4(DQ / 8)… Formula 1

[0025] As shown in Equation 1, 〖BS〗_th represents the threshold burst length, and tFAW represents the tFAW window. In addition, the calculation formula for the block size of a Dynamic Random-Access Memory (DRAM) is as follows:

[0026] B_size = BL × (DQ / 8) … Equation 2

[0027] As shown in Equation 2, B_size represents the block size, and BL represents the burst length. For example, assuming that the CKR (WCK:CK) of the Low Power Double Data Rate 5 (LPDDR5)-6400 is 4:1, DQ is 16 (bit), and tFAW is 20 (ns), substituting into Equation 1 and Equation 2 is as follows:

[0028] 〖BS〗_th = RU(20 / 1.25) × 2 × 4 × (16 / 8) = 256 (B)

[0029] B_size = 16 × (16 / 8) = 32 (B)

[0030] In another example, assuming that the CKR of the LPDDR5-6400 is 4:1, DQ is 32, and tFAW is 20, substituting into Equation 1 and Equation 2 is as follows:

[0031] 〖BS〗_th = RU(20 / 1.25) × 2 × 4 × (32 / 8) = 512 (B)

[0032] B_size = 16 × (32 / 8) = 64 (B)

[0033] Please refer to Figure 4 , since the total burst length is less than the threshold burst length, therefore, the subsequent command A5 will be delayed, and the data corresponding to the command A5 will also be executed later, resulting in discontinuous data. Figure 5 For one refresh occurring in the tFAW window, it can be seen from the figure that the refresh will cause more serious discontinuous data.

[0034] To improve the discontinuous data caused by command delay, in this case, the arbiter 140 can pre-determine multiple main commands Am1 to Am4 that the preprocessing storage device 110 will transmit to the current storage device 130 according to the polling order, and calculate the predicted burst lengths corresponding to the multiple main commands Am1 to Am4. Subsequently, in this case, corresponding adjustments can be made according to the above predicted burst lengths to avoid command delay, and the detailed description is as follows.

[0035] Please refer back to Figure 1 and Figure 2 , in step 220, if the predicted burst lengths corresponding to multiple main commands Am1-Am4 are less than the threshold burst length, the arbitration unit 140 transmits a selection signal Ssel to the selector 120. In step 230, a part of the main commands (such as main commands Am2-Am4) among the multiple main commands Am1-Am4 and at least one secondary command (such as secondary command As1) among the multiple secondary commands As1-Asn are transmitted to the current storage device 130 via the preprocessing storage device 110 through the selector 120.

[0036] Please refer to Figure 1 and Figure 6 , for example, if the predicted burst length is less than the threshold burst length, it may cause command delay, which in turn leads to data discontinuity. At this time, the arbitration unit 140 transmits the selection signal Ssel to the selector 120 to select the secondary command As1 from the main command Am1 and the secondary command As1. In other words, the secondary command As1 replaces the main command Am1. Subsequently, the preprocessing storage device 110 transmits a part of the main commands Am2-Am4 among the main commands Am1-Am4 and at least one secondary command As1 among the secondary commands As1-Asn to the current storage device 130 through the selector 120. In this way, the predicted burst lengths corresponding to a part of the main commands Am2-Am4 and at least one secondary command As1 will no longer be less than the threshold burst length, thereby avoiding command delay and the resulting data discontinuity.

[0037] In some embodiments, the current burst lengths corresponding to a part of the main commands Am2-Am4 among the main commands Am1-Am4 and at least one secondary command As1 among the secondary commands As1-Asn are greater than or equal to the threshold burst length. In other words, the current burst length after replacing the main command Am1 with the secondary command As1 will be greater than or equal to the threshold burst length, thereby avoiding command delay and the resulting data discontinuity.

[0038] Please refer to Figure 7 , when a refresh occurs in the tFAW window, as can be seen from the figure, the refresh will cause more serious data discontinuity. In this case, the arbitration unit 140 can also transmit the selection signal Ssel to the selector 120 to select the secondary command As1. In other words, the secondary command As1 replaces the main command Am1 to avoid command delay and the resulting data discontinuity.

[0039] Please refer back to Figure 1, in some embodiments, the arbiter 140 pre-computes the predicted burst lengths corresponding to the four main commands Am1-Am4 that the current storage device 130 is expected to receive according to a round-robin order and according to the Four Active Window (tFAW) limit. If the predicted burst lengths corresponding to the four main commands Am1-Am4 are less than the threshold burst length, the arbiter 140 transmits a selection signal Ssel to the selector 120, so that the pre-processing storage device 110 transmits, through the selector 120 according to the tFAW limit, some of the four main commands Am2-Am4 among the four main commands Am1-Am4 and at least one of the secondary commands As1-Asn, i.e., As1, to the current storage device 130.

[0040] In some embodiments, the pre-processing storage device 110 includes a main queue pool 111 and a secondary queue pool 113. The main queue pool 111 is used to provide the main commands Am1-Am n. The secondary queue pool 113 is used to provide the secondary commands As1-Asn. The arbiter 140 is used to pre-compute the predicted burst lengths corresponding to the default number of main commands (e.g., 4 main commands) that the main queue pool 111 is expected to transmit to the current storage device 130 according to a round-robin order.

[0041] If the predicted burst lengths corresponding to the default number of main commands (e.g., 4 main commands) are less than the threshold burst length, the arbiter 140 transmits a selection signal Ssel to the selector 120, so that the main queue pool 111 transmits, through the selector 120, some of the main commands Am2-Am4 among the main commands Am1-Am4 to the current storage device 130, and the secondary queue pool 113 transmits, through the selector 120, at least one of the secondary commands As1-Asn, i.e., As1, to the current storage device 130. The total number of some of the main commands Am2-Am4 among the main commands Am1-Am4 and at least one of the secondary commands As1-Asn, i.e., As1, is a preset number (e.g., 4).

[0042] In some embodiments, the main queue pool 111 includes a plurality of main queues Bm1-Bmn, the secondary queue pool 113 includes a plurality of secondary queues Bs1-Bsn, and the selector 120 includes a plurality of multiplexers MUX1-MUXn. At least one of the multiplexers MUX1-MUXn, i.e., MUX1, is coupled to at least one of the main queues Bm1-Bmn, i.e., Bm1, and at least one of the secondary queues Bs1-Bsn, i.e., Bs1.

[0043] If the predicted burst length corresponding to the default number of main commands (e.g., 4 main commands) is less than the threshold burst length, the arbiter 140 transmits a selection signal Ssel to at least one multiplexer MUX1 among the multiplexers MUX1 to MUXn of the selector 120. At least one multiplexer MUX1 among the multiplexers MUX1 to MUXn prohibits at least one main queue Bm1 in the main queue pool 111 from transmitting the main command Am1 to the current storage device 130. At least one multiplexer MUX1 among the multiplexers MUX1 to MUXn allows at least one secondary queue Bs1 in the secondary queue pool 113 to transmit at least one secondary command As1 among the secondary commands As1 to Asn to the current storage device 130.

[0044] In some embodiments, each of the multiplexers MUX1 to MUXn is coupled to one of the main queues Bm1 to Bmn and one of the secondary queues Bs1 to Bsn. For example, multiplexer MUX1 is coupled to main queue Bm1 and secondary queue Bs1, multiplexer MUX2 is coupled to main queue Bm2 and secondary queue Bs2, and so on.

[0045] If the predicted burst length corresponding to the default number of main commands (e.g., 4 main commands) is less than the threshold burst length, the arbiter 140 transmits a selection signal Ssel to at least one multiplexer MUX1 among the multiplexers MUX1 to MUX4 of the selector 120. At least one multiplexer MUX1 among the multiplexers MUX1 to MUX4 prohibits at least one main queue Bm1 among the main queues Bm1 to Bm4 from transmitting the main command Am1 to the current storage device 130. The other multiplexers MUX2 to MUX4 among the multiplexers MUX1 to MUX4 allow at least one of the main queues Bm2 to Bm4 other than at least one main queue Bm1 among the main queues Bm1 to Bm4 to transmit some of the main commands Bm2 to Bm4 among the main commands Bm1 to Bm4 to the current storage device 130. At least one multiplexer MUX1 among the multiplexers MUX1 to MUX4 allows at least one secondary queue Bs1 among the secondary queues Bs1 to Bs4 to transmit at least one secondary command As1 among the secondary commands As1 to As4 to the current storage device 130.

[0046] Figure 8 To draw one according to some embodiments of the present case Figure 1Partial structural schematic diagram of the memory scheduling device 100. As shown in the figure, the main queue pool 111 includes a first main queue Bm1, a second main queue Bm2, a third main queue Bm3, and a fourth main queue Bm4. The secondary queue pool 113 includes a first secondary queue Bs1, a second secondary queue Bs2, a third secondary queue Bs3, and a fourth secondary queue Bs4. The selector 120 includes a first multiplexer MUX1, a second multiplexer MUX2, a third multiplexer MUX3, and a fourth multiplexer MUX4.

[0047] The first main queue Bm1 is used to provide the first main command Am1 among the main commands Am1 to AM4, the second main queue Bm2 is used to provide the second main command Am2 among the main commands Am1 to AM4, the third main queue Bm3 is used to provide the third main command Am3 among the main commands Am1 to AM4, and the fourth main queue Bm4 is used to provide the fourth main command Am4 among the main commands Am1 to AM4. The first secondary queue Bs1 is used to provide the first secondary command As1 among the secondary commands As1 to As4, the second secondary queue Bs2 is used to provide the second secondary command As2 among the secondary commands As1 to As4, the third secondary queue Bs3 is used to provide the third secondary command As3 among the secondary commands As1 to As4, and the fourth secondary queue Bs4 is used to provide the fourth secondary command As4 among the secondary commands As1 to As4.

[0048] The first multiplexer MUX1 is coupled to the first main queue Bm1 and the first secondary queue Bs1, and transmits the first main command Am1 or the first secondary command As1 according to the selection signal Ssel. The second multiplexer MUX2 is coupled to the second main queue Bm2 and the second secondary queue Bs2, and transmits the second main command Am2 or the second secondary command As2 according to the selection signal Ssel. The third multiplexer MUX3 is coupled to the third main queue Bm3 and the third secondary queue Bs3, and transmits the third main command Am3 or the third secondary command As3 according to the selection signal Ssel. The fourth multiplexer MUX4 is coupled to the fourth main queue Bm4 and the fourth secondary queue Bs4, and transmits the fourth main command Am4 or the fourth secondary command As4 according to the selection signal Ssel.

[0049] In some embodiments, the arbiter 140 pre-computes the predicted burst lengths corresponding to the first main command Am1 of the first main queue B1m, the second main command Am2 of the second main queue Bm2, the third main command Am3 of the third main queue Bm3, and the fourth main command Am4 of the fourth main queue Bm4 that the current storage device 130 is expected to receive according to the polling order.

[0050] If the predicted burst lengths corresponding to the first major command Am1, the second major command Am2, the third major command Am3, and the fourth major command Am4 are less than the threshold burst length, the arbiter 130 transmits the selection signal Ssel to the first multiplexer MUX1, the second multiplexer MUX2, the third multiplexer MUX3, and the fourth multiplexer MUX4 of the selector 120, so that the first minor queue Bs1 transmits the first minor command As1 to the current storage device 130 through the first multiplexer MUX1, the second major queue Bm2 transmits the second major command Am2 to the current storage device 130 through the second multiplexer MUX2, the third major queue Bm3 transmits the third major command Am3 to the current storage device 130 through the third multiplexer MUX3, and the fourth major queue Bm4 transmits the fourth major command Am4 to the current storage device 130 through the fourth multiplexer MUX4.

[0051] In some embodiments, the current burst lengths corresponding to the first minor command As1 of the first minor queue Bs1, the second major command Am2 of the second major queue Bm2, the third major command Am3 of the third major queue Bm3, and the fourth major command Am4 of the fourth major queue Bm4 are greater than or equal to the threshold burst length.

[0052] In some embodiments, the major queue pool 111 of the preprocessing storage device 110 receives the major commands Am1-Am n through the major data access interface, and the minor queue pool 113 of the preprocessing storage device 110 receives the minor commands As1-As n through the direct memory access interface.

[0053] It should be noted that this case is not limited to the embodiments shown in FIGS. 1 to 8. It is only used to illustratively show one of the implementation manners of this case to make the technology of this case easy to understand. The patent scope of this case shall be subject to the scope of the invention patent application. Those skilled in the art, without departing from the spirit of this case, the modifications and refinements made to the embodiments of this case still fall within the scope of the invention patent application of this case.

[0054] In summary, the technical means embodied in the embodiments of this case can improve at least one of the disadvantages of the prior art. The memory scheduling device and the memory scheduling method of this case can, according to the polling order, pre-determine which main commands the current storage device has received, and calculate the predicted burst lengths corresponding to these main commands. If the predicted burst length is less than the threshold burst length, the main command may be delayed due to tFAW, resulting in a discontinuous data transmission situation before the data is accessed accordingly. At this time, this case can transmit a selection signal to the selector, so that the preprocessing storage device transmits a secondary command through the selector to replace one of the originally to-be-transmitted main commands. In this way, the predicted burst lengths corresponding to all commands (including main and secondary commands) will be greater than or equal to the threshold burst length, thereby avoiding the occurrence of a discontinuous data transmission situation before the command is delayed and the data is accessed accordingly.

[0055] Although the embodiments of this case are as described above, these embodiments are not used to limit this case. Those with ordinary knowledge in the technical field can make changes to the technical features of this case based on the explicit or implicit content of this case. All such changes may fall within the scope of patent protection sought by this case. In other words, the scope of patent protection of this case shall be determined by the scope of patent application defined in this specification.

[0056]

Symbol Explanation

[0057] 100: Memory Scheduling Device

[0058] 110: Preprocessing Storage Device

[0059] 111: Main Queue Pool

[0060] 113: Secondary Queue Pool

[0061] 120: Selector

[0062] 130: Current Storage Device

[0063] 140: Arbiter

[0064] 150: Multiplexer

[0065] 160: Scheduler

[0066] 200: Method

[0067] 210~230: Steps

[0068] Bm0~Bmn: Main Queues

[0069] Bs0~Bsn: Secondary Queues

[0070] BS: Burst Length

[0071] Am1 to Amn: Main commands

[0072] As1 to Asn: Secondary commands

[0073] MUX1 to MUSn: Multiplexers

[0074] Ssel: Selection signal

Claims

1. A memory scheduling device, comprising: A preprocessing storage device for providing a plurality of primary commands and a plurality of secondary commands; A selector coupled to the preprocessing storage device and configured to select the plurality of primary commands and / or the plurality of secondary commands according to a selection signal; A current storage device coupled to the selector and configured to receive the plurality of primary commands and / or the plurality of secondary commands transmitted by the selector; And An arbiter for pre-computing a predicted burst length corresponding to the plurality of primary commands expected to be received by the current storage device according to a polling order. If the predicted burst length corresponding to the plurality of primary commands is less than a threshold burst length, the arbiter transmits the selection signal to the selector, so that the preprocessing storage device transmits, through the selector, some of the plurality of primary commands and at least one of the plurality of secondary commands to the current storage device.

2. The memory scheduling device according to claim 1, wherein a current burst length corresponding to some of the plurality of primary commands and at least one of the plurality of secondary commands is greater than or equal to the threshold burst length.

3. The memory scheduling device according to claim 1, wherein the arbiter pre-computes the predicted burst length corresponding to the plurality of primary commands expected to be received by the current storage device according to the polling order and according to a Four Active Window (tFAW) limit; Wherein if the predicted burst length corresponding to the plurality of primary commands is less than the threshold burst length, the arbiter transmits the selection signal to the selector, so that the preprocessing storage device transmits, through the selector, some of the plurality of primary commands and at least one of the plurality of secondary commands to the current storage device according to the Four Active Window limit.

4. The memory scheduling device according to claim 1, wherein the preprocessing storage device comprises: A primary queue pool for providing the plurality of primary commands; And A secondary queue pool for providing the plurality of secondary commands; Wherein the arbiter is configured to pre-compute the predicted burst length corresponding to a preset number of the plurality of primary commands expected to be transmitted from the primary queue pool to the current storage device according to the polling order; Wherein if the predicted burst length corresponding to the preset number of the plurality of primary commands is less than the threshold burst length, the arbiter transmits the selection signal to the selector, so that the primary queue pool transmits, through the selector, some of the plurality of primary commands to the current storage device, and the secondary queue pool transmits, through the selector, at least one of the plurality of secondary commands to the current storage device, and a total number of some of the plurality of primary commands and at least one of the plurality of secondary commands is the preset number.

5. The memory scheduling device according to claim 4, wherein the main queue pool includes a plurality of main queues, the secondary queue pool includes a plurality of secondary queues, and the selector includes a plurality of multiplexers, wherein at least one of the plurality of multiplexers is coupled to at least one of the plurality of main queues and at least one of the plurality of secondary queues; Wherein if the predicted burst length corresponding to the default number of the plurality of main commands is less than the threshold burst length, the arbiter transmits the selection signal to at least one of the plurality of multiplexers of the selector, and at least one of the plurality of multiplexers prohibits at least one of the main queues in the main queue pool from transmitting the main command to the current storage device, and at least one of the plurality of multiplexers allows at least one of the secondary queues in the secondary queue pool to transmit at least one of the plurality of secondary commands to the current storage device.

6. The memory scheduling device according to claim 5, wherein each of the plurality of multiplexers is coupled to one of the plurality of main queues and one of the plurality of secondary queues; If the predicted burst length corresponding to the default number of the plurality of main commands is less than the threshold burst length, the arbiter transmits the selection signal to at least one of the plurality of multiplexers of the selector, and at least one of the plurality of multiplexers prohibits at least one of the main queues in the plurality of main queues from transmitting the main command to the current storage device, and some of the multiplexers other than at least one of the plurality of multiplexers allow some of the main queues other than at least one of the plurality of main queues to transmit some of the plurality of main commands to the current storage device, and at least one of the plurality of multiplexers allows at least one of the plurality of secondary queues to transmit at least one of the plurality of secondary commands to the current storage device.

7. The memory scheduling device according to claim 1, wherein the preprocessing storage device includes: A main queue pool, including: A first main queue for providing a first main command among the plurality of main commands; A second main queue for providing a second main command among the plurality of main commands; A third main queue for providing a third main command among the plurality of main commands; and A fourth main queue for providing a fourth main command among the plurality of main commands; and A secondary queue pool, including: A first secondary queue for providing a first secondary command among the plurality of secondary commands; A second secondary queue for providing a second secondary command among the plurality of secondary commands; A third secondary queue for providing a third secondary command among the plurality of secondary commands; and A fourth secondary queue for providing a fourth secondary command among the plurality of secondary commands; Wherein the selector includes: The first multiplexer is coupled to the first main queue and the first secondary queue, and transmits the first main command or the first secondary command according to the selection signal; The second multiplexer is coupled to the second main queue and the second secondary queue, and transmits the second main command or the second secondary command according to the selection signal; The third multiplexer is coupled to the third main queue and the third secondary queue, and transmits the third main command or the third secondary command according to the selection signal; and The fourth multiplexer is coupled to the fourth main queue and the fourth secondary queue, and transmits the fourth main command or the fourth secondary command according to the selection signal.

8. The memory scheduling device according to claim 7, wherein the arbiter pre-computes the predicted burst lengths corresponding to the first main command of the first main queue, the second main command of the second main queue, the third main command of the third main queue, and the fourth main command of the fourth main queue that the current storage device is expected to receive according to the polling order; If the predicted burst lengths corresponding to the first main command, the second main command, the third main command, and the fourth main command are less than the threshold burst length, the arbiter transmits the selection signal to the first multiplexer, the second multiplexer, the third multiplexer, and the fourth multiplexer of the selector, so that the first secondary queue transmits the first secondary command to the current storage device through the first multiplexer, the second main queue transmits the second main command to the current storage device through the second multiplexer, the third main queue transmits the third main command to the current storage device through the third multiplexer, and the fourth main queue transmits the fourth main command to the current storage device through the fourth multiplexer.

9. The memory scheduling device according to claim 8, wherein the current burst lengths corresponding to the first secondary command of the first secondary queue, the second main command of the second main queue, the third main command of the third main queue, and the fourth main command of the fourth main queue are greater than or equal to the threshold burst length.

10. A memory scheduling method, comprising: Pre-computing, via an arbiter according to a polling order, the predicted burst lengths corresponding to a plurality of main commands that a current storage device is expected to receive; If the predicted burst lengths corresponding to the plurality of main commands are less than a threshold burst length, transmitting, via the arbiter, a selection signal to a selector; and Transmitting, via a preprocessing storage device through the selector, some of the plurality of main commands and at least one secondary command of the plurality of secondary commands to the current storage device.

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