Storage device, storage system including the same, and method of operating the storage device

Abstract

A memory device includes: a non-volatile memory including a plurality of planes, each plane including a plurality of pages; and a controller configured to control the non-volatile memory. The controller may be configured to: receive a plurality of commands from a host; merging a plurality of read commands associated with at least two different planes among the plurality of planes and with at least two different pages among the plurality of pages among the plurality of commands, and transmitting a merging command signal to the non-volatile memory; and applying the merge command signal to the non-volatile memory.

Description

Cross - reference to Related Applications

[0001] This application claims the priority of Korean Patent Application No. 10 - 2024 - 0016215, filed with the Korean Intellectual Property Office on February 1, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Example embodiments relate to a storage device, a storage system including the storage device, and a method of operating the storage device. Background Art

[0003] Generally, semiconductor memory devices can be classified into volatile memory devices and non - volatile memory devices. Volatile memory devices (such as dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices) have high read and write speeds but lose the stored data when the power is interrupted, while non - volatile memory devices can retain the stored data even when the power is interrupted.

[0004] With the advancement of semiconductor technology, storage devices based on non - volatile memory are evolving. In a semiconductor memory having a single - plane structure, a memory operation is performed on only one block at a time. However, in a semiconductor memory having a multi - plane structure, memory operations can be performed simultaneously on adjacent blocks arranged in consecutive planes, thereby improving performance. Therefore, such a multi - plane structure is adopted to improve the performance of semiconductor memory devices.

[0005] A plane - independent read (PIR) function that supports independent read operations for each plane can be used to perform read operations on multiple planes. Currently, it may be difficult to selectively read desired pages of each plane, and only read operations on aligned pages of all planes can be performed. In addition, the PIR function may require status checks for each plane, which can result in inefficiencies in terms of input and output. Summary of the Invention

[0006] Example embodiments provide a storage device for performing read operations on unaligned pages of each plane, a storage system including the storage device, and a method of operating the storage device.

[0007] According to an example embodiment, a storage device includes: a non-volatile memory including a plurality of planes, each plane including a plurality of pages; and a controller configured to control the non-volatile memory. The controller may be configured to: receive a plurality of commands from a host, and merge a plurality of read commands among the plurality of commands into a merged command signal. Among the plurality of commands, the plurality of read commands are associated with at least two different planes among the plurality of planes and are associated with at least two different pages among the plurality of pages. The controller is further configured to: send the merged command signal to the non-volatile memory and apply the merged command signal to the non-volatile memory.

[0008] According to an example embodiment, a method of operating a controller includes: receiving a plurality of commands from a host, and merging a plurality of read commands among the plurality of commands into a merged command signal. The plurality of read commands are associated with at least two different planes among the plurality of planes. Each of the plurality of planes includes a plurality of pages, and the plurality of read commands are associated with at least two different pages among the plurality of pages. The method includes: sending the merged command signal to the non-volatile memory.

[0009] According to an example embodiment, a storage system includes: a host configured to apply a plurality of commands; and a storage device configured to receive the plurality of commands from the host, and merge a plurality of read commands among the plurality of commands into a merged command signal. The plurality of read commands are associated with at least two different planes among the plurality of planes. Each of the plurality of planes includes a plurality of pages, and the plurality of read commands are associated with at least two different pages among the plurality of pages. The storage device is further configured to: perform a read operation based on the merged command signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0011] Figure 1 is a diagram of a storage device according to an example embodiment.

[0012] Figure 2 is a diagram showing Figure 1 an example of the non-volatile memory shown in

[0013] Figure 3 is a diagram showing a controller according to an example embodiment.

[0014] Figure 4 is a diagram showing a queuing operation of a controller according to an example embodiment.

[0015] Figure 5 is a diagram showing a speed queuing operation of a controller according to an example embodiment.

[0016] Figure 6It is a diagram showing a plane as a read target according to an exemplary embodiment.

[0017] Figure 7 It is a diagram showing a storage device according to an exemplary embodiment.

[0018] Figure 8 It is a diagram showing a read operation and a status check operation according to an exemplary embodiment.

[0019] Figure 9 It is a diagram showing an example of a storage block including a memory cell array according to an exemplary embodiment.

[0020] Figure 10 It is a diagram showing a read operation by page type according to an exemplary embodiment.

[0021] Figure 11 It is a diagram showing a read operation according to an exemplary embodiment.

[0022] Figure 12 It is a diagram showing a read voltage level adjustment operation according to an exemplary embodiment.

[0023] Figure 13 It is a diagram showing a read voltage level adjustment operation according to an exemplary embodiment.

[0024] Figure 14 It is a flowchart showing a method of an operation controller according to an exemplary embodiment.

[0025] Figure 15 It is a flowchart showing a method of a command merging operation for the same type of page according to an exemplary embodiment.

[0026] Figure 16 It is a flowchart showing a method of a command processing operation of a controller according to an exemplary embodiment.

[0027] Figure 17 It is a flowchart showing a method of a command processing operation of a controller according to an exemplary embodiment.

[0028] Figure 18 It is a diagram showing a storage system according to an exemplary embodiment. Detailed Description

[0029] Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings.

[0030] Figure 1 It is a diagram of a storage device according to an exemplary embodiment.

[0031] Refer to Figure 1, the storage device 100 according to the exemplary embodiment may include a controller 110 and a non-volatile memory (NVM) 120. The storage device 100 may store data DAT in the non-volatile memory 120 under the control of the controller 110. For example, each of the controller 110 and the non-volatile memory 120 may be provided in a single chip, a single package, or a single module. According to some embodiments, the controller 110 and the non-volatile memory 120 may be formed into a single chip, a single package, or a single module, and provided as a storage device, such as an embedded memory, a memory card, a memory stick, or a solid state drive (SSD).

[0032] The controller 110 may control the non-volatile memory 120. For example, the controller 110 may be implemented in hardware (e.g., logic circuits), software, firmware, or a combination of hardware, software, and firmware. Examples of logic circuits include dedicated hardwired logic circuits (e.g., one or more state machine logic circuits), programmable logic circuits (e.g., field programmable gate arrays (FPGAs) or programmable logic arrays (PLAs)). For example, the logic circuit may be designed to execute program code, such as SSD firmware (e.g., an embedded processor, an embedded controller, etc.). The controller 110 may perform access operations according to requests from a host to program and write data DAT in the non-volatile memory 120 or read data DAT stored in the non-volatile memory 120. The controller 110 may generate, process, and manage commands, addresses, and control signals for accessing the non-volatile memory 120.

[0033] The non-volatile memory 120 may include a plurality of planes (which may also be referred to as mats). Each of the plurality of planes may include a plurality of memory blocks. For example, each of the plurality of memory blocks may have a vertical 3D structure. Each of the plurality of memory blocks may include a plurality of pages, and each of the plurality of pages may include a plurality of memory cells. Each memory block may be an erase unit, and each page may be a programming or reading unit. Each memory cell may store multi-bit data. For example, the memory cell may include a single-level cell (SLC) that stores 1-bit data, a multi-level cell (MLC) that stores 2-bit data, a triple-level cell (TLC) that stores 3-bit data, a quad-level cell (QLC) that stores 4-bit data, or a cell that stores more bit data.

[0034] For ease of description, Figure 1 the i-th plane PLNi (where i is a positive integer) and the j-th plane PLNj (where j is a positive integer different from i) are shown, but the exemplary embodiment is not limited thereto.

[0035] According to an exemplary embodiment, the controller 110 may combine read commands for unaligned pages of a plurality of planes included in the non-volatile memory 120. The term "unaligned pages of each plane" may refer to pages having different indexes of pages requested to be accessed on a plurality of planes. For example, Figure 1 the m-th page PGm and the n-th page PGn shown in Figure 1 (where m and n are different positive integers from each other) may be regarded as unaligned pages of each of the i-th plane PLNi and the j-th plane PLNj.

[0036] The controller 110 may receive a plurality of commands CMD for a plurality of planes. The plurality of commands CMD may be commands instructing the controller 110 to perform access operations (such as programming, reading, and erasing operations) on the non-volatile memory 120. The programming command and the read command may indicate programming and reading operations on pages included in each plane.

[0037] The controller 110 may select read commands for unaligned pages of each plane from among the received plurality of commands CMD, and combine the selected read commands. For example, the controller 110 may combine a plurality of read commands associated with at least two different pages among the received plurality of commands CMD. For example, the controller 110 may select a read command for the m-th page PGm included in the i-th plane PLNi and a read command for the n-th page PGn included in the j-th plane PLNj from the commands, and may combine the selected read commands to generate a combined command signal MCMD.

[0038] The combined command signal MCMD generated by the controller 110 may be defined as a command signal for instructing the non-volatile memory 120 to perform read operations on different pages of different planes in sequence. The combined command signal MCMD may be defined as a signal including all or many elements, including commands (such as read commands), addresses at which the commands are to be executed, and various control signals for executing the commands.

[0039] The controller 110 may invoke (or send or issue) the generated merge command signal MCMD to the non-volatile memory 120. According to an example embodiment, when a read operation is performed on different planes and pages based on the merge command signal MCMD, compared with plane independent read (PIR) where a read command should be invoked for each plane, the input / output (I / O) efficiency can be improved and the power consumption can be reduced. In the case of PIR, the number of times the controller 110 invokes a unit command for a single plane and a single page is as many as the number of misaligned pages of each plane for which the read operation is to be performed. In addition, after the read operation is completed, the status check command for checking the status information of the plane should also be executed as many times as the number of misaligned pages of each plane. In the example embodiment, the controller 110 merges the read commands for the misaligned pages of each plane and invokes the merge command signal MCMD, thereby reducing the number of times of invoking commands and the number of times of performing status checks. In addition, in the case of merging read commands, the power consumption can also be reduced compared with PIR.

[0040] In addition, when a read operation is performed on the misaligned pages of each plane by the controller 110 according to an example embodiment, even when the storage device 100 performs garbage collection, different blocks can be processed simultaneously.

[0041] Upon receiving the merge command signal MCMD from the controller 110, the non-volatile memory 120 may perform a read operation on different pages of different planes (e.g., misaligned pages of each plane). The non-volatile memory 120 may read the data DAT stored in each of the different pages of different planes and send the read data DAT to the controller 110.

[0042] Compared with PIR, the storage device 100 according to the above embodiment can improve the I / O efficiency and reduce the power consumption by merging the read commands for the misaligned pages of each plane and invoking the merge command signal MCMD to the non-volatile memory 120.

[0043] Figure 2 is a diagram showing Figure 1 an example of the non-volatile memory shown in

[0044] Referring to Figure 2 , the non-volatile memory 200 according to an example embodiment may include a memory cell array 210, an address decoder 220, a page buffer circuit 230, a data input / output (I / O) circuit 240, a voltage generator 250, and a control circuit 260.

[0045] The memory cell array 210 can be connected to the address decoder 220 through the string select line SSL, multiple word lines WL, and the ground select line GSL. The memory cell array 210 can be connected to the page buffer circuit 230 through multiple bit lines BL.

[0046] The memory cell array 210 can include multiple planes, and each of the multiple planes can include multiple non-volatile memory cells connected to multiple word lines WL and multiple bit lines BL. The non-volatile memory cells connected to each of the multiple word lines can be pages. Therefore, each of the multiple planes can include multiple pages.

[0047] According to an example embodiment, the memory cell array 210 can be a three-dimensional memory cell array 210 formed in a three-dimensional structure (or a vertical structure) on a substrate. In an example embodiment, the memory cell array 210 can include vertical memory cell strings, and the vertical memory cell strings include multiple stacked memory cells.

[0048] The address decoder 220 can be connected to the memory cell array 210 through the string select line SSL, multiple word lines WL, and the ground select line GSL. During a programming operation or a read operation, the address decoder 220 can determine one of the multiple word lines WL as the selected word line based on the row address RADDR provided by the control circuit 260, and determine the remaining word lines WL among the multiple word lines WL as unselected word lines.

[0049] The page buffer circuit 230 can be connected to the memory cell array 210 through multiple bit lines BL. The page buffer circuit 230 can include multiple page buffers. The page buffer circuit 230 can temporarily store the data to be programmed in the selected page during a programming operation, and can temporarily store the data read from the selected page during a read operation.

[0050] The data input / output circuit 240 can be connected to the page buffer circuit 230 through multiple data lines DL. During a programming operation, the data input / output circuit 240 can receive the programming data DAT from the controller as described above Figure 1 and provide the programming data DAT to the page buffer circuit 230 based on the column address CADDR provided by the control circuit 260. During a read operation, the data input / output circuit 240 can provide the read data DAT stored in the page buffer circuit 230 to the controller based on the column address CADDR provided by the control circuit 260.

[0051] The voltage generator 250 can generate the word line voltage VWL required for the operation of the non-volatile memory 200 based on the control signal CTL provided by the control circuit 260. The word line voltage VWL generated by the voltage generator 250 can be applied to the multiple word lines WL through the address decoder 220.

[0052] The control circuit 260 can control various operations of the non-volatile memory 200. The control circuit 260 can receive a command signal CMD, a control signal CTRL, and an address signal ADDR from the controller, and can perform a programming operation, a read operation, an erase operation, etc. on the non-volatile memory 200 based on the command signal CMD, the control signal CTRL, and the address signal ADDR. For example, the control circuit 260 can generate a control signal CTL based on the command signal CMD to control the voltage generator 250, generate a page buffer control signal PCTL to control the page buffer circuit 230, and can generate a row address RADDR and a column address CADDR based on the address signal ADDR. The control circuit 260 can provide the row address RADDR to the address decoder 220, and provide the column address CADDR to the data input / output circuit 240.

[0053] According to an exemplary embodiment, the control circuit 260 can receive a merge command signal MCMD from the controller, and perform a read operation on different pages of different planes based on the merge command signal MCMD. For example, the control circuit 260 can generate a control signal CTL based on the merge command signal MCMD to select word lines corresponding to the m-th page PGm of the i-th plane PLNi and the n-th page PGn of the j-th plane PLNj, and send the selected word lines to the voltage generator 250. In addition, the control circuit 260 can generate a row address RADDR and a column address CADDR corresponding to the m-th page PGm of the i-th plane PLNi and the n-th page PGn of the j-th plane PLNj respectively based on the address information of the merge command signal MCMD, and send the generated row address RADDR and column address CADDR to the address decoder 220 and the data input / output circuit 240.

[0054] According to an exemplary embodiment, the non-volatile memory 200 can perform a set-up on at least two different pages based on the received merge command signal MCMD. For example, the set-up can include power-on / power-off operations, ready and busy (RnB) operations, etc. on the page buffer for each plane. When the merge command signal MCMD is received, the control circuit 260 can perform a set-up once for the read operation of the misaligned pages of each plane. Since the set-up is performed on all planes associated with the misaligned pages of each plane, operations that can be commonly performed on all planes among the operations included in the set-up can be performed once. In contrast, in the case of PIR, whenever a cell command for each plane is received, the non-volatile memory 200 should perform the set-up separately. Therefore, the non-volatile memory 200 according to an exemplary embodiment can perform the set-up for the read operation more efficiently than PIR based on the merge command signal MCMD.

[0055] Compared with PIR, among the circuits operating for the setting operation, for the circuits sharing a plane, the setting can even be performed by one operation. Therefore, compared with PIR, the non-volatile memory 200 according to the exemplary embodiment can reduce power consumption.

[0056] Figure 3 FIG. is a diagram showing a controller according to an exemplary embodiment.

[0057] Referring to Figure 3 , the controller 300 according to the exemplary embodiment may include a queue 310 and a scheduling logic circuit 320. The controller 300 may store a plurality of commands CMD received from a host in the queue 310.

[0058] The queue 310 may store a plurality of commands CMD and may be implemented in the controller 300 to generate a merged command signal according to the above embodiment. For example, the queue 310 may be implemented using hardware, software, firmware, or a combination of hardware, software, and / or firmware. For example, the queue 310 may be implemented using a first-in-first-out (FIFO) memory or a data structure of firmware or software (e.g., an array, a linked list, or other data structures). The queue 310 may include x entries (where x is a positive integer) to accept a plurality of commands CMD received from the host. A single command requesting access to a single plane and a single page may be stored in a single entry.

[0059] The scheduling logic circuit 320 may be configured to select a plurality of read commands from the queue 310 and sequentially merge the plurality of read commands. For example, the scheduling logic circuit 320 may select a plurality of read commands requesting read operations on different planes and different pages from the queue 310, and may merge the read commands such that the selected read commands are set (or stored) in consecutive entries. Therefore, the scheduling logic circuit 320 may allow the non-volatile memory to simultaneously read the addresses of different pages of different planes through command merging.

[0060] The merged command signal within the queue 310 may be called to the non-volatile memory by the controller 300 once at one timing. In the case of PIR, a single command should be separately called at each timing so that a plurality of commands CMD for unaligned pages of each plane can be called at the same timing or different timings in terms of the call operation. Therefore, within the queue 310, when one command is called, other commands should wait for the order in which they are called. In the exemplary embodiment, within the queue 310, the read commands for unaligned pages of each plane may be merged into a single merged command signal by the scheduling logic circuit 320, so that the unaligned pages of each plane can be read with only one call operation at one timing.

[0061] Figure 4is a diagram illustrating a queuing operation of a controller according to an example embodiment.

[0062] Reference Figure 4 The controller according to an example embodiment may sequentially store multiple commands received from the host in a queue. For example, the commands may be stored in the queue 310a in the following order: a first command CMD1 requesting a read operation on the mth page PGm of the i-th plane PLNi; a second command CMD2; a third command CMD3 requesting a read operation on the nth page PGn of the j-th plane PLNj; a fourth command CMD4; and a fifth command CMD5.

[0063] When a read operation is required for each plane's misaligned pages, the controller can merge the misaligned page read commands (first command CMD1 and third command CMD3) in the queue for each plane through scheduling logic to generate a merge command signal MCMD. As a result, the first command CMD1 and the third command CMD3 can be set (or stored) in consecutive entries within the queue 310b. The controller can then perform a sequential read operation on the non-volatile memory based on the first command CMD1 and the third command CMD3. For example, the controller can invoke the merge command signal MCMD to the queue at a single timing.

[0064] In the case of PIR, rather than calling a single merge command signal (MCMD) unit as described in the exemplary embodiment, separate read commands are called for the number of planes to be read, and the corresponding status checks are also performed the same number of times. According to the exemplary embodiment, by having the controller merge read commands for misaligned pages for each plane in different planes, only one call operation and one status check can be performed, thereby improving input / output efficiency and reducing power consumption.

[0065] Figure 5 is a diagram illustrating a speed queuing operation of a controller according to an example embodiment.

[0066] Reference Figure 5, according to an example embodiment, the controller may determine the number of unit commands to be merged according to the speed mode. Hereinafter, the term "unit command" may refer to a read command for a single plane. The controller may perform a read operation on multiple planes in the speed mode. For example, the controller may perform a read operation on N planes in the nX speed mode (where N is a positive integer and is the number of planes). In the speed mode, the controller may perform a read operation on N planes. In the speed mode, the controller may determine N as the number of planes on which the read operation is to be performed. When the controller determines N as the number of planes, this is regarded as determining the number of unaligned pages (e.g., at least two different pages) of each plane that are to be the target of the merge command signal MCMD.

[0067] According to an example embodiment, the controller may merge read commands for N unaligned pages of N different planes in the speed mode to generate a merge command signal MCMD. For example, the controller may select read commands for N planes (e.g., the first command CMD1 to the Nth command CMDN) from a plurality of commands stored in the queue 310c according to the speed mode, and may merge the selected read commands.

[0068] As a result, the storage device according to the above embodiment may merge unit commands corresponding to the number of planes for which unaligned page requests for reading are made for each plane in the speed mode.

[0069] Figure 6 is a diagram showing planes that are read targets according to an example embodiment.

[0070] Referring to Figure 6 , for example, the first plane PLN0 to the fourth plane PLN3 are different from each other and may be the targets of read commands. Each plane may include a plurality of different blocks. The blocks may be included in any one plane. Each block may include a plurality of pages.

[0071] Examples are provided where the controller receives from the host a first read command for the first page PGm of the fifth block BLK4 of the first plane PLN0, a second read command for the second page PGn of the tenth block BLK9 of the second plane PLN1, a third read command for the third page PGo of the (i + 2)th block BLKi+2 of the third plane PLN2, and a fourth read command for the fourth page PGp of the fourth block BLK3 of the fourth plane PLN3. In the above example, the target pages of the read operation may have different indexes for each plane. For example, read requests for unaligned pages of each plane for different planes may be issued from the host.

[0072] The controller may combine corresponding read commands according to the above embodiments to generate a combined command signal. The controller may perform sequential read operations on unaligned pages (the first page to the fourth page) of each of the shown planes by invoking a timed combined command signal (i.e., where the timings of various signals are aligned in time or based on a common timing reference). As a result, the storage device according to the example embodiment may perform sequential read operations on different pages of different planes through the read command combination and invocation operations of the controller.

[0073] Figure 7 FIG. is a diagram illustrating a storage device according to an example embodiment.

[0074] Referring to Figure 7 , the storage device 400 according to the example embodiment may combine read commands for unaligned pages (e.g., the m-th page PGm and the n-th page PGn) for each plane among a plurality of commands CMD received from a host according to the above embodiments, and may invoke a combined command signal MCMD to the non-volatile memory 420. The non-volatile memory 420 may read data DAT from unaligned pages of each of a plurality of planes (e.g., the i-th plane PLNi and the j-th plane PLNj), and send the read data DAT to the controller 410.

[0075] The controller 410 may invoke a status check command SC to the non-volatile memory 420 to check the status of the non-volatile memory 420. The non-volatile memory 420 may send status information SI to the controller 410 in response to the status check command SC. For example, the status information SI may be status information SI about the planes of the non-volatile memory 420, and may include read pass / fail information, program pass / fail information, ready / busy information, etc.

[0076] According to an example embodiment, the controller 410 may call a merge command signal MCMD to the non-volatile memory 420 and call a status check command SC to the non-volatile memory 420. In the example embodiment, the controller 410 may call only one status check command SC to the plane associated with the misaligned pages of each plane, rather than calling a status check command SC to each plane. For example, the controller 410 may send a merge command signal MCMD to the non-volatile memory 420 and then call a single status check command SC for at least two different planes (including at least two different pages) to the non-volatile memory 420. Since the controller 410 merges the unit commands for the misaligned pages of each plane into a merge command signal MCMD and calls the merge command signal MCMD at one timing, the controller 410 may not call a status check command SC to each plane. The called status check command SC may be defined as a command requesting a status check for at least two different planes, rather than a command requesting a status check for a single plane.

[0077] In the case of PIR, multiple single commands are called to each plane such that a status check operation should be performed for each plane. For example, in PIR, the number of times the status check command SC is called may be the same as the number of planes. Each time the status check command SC is called, the data line between the controller 410 and the non-volatile memory 420 is used, and other signals should wait during this period.

[0078] According to the above embodiment, the storage device 400 may improve the input / output efficiency and reduce the power consumption by performing a read operation on the planes including the misaligned pages of each plane and then calling only one status check command SC, rather than calling a status check command SC to each plane.

[0079] Figure 8 is a diagram showing a read operation and a status check operation according to an example embodiment.

[0080] Referring to Figure 8 , the controller may merge the unit commands U1 to U4 to generate a merge command signal MCMD. Each unit may have an address different from the address of the read command (e.g., 00h or 32h), and each address may include a column address CADDR and a row address RADDR in the non-volatile memory to represent different planes and different pages.

[0081] The length of the merge command signal MCMD in the time domain can be the same as the sum of the lengths of the unit commands. However, in terms of command invocation operations, each unit command can be invoked once instead of N times. The last unit command of the merge command signal MCMD can include commands for initiating access to the non-volatile memory and read operations on the non-volatile memory (e.g., 30h).

[0082] After invoking the merge command signal MCMD, the controller can invoke a single status check command SC for the plane (and at least two different pages). In an example embodiment, the invoked status check command SC can be a command for checking the status information of all planes associated with the merge command signal MCMD invoked before the status check command SC, rather than a command for checking the status information of each plane. In the case of PIR, the unit commands for each plane are invoked N times at different timings, such that even if the status check command is invoked together with a single unit command, the status information of all planes cannot be checked through the status check.

[0083] The storage device according to the example embodiment performs read operations on all planes simultaneously by invoking the merge command signal MCMD at one timing. Therefore, the status information of all planes can be checked by invoking only one status check command SC. As a result, the storage device according to the example embodiment can invoke only one status check command SC instead of N status check commands SC, thereby improving input / output efficiency and reducing power consumption.

[0084] Figure 9 is a diagram showing an example of a memory block having a memory cell array according to an example embodiment.

[0085] Referring to Figure 9 , a plurality of strings STR can be arranged in a row and column manner on the substrate SUB. The plurality of strings STR can be commonly connected to a common source line CSL formed on (or in) the substrate SUB. In Figure 9 , for better understanding of the structure of the memory block BLKa, the position of the substrate SUB is shown as an example.

[0086] In Figure 9 , the common source line CSL is shown as being connected to the lower end of the string STR. However, the common source line CSL can be any string as long as it is electrically connected to the lower end of the string STR, and is not limited to being physically located at the lower end of the string STR. For example, in Figure 9 , the strings STR are shown as being arranged in a 4x4 array, but the memory block BLKa can include a smaller or larger number of strings.

[0087] The strings STR in each row can be commonly connected to the ground selection line GSL1 or GSL2. For example, the strings STR1 and STR2 in the first row and the second row can be commonly connected to the first ground selection line GSL1, and the strings STR3 and STR4 in the third row and the fourth row can be commonly connected to the second ground selection line GSL2. However, this is merely an example, and four different ground selection lines can be provided, and the strings STR in each row can be implemented to be connected to different ground selection lines.

[0088] The strings STR in each row can be connected to the corresponding string selection line among the first string selection line SSL1, the second string selection line SSL2, the third string selection line SSL3, and the fourth string selection line SSL4. The unit strings STR in each column can be connected to the corresponding bit line among the first bit line BL1, the second bit line BL2, the third bit line BL3, and the fourth bit line BL4.

[0089] Each string can include at least one ground selection transistor GST connected to the ground selection line GSL1 or GSL2, a plurality of memory cells MC1 to MC8 respectively connected to a plurality of word lines WL1 to WL8, and string selection transistors SST respectively connected to the string selection lines SSL1, SSL2, SSL3, and SSL4.

[0090] In each string, the ground selection transistor GST, the memory cells MC1 to MC8, and the string selection transistors SST can be connected in series in a direction perpendicular to the substrate SUB, and can be sequentially stacked in a direction perpendicular to the substrate SUB. In each string STR, at least one of the memory cells MC1 to MC8 can be used as a dummy memory cell. The dummy memory cell can be not programmed (for example, programming is prohibited) or can be programmed in a different manner from the memory cells MC1 to MC8.

[0091] The circuit structure of the memory cells included in the memory block BLK has been briefly described. However, the circuit structure of the shown memory block is a simplified structure for ease of description, and the actual memory block is not limited to the shown example. For example, it will be understood that a single physical block can include more semiconductor layers, bit lines BL, and string selection lines SSL.

[0092] Figure 10 FIG. is a diagram showing a read operation performed in a page type according to an exemplary embodiment.

[0093] Referring to Figure 10 , according to the above embodiment, a plurality of memory cells MC can be connected to the i-th word line WLi (for example, Figure 9 one of the word lines). Each word line and the memory cell MC can correspond to a physical page. For example, Figure 10 the physical page can include memory cells MC arranged in a region where a single word line WLi and a plurality of bit lines BL0 to BLm-1 intersect each other.

[0094] Each memory cell MC may be a multi - level cell storing two or more bits of data. For example, when the memory cells MC included in a physical page are multi - level cells storing 2 - bit data, each memory cell MC may store least significant bit (LSB) data and most significant bit (MSB) data. In an exemplary embodiment, the physical page may include two logical pages, i.e., a first logical page LP1 and a second logical page LP2. For example, when the memory cells MC included in a physical page are triple - level cells TLC storing 3 - bit data, each memory cell MC may store least significant bit (LSB) data, central significant bit (CSB) data, and most significant bit (MSB) data. In an exemplary embodiment, the physical page may include three logical pages, i.e., a first logical page LP1 (e.g., the logical page corresponding to the MSB data), a second logical page LP2, and a third logical page LP3 (e.g., the logical page corresponding to the LSB data). For example, when the memory cells MC included in a physical page are cells storing 4 or more bits of data, one or more intermediate bit data may be stored in each memory cell according to the additional bits.

[0095] In summary, each of the multiple pages may be classified as one of the multiple logical pages corresponding to k bits (where k is a positive integer greater than or equal to 2) that can be represented by a single cell. A single cell may have a threshold voltage distribution represented by a set of multiple threshold voltages, depending on the value of k and the erased state and multiple programmed states programmed in the single cell. Thus, the logical pages exhibit different read speeds according to the threshold voltages. For example, a logical page that requires a larger number of read voltages for a read operation may exhibit a lower read speed, and a logical page that requires a smaller number of read voltages for a read operation may exhibit a higher read speed. In addition, even if the same number of read voltages is required, the read speed may vary according to the amplitude of the read voltages.

[0096] Figure 11 is a diagram showing a read operation according to an exemplary embodiment.

[0097] Referring to Figure 11 , when the controller according to an exemplary embodiment combines the unit commands U1 to U4 for unaligned pages for each plane, it may consider the type of the logical pages described above Figure 10 . For example, the controller may combine multiple read commands into units of multiple logical pages. As Figure 10 described, the logical pages may exhibit different read speeds according to the type. Thus, when a read operation is performed without considering the logical page type, the speed of the read operation for multiple planes and pages is inevitably limited by the logical pages with a relatively lower read speed.

[0098] Considering that the read speed varies according to the logical page, the controller can combine multiple read commands into units of only the same logical page among multiple logical pages. For example, as shown in the figure, the controller can combine unit commands requesting a read operation on any first logical page to generate a combined command signal MCMD. Accordingly, the addresses P1ADD1, P1ADD2, P1ADD3, and P1ADD4 of the corresponding combined unit commands can all represent the same type of logical page (e.g., the first logical page). The addresses P1ADD1, P1ADD2, P1ADD3, and P1ADD4 of the corresponding unit commands can have only the same type of logical page, but can represent different unaligned pages (e.g., different physical pages) of each plane.

[0099] The non-volatile memory that receives the corresponding combined command signal MCMD from the controller can perform a sequential read operation on the same type of logical page. Since the logical pages have the same type, the non-volatile memory can perform a read operation on the unaligned pages of each plane without loss of read speed.

[0100] Figure 12 is a diagram showing a read voltage level adjustment operation according to an exemplary embodiment.

[0101] Referring to Figure 12 , the controller according to the exemplary embodiment can adjust the read voltage level for the read operation of each plane. The read voltage level can refer to the voltage level applied to each storage cell for reading, which depends on the number of bits that a single cell can represent. The number, amplitude, etc. of the read voltage levels can be set according to whether the single storage cell is the above-mentioned SLC, MLC, TLC, or QLC.

[0102] According to the exemplary embodiment, unit commands can be provided as shown in the figure to adjust the read voltage level of the controller. The unit command can be a command for a single plane and can be received by the controller from the host. The unit command generally can include a read command (e.g., 00h) and an address for each plane (e.g., ADDR0 or ADDR1), and can additionally include level adjustment information LAI1 and LAI2 to adjust the read voltage level or read voltage of the read operation for each of the multiple planes.

[0103] According to the exemplary embodiment, the level adjustment information LAI1 and LAI2 can include a reserved field rev and multiple voltage adjustment data. According to the exemplary embodiment, the reserved field rev can be omitted. The number and amplitude of the multiple voltage adjustment data can be set according to the type of storage cell.

[0104] According to an example embodiment, the number of pieces of voltage adjustment data may be set according to the number of logical pages of a storage cell. For example, when the storage cell targeted by a command for each plane is TLC, the number of pieces of voltage adjustment data may be 3 (which is the number of logical pages of TLC). Then, in Figure 12 this case, k = 3, and RV1-1, RV1-2, and RV1-3 may each be voltage adjustment data for adjusting the read voltage level or read voltage of different logical pages among the logical pages (e.g., LSB, CSB, and MSB) included in the first plane. In addition, RV2-1, RV2-2, and RV2-3 may each be voltage adjustment data for adjusting the read voltage level of different logical pages among the logical pages included in the second plane.

[0105] The controller may call a unit command including voltage adjustment data to the non-volatile memory. According to the above embodiment, the unit command called to each plane may include the voltage adjustment data of each plane. Therefore, the storage device according to the example embodiment may adjust the read voltage level for reading multi-bit data of each plane and the read voltage level of unaligned pages of each plane.

[0106] Figure 13 is a diagram showing a read voltage level adjustment operation according to an example embodiment.

[0107] Referring to Figure 13 , the unit command according to the example embodiment may be configured such that the reserved field according to Figure 12 includes plane information PLN ID for adjusting the read voltage level. For example, the level adjustment information LAI may additionally include the plane information PLN ID. The plane information PLN ID may be defined as information for identifying the plane for which the read voltage level is to be adjusted based on the voltage adjustment data RV1 to RV3. Compared with Figure 12 , the controller may notify the non-volatile memory of the plane to which the voltage adjustment data RV1 to RV3 are to be applied through the plane information PLN ID without generating different voltage adjustment data RV1 to RV3 for each plane.

[0108] The controller may merge the unit commands including the level adjustment information LAI to generate and call a merged command signal, and the level adjustment information LAI includes the plane information PLN ID for adjusting the read voltage level. Through the plane information PLN ID, each plane may receive the voltage adjustment data RV1 to RV3 from the controller without being affected by another plane.

[0109] Figure 14 is a flowchart showing a method of operating a controller according to an example embodiment.

[0110] Reference Figure 14 In operation S110, the controller may receive multiple commands from a host for multiple planes, each plane including multiple pages. The multiple commands received from the host may be commands for requesting various accesses (e.g., programming, reading, erasing, etc.) to the non-volatile memory.

[0111] In operation S120, the controller may merge multiple read commands among the multiple commands received from the host that are associated with at least two pages (e.g., unaligned pages of each plane) among the multiple pages. The merging operation may result in generating a merged command signal, where the unit commands (e.g., read commands) for each plane are sequentially merged. In an example embodiment, the merged command may be constructed such that the command for initiating the read operation is set in the last unit command.

[0112] In operation S130, the controller may invoke or send the merged command signal to the non-volatile memory. The merged command signal is a merged sequence of unit commands for multiple planes, and the command for initiating the read is located in the last unit command. The controller may invoke the merged command signal to the non-volatile memory in one timing, and when the non-volatile memory receives the merged command signal, it may perform a read operation on the unaligned pages of each plane simultaneously.

[0113] In operation S140, the controller may invoke a single status check command to the non-volatile memory for at least two different planes including at least two different pages. By invoking the merged command that merges multiple unit commands in operation S130, even if only one status check command is invoked, the controller can check the status of all planes. Therefore, according to the above operation method, the input / output efficiency of command invocation for unaligned pages of each plane can be improved, and the power consumption can be reduced.

[0114] Figure 15 is a flowchart showing a method for merging commands for the same type of pages according to an example embodiment.

[0115] Reference Figure 15 In operation S210, the controller may determine whether there are different types of pages among the multiple read commands to be merged. The term "type" may refer to the type of the logical page of a single storage unit. For example, the controller may determine whether the multiple read commands are for different types of pages. For example, when read commands for a first logical page and a second logical page are mixed, the controller may determine that there are different types of pages.

[0116] When it is determined in operation S210 that there are different types of pages, the process proceeds to operation S220, in which the controller may combine multiple read commands into the same logical page among multiple logical pages. For example, a single combined command signal may be a signal that combines cell commands for the same logical page. The controller may call a combined command signal (S130) to the non-volatile memory to process the read operation of pages with the same read speed.

[0117] According to some embodiments, when all pages are of the same type, the controller may also combine cell commands for pages of the same type (operation S120).

[0118] Figure 16 is a flowchart showing a method of command processing operations of a controller according to an exemplary embodiment.

[0119] Refer to Figure 16 In operation S310, the controller may call an erase command to the non-volatile memory. The non-volatile memory may perform an erase operation in units of blocks based on the received erase command.

[0120] In operation S320, the controller may determine whether there are multiple read commands for different pages of different planes. When there are no multiple read commands, the process proceeds to operation S330, in which the controller may call a cell command to the non-volatile memory.

[0121] According to some embodiments, when there are multiple read commands, the controller may combine the read commands (S120) according to the above embodiments or determine whether there are pages of the same type (operation S210).

[0122] Figure 17 is a flowchart showing a method of command processing operations of a controller according to an exemplary embodiment.

[0123] Refer to Figure 17 In operation S410, the controller may call a programming command to the non-volatile memory. The non-volatile memory may perform a programming operation in units of pages based on the received programming command.

[0124] In operation S420, the controller may determine whether there are multiple read commands for different pages of different planes. When there are no multiple read commands, the process proceeds to operation S430, in which the controller may call a cell command to the non-volatile memory.

[0125] According to some embodiments, when there are multiple read commands, the controller may combine the read commands (S120) according to the above embodiments or determine whether there are pages of the same type (operation S210).

[0126] Figure 18 FIG. is a diagram showing a storage system according to an exemplary embodiment.

[0127] Referring Figure 18 , the storage system 500 according to an exemplary embodiment may include a host 510 and a storage device 520.

[0128] The host 510 may include a host controller 511 and a host memory 512. The host memory 512 may be used as a buffer memory 536 to temporarily store data to be sent to the storage device 520 or data sent from the storage device 52.

[0129] The host 510 may include, for example, a personal computer (PC), a laptop computer, a mobile phone, a smart phone, or a tablet PC. The host 510 may call a plurality of commands CMD for a plurality of planes to the storage device 520, and each plane includes a plurality of pages.

[0130] The storage device 520 may include a storage controller 530 and a non-volatile memory 540.

[0131] According to an exemplary embodiment, the storage device 520 may be configured to receive a plurality of commands CMD from the host 510, merge a plurality of read commands among the plurality of commands CMD associated with at least two different pages, and perform a read operation based on the merged command signal.

[0132] The storage device 520 may include a storage medium for storing data in response to a request from the host 510. For example, the storage device 520 may include at least one of a solid state drive (SSD), an embedded memory, and a removable external memory. When the storage device 520 is an SSD, the storage device 520 may be a device compliant with the Non-Volatile Memory Express (NVMe) standard. When the storage device 520 is an embedded memory or an external memory, the storage device 520 may be a device compliant with the Universal Flash Storage (UFS) or Embedded MultiMediaCard (eMMC) standard. Each of the host 510 and the storage device 520 may generate a data packet based on the adopted standard protocol and send the generated data packet.

[0133] When the non-volatile memory 540 of the storage device 520 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. For example, the storage device 520 may further include various other types of non-volatile memories. For example, the storage device 520 may employ a magnetic random access memory (MRAM), a spin transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase RAM (PRAM), a resistive RAM, or other types of memories.

[0134] According to an example embodiment, the host controller 511 and the host memory 512 may be implemented as additional semiconductor chips. In some embodiments, the host controller 511 and the host memory 512 may be integrated into the same semiconductor chip. For example, the host controller 511 may be a module among a plurality of modules provided in an application processor, and the application processor may be implemented as a system on chip (SoC). In addition, the host memory 512 may be an embedded memory provided inside the application processor, or may be a non-volatile memory or a memory module provided outside the application processor.

[0135] The host controller 511 may manage operations of storing data (e.g., programming data) in the buffer in the non-volatile memory 540 or storing data (e.g., read data) in the non-volatile memory 540 in the buffer.

[0136] The storage controller 530 may include a host interface 531, a memory interface 532, a processor 533, a flash translation layer (FTL) 534, a packet manager 535, a buffer memory 536, an error correction circuit (ECC) 537, and a queue 538. The storage controller 530 may further include a working memory (not shown), to which the FTL 534 is loaded, and may control data programming and read operations on the non-volatile memory 540 based on the processor 533 executing the FTL 534.

[0137] The host interface 531 may send a data packet to the host 510 and receive a data packet from the host 510. The data packet sent from the host 510 to the host interface 531 may include a command (e.g., the plurality of commands CMD described above) or data to be programmed in the non-volatile memory 540, and the data packet sent from the host interface 531 to the host 510 may include a response to the command or data read from the non-volatile memory 540. According to an example embodiment, the plurality of commands CMD sent from the host interface 531 may include level adjustment information for adjusting a read voltage level in each of a plurality of planes.

[0138] The memory interface 532 may send data to be programmed in the non-volatile memory 540 to the non-volatile memory 540, or receive data read from the non-volatile memory 540. The memory interface 532 may be implemented to conform to a standard protocol, such as Toggle or Open NAND Flash Interface (ONFI).

[0139] The processor 533 may perform data programming and read operations on the non-volatile memory 540. According to an example embodiment, the processor 533 may be configured according to the above embodiments (e.g., Figures 1 to 17)(Perform operations of the controller. For example, the processor 533 may combine multiple read commands and call a combined command signal to the non-volatile memory 540 through the memory interface 532.)

[0140] The FTL 534 may perform various functions such as address mapping, wear leveling, and garbage collection. Address mapping is an operation of converting a logical address received from the host 510 into a physical address for actually storing data in the non-volatile memory 540. Wear leveling is a technique for preventing excessive degradation of a specific block by allowing blocks in the non-volatile memory 540 to be evenly used. For example, wear leveling may be implemented by a firmware technique that balances the number of erase times of physical blocks. Garbage collection is a technique for ensuring the available capacity in the non-volatile memory 540 by copying valid data of a block to a new block and then erasing the existing block.)

[0141] The packet manager 535 may generate packets based on the protocol of the interface negotiated with the host 510, or may parse various types of information from the packets received from the host 510. The buffer memory 536 may temporarily store data to be written to the non-volatile memory 540 or data read from the non-volatile memory 540. The buffer memory 536 may be configured to be included in the controller 110. In an exemplary embodiment, the buffer memory 53 may be provided outside the controller 110.)

[0142] The ECC 537 may detect and correct errors in the read data read from the non-volatile memory 540. For example, the ECC 537 may generate parity bits for the write data to be written to the non-volatile memory 540, and the generated parity bits may be stored in the non-volatile memory 540 together with the write data. When reading data from the non-volatile memory 540, the ECC 537 may use the parity bits read from the non-volatile memory 540 together with the read data to correct errors in the read data and output the error-corrected read data.)

[0143] The queue 538 may store multiple commands CMD received from the host 510. The processor 533 may select multiple read commands from the queue 538 and may continuously combine multiple read commands. Therefore, the storage system according to the above embodiment may improve input / output efficiency and reduce power consumption through read operations of unaligned pages in each plane.)

[0144] As described above, according to an exemplary embodiment, a storage device for performing a read operation on unaligned pages in each plane, a storage system including the storage device, and a method of operating the storage device may be provided.)

[0145] Although example embodiments have been shown and described above, those skilled in the art will appreciate that modifications and changes can be made without departing from the scope of the inventive concept defined by the appended claims.

[0146] As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having" and any other variation thereof specify the presence of the stated feature, step, operation, element, component, and / or group thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Further, it should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Rather, these terms are only used to distinguish one element from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of this disclosure.

Claims

1. A storage device, comprising: A non - volatile memory, including a plurality of planes, each plane including a plurality of pages; And A controller configured to control the non - volatile memory, Wherein, the controller is configured to perform operations, and the operations include: Receiving a plurality of commands from a host; Merging a plurality of read commands among the plurality of commands into a merged command signal, wherein the plurality of read commands are associated with at least two different planes among the plurality of planes and are associated with at least two different pages among the plurality of pages; Sending the merged command signal to the non - volatile memory; and Applying the merged command signal to the non - volatile memory.

2. The storage device according to claim 1, wherein, The controller is configured to: after sending the merged command signal, send a single status check command to the non - volatile memory for the at least two different planes including the at least two different pages.

3. The storage device according to claim 1, wherein, The controller is configured to: determine the number of the at least two different pages.

4. The storage device according to claim 1, wherein, Each of the plurality of pages is classified as one of a plurality of logical pages corresponding to k bits represented by a single storage cell, Where k is a positive integer greater than or equal to 2, and Wherein, the controller is configured to: merge the plurality of read commands into a unit of the plurality of logical pages.

5. The storage device according to claim 4, wherein, The controller is configured to: merge the plurality of read commands into the same logical page among the plurality of logical pages.

6. The storage device according to claim 1, wherein, The merged command signal includes level adjustment information for adjusting the read voltage of the read operation of each of the plurality of planes.

7. The storage device according to claim 6, wherein, The level adjustment information includes plane information for adjusting the read voltage.

8. The storage device according to claim 1, wherein, The non - volatile memory is configured to: perform settings on the at least two different pages based on receiving the merged command signal.

9. The storage device according to claim 1, wherein, The controller is configured to: store the plurality of commands in a queue, select the plurality of read commands from the queue, and continuously merge the plurality of read commands from the queue into the merged command signal.

10. The storage device according to claim 1, wherein, The controller is configured to: adjust the read voltage of the read operation of each of the plurality of planes.

11. A method of operating a controller, the method comprising: Receiving a plurality of commands from a host; Merging a plurality of read commands among the plurality of commands into a merged command signal, wherein the plurality of read commands are associated with at least two different planes among a plurality of planes, wherein each of the plurality of planes includes a plurality of pages, and the plurality of read commands are associated with at least two different pages among the plurality of pages; and Sending the merged command signal to a non - volatile memory.

12. The method according to claim 11, further comprising: Determining the number of the at least two different pages; And Merging a subset of the plurality of read commands corresponding to the number into the merged command signal.

13. The method according to claim 11, further comprising: Sending a single status check command to the non - volatile memory for the at least two different planes including the at least two different pages.

14. The method according to claim 11, wherein, Each of the plurality of pages is classified as one of a plurality of logical pages corresponding to k bits represented by a single storage cell, where k is a positive integer greater than or equal to 2, and wherein combining the plurality of read commands includes: combining the plurality of read commands into units of the plurality of logical pages.

15. The method according to claim 11, wherein The combined command signal includes level adjustment information for adjusting a read voltage of a read operation for each of the plurality of planes, and wherein the level adjustment information includes plane information for which the read voltage is to be adjusted.

16. The method according to claim 11, further comprising: storing the plurality of commands in a queue; selecting the plurality of read commands from the queue; and successively combining the plurality of read commands from the queue into the combined command signal.

17. The method according to claim 11, further comprising: adjusting a read voltage of a read operation for each of the plurality of planes.

18. A storage system, comprising: a host configured to apply a plurality of commands; and a storage device configured to receive the plurality of commands from the host, combine a plurality of read commands among the plurality of commands into a combined command signal, wherein the plurality of read commands are associated with at least two different planes among the plurality of planes, wherein each of the plurality of planes includes a plurality of pages, and the plurality of read commands are associated with at least two different pages among the plurality of pages, wherein the storage device is further configured to: perform a read operation based on the combined command signal.

19. The storage system according to claim 18, wherein, The storage device includes: a non-volatile memory including the plurality of planes; and a storage controller configured to combine the plurality of read commands and send the combined command signal to the non-volatile memory.

20. The storage system according to claim 18, wherein, The plurality of commands include level adjustment information for adjusting a read voltage of a read operation for each of the plurality of planes.

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