Pre-analysis optimization method and device, equipment and storage medium

Abstract

The invention provides a pre-analysis optimization method and device, equipment and a storage medium. The method comprises the following steps: extracting a preset number of blocks; extracting pages from the extracted blocks according to a preset interval proportion, wherein the position interval range of the extracted pages needs to cover the full-page interval range of the Flash; and analyzing the extracted page, generating attribute data of Flash according to an analysis result, and completing pre-analysis. According to the method, the preset number of blocks are extracted, and the position interval range of the extracted pages covers the full-page interval range of the Flash, so that the attribute data of the Flash can be pre-analyzed under the condition that full-disk scanning does not need to be executed on the Flash in the mass production stage, the pre-analysis time of the Flash can be greatly shortened, and the mass production efficiency of the Flash is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of flash memory, and in particular to a pre-analysis optimization method, device, equipment and storage medium. Background Art

[0002] To enable NAND Flash (hereinafter referred to as Flash) to function as a mainstream storage medium for data storage, it needs to be mass-produced with a storage control chip. Mass production involves storing the "operating system" (i.e., firmware code) that manages the Flash into the Flash. When the Flash is to write or read data, the storage control chip needs to read and load the "operating system" in advance. The "operating system" records data such as the attribute characteristics and management tables of the Flash. Based on this information, the storage control chip realizes operations such as writing, reading, and erasing of the Flash.

[0003] The data such as the attribute characteristics and management tables of the Flash recorded in the "operating system" are generated by scanning with the computing power of the host side during the pre-analysis stage of mass production. Due to the complexity of the physical structure of the Flash, pre-analysis consumes a large amount of time. Currently, the demand for high-capacity Flash in terminal applications is becoming increasingly prominent. The market has developed many high-capacity Flash products to meet this demand, which are all achieved by increasing the number of internal Blocks and Pages. However, the increase in the number of Blocks and Pages will significantly increase the pre-analysis time, resulting in low mass production efficiency of the Flash. Therefore, it is necessary to optimize the existing Flash pre-analysis. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a pre-analysis optimization method, device, equipment and storage medium, which can shorten the pre-analysis time of the Flash and improve the mass production efficiency.

[0005] The first aspect of the present application provides a pre-analysis optimization method, including:

[0006] Extracting a predetermined number of blocks;

[0007] Extracting pages from the extracted blocks according to a preset interval ratio, where the position interval range of the extracted pages needs to cover the full-page interval range of the Flash;

[0008] Analyzing the extracted pages, and generating attribute data of the Flash according to the analysis result to complete the pre-analysis.

[0009] Preferably, in one preferred embodiment, before extracting the predetermined number of blocks, it further includes:

[0010] Remove abnormal blocks and filter out blocks that can read and write data normally.

[0011] Preferably, in one preferred embodiment, removing abnormal blocks and screening out blocks capable of reading and writing data normally includes:

[0012] Read and load the bad block table that comes with the Flash memory before it leaves the factory. Remove abnormal blocks from the Flash memory based on the bad block table, and filter out blocks that can read and write data normally.

[0013] Preferably, in one preferred embodiment, after reading and loading the bad block table provided by the Flash at the factory, removing abnormal blocks of the Flash according to the bad block table, and screening and retaining blocks that can read and write data normally, the method further includes:

[0014] Processing the retained blocks according to preset processing rules to generate a common page template;

[0015] The common page template is used to uniformly manage the retained blocks.

[0016] Preferably, in one preferred embodiment, the preset processing rules include:

[0017] Configure the error correction bit threshold;

[0018] determining the number of error bits of each page in the retained block;

[0019] Determining the quality of each page according to the number of error bits of each page in each block and the error correction bit number threshold;

[0020] Generate corresponding bit line marks according to the ratio of the number of good pages and bad pages included in the current bit line, and execute the loop until the bit line marks corresponding to all the bit lines are generated;

[0021] Based on the bitline markings, a common page template is created.

[0022] Preferably, in one preferred embodiment, determining the number of error bits of each page in the retained block includes:

[0023] Performing two read and write operations on each page in the retained block, performing XOR processing on the results of the two read and write operations, and analyzing the number of bad pixels based on the results of the XOR processing;

[0024] According to the number of bad pixels included in each frame in the current page, the maximum number of bad pixels is used as the number of error bits of the current page.

[0025] Preferably, in one of the preferred embodiments, the preset interval ratio is equal to the total number of pages of the block divided by the total number of blocks extracted.

[0026] The second aspect of the present application provides a pre-analysis optimization device, including:

[0027] A block extraction module for extracting a predetermined number of blocks;

[0028] A page extraction module for extracting pages from the extracted blocks according to a preset interval ratio, wherein the position interval range of the extracted pages needs to cover the full-page interval range of the Flash;

[0029] A pre-analysis module for parsing the extracted pages and generating attribute data of the Flash according to the parsing results to complete the pre-analysis.

[0030] The third aspect of the present application provides an electronic device, including:

[0031] A processor; and

[0032] A memory having executable code stored thereon, characterized in that when the executable code is executed by the processor, the processor is caused to execute the pre-analysis optimization method as described above.

[0033] The fourth aspect of the present application provides a computer-readable storage medium, characterized in that it stores executable code, and when the executable code is executed by a processor of an electronic device, the processor is caused to execute the pre-analysis optimization method as described above.

[0034] The technical solution of the present application includes: extracting a predetermined number of blocks; extracting pages from the extracted blocks according to a preset interval ratio, wherein the position interval range of the extracted pages needs to cover the full-page interval range of the Flash; parsing the extracted pages and generating attribute data of the Flash according to the parsing results to complete the pre-analysis. By extracting a predetermined number of blocks and the position interval range of the extracted pages covering the full-page interval range of the Flash, it is possible to pre-analyze the attribute data of the Flash without performing a full scan of the Flash during the mass production stage, which can greatly shorten the pre-analysis time of the Flash and thus improve the mass production efficiency of the Flash. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0036] Figure 1 is a schematic flowchart of a pre-analysis optimization method shown in an embodiment of the present application;

[0037] Figure 2 is a schematic flowchart of a pre-analysis optimization method shown in another embodiment of the present application;

[0038] Figure 3 is a schematic flowchart of a pre-analysis optimization method shown in yet another embodiment of the present application;

[0039] Figure 4 shows a schematic structural diagram of a pre-analysis optimization device in an embodiment of the present application;

[0040] Figure 5 shows a schematic structural diagram of a pre-analysis optimization device in another embodiment of the present application;

[0041] Figure 6 shows a schematic structural diagram of a pre-analysis optimization device in yet another embodiment of the present application;

[0042] Figure 7 shows a schematic structural diagram of an electronic device in an embodiment of the present application. Detailed Description of the Invention

[0043] For ease of understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present invention can be understood more thoroughly and comprehensively.

[0044] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only and do not represent the only embodiments.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0046] In related technologies, due to the complexity of the Flash physical structure, pre-analysis consumes a large amount of time. Currently, the demand for high-capacity Flash in terminal applications is becoming increasingly prominent. The market has developed many high-capacity Flash products to meet this demand, which are all achieved by increasing the number of internal Blocks and Pages. However, the increase in the number of Blocks and Pages will significantly increase the pre-analysis time, resulting in low mass production efficiency of Flash.

[0047] Therefore, to solve the above technical problems, the present application provides a pre-analysis optimization method, which can shorten the pre-analysis time of Flash and improve the mass production efficiency.

[0048] The technical solution of the present application will be described in detail below with reference to the accompanying drawings.

[0049] Figure 1 The flowchart of the pre-analysis optimization method in an embodiment of the present application is shown.

[0050] Please refer to Figure 1 , a pre-analysis optimization method, including the following steps:

[0051] Step S110: Extract a predetermined number of blocks.

[0052] In previous firmware code designs, in order to obtain complete Flash attribute data during the pre-analysis stage, a full disk scan of the Flash was performed. A full disk scan means performing read and write operations on all blocks of the Flash, and parsing the Flash attribute data based on the read and write results. However, since the above method involves processing each block of the Flash, the time-consuming duration is quite large, so the pre-analysis time will occupy most of the mass production time. In this embodiment, considering that all blocks in the Flash are produced from the same Flash, there is a very high similarity between blocks and between pages, and even the physical structure characteristics of most blocks and pages are identical. Based on this condition, a process of extracting a predetermined number of blocks to replace all blocks for pre-analysis can be adopted to reduce the pre-analysis time and thus improve the mass production efficiency.

[0053] It should be noted that the "predetermined number" is determined according to the number of blocks included in the Flash, that is, the more blocks the Flash contains, the larger the predetermined number. In this embodiment, the extraction ratio is 30-40%, that is:

[0054] Predetermined number = Total number of blocks in Flash * Extraction ratio 1)

[0055] The extraction ratio is selected to be between 30% and 40%, which can ensure that the number of analysis blocks during pre-analysis is not too small. Additionally, for some Flash blocks, they may exhibit concentration, that is, the good Flash blocks are concentrated at the front, while the unstable or bad blocks are concentrated at the back. To improve the uniformity as much as possible when extracting blocks, in this embodiment, when extracting a predetermined number of blocks, the "spacing" method of block extraction needs to be adopted. For example, assuming the total number of Flash blocks is 10,000, and the extraction ratio is selected to be 40%, according to formula (1), the calculated predetermined number is 4,000. Then, the "spacing" = 10,000 / 4,000 = 2, that is, one block is extracted for every two adjacent spacing points, so that the uniformity of the extracted blocks is strong enough to avoid the extracted blocks being concentrated in a certain interval.

[0056] Step S120: Extract pages from the extracted blocks according to a preset interval ratio, where the position interval range for page extraction needs to cover the entire page interval range of the Flash.

[0057] In this embodiment, the preset interval ratio is equal to the total number of pages of the blocks divided by the total number of extracted blocks.

[0058] On the premise of meeting the requirements for the number and uniformity of the extracted blocks, since a block is the smallest erasable unit of the Flash, and a page is the smallest read / write unit of the Flash, how to extract pages is also a very crucial step. In this embodiment, different from block extraction, page extraction needs to cover the entire page interval range of the Flash. That is, if the maximum number of pages per Flash block is 4,000 pages, then the position interval range of the pages extracted from the extracted blocks needs to completely cover these 4,000 pages. Continuing with the above example, the total number of extracted blocks is 4,000, and the total number of pages per block is 4,000 pages. If the position interval range of the extracted pages is to cover the entire page interval range of the Flash, then the number of pages to be extracted for each extracted block is 1 page. Number these 4,000 extracted blocks as block 0 to block 3,999, then the following can be obtained:

[0059] Block 0: The interval range of the pages to be extracted is page 0;

[0060] Block 1: The interval range of the pages to be extracted is page 1;

[0061] Block 2: The interval range of the pages to be extracted is page 2;

[0062] Block 3: The interval range of the pages to be extracted is page 3;

[0063] ……

[0064] Block 3,999: The interval range of the pages to be extracted is page 3,999.

[0065] In this way, it can be ensured that the position interval range of the extracted page covers the full page interval range of the Flash.

[0066] Step S130: parse the extracted page, generate Flash attribute data according to the parsing result, and complete the pre-analysis.

[0067] It should be noted that after the extraction of the extracted pages is completed, these extracted pages can be parsed. The specific operation is to perform read and write operations on these extracted pages, compare the written data with the read data, generate parsing results based on the comparison results, and finally complete the Flash attribute data. In this embodiment, by extracting a predetermined number of blocks and the location range of the extracted pages covering the entire page range of the Flash, the Flash attribute data can be pre-analyzed in the mass production stage without performing a full scan of the Flash. This can greatly shorten the Flash pre-analysis time and thus improve the efficiency of Flash mass production.

[0068] Figure 2 A schematic flow chart of a pre-analysis optimization method in another embodiment of the present application is shown.

[0069] See also Figure 2 , a pre-analysis optimization method, comprising the following steps:

[0070] Step S210: Remove abnormal blocks and filter out blocks that can read and write data normally.

[0071] It should be noted that, since Flash is naturally equipped with abnormal blocks, these defective blocks can be directly skipped during the mass production stage. These abnormal blocks include blocks that are unstable or cannot write data normally. When Flash leaves the factory, the Flash designer will internally establish a bad block table that records the locations of these abnormal blocks. Users can find these abnormal blocks by reading and loading the bad block table. In this embodiment, before extracting a predetermined number of blocks, it is also possible to read and load the bad block table that comes with the Flash when it leaves the factory, remove the abnormal blocks of the Flash according to the bad block table, prevent these abnormal blocks from being extracted, and enter the pre-analysis process. The purpose of this step is to exclude the abnormal blocks before the blocks are extracted. There is no point in extracting the abnormal blocks. After excluding them, the normal blocks are left. This can eliminate the interference of the abnormal blocks on the accuracy of the pre-analysis results as much as possible, so that the Flash attribute data parsed by the pre-analysis is closer to the real results.

[0072] Step S220: extract a predetermined number of blocks.

[0073] In the previous firmware code design, in order to obtain the complete attribute data of the Flash during the pre-analysis stage, a full scan of the Flash was performed. A full scan means performing read and write operations on all blocks of the Flash, and parsing the attribute data of the Flash based on the read and write results. However, since the above method involves processing each block of the Flash, the time-consuming duration is quite long. Therefore, the pre-analysis time will occupy most of the mass production time. In this embodiment, considering that all blocks in the Flash are produced from the same Flash, there is a very high similarity between blocks and between pages, and even the physical structure characteristics of most blocks and pages are identical. Based on this condition, the process of performing pre-analysis can be carried out by extracting a predetermined number of blocks to replace all blocks, thereby reducing the pre-analysis time and improving the mass production efficiency.

[0074] For the concepts of "predetermined number" and "extraction ratio" and the related cases, please refer to step S110, which will not be elaborated here.

[0075] Step S230: Extract pages from the extracted blocks according to a preset interval ratio, where the position interval range of the extracted pages needs to cover the entire page interval range of the Flash.

[0076] On the premise of meeting the quantity of the extracted blocks and the uniformity of the extracted blocks, since a block is the smallest erasure unit of the Flash and a page is the smallest read / write unit of the Flash, how to extract pages is also a very crucial link. In this embodiment, different from extracting blocks, extracting pages needs to cover the entire page interval range of the Flash. That is, if the maximum number of pages per block of the Flash is 4000 pages, then the position interval range of the pages extracted from the extracted blocks needs to completely cover these 4000 pages.

[0077] For the case of how to extract pages, please refer to step S120, which will not be elaborated here.

[0078] Step S240: Parse the extracted pages, and generate the attribute data of the Flash according to the parsing results to complete the pre-analysis.

[0079] It should be noted that after the extraction of the extracted pages is completed, these extracted pages can be parsed. The specific operation is to perform read and write operations on these extracted pages, compare the written data with the read data, generate parsing results according to the comparison results, and finally complete the attribute data of the Flash. In this embodiment, by extracting a predetermined number of blocks and the position interval range of the extracted pages covering the entire page interval range of the Flash, it is possible to pre-analyze the attribute data of the Flash during the mass production stage without performing a full scan of the Flash, which can greatly shorten the pre-analysis time of the Flash and improve the mass production efficiency of the Flash.

[0080] Figure 3 A schematic flow chart of a pre-analysis optimization method in another embodiment of the present application is shown.

[0081] See also Figure 3 , a pre-analysis optimization method, comprising the following steps:

[0082] Step S310: read and load the bad block table that comes with the Flash memory before it leaves the factory, remove abnormal blocks in the Flash memory according to the bad block table, and filter out blocks that can read and write data normally.

[0083] The description of step S310 can be found in step S210 and will not be repeated here.

[0084] Step S320: Process the retained blocks according to preset processing rules to generate a common page template.

[0085] It should be noted that there may be slight differences between Flash blocks and pages, so in order to make the pre-analysis results as accurate as possible, in this embodiment, a common page template is used to uniformly manage the retained blocks. The common page template is a page template that can be used by all retained blocks. The common page template can reduce the management overhead resources of the storage control chip. The storage control chip only needs to maintain a common page template to achieve page template management for all blocks.

[0086] In this embodiment, the preset processing rules can be executed as follows: configure the error correction bit number threshold; determine the number of error bits for each page in the retained block; judge the good or bad status of each page based on the number of error bits for each page in each block in combination with the error correction bit number threshold; generate corresponding bit line marks based on the ratio of the number of good pages and bad pages included in the current bit line, and execute the rule in a loop until the bit line marks corresponding to all bit lines are generated; and create a common page template based on the bit line marks.

[0087] In this embodiment, the number of error bits on each page of the retained block can be determined by performing two consecutive read and write operations on each page of the retained block. The results of the two read and write operations are then XORed. Based on the XOR result, the number of bad pixels is parsed. Based on the number of bad pixels included in each frame of the current page, the maximum number of bad pixels is used as the number of error bits for the current page. The purpose of performing two consecutive read and write operations is to obtain the most accurate bad pixel location. For Flash, each bit has an initial state of "1". If the data written first is "1", the initial state of the bit will not change. At this time, it is impossible to determine whether the current bit is usable or damaged. Therefore, it is necessary to perform two consecutive write and read operations and XOR the results of the two reads to determine the quality of the current bit.

[0088] For example, if the initial data of the current Bit is "1", during the first write and read operations, the data written is still "1", and the data read is also "1". During the second write and read operations, the data written is "0", and the data read is "0". After performing an exclusive OR operation on "1" and "0", the output is "1", indicating that the current Bit is good.

[0089] If the initial data of the current Bit is "1", during the first write and read operations, the data written is still "1", and the data read is also "1". During the second write and read operations, the data written is "0", and the data read is "1". After performing an exclusive OR operation on "1" and "1", the output is "0", indicating that the current Bit is bad.

[0090] In the firmware code design, each page is composed of several Frames. The page size of most Flash is 16K. In the firmware code design, it is divided into 16 Frames, each Frame is 1K in size, and a certain number of Bit errors will occur in each Frame. In this embodiment, according to the number of bad points included in each Frame in the current page, the maximum number of bad points is used as the error bit number of the current page.

[0091] Subsequently, configure the error correction bit number threshold of the storage control chip to be equal to 72Bit / 1K, that is, the data of each 1K byte can correct at most 72Bit of errors, and errors cannot be corrected if exceeded. Now, the error bit numbers of 5 pages of a certain block are read as 30Bit, 20Bit, 10Bit, 77Bit, and 56Bit respectively. Then there is 1 bad page in this block, and the rest are good pages. Using the above method to complete the judgment of all the remaining blocks, the following Table 1 is obtained. In Table 1, "1" represents that the page at the current page offset is a good page, and "0" represents that the page at the current page offset is a bad page.

[0092] Bit line BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7 Serial number P0 P1 P2 P3 P4 P5 P6 P7 B0 1 1 0 1 1 0 1 1 B1 1 1 0 1 0 1 0 0 B2 1 1 0 1 1 1 1 0 B3 1 0 0 0 0 0 0 0 B4 1 1 0 1 1 1 1 1 B5 1 1 0 1 0 0 1 1

[0093] Table 1

[0094] At the management level, the storage control chip assigns pages at the same offset position in different blocks, and a bit line scheduling is correspondingly assigned. Based on this, a common page template can be created to uniformly manage the pages of each block. According to the quantity ratio of good pages and bad pages included in the current bit line, corresponding bit line marks are generated. For example, on this BL7 bit line, there are 3 good pages and 4 bad pages, and the bad page ratio reaches more than 50%. Then all the pages on this bit line are marked as bad pages, that is, the bit line mark is "0". This is looped until the bit line marks corresponding to all bit lines are generated. Finally, based on the bit line marks, a common page template is created. In the case of Table 1, the finally generated common page template is "1101 100"

[0095] Step S330: Uniformly manage the remaining blocks using the common page template.

[0096] After the creation of the common page template, since not all blocks can be adapted to all blocks, before uniformly managing all blocks with the common page template, it is also necessary to remove the blocks that cannot be adapted to the common page template.

[0097] It should be noted that the management method using the common page template can eliminate the difference problems between blocks and between pages. In the previous two embodiments, the management method using the common page template was not adopted, and the method of directly extracting blocks was used. Although for Flash, the similarity of most blocks and pages is very high, there are still differences in some blocks and pages. And the pre-analysis result is a key link in obtaining Flash attribute data. Before the formal pre-analysis starts, it is necessary to optimize the internal unity of Flash as much as possible, eliminate the gaps between blocks and between pages, and achieve unified management. As a chip product with limited memory management resources, the storage control chip cannot establish a dedicated management template for each block and page of Flash. This will not only greatly increase the management overhead of the storage control chip, but also Flash cannot sacrifice such a large storage capacity to specifically store these exclusive data, which will lead to a significant decrease in the capacity of the mass-produced Flash and affect the price of the terminal mobile storage product. Therefore, in this embodiment, before the formal pre-analysis stage, the internal unity of Flash is realized first, and after eliminating the differences between blocks and pages, it enters the pre-analysis stage to obtain more accurate Flash attribute data.

[0098] Step S340: Extract a predetermined number of blocks.

[0099] For the description of Step S340, please refer to Step S220 and will not be elaborated here.

[0100] Step S350: Extract pages from the extracted blocks according to a preset interval ratio, where the position interval range of the extracted pages needs to cover the full-page interval range of the Flash.

[0101] For the description of step S350, please refer to step S230.

[0102] Step S360: Parse the extracted pages, generate attribute data of the Flash according to the parsing results, and complete the pre-analysis.

[0103] For the description of step S360, please refer to step S240.

[0104] Similar to the foregoing method embodiments, this application discloses a pre-analysis optimization device and its corresponding embodiments.

[0105] Figure 4 The structural schematic diagram of the pre-analysis optimization device in an embodiment of this application is shown.

[0106] Please refer to Figure 4 , a pre-analysis optimization device 400, includes: a block extraction module 410, a page extraction module 420, and a pre-analysis module 430. Among them:

[0107] The block extraction module 410 is used to extract a predetermined number of blocks.

[0108] The page extraction module 420 is used to extract pages from the extracted blocks according to a preset interval ratio, where the position interval range of the extracted pages needs to cover the full-page interval range of the Flash.

[0109] The pre-analysis module 430 is used to parse the extracted pages, generate attribute data of the Flash according to the parsing results, and complete the pre-analysis.

[0110] It should be noted that the pre-analysis optimization method implemented by the pre-analysis optimization device disclosed in this embodiment is as described in the foregoing embodiment, so it will not be elaborated here in detail. Optionally, each module in this embodiment and the above other operations or functions are respectively used to implement the method in the foregoing embodiment.

[0111] Figure 5 The structural schematic diagram of the pre-analysis optimization device in another embodiment of this application is shown.

[0112] Please refer to Figure 5 , a pre-analysis optimization device 400, includes: a removal module 440, a block extraction module 410, a page extraction module 420, and a pre-analysis module 430. Among them: For the block extraction module 410, the page extraction module 420, and the pre-analysis module 430, please refer to , which will not be elaborated here.

[0113] The removal module 440 is used to remove abnormal blocks and filter out blocks that can read and write data normally.

[0114] In this embodiment, the removal module 440 reads and loads the bad block table provided by the Flash at the factory, removes abnormal blocks of the Flash according to the bad block table, prevents these abnormal blocks from being extracted, and enters the pre-analysis process.

[0115] It should be noted that the pre-analysis optimization method implemented by the pre-analysis optimization device disclosed in this embodiment is the same as the above embodiment, so it will not be described in detail here. Optionally, the various modules in this embodiment and the above other operations or functions are respectively for implementing the methods in the above embodiments.

[0116] Figure 4 A schematic structural diagram of a pre-analysis optimization device in another embodiment of the present application is shown.

[0117] See also Figure 6 A pre-analysis optimization device 400 includes: a removal module 440, a processing module 450, a management module 460, a block extraction module 410, a page extraction module 420, and a pre-analysis module 430. The removal module 440, the block extraction module 410, the page extraction module 420, and the pre-analysis module 430 are described in detail in the following sections. Figure 6 , I will not go into details here.

[0118] The processing module 450 is used to process the retained blocks according to preset processing rules to generate a common page template.

[0119] The management module 460 is used to manage the reserved blocks in a unified manner using a common page template.

[0120] It should be noted that the pre-analysis optimization method implemented by the pre-analysis optimization device disclosed in this embodiment is the same as the above embodiment, so it will not be described in detail here. Optionally, the various modules in this embodiment and the above other operations or functions are respectively for implementing the methods in the above embodiments.

[0121] See Figure 5 Figure 7 Another embodiment of the present application shows a computing electronic device 700 including: a processor 710 and a memory 720.

[0122] The processor 710 may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0123] The general-purpose processor may be a microprocessor, or the processor may also be any conventional processor. The memory 710 may include various types of storage units, such as system memory, read-only memory (ROM), and permanent storage devices.

[0124] Among them, the ROM may store static data or instructions required by the processor 720 or other modules of the computer. The permanent storage device may be a readable and writable storage device. The permanent storage device may be a non-volatile storage device that does not lose the stored instructions and data even when the computer is powered off. In some embodiments, the permanent storage device uses a mass storage device (such as a magnetic or optical disk, flash memory) as the permanent storage device.

[0125] In some other embodiments, the permanent storage device may be a removable storage device (such as a floppy disk, optical drive). The system memory may be a readable and writable storage device or a volatile readable and writable storage device, such as dynamic random access memory. The system memory may store some or all of the instructions and data required by the processor during operation.

[0126] In addition, the memory 720 may include any combination of computer-readable storage media, including various types of semiconductor storage chips (such as DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), and magnetic disks and / or optical disks may also be used.

[0127] In some embodiments, the memory 720 may include a removable storage device that is readable and / or writable, such as a compact disc (CD), read-only digital versatile disc (such as DVD-ROM, dual-layer DVD-ROM), read-only Blu-ray disc, super density disc, flash memory card (such as SD card, min SD card, and Micro-SD card, etc.), magnetic floppy disk, etc. The computer-readable storage medium does not include carrier waves and instantaneous electronic signals transmitted wirelessly or by wire. Executable code is stored on the memory 720, and when the executable code is processed by the processor 710, it can cause the processor 710 to execute some or all of the methods described above.

[0128] In addition, the method according to the present application can also be implemented as a computer program or a computer program product, which includes computer program code instructions for performing some or all of the steps in the above method of the present application.

[0129] Alternatively, the present application can also be implemented as a computer-readable storage medium (or non-transitory machine-readable storage medium or machine-readable storage medium), on which executable code (or computer program or computer instruction code) is stored. When the executable code (or computer program or computer instruction code) is executed by a processor of an electronic device (or a server, etc.), the processor is caused to execute some or all of the steps of the above method according to the present application.

[0130] The embodiments of the present application have been described above. The above description is exemplary and not exhaustive, and is also not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, the practical application, or the improvement of the technology in the market, or to enable other ordinary skill in the art in the technical field to understand the embodiments disclosed herein.

Claims

1. A pre-analysis optimization method, characterized in that, include: extracting a predetermined number of blocks; Extracting pages from the extracted block according to a preset interval ratio, wherein the position interval range of the extracted page needs to cover the full page interval range of the Flash; The extracted page is parsed, and Flash attribute data is generated according to the parsing result to complete the pre-analysis.

2. The pre-analysis optimization method according to claim 1, wherein Before extracting the predetermined number of blocks, the method further includes: Remove abnormal blocks and filter out blocks that can read and write data normally.

3. The pre-analysis optimization method according to claim 2, wherein The process of removing abnormal blocks and filtering out blocks that can read and write data normally includes: Read and load the bad block table that comes with the Flash memory before it leaves the factory. Remove abnormal blocks from the Flash memory based on the bad block table, and filter out blocks that can read and write data normally.

4. The pre-analysis optimization method according to claim 2, wherein The process of reading and loading the bad block table provided by the Flash, removing abnormal blocks of the Flash according to the bad block table, and selecting and retaining blocks that can read and write data normally further includes: Processing the retained blocks according to preset processing rules to generate a common page template; The common page template is used to uniformly manage the retained blocks.

5. The pre-analysis optimization method according to claim 4, wherein The preset processing rules include: Configure the error correction bit threshold; determining the number of error bits of each page in the retained block; Determining the quality of each page according to the number of error bits of each page in each block and the error correction bit number threshold; Generate corresponding bit line marks according to the ratio of the number of good pages and bad pages included in the current bit line, and execute the loop until the bit line marks corresponding to all the bit lines are generated; Based on the bitline markings, a common page template is created.

6. The pre-analysis optimization method according to claim 5, wherein Determining the number of error bits of each page in the retained block includes: Performing two read and write operations on each page in the retained block, performing XOR processing on the results of the two read and write operations, and analyzing the number of bad pixels based on the results of the XOR processing; According to the number of bad pixels included in each frame in the current page, the maximum number of bad pixels is used as the number of error bits of the current page.

7. The pre-analysis optimization method according to any one of claims 1 to 6, characterized in that The preset interval ratio is equal to the total number of pages of the block divided by the total number of extracted blocks.

8. A pre-analysis optimization device, characterized in that, include: A block extraction module, configured to extract a predetermined number of blocks; A page extraction module is used to extract pages from the extracted blocks according to a preset interval ratio, wherein the position interval range of the extracted pages needs to cover the full page interval range of the Flash; The pre-analysis module is used to parse the extracted page and generate Flash attribute data according to the parsing result to complete the pre-analysis.

9. An electronic device comprising: processor; as well as A memory having executable code stored thereon, characterized in that when the executable code is executed by the processor, the processor is caused to execute the pre-analysis optimization method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, An executable code is stored, and when the executable code is executed by a processor of an electronic device, the processor is caused to execute the pre-analysis optimization method according to any one of claims 1 to 7.

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