Hardware-accelerated intelligent PCIe SSD optimization system

Abstract

This invention relates to the field of storage control technology, specifically to a hardware-accelerated intelligent PCIe SSD optimization system. The system includes a channel quality monitoring module, an acceleration path identification module, a parameter mapping and filtering module, a balanced link loading module, and a collaborative transmission execution module. This invention achieves dynamic evaluation of storage channel quality by real-time monitoring of signal voltage sampling values ​​and clock offset values, optimizing channel performance configuration, accurately determining channel performance status, and improving data transmission accuracy and efficiency. Through real-time environmental parameter monitoring, it can automatically adjust data paths according to different temperature and voltage conditions, improving system reliability and adaptability. By automatically identifying and adjusting transmission parameters, it reduces the need for manual configuration, lowers operational latency and error rates, enhances overall throughput performance, improves data access speed, and ensures stability and long-term reliability under different operating conditions.

Description

Technical Field

[0001] This invention relates to the field of storage control technology, and in particular to a hardware-accelerated intelligent PCIe SSD optimization system. Background Technology

[0002] Storage control technology primarily involves the organization, management, and access control mechanisms of data within storage devices. Specifically, it covers key technologies such as controller architecture design, interface protocol management, data scheduling strategies, write-erase balancing algorithms, error detection and correction mechanisms, cache management, power consumption control, and data consistency maintenance. In PCIe SSD applications, storage control particularly focuses on queue scheduling for high-concurrency I / O requests, command initiation and completion management, efficient maintenance of flash block mapping tables, and firmware and hardware collaborative processing mechanisms to achieve low-latency, high-throughput, and long-lifespan storage system performance.

[0003] The Intelligent PCIe SSD Optimization System is a PCIe interface solid-state drive control system based on intelligent scheduling and resource adaptive management mechanisms. It aims to improve data access efficiency of SSDs in multi-service, multi-task scenarios. This solution introduces functional components such as a load balancer scheduler, a dynamic queue allocation module, and an access pattern recognizer to identify, classify, and schedule different types of I / O requests. It also adjusts data paths based on real-time performance metrics to optimize resource utilization, reduce system latency, and improve overall throughput.

[0004] Traditional optimization systems lack the ability to dynamically respond to real-time environmental changes. Channel quality assessment is based on static preset standards, neglecting real-time physical environmental changes such as temperature fluctuations and voltage instability. This leads to frequent data transmission errors and performance degradation in practical applications. When handling high-concurrency I / O requests, traditional systems fail to effectively differentiate and optimize the performance of each channel, resulting in uneven resource allocation and impacting overall data processing efficiency. This fixed approach is inflexible in dynamic application environments, failing to fully utilize the potential performance of the hardware and limiting the performance improvement and application expansion of the storage system. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing technologies by proposing a hardware-accelerated intelligent PCIeSD optimization system.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: a hardware-accelerated intelligent PCIe SSD optimization system, the system comprising:

[0007] The channel quality monitoring module acquires the signal voltage sampling value and clock offset value on each lane of the SSD. Based on three judgment conditions, the eye diagram opening is less than the set graph threshold, the voltage fluctuation is greater than the set stability threshold, and the clock offset exceeds the set synchronization threshold, the channel that meets the conditions is marked as the channel that needs to be skipped, and a set of channel identifiers that need to be skipped is generated.

[0008] The accelerated path identification module calculates the deviation score between the current channel data and the reference value based on the required skip channel identifier set, selects the GEN level with the lowest deviation score as the suggested skip channel level, summarizes all Lane suggested levels, and generates a list of channel skip levels.

[0009] The parameter mapping and filtering module searches the pre-loaded GEN level configuration data in the firmware for each channel according to the channel skipping level list. It filters the target parameter combination corresponding to the current temperature and voltage combination, constructs the channel-parameter mapping relationship according to the Lane number, and generates the Lane equalization loading parameter table.

[0010] Based on the Lane equalization loading parameter table, the equalization link loading module determines whether the identified channel is in equalization preparation state, assembles all channel status information into a link activation preparation record, and generates a link equalization startup verification list.

[0011] The present invention improves upon this invention by including the following improvements: the channel identifier set requiring tiering includes channel number identifier, channel matching anomaly label, training stability judgment criteria, signal fluctuation identifier factor, and channel priority processing identifier; the channel tiering level list specifically refers to the channel rate target level, rate level adaptation identifier, level suggestion label, and level selection reason code; the Lane equalization loading parameter table includes equalization level index, electrical configuration number, channel parameter call path, channel parameter structure key value, and configuration mapping relationship key group; and the link equalization startup verification list specifically includes clock lock status label, impedance error judgment identifier, voltage response status field, channel configuration completion mark, and startup confirmation label set.

[0012] The present invention is improved in that the channel quality monitoring module includes:

[0013] The voltage fluctuation extraction submodule obtains the signal voltage sampling value and clock offset value on each lane of the SSD. Combined with the real-time monitoring data collected by the power supply voltage and temperature sensors, it calculates the voltage change amplitude and current fluctuation range value of each channel under the current operating temperature and voltage. It also determines whether the voltage change amplitude is greater than the voltage stability threshold and whether the current fluctuation range is greater than the current tolerance threshold, and obtains the fluctuation offset degree of each channel under the current operating conditions, generating current and voltage offset information.

[0014] The synchronization offset analysis submodule uses current and voltage offset information to call the clock phase data and sampling interval time data of each channel under the current power supply state, calculates the clock phase difference and signal synchronization time difference, and determines whether it exceeds the set synchronization threshold. It extracts the channels that exceed the threshold and marks them as synchronization abnormal channels, retains the eye diagram opening value corresponding to the abnormal channels, and generates the synchronization offset amplitude of the abnormal channels.

[0015] The channel screening and judgment submodule extracts the recorded eye diagram opening based on the synchronous offset amplitude of the abnormal channel, calculates the opening change trend value, and determines whether it is less than the image stability threshold. At the same time, it combines the current and voltage offset information of the channel with the offset amplitude value for judgment. The channel numbers that meet all three abnormal conditions are summarized as objects to be processed, and a set of channel identifiers that need to be skipped is generated.

[0016] The present invention is improved in that the accelerated path identification module includes:

[0017] The record extraction submodule extracts the three most recent GEN2, GEN3, and GEN4 level training records for each numbered channel in the system based on the required skip channel identifier set, and reads the corresponding ambient temperature, voltage stability rate, and training completion time from the records to generate a channel training level sample set.

[0018] The similarity calculation submodule reads the real-time eye opening, voltage change value, and training preparation time of the current channel from the channel training level sample set, and normalizes them with each data point of the same level in the sample record using the formula:

[0019]

[0020] The calculation yields a score indicating the degree of deviation from the assigned level.

[0021] Among them, R c E represents the deviation score of the rating. m E represents the current eye opening. r For reference gear eye diagram values, V m V represents the current voltage change. r T represents the historical voltage stability rate. m To allow time for training preparation, T r For historical training time, S r For reference gear level sequence number;

[0022] The grade filtering submodule determines whether the deviation ratio is lower than the set deviation threshold based on the grade deviation score. It extracts the GEN grade corresponding to the lowest grade deviation score in each channel score and records it as the channel skipping suggestion grade. It then assembles and summarizes each channel suggestion grade by Lane number to generate a channel skipping grade list.

[0023] The present invention is improved in that the parameter mapping and filtering module includes:

[0024] The parameter calling submodule extracts the GEN level of each channel according to the channel skipping level list, retrieves the pre-loaded GEN level configuration data in the firmware for each channel, extracts the pre-emphasis value, deemphasis ratio, equalization coefficient group and impedance target value, organizes them into a structured parameter set according to the Lane number, and generates a channel configuration parameter structure group.

[0025] The combined matching submodule, based on the channel configuration parameter structure group, calls the successfully trained parameter data recorded for each channel under the current temperature and voltage combination. It reads the historical success count, configuration temperature value, historical impedance data, and eye diagram opening for each channel with known parameter combinations, and compares it with the current channel's eye diagram opening using the following formula:

[0026]

[0027] The calculation obtains the matching and adaptation value of the channel parameter combination;

[0028] Among them, C z E represents the number of successful training sessions in the combined history. z ΔT represents the average eye opening value of the corresponding combination in historical records. z R represents the normalized temperature difference between the current channel ambient temperature and the corresponding historical configuration temperature. ez D represents the ratio of the difference between the current channel target impedance and the corresponding combined reference impedance. z M represents the total number of failures of the corresponding combination in the historical record. pz This indicates the matching and adaptation value for the combination of channel parameters;

[0029] The mapping generation submodule selects the parameter combination with the highest matching value for each channel based on the matching adaptation value of the channel parameter combination, establishes a key-value correspondence between the Lane number and the parameter combination, and builds an index list according to the Lane order to generate the Lane balanced loading parameter table.

[0030] The present invention is improved in that the load balancing link module includes:

[0031] Based on the Lane equalization loading parameter table, the parameter writing submodule writes the pre-emphasis value, equalization coefficient group and target impedance value corresponding to each channel into the PHY register area. After completing the configuration of each channel, it records the parameter writing status identifier and register response delay information, establishes a mapping pair between the Lane and the parameter response status, and generates the parameter loading and writing delay value.

[0032] The feedback measurement submodule loads and writes the delay value according to the parameters, reads the current impedance value, voltage adjustment amplitude and clock phase-locked time of each channel after configuration, calculates the deviation value between the feedback index and the target parameter, compares it with the corresponding error threshold, extracts the channel number where all three errors are less than the threshold and marks it as feedback compliant, and generates a set of channel feedback error ratios.

[0033] The channel confirmation submodule filters the channel numbers that meet the feedback standards based on the channel feedback error ratio set, extracts the configuration completion status flag, integrates the channel information that meets the equalization conditions into a unified link loading record, establishes a structured activation preparation information set, and generates a link equalization startup verification list.

[0034] The present invention has an improvement, wherein the system further includes:

[0035] According to the link balancing start verification list, the collaborative transmission execution module initiates the training sequence TS1 instruction, sends a hop handshake request for the target GEN level, and compares the number of response channels with the total number of channels after the channel returns the TS2 confirmation response. It calculates the handshake success rate and compares it with the set success rate threshold. If the judgment is passed, the SSD is instructed to enter the L0 transmission state and record the hop-up successful channels and the loaded parameter content, generating a hop balancing success mapping record.

[0036] The successful tier balancing mapping record includes a channel tier balancing result mapping table, a GEN level handshake success label, a transmission status record field, a parameter loading history index, and a confirmed channel set.

[0037] The present invention is improved in that the collaborative transmission execution module includes:

[0038] The handshake initiation submodule, based on the link balancer startup verification list, generates a TS1 training request sequence for each channel according to the recorded channel configuration status and GEN level configuration items, writes the GEN level target value field and sends a handshake request, records the number of TS2 response sequences returned by the host and the channel number sequence, and generates a handshake response channel set.

[0039] The channel confirmation submodule calculates the response ratio between the number of channel responses and the total number of packets sent, based on the handshake response channel set, and calculates the channel response interval difference and the number of handshake packet losses using the following formula:

[0040]

[0041] The handshake stability coefficient of the channel is obtained through calculation;

[0042] Among them, S x A represents the handshake stability coefficient of the channel. x L represents the percentage of handshake fields in the data segment sent through the channel.x T represents the packet loss rate during the channel handshake. x B represents the total duration of the channel handshake feedback. x D represents the number of buffer write bursts for the corresponding channel at the host receiver. x This represents the variance of the handshake delay between channels;

[0043] The mapping generation submodule excludes channels with stability coefficients lower than the set response threshold based on the handshake stability coefficient of the channels, summarizes the remaining channels into a set of channels that can enter the L0 state, retrieves the GEN level and parameter group number configured for the channel, establishes a mapping index table of channel number, skip level and parameter group triplet, integrates them in the order of channels to generate a unified record structure, and generates a skip level balancing successful mapping record.

[0044] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0045] In this invention, by real-time monitoring of signal voltage sampling values ​​and clock offset values, dynamic evaluation of storage channel quality is achieved, optimizing channel performance configuration. By comprehensively analyzing eye diagram opening, voltage and current fluctuations, the performance status of the channel is accurately determined, improving the accuracy and efficiency of data transmission. Through real-time environmental parameter monitoring, the data path can be automatically adjusted according to different temperature and voltage conditions, improving the reliability and adaptability of the system. By automatically identifying and adjusting transmission parameters, the need for manual configuration is reduced, while operating latency and error rate are lowered, enhancing overall throughput performance, improving data access speed, and ensuring stability and long-term reliability under different operating conditions. Attached Figure Description

[0046] Figure 1 This is a system flowchart of the present invention;

[0047] Figure 2 This is a flowchart of the channel quality monitoring module of the present invention;

[0048] Figure 3 This is a flowchart of the accelerated path recognition module of the present invention;

[0049] Figure 4 This is a flowchart of the parameter mapping and filtering module of the present invention;

[0050] Figure 5 This is a flowchart of the load balancing module of the present invention;

[0051] Figure 6 This is a flowchart of the collaborative transmission execution module of the present invention. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0053] In the description of this invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, in the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0054] Please see Figure 1 This invention provides a technical solution: a hardware-accelerated intelligent PCIe SSD optimization system, the system comprising:

[0055] The channel quality monitoring module acquires the signal voltage sampling value and clock offset value on each lane of the SSD, reads the eye diagram opening, voltage stability, and current fluctuation range of each channel, and collects the current power supply voltage and working environment parameters detected by the temperature sensor. The data group is integrated according to the lane number, and the channel is screened based on three judgment conditions: eye diagram opening less than the set graphic threshold, voltage fluctuation greater than the set stability threshold, and clock offset exceeding the set synchronization threshold. Channels that meet the conditions are marked as channels that need to be skipped, and a set of channel identifiers that need to be skipped is generated.

[0056] The accelerated path identification module is based on the channel identification set that needs to be skipped. It reads the historical records of each marked channel successfully establishing GEN2, GEN3, and GEN4 links in the last three training sessions, extracts the eye diagram opening reference value, voltage stability rate, and training time records under the corresponding temperature range, calculates the deviation score between the current channel data and the reference value, selects the GEN level with the lowest deviation score as the suggested channel skipping level, summarizes all Lane suggested levels, and generates a list of channel skipping levels.

[0057] The parameter mapping and filtering module searches the pre-loaded GEN level configuration data in the firmware for each channel according to the channel skipping level list. This includes the pre-emphasis value, deemphasis ratio, equalization coefficient group and target impedance value, corresponding to the current temperature and voltage combination. It filters the target parameter combination, constructs the channel-parameter mapping relationship according to the Lane number, and generates the Lane equalization loading parameter table.

[0058] The equalization link loading module is based on the Lane equalization loading parameter table. It writes the selected parameters of each channel into the PHY register area, sets the pre-emphasis, equalization coefficient group and impedance value, reads the configuration and then feeds back the impedance matching error, voltage adjustment amplitude and clock phase-locked time. If the three feedback values ​​are all less than the set error threshold, it indicates that the channel has the equalization preparation state. It assembles all channel status information into a link activation preparation record and generates a link equalization start verification list.

[0059] The collaborative transmission execution module initiates the training sequence TS1 instruction according to the link balancing start verification list, sends a hop handshake request for the target GEN level, and compares the number of response channels with the total number of channels after the channel returns the TS2 confirmation response, calculates the handshake success rate and compares it with the set success rate threshold. If the judgment is passed, the SSD is instructed to enter the L0 transmission state and record the channels that have successfully hopped and the loaded parameter content, and generates a hop balancing success mapping record.

[0060] The required tiered channel identifier set includes channel number identifier, channel matching anomaly label, training stability judgment basis, signal fluctuation identifier factor, and channel priority processing identifier. The channel tiered level list specifically refers to the channel rate target level, rate level adaptation identifier, level suggestion label, and level selection reason code. The Lane equalization loading parameter table includes equalization level index, electrical configuration number, channel parameter call path, channel parameter structure key value, and configuration mapping relationship key group. The link equalization start verification list specifically includes clock lock status label, impedance error judgment identifier, voltage response status field, channel configuration completion mark, and start confirmation label set. The tiered equalization successful mapping record includes the channel tiered result mapping table, GEN level handshake success label, transmission status record field, parameter loading history index, and confirmed completion channel set.

[0061] Please see Figure 2 The channel quality monitoring module includes:

[0062] The voltage fluctuation extraction submodule obtains the signal voltage sampling value and clock offset value on each lane of the SSD. Combined with the real-time monitoring data collected by the power supply voltage and temperature sensors, it calculates the voltage change amplitude and current fluctuation range value of each channel under the current operating temperature and voltage. It also determines whether the voltage change amplitude is greater than the voltage stability threshold and whether the current fluctuation range is greater than the current tolerance threshold, and obtains the fluctuation offset degree of each channel under the current operating conditions, generating current and voltage offset information.

[0063] To obtain the signal voltage and current feedback values ​​on all lanes of the SSD, it is necessary to retrieve the voltage signal and current feedback data sampled every 0.5 microseconds from the front-end sensing sampling point of each channel. With the data point time range set to 10 microseconds, a total of 20 sets of sample values ​​are collected per channel and stored in array format. For example, the sample values ​​could be represented as a voltage sequence like V. s1 V s2 ,...,V s20 The current sequence is I s1 ,I s2 ,...,I s20 Based on the current power supply voltage (set to 3.3V) and the real-time monitoring value of the temperature sensor (set to 50℃), the basic state of the channel's operating environment is constructed, and the voltage change amplitude of each channel is calculated as ΔV = max(V s1..s20 )-min(V s1..s20 The calculation method for the current fluctuation range is the same, set as ΔI = max(I s1..s20 )-min(I s1..s20 To determine whether a channel is in an abnormal voltage or current fluctuation state, a voltage stability threshold and a current tolerance threshold need to be set. The voltage stability threshold is based on the recommended operating voltage range of the SSD controller chip, set to a normal operating voltage of 3.3V ± 4.5%. Therefore, the allowable voltage fluctuation range is ± 0.1485V, rounded up to 0.15V for easier grading. Thus, a voltage fluctuation exceeding 0.3V (i.e., ± 0.15V bidirectional) is set as the voltage stability threshold. The current tolerance threshold is based on the dynamic current range of the PHY layer register under signal loading conditions, set according to the datasheet to a fluctuation range of around 0.1A, i.e., a threshold of 0.1A. If a channel's ΔV > 0.3V and ΔI > 0.1A, then the channel is marked as a fluctuating channel, its number is written into the channel evaluation table, and the next step proceeds to determine the synchronization offset state. At this stage, the ratio of voltage change amplitude to current fluctuation range needs to be generated for subsequent channel behavior structure judgment. The formula is... In the example, if ΔV = 0.35V and ΔI = 0.08A, then R vi =0.35 / 0.08=4.375. In this section, the evaluation of whether this ratio is abnormal needs to refer to the general power consumption stability benchmark, and take its warning value as 4.0. It is determined based on the impedance voltage response balance point under the simulation board experiment. If the Rvi value exceeds 4.0, it means that the voltage response to current change is abnormal and should trigger the channel attention mark. This ratio characterizes the intensity of voltage instability performance of the channel under unit current fluctuation conditions. If it exceeds the preset evaluation benchmark value of 4, it is considered that the fluctuation is serious, and its voltage current offset ratio is recorded as a valid evaluation value and participates in the subsequent channel identification generation.

[0064] The synchronization offset analysis submodule uses current and voltage offset information to call the clock phase data and sampling interval time data of each channel under the current power supply state, calculates the clock phase difference and signal synchronization time difference, and determines whether it exceeds the set synchronization threshold. It extracts the channels that exceed the threshold and marks them as synchronization abnormal channels, retains the eye diagram opening value corresponding to the abnormal channels, and generates the synchronization offset amplitude of the abnormal channels.

[0065] Based on the current-voltage offset ratio, it is necessary to further call the phase-locked signal sampling data fed back from the current clock control register of each channel. Let the phase-locked output of each channel be the clock reference pulse interval sequence θ1,θ2,...,θ 20 The theoretical sampling interval for each channel is 10ns. However, in real-world environments, there may be slight perturbations. Therefore, it is necessary to calculate the phase difference between consecutive sampling points. The clock phase difference for each channel is defined as Δφ = max(θ). i -θ i-1 Taking 10ns as an ideal reference, if channel A has θ i-1 =10.1ns, θ i =10.5ns, then Δφ = 0.4ns. The synchronization threshold here is set based on the stable boundary value of the PHY module's internal phase-locked loop output. If the continuous offset of the sampling point in the PLL feedback exceeds 0.3ns, it causes a sampling synchronization fault. Therefore, the synchronization threshold is set to 0.3ns. When Δφ > 0.3ns, it is considered a phase-locked loop fluctuation state. Simultaneously, the eye diagram opening value ε of the channel signal sampling is extracted. If it is a normalized value after modularization, the range is limited to 0.0, 1.0. For example, if the sampling result is ε = 0.58, and Δφ > 0.3ns, the channel is considered to have a synchronization anomaly. The values ​​of Δφ and ε need to be recorded to form a channel structure evaluation table. The synchronization offset amplitude is defined as S. sync =Δφ×(1-ε), substituting the example value S sync =0.4×(1-0.58)=0.168ns. The synchronous offset evaluation reference value is set based on the average minimum fault tolerance of 0.15ns in the phase-locked loop stability evaluation experiment. When the synchronous offset amplitude exceeds this value, it is considered that the offset fluctuation affects the stable response of the system in the initial stage of training. If it is greater than the set synchronous evaluation reference amplitude of 0.15ns, the channel is recorded as an abnormal channel and its number is incorporated into the subsequent graphic trend calculation process.

[0066] The channel screening and judgment submodule extracts the recorded eye diagram opening based on the synchronous offset amplitude of the abnormal channel, calculates the opening change trend value, and determines whether it is less than the image stability threshold. At the same time, it combines the current and voltage offset information of the channel with the offset amplitude value for judgment, and summarizes the channel numbers that meet the three abnormal conditions into objects to be processed, generating a set of channel identifiers that need to be skipped.

[0067] Based on the synchronization offset amplitude of the abnormal channel, a time-series analysis needs to be performed on the eye opening ε sequence recorded by the abnormal channel. Let each channel have 8 consecutive eye opening samples as arrays ε1, ε2, ..., ε8. The trend value of the opening change is the absolute average of its first-order differences, defined as... If a channel records values ​​of 0.62, 0.59, 0.55, 0.54, 0.52, 0.49, 0.47, 0.45, then T ε = (|0.59-0.62|+...+|0.45-0.47|) / 7 = 0.0243. The image stability threshold in the opening trend judgment is set according to the acceptable range of the image quality degradation rate of the judgment channel in the modulus judgment. If it is lower than 0.03, it is considered that the trend is declining and tending to converge, and is easily affected by non-adjustable factors. The value setting depends on twice the grating calculation accuracy error ±0.015 under the board-level ADC reflection response as the steady-state limit, which is 0.03. If this value is less than the image stability threshold of 0.03, it is judged as an opening trend. The convergence of potential indicates that the channel may be subject to both signal interference and hardware jitter in the current environment. Combined with the channel's voltage-to-current offset ratio of 4.375 and synchronization offset amplitude of 0.168ns, a joint judgment is made. The channel marking rule is defined as follows: when all three evaluation indicators exceed their corresponding thresholds (voltage-to-current ratio greater than 4, synchronization offset amplitude greater than 0.15ns, and opening trend value less than 0.03), the channel is officially marked as a channel requiring hopping, and its number is written into the structure control word. Finally, a set of identifiers for channels requiring hopping is generated. This combined rule is used to logically separate channels under multiple mismatches such as physical interference, electrical instability, and protocol synchronization, and provides an effective initial identification set for subsequent path identification.

[0068] Please see Figure 3 The accelerated path recognition module includes:

[0069] The record extraction submodule extracts the three most recent GEN2, GEN3, and GEN4 level training records for each numbered channel in the system based on the channel identifier set that needs to be skipped, and reads the corresponding ambient temperature, voltage stability rate, and training completion time from the records to generate a channel training level sample set.

[0070] Obtain all channel numbers from the set of channel identifiers that need to be skipped, denoted as C1, C2, ..., C... nThe number is passed to the SSD controller training log reading interface, and the three most recent GEN2, GEN3, and GEN4 level training records for each channel are read. Let the three records for channel C_5 be GEN2-success, GEN3-failure, and GEN4-success, respectively. The three indicators of temperature, voltage stability rate and training time recorded in the corresponding training process record fields are extracted. The training temperatures are set to 45℃, 48℃ and 50℃, the voltage stability rate is recorded as 98%, 95% and 96% respectively, and the training completion time is 240μs, timeout and 220μs respectively. The voltage stability rate is defined as the normalized result of the average voltage / maximum voltage, with a stability benchmark set at 95%. Based on the 3.3V ± 5% fluctuation range defined by JEDEC in the flash memory interface standard, the stable range is 3.135V to 3.465V. Fluctuations greater than ± 0.165V are considered unstable. A normalized value exceeding 0.95 is considered stable. Therefore, a stability rate value greater than 0.95 recorded in the training log indicates excellent voltage maintenance, while a value lower indicates a non-ideal state. The training completion time is directly read from the channel timer register return value, in microseconds. The generated training level sample set is structured as a three-field tuple "temperature, voltage stability rate, time consumption". After mapping with GEN level as index, it is combined into a third-order sample dictionary, such as: GEN2:{45,0.98,240}, GEN3:{48,0.95,timeout}, GEN4:{50,0.96,220}. The data of each level is organized into the historical training mapping base of the channel, and finally the channel training level sample set is generated.

[0071] The similarity calculation submodule reads the real-time eye opening, voltage change value, and training preparation time of the current channel from the channel training level sample set, and normalizes them with each data point of the same level in the sample record using the formula:

[0072]

[0073] The calculation yields a score indicating the degree of deviation from the assigned level.

[0074] Among them, R c E represents the deviation score of the rating. m E represents the current eye opening. r For reference gear eye diagram values, V m V represents the current voltage change. r T represents the historical voltage stability rate. m To allow time for training preparation, T r For historical training time, S r For reference gear level sequence number;

[0075] Based on the channel training level sample set, read the real-time status indicators of the current channel, including eye opening, voltage change value, and training preparation time. Let E be the eye opening read by the current channel C_5 in the current training state. m =0.72, voltage change value is V m =0.14V, training preparation time is T m =180μs, extract the reference value E corresponding to GEN2 level from the training level sample set generated in the previous step. r =0.69, V r =0.15V,T r =240μs, GEN level number is defined as: GEN2 is S r =2, GEN3 is 3, GEN4 is 4. To standardize the above differences, the three participating terms are expressed as direct differences or square roots, and then the GEN level number plus one is used as the normalization division term. Substituting these values ​​into the original formula:

[0076]

[0077] After substituting the parameters, the calculation process is as follows:

[0078] |E m -E r |=|0.72-0.69|=0.03;

[0079] |V m -V r |=|0.14-0.15|=0.01V;

[0080] |T m -T r |=|180-240|=60, then

[0081] Substituting into the formula, we get:

[0082]

[0083] Among them, E m This represents the real-time eye opening under the current training environment. The data is collected from the PHY link monitoring module, and the unit is a normalized scale value; E r V represents the opening value in the GEN2 training history; m This represents the voltage fluctuation range within the current sampling period, calculated as the maximum voltage minus the minimum voltage; V r The average stable amplitude in the historical records of GEN2, in volts; T m T is the latency count between the current configuration and the start of training, in microseconds; rThe time taken to complete the previous training task in GEN2 mode; S r This is the GEN level number. No weighting factors are used in this formula, therefore the three feature items have equal weight in the score. If a weight control mechanism is needed later, a weighting factor can be introduced for the difference item, but the current version maintains consistency with the benchmark. The deviation threshold is set to 2.8 based on the median range of the inter-channel score distribution in the empirical training records, i.e., if R... c A score <2.8 is considered a successful match. This score represents the overall deviation strength between the current channel C_5 and the GEN2 training level in three dimensions: eye diagram, voltage, and time. The lower the value, the higher the degree of matching with the historical state, and the more suitable it is as a target for skipping levels. This deviation score will be used to determine the level in the following section.

[0084] The grade filtering submodule determines whether the deviation ratio is lower than the set deviation threshold based on the grade deviation score. It extracts the GEN grade corresponding to the lowest grade deviation score in each channel score and records it as the channel skipping suggestion grade. It then assembles and summarizes each channel suggestion grade by Lane number to generate a channel skipping grade list.

[0085] Based on the deviation score, the minimum score of all GEN levels for the current channel needs to be selected as the recommended level for channel upgrade. Let's assume channel C_5 has the following scores across the three levels: GEN2 score of 2.5953 (already calculated), GEN3 score of 3.1821, and GEN4 score of 2.9914. Comparing these values, the minimum is 2.5953 for GEN2. The deviation threshold is set to 2.8, based on the upper quartile of the deviation from the matched level, calculated from a large amount of historical scoring data in actual SSD operation. This quartile represents the maximum tolerance threshold for accurate matching. This setting allows for reasonable matching even with variations in temperature and voltage in the training environment. Therefore, if the score is less than 2.8, it means the channel highly matches the training characteristics of a certain level, and it can be directly selected as the target for upgrade. During the judgment step, the system first sorts the GEN scores and compares them with a deviation threshold of 2.8. Only GEN levels below this threshold are selected; if multiple levels meet the criteria, the lowest score is chosen. Channel C_5's score satisfies that GEN2 is the lowest and below the threshold, therefore it is recorded as the channel's suggested level GEN2, completing the score-level mapping. Finally, all channel numbers are iterated through, and the suggested GEN levels for each channel are summarized sequentially by Lane number, forming an indexed data structure such as: Lane0:GEN2, Lane1:GEN4, Lane2:GEN3... The output is then formatted uniformly to generate a list of channel skip levels.

[0086] Please see Figure 4 The parameter mapping filtering module includes:

[0087] The parameter call submodule extracts the GEN level of each channel according to the channel skipping level list, retrieves the pre-loaded GEN level configuration data in the firmware for each channel, extracts the pre-emphasis value, deemphasis ratio, equalization coefficient group and impedance target value, organizes them into a structured parameter set according to the Lane number, and generates a channel configuration parameter structure group.

[0088] Based on the GEN level of each channel in the channel hopping level list, the firmware preset configuration template is retrieved channel by channel. Let's assume the currently processed channel is Lane_3, with a recommended GEN level of GEN3. The GEN3 level configuration index table preloads four different configuration templates. The templates record the following fields: Pre-emphasis value (Pre), De-emphasis ratio (Post), Equalization coefficient group (EqSet), and Impedance target value (Zref). Pre and Post are in dB, EqSet is the normalized level value, and Zref is in ohms. The current template's field group is read as: Pre = 6dB, Post = 3dB, EqSet = 0.85, Zref = 50Ω. These are then associated with the Lane number to form a structured array item. The channel hopping level list contains eight channel numbers, from Lane_0 to Lane_7, covering three GEN levels: GEN2 to GEN4. GEN2 corresponds to three preset templates, and GEN4 corresponds to five preset templates. The number of templates varies depending on hardware firmware resource limitations. After the retrieval is complete, all configuration groups under the corresponding GEN level for each channel are associated and organized according to the channel number. The data structure is designed as a key-value mapping: the key is the Lane number, and the value is the configuration array. Each group of configurations in the array is represented by field pairs, and finally, a channel configuration parameter structure group is constructed. The data type of all configuration groups is a fixed value with a range label. For example, the Pre value is limited to 4-10dB, the Post value is limited to 2-6dB, the EqSet is normalized to the range of 0.5-1.0, and the Zref is limited to the range of 40-60Ω. If the read data is not within the range, the template is marked as invalid and excluded from the configuration set.

[0089] The combined matching submodule, based on the channel configuration parameter structure group, retrieves the successfully trained parameter data recorded for each channel under the current temperature and voltage combination. It reads the historical success rate, configuration temperature value, historical impedance data, and eye diagram opening for each channel with known parameter combinations, and compares it with the current channel's eye diagram opening using the following formula:

[0090]

[0091] The calculation obtains the matching and adaptation value of the channel parameter combination;

[0092] Among them, C zE represents the number of successful training sessions in the combined history. z ΔT represents the average eye opening value of the corresponding combination in historical records. z R represents the normalized temperature difference between the current channel ambient temperature and the corresponding historical configuration temperature. ez D represents the ratio of the difference between the current channel target impedance and the corresponding combined reference impedance. z M represents the total number of failures of the corresponding combination in the historical record. pz This indicates the matching and adaptation value for the combination of channel parameters;

[0093] Before performing adaptability scoring on each parameter combination based on the channel configuration parameter structure group, the current channel's operating temperature and actual sampled eye diagram opening were collected. The current Lane_3 operating temperature was set to 54℃, eye diagram opening to 0.73, and target impedance to 52Ω. Three usable templates were found in the GEN3 level configuration, corresponding to C success rates in the historical records. z =7, 9, 11 times, average eye diagram E z The values ​​are 0.71, 0.69, and 0.74 respectively; the historical configuration temperatures are 52℃, 53℃, and 55℃; the historical impedance values ​​are 50Ω, 49Ω, and 53Ω; and the number of failures is D. z For iterations 1, 3, and 2, the absolute value of the difference between the current temperature of 54℃ and the template temperature is |ΔT|. z | and normalize to [0,1]. Assume the maximum allowable temperature difference is 10℃, i.e., normalized temperature difference = actual difference / 10. The impedance difference ratio is calculated as R. ez =|Z m -Z r | / Z r Where Z_m is the current channel target impedance of 52Ω, and Z_r is the template impedance, the three sets of parameters obtained by substituting the data are as follows:

[0094] Group 1: C z =7,E z =0.71, ΔT z =|54-52| / 10=0.2, R ez =|52-50| / 50=0.04, D z =1;

[0095] Group 2: C z =9,E z =0.69, ΔT z =0.1, R ez =0.06, D z =3;

[0096] Group 3: C z =11,E z =0.74, ΔTz =0.1, R ez =0.019, D z =2;

[0097] Substitute into the formula to calculate the matching fit value:

[0098]

[0099] The final results show that the third set of parameter combinations in the three sets of templates matches the adaptation value M. p3 =2.634 is the maximum value. This value represents the best fit of the current channel configuration with historical data. It has small deviation, stable eye diagram performance, controllable impedance deviation, and low failure rate. Therefore, it is the best configuration choice for this channel.

[0100] Parameter description:

[0101] C z The number of times a template has been successfully trained in history indicates its reliability.

[0102] E z : The average eye diagram opening recorded during successful training, with a value of [0.0, 1.0];

[0103] ΔT z The difference between the current temperature and the historical temperature of the template is normalized, with the normalization benchmark set to 10℃.

[0104] R ez Impedance difference ratio, defined as the absolute difference between the target impedance and the historical impedance divided by the historical impedance;

[0105] D z The number of times this combination has failed in the past is used as a failure penalty factor;

[0106] M pz : Matching and adaptation value for channel parameter combinations; the larger the value, the better the match.

[0107] The advantage of the formula lies in its ability to construct a comprehensive scoring model by simultaneously incorporating eye diagram opening performance, environmental differences (temperature normalization), impedance differences, and historical success / failure distribution. This gives the scoring mechanism robustness against interference and multi-factor correlation. With ΔT z Suppressing the linear amplification of extreme bias terms improves model stability.

[0108] The mapping generation submodule selects the parameter combination with the highest matching value for each channel based on the matching adaptation value of the channel parameter combination, establishes a key-value correspondence between the Lane number and the parameter combination, and builds an index list according to the Lane order to generate the Lane balanced loading parameter table.

[0109] Based on the matching adaptation values ​​of each channel combination, the highest-scoring group from the templates retrieved for each channel is selected. Assuming three groups of scores for Lane_3 are already obtained, the maximum score is M. p3 =2.634, then the third configuration group is selected as the final configuration item for Lane_3. Here, a key-value relationship needs to be established, mapping Lane_3 to the configuration number P3 of this group. This operation is performed sequentially on other channels. Lane numbers are arranged in order starting from 0, and summarized into a structured mapping list, such as:

[0110] Lane0:P2, Lane1:P4, Lane2:P1, Lane3:P3... are recorded in JSON format and written into the controller data exchange block to complete the configuration distribution preparation. Finally, a Lane load balancing parameter table is generated for subsequent PHY register loading operations and status feedback verification. This parameter table is the core data structure in the system configuration closed-loop chain, directly determining the execution result of the configuration distribution and the accuracy of the load balancing path construction.

[0111] Please see Figure 5 The load balancing module includes:

[0112] The parameter writing submodule is based on the Lane equalization loading parameter table. It writes the pre-emphasis value, equalization coefficient group and target impedance value corresponding to each channel into the PHY register area. After completing the configuration of each channel, it records the parameter writing status identifier and register response delay information, establishes a mapping pair between the Lane and the parameter response status, and generates the parameter loading and writing delay value.

[0113] Based on the Lane equalization loading parameter table, the system calls the corresponding parameter set for each channel number item by item. Each item contains three control fields: pre-emphasis value, equalization coefficient group, and target impedance value. Assuming the pre-emphasis value to be written to Lane_2 is 2.5dB, the corresponding coefficient group is 0.9, 1.0, 0.85, and the target impedance value is set to 33Ω, the system first initializes the PHY register interface state, enables write access to the channel, and writes each parameter field by field to its corresponding register address, such as pre-emphasis value write address 0xA0, equalization coefficient group write addresses 0xA1-0xA3, and target impedance write address 0xA4. After each write operation, the system reads the register control... The write operation is controlled to determine whether the write operation is complete. The built-in timer module records the response time from the issuance of the write command to the return of the ACK signal in the register. If the ACK responses for the three fields of Lane_2 are 4μs, 6μs, and 5μs respectively, the maximum response value is recorded as the write delay value for that channel, which is 15μs. The write status flag is a binary flag of "complete" or "failure". The failure flag appears when the register response value is incorrect or the time limit is exceeded. For example, when the response delay value exceeds 20μs, it is recorded as failure. In the current example, 15μs is within the valid range. The mapping is constructed as: Lane_2 → complete, 15μs. All channel records are summarized, and the parameter loading write delay value is generated.

[0114] The feedback measurement submodule loads and writes the delay value according to the parameters, reads the current impedance value, voltage adjustment amplitude and clock phase-locked time of each channel after configuration, calculates the deviation between the feedback index and the target parameter, compares it with the corresponding error threshold, extracts the channel number where all three errors are less than the threshold and marks it as feedback compliant, and generates a set of channel feedback error ratios.

[0115] Based on the parameter loading and writing delay value, the system enters the feedback reading phase, calling the feedback interface channel by channel to read the current impedance value, voltage adjustment amplitude, and clock phase-locked time of the configured channel. Assuming the data returned after Lane_2 is written is 35.1Ω, voltage adjustment is 0.12V, and phase-locked time is 210μs, the error is calculated by comparing it with the set target impedance of 33Ω, voltage adjustment reference value of 0.1V, and target phase-locked time of 200μs, resulting in the impedance deviation. Voltage amplitude modulation error is Phase-locked time error is The system sets the following error thresholds: impedance difference threshold 0.08, voltage amplitude modulation threshold 0.25, and phase-locked time deviation threshold 0.1. These thresholds are based on the signal tolerance specifications allowed for SSD link establishment. For example, JEDEC recommends that the impedance deviation should not exceed 10%, which is set to 8% here for convergence control. The phase-locked time is set to a maximum tolerance deviation of 10% according to the stable phase-locking requirements in the control chip manual, which is normalized to a threshold of 0.1. The voltage amplitude modulation is set to 0.25 with reference to the sampling average voltage tolerance. After calculation, all values ​​do not exceed their respective thresholds. Therefore, Lane_2 is recorded as the feedback compliant channel. Its number and the ratio of the three errors are recorded to generate a channel feedback error ratio set.

[0116] The channel confirmation submodule filters the channel numbers that meet the feedback standards based on the channel feedback error ratio set, extracts the configuration completion status flag, integrates the channel information that meets the equalization conditions into a unified link loading record, establishes a structured activation preparation information set, and generates a link equalization startup verification list.

[0117] Based on the channel feedback error ratio set, the system filters all channels that meet the feedback criteria, checks whether their parameter write status flag is "complete," and further extracts the PHY controller status field of these channels. Only channels whose configuration completion confirmation flag is 1 can proceed to the next step of the activation preparation set generation process. Assuming that Lane_2 and Lane_3 meet all conditions, their numbers, loaded parameter contents, response delay values, and error values ​​are encapsulated in a structured data structure to form a complete link loading confirmation record. The system then summarizes all channel confirmation records and organizes them into a Lane index structure to generate a link balancing startup verification list. This list will serve as the basis for the judgment input in the next stage, the TS handshake stage.

[0118] Please see Figure 6 The collaborative transmission execution module includes:

[0119] The handshake initiation submodule is based on the link balancer start verification list. According to the recorded channel configuration status and GEN level configuration items, it generates a TS1 training request sequence for each channel, writes it into the GEN level target value field and sends a handshake request. It records the number of TS2 response sequences returned by the host and the channel number sequence, and generates a handshake response channel set.

[0120] Based on the channel configuration status and GEN level configuration items recorded in the link balancing startup verification list, the system sequentially retrieves the corresponding GEN level field and loading parameter group for each channel and writes them into the control segment of the TS1 training sequence packet. The GEN target level item is directly assigned a value according to the verification list content. For example, if the target level of Lane_4 is GEN3, then the target level field in its TS1 structure is set to 03h. Subsequently, based on the TS command sending mechanism, the system uses the PHY channel broadcast mechanism to send TS1 frames. Assuming there are 16 Lanes in the channel group, the system sequentially completes the TS1 writing and sending operations for all Lanes at 500ns intervals. After receiving the data, the host returns a TS2 response packet. The system calls the controller's built-in TS2 detection mechanism to record the response frame in the receive buffer. Let the response channel number set be Lane0, Lane1, Lane3, Lane4, Lane6, Lane7, Lane9, Lane2. 12 Lane 13 There are a total of 9 channels, and their numbers and timestamps are recorded as receipt logs for subsequent stability judgment operations to generate a handshake response channel set.

[0121] The channel acknowledgment submodule calculates the response ratio between the number of channel responses and the total number of packets sent, based on the handshake response channel set, and also calculates the channel response interval difference and the number of handshake packet losses using the following formula:

[0122]

[0123] The handshake stability coefficient of the channel is obtained through calculation;

[0124] Among them, S x A represents the handshake stability coefficient of the channel. x L represents the percentage of handshake fields in the data segment sent through the channel. x T represents the packet loss rate during the channel handshake. x B represents the total duration of the channel handshake feedback. x D represents the number of buffer write bursts for the corresponding channel at the host receiver. x This represents the variance of the handshake delay between channels;

[0125] Based on the handshake response channel set, the number of TS2 response channels is counted as 9. Compared to the total number of transmissions (16), the response ratio is [value missing]. For each channel, calculate its handshake stability coefficient. Taking Lane_4 as an example, its handshake field accounts for A. x The packet loss rate L is 0.22. x Set to 0.04, total feedback time T x The burst write count of the host is 1.6ms. x The variance of the handshake delay is 3, and the variance is D. xThe value is 2.25 μs², which is then substituted into the formula:

[0126]

[0127] final:

[0128] S x =0.0817 + 1.5 = 1.5817;

[0129] The system sets the response threshold to 1.3. Based on the stable delay mean variance formed within ±3μs range of channel jitter range in actual SSD link handshake behavior, the threshold is determined by setting the stable interval of 95% of channels in historical response records. The current Lane_4 result is greater than 1.3, so it is determined to be a stable channel. If a channel's response coefficient is lower than the threshold due to sudden delay or abnormal TS2 response time, it is removed from the candidates. Finally, the channel numbers that meet the stability conditions are selected to form a set for subsequent activation record mapping to generate the channel handshake stability coefficient.

[0130] The mapping generation submodule excludes channels with stability coefficients lower than the set response threshold based on the handshake stability coefficient of the communication channel, summarizes the remaining channels into a set of channels that can enter the L0 state, retrieves the GEN level and parameter group number configured for the channel, establishes a mapping index table of channel number, skip level and parameter group triplet, integrates them in the order of the channels to generate a unified record structure, and generates a skip level balancing successful mapping record.

[0131] Based on the set of channel numbers determined to be stable in the channel handshake stability coefficient, such as the filtered channel set being Lane0, Lane1, Lane3, Lane4, Lane7, Lane9, the system sequentially calls the GEN hop level and the loaded parameter group number corresponding to each channel in the verification list. Let's say Lane_4 has a hop level of GEN3 and a corresponding parameter group number of P17, then the triplet {Lane_4, GEN3, P17} is recorded. All channel triplets are sorted in ascending order by Lane number and output as a structured record table. This table serves as a mapping reference for subsequent data path scheduling and L0 state initialization configuration in the SSD master control program. The record format is Lane... x The GEN level and parameter group number are combined to form a complete set of structures, generating a successful skip-level balancing mapping record.

[0132] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A hardware-accelerated intelligent PCIe SSD optimization system, characterized in that: The system includes: The channel quality monitoring module acquires the signal voltage sampling value and clock offset value on each lane of the SSD. Based on three judgment conditions, the eye diagram opening is less than the set graph threshold, the voltage fluctuation is greater than the set stability threshold, and the clock offset exceeds the set synchronization threshold, the channel that meets the conditions is marked as the channel that needs to be skipped, and a set of channel identifiers that need to be skipped is generated. The accelerated path identification module calculates the deviation score between the current channel data and the reference value based on the required skip channel identifier set, selects the GEN level with the lowest deviation score as the suggested skip channel level, summarizes all Lane suggested levels, and generates a list of channel skip levels. The accelerated path identification module includes: The record extraction submodule extracts the three most recent GEN2, GEN3, and GEN4 level training records for each numbered channel in the system based on the required skip channel identifier set, and reads the corresponding ambient temperature, voltage stability rate, and training completion time from the records to generate a channel training level sample set. The similarity calculation submodule reads the real-time eye opening, voltage change value, and training preparation time of the current channel from the channel training level sample set, and normalizes them with each data point of the same level in the sample record using the formula: ； The calculation yields a score indicating the degree of deviation from the assigned level. in, The score represents the deviation from the rating. The current eye opening. For reference gear position eye diagram opening, This represents the current voltage change value. Historical voltage stability rate For training preparation time, The time spent on historical training For reference gear level sequence number; The grade filtering submodule determines whether the deviation ratio is lower than the set deviation threshold based on the grade deviation score. It extracts the GEN grade corresponding to the lowest grade deviation score in each channel score and records it as the channel skipping suggestion grade. It then assembles and summarizes each channel suggestion grade by Lane number to generate a channel skipping grade list. The parameter mapping and filtering module searches the pre-loaded GEN level configuration data in the firmware for each channel according to the channel skipping level list. It filters the target parameter combination corresponding to the current temperature and voltage combination, constructs the channel-parameter mapping relationship according to the Lane number, and generates the Lane equalization loading parameter table. Based on the Lane equalization loading parameter table, the equalization link loading module determines whether the identified channel is in equalization preparation state, assembles all channel status information into a link activation preparation record, and generates a link equalization startup verification list.

2. The hardware-accelerated intelligent PCIe SSD optimization system according to claim 1, characterized in that, The set of channel identifiers requiring tier skipping includes channel number identifiers, channel matching anomaly tags, training stability judgment criteria, signal fluctuation identifier factors, and channel priority processing identifiers. The channel tier skipping level list specifically refers to the channel rate target level, rate level adaptation identifier, level suggestion tag, and level selection reason code. The Lane equalization loading parameter table includes equalization level index, electrical configuration number, channel parameter call path, channel parameter structure key value, and configuration mapping relationship key group. The link equalization start verification list specifically includes clock lock status tag, impedance error judgment identifier, voltage response status field, channel configuration completion mark, and start confirmation tag set.

3. The hardware-accelerated intelligent PCIe SSD optimization system according to claim 2, characterized in that, The channel quality monitoring module includes: The voltage fluctuation extraction submodule obtains the signal voltage sampling value and clock offset value on each lane of the SSD. Combined with the real-time monitoring data collected by the power supply voltage and temperature sensors, it calculates the voltage change amplitude and current fluctuation range value of each channel under the current operating temperature and voltage. It also determines whether the voltage change amplitude is greater than the voltage stability threshold and whether the current fluctuation range is greater than the current tolerance threshold, and obtains the fluctuation offset degree of each channel under the current operating conditions, generating current and voltage offset information. The synchronization offset analysis submodule uses current and voltage offset information to call the clock phase data and sampling interval time data of each channel under the current power supply state, calculates the clock phase difference and signal synchronization time difference, and determines whether it exceeds the set synchronization threshold. It extracts the channels that exceed the threshold and marks them as synchronization abnormal channels, retains the eye diagram opening value corresponding to the abnormal channels, and generates the synchronization offset amplitude of the abnormal channels. The channel screening and judgment submodule extracts the recorded eye diagram opening based on the synchronous offset amplitude of the abnormal channel, calculates the opening change trend value, and determines whether it is less than the image stability threshold. At the same time, it combines the current and voltage offset information of the channel with the offset amplitude value for judgment. The channel numbers that meet all three abnormal conditions are summarized as objects to be processed, and a set of channel identifiers that need to be skipped is generated.

4. The hardware-accelerated intelligent PCIe SSD optimization system according to claim 3, characterized in that, The parameter mapping and filtering module includes: The parameter calling submodule extracts the GEN level of each channel according to the channel skipping level list, retrieves the pre-loaded GEN level configuration data in the firmware for each channel, extracts the pre-emphasis value, deemphasis ratio, equalization coefficient group and impedance target value, organizes them into a structured parameter set according to the Lane number, and generates a channel configuration parameter structure group. The combined matching submodule, based on the channel configuration parameter structure group, calls the successfully trained parameter data recorded for each channel under the current temperature and voltage combination. It reads the historical success count, configuration temperature value, historical impedance data, and eye diagram opening for each channel with known parameter combinations, and compares it with the current channel's eye diagram opening using the following formula: ； The calculation obtains the matching and adaptation value of the channel parameter combination; in, This indicates the number of times the combination has been successfully trained in the past. This represents the average eye opening value for the corresponding combination in historical records. This represents the normalized temperature difference between the current ambient temperature and the corresponding historical configuration temperature. This represents the ratio of the difference between the current channel target impedance and the corresponding combined reference impedance. This represents the total number of failures of the corresponding combination in the historical record. This indicates the matching and adaptation value for the combination of channel parameters; The mapping generation submodule selects the parameter combination with the highest matching value for each channel based on the matching adaptation value of the channel parameter combination, establishes a key-value correspondence between the Lane number and the parameter combination, and builds an index list according to the Lane order to generate the Lane balanced loading parameter table.

5. The hardware-accelerated intelligent PCIe SSD optimization system according to claim 4, characterized in that, The balanced link loading module includes: Based on the Lane equalization loading parameter table, the parameter writing submodule writes the pre-emphasis value, equalization coefficient group and target impedance value corresponding to each channel into the PHY register area. After completing the configuration of each channel, it records the parameter writing status identifier and register response delay information, establishes a mapping pair between the Lane and the parameter response status, and generates the parameter loading and writing delay value. The feedback measurement submodule loads and writes the delay value according to the parameters, reads the current impedance value, voltage adjustment amplitude and clock phase-locked time of each channel after configuration, calculates the deviation value between the feedback index and the target parameter, compares it with the corresponding error threshold, extracts the channel number where all three errors are less than the threshold and marks it as feedback compliant, and generates a set of channel feedback error ratios. The channel confirmation submodule filters the channel numbers that meet the feedback standards based on the channel feedback error ratio set, extracts the configuration completion status flag, integrates the channel information that meets the equalization conditions into a unified link loading record, establishes a structured activation preparation information set, and generates a link equalization startup verification list.

6. The hardware-accelerated intelligent PCIe SSD optimization system according to claim 5, characterized in that, The system also includes: According to the link balancing start verification list, the collaborative transmission execution module initiates the training sequence TS1 instruction, sends a hop handshake request for the target GEN level, and compares the number of response channels with the total number of channels after the channel returns the TS2 confirmation response. It calculates the handshake success rate and compares it with the set success rate threshold. If the judgment is passed, the SSD is instructed to enter the L0 transmission state and record the hop-up successful channels and the loaded parameter content, generating a hop balancing success mapping record. The successful tier balancing mapping record includes a channel tier balancing result mapping table, a GEN level handshake success label, a transmission status record field, a parameter loading history index, and a confirmed channel set.

7. The hardware-accelerated intelligent PCIe SSD optimization system according to claim 6, characterized in that, The collaborative transmission execution module includes: The handshake initiation submodule, based on the link balancer startup verification list, generates a TS1 training request sequence for each channel according to the recorded channel configuration status and GEN level configuration items, writes the GEN level target value field and sends a handshake request, records the number of TS2 response sequences returned by the host and the channel number sequence, and generates a handshake response channel set. The channel confirmation submodule calculates the response ratio between the number of channel responses and the total number of packets sent, based on the handshake response channel set, and calculates the channel response interval difference and the number of handshake packet losses using the following formula: ； The handshake stability coefficient of the channel is obtained through calculation; in, This represents the handshake stability coefficient of the channel. This indicates the proportion of handshake fields in the data segment sent through the channel. Indicates the packet loss rate during the channel handshake. This indicates the total duration of the channel handshake feedback. This indicates the number of buffer write bursts for the corresponding channel at the host receiver. This represents the variance of the handshake delay between channels; The mapping generation submodule excludes channels with stability coefficients lower than the set response threshold based on the handshake stability coefficient of the channels, summarizes the remaining channels into a set of channels that can enter the L0 state, retrieves the GEN level and parameter group number configured for the channel, establishes a mapping index table of channel number, skip level and parameter group triplet, integrates them in the order of channels to generate a unified record structure, and generates a skip level balancing successful mapping record.

Images