Random adder, random calculation circuit, in-memory calculation integrated circuit and design method

Abstract

The invention discloses a random adder which is based on a storage unit array, storage units of the storage unit array are connected through word lines and bit lines to form an array, a first addend input into the adder is stored in the storage units on the first word line, and a second addend input into the adder is stored in the storage units on the second word line. A second addend input into the adder is stored in a storage unit on a second word line, and the storage unit array activates the first word line and the second word line at the same time under the driving of the row decoder under the control logic, so that the random addition operation of the first addend and the second addend is realized. The memory cell array sequentially activates the first word line and the second word line under the driving of the row decoder under the control logic, and keeps the first word line and the second word line in a simultaneous activation state. And the memory unit is a DRAM (Dynamic Random Access Memory) unit storage unit and is of a 1T1C structure. And the same corresponding bit line and the complementary bit line of the storage unit are connected to the input end of the sensing amplifier corresponding to the bit line.

Description

Technical Field

[0001] This disclosure belongs to the field of integrated circuit technology, and particularly relates to a stochastic adder based on DRAM for in-memory computing / stochastic computing and its design method. Background Art

[0002] General matrix-vector multiplication (GEMV) is a core operation in many computational workloads, covering fields such as scientific computing, machine learning, and large language models (LLMs). However, GEMV is still essentially limited by memory and often restricted by data transfer bottlenecks and memory access latency. Processing-in-memory (PIM) aims to alleviate these problems by directly integrating computing into the memory array to reduce energy-consuming data transfer. Dynamic random access memory (DRAM), with its maturity, scalability, and high storage density, has become a popular choice for developing DRAM-based processing-in-memory (DRAM-PIM) architectures. Prototype products such as Samsung's FIMDRAM [5], Hynix's AiM [6], and commercial products like UPMEM [4] have demonstrated significant progress in this field. Nevertheless, DRAM-PIM architectures still have limitations, especially in terms of computational performance. For example, in DRISA [3], the multiplication operation takes up to 1600 nanoseconds, which restricts their application in computationally intensive tasks.

[0003] To address this issue, Samsung introduced stochastic computing (SC) into DRAM-based processing-in-memory (DRAM-PIM), achieving a peak performance improvement of up to 4 times. The DRAM–PIM structure is well-suited for stochastic computing because stochastic computing can perform multiplication operations using simple AND gates, and AND gates are easily implemented in DRAM. The synergy between stochastic computing and DRAM-PIM has shown great potential in accelerating key operations such as generalized matrix-vector multiplication (GEMV) and convolutional neural networks (CNNs) [1][2].

[0004] In existing in-memory computing (PIM) architectures based on dynamic random access memory (DRAM), the implementation of stochastic multiplication and addition is an important part of stochastic computing (SC). As Figure 1 shown, there are four common implementation methods for stochastic operations. Among them, (a), (b), and (c) can all be well integrated into DRAM for in-memory computing, while Figure 1 the MUX-based addition shown in -c cannot be well integrated into DRAM because it requires a multiplexer hardware.

[0005] Figure 1These are several common implementation methods of random operations, including (a) AND-based multiplication; (b) OR-based addition (c) MUX-based addition (d) APC-based addition. Figure 1 The Chinese and English terms include:

[0006] AND-based Multiplication——AND-based multiplication

[0007] OR-based Addition——OR-based addition

[0008] MUX-based Addition——MUX-based addition

[0009] APC-based Addition——APC-based addition

[0010] DRAM——Dynamic Random Access Memory

[0011] PIM——Processing In Memory

[0012] Figure 1 It shows several common methods for implementing stochastic multiplication and addition in Stochastic Computing (SC). Stochastic computing is a method that uses randomness for computing, which can improve computing efficiency or simplify the problem-solving process in some cases. Among them,

[0013] AND-based Multiplication uses an AND gate to perform the multiplication operation of two binary numbers. This method can be well integrated into DRAM for Processing In Memory (PIM);

[0014] OR-based Addition uses an OR gate to perform the addition operation of two binary numbers. Similar to AND-based multiplication, this method can also be integrated into DRAM for in-memory computing;

[0015] MUX-based Addition uses a multiplexer (MUX) to perform the addition operation. Since the integration of MUX hardware in DRAM is relatively complex, this method is not easily integrated into DRAM;

[0016] APC-based Addition uses an Arithmetic and Logic Unit (APC) to perform addition operations. This method is typically used in traditional processors rather than in DRAM.

[0017] In stochastic computing, stochastic addition is one of the core operations. Among them, the method based on AND gates and OR gates is more suitable for implementation in DRAM because they can utilize the native structure of DRAM for in-memory computing, thereby improving computing efficiency and reducing power consumption. The method based on MUX cannot be directly integrated into DRAM because it requires additional hardware support. Summary of the Invention

[0018] One embodiment of the present disclosure provides a stochastic adder, which includes a memory cell array.

[0019] The memory cells of the memory cell array are connected by word lines and bit lines to form an array.

[0020] The first addend input to the adder is stored in the memory cells on the first word line.

[0021] The second addend input to the adder is stored in the memory cells on the second word line.

[0022] The row decoder of the memory cell array simultaneously activates the first word line and the second word line under the drive of the control logic to perform the stochastic addition operation on the first addend and the second addend.

[0023] Alternatively, the row decoder of the memory cell array sequentially activates the first word line and the second word line under the drive of the control logic and maintains the simultaneous activation state of the first word line and the second word line.

[0024] The same corresponding bit line and the complementary bit line of the memory cell are connected to the input end of the sense amplifier corresponding to the bit line.

[0025] The memory cell includes the source or drain of the first transistor corresponding to the first addend bit and the source or drain of the second transistor corresponding to the second addend bit, which are connected in parallel and then connected to the input end of the sense amplifier.

[0026] The memory cell is a DRAM cell memory cell, and the memory cell includes a 1T1C structure.

[0027] The memory cell further includes a precharge circuit.

[0028] One embodiment of the present disclosure provides a method for performing stochastic addition through a SA in a DRAM cell, which includes:

[0029] Based on a DRAM memory cell array,

[0030] Store the first addend input to the adder in the memory cells on the first word line.

[0031] Store the second addend input to the adder in the memory cells on the second word line.

[0032] Connect the same corresponding bit line and the complementary bit line of the memory cell to the input end of the sense amplifier corresponding to this bit line.

[0033] The present disclosure proposes a random addition method based on the Sense Amplifier (SA) inside DRAM. This method realizes random addition through the internal sense amplifier structure of DRAM, utilizes the native SA structure and function of DRAM, and directly completes the random addition operation in the memory, thereby not only reducing the hardware overhead and the energy consumption of data movement, but also improving the calculation accuracy. Brief Description of the Drawings

[0034] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the drawings, several embodiments of the present disclosure are shown in an exemplary rather than restrictive manner, wherein:

[0035] Figure 1 Schematic diagram of the existing random operation implementation principle.

[0036] Figure 2 Schematic diagram of the random adder principle according to one embodiment of the present disclosure.

[0037] Figure 3 Schematic diagram of the random adder performance comparison according to one embodiment of the present disclosure.

[0038] Figure 4 It is a schematic diagram of a typical circuit structure of an existing DRAM memory cell. Detailed Embodiments

[0039] Through the analysis of the existing solutions, the present disclosure summarizes the defects of the existing solutions, including:

[0040] 1. The calculation accuracy is limited. The methods that can be well integrated into DRAM to complete random addition face challenges in calculation accuracy. As shown in (b) and (c) of Figure 1 , the calculation errors are much higher than those of the method based on MUX (see Figure 3 (a)).

[0041] 2. Frequent data movement. Existing stochastic computing architectures cannot directly perform stochastic addition operations with high computational precision within a dynamic random access memory (DRAM) array, which requires data to be transferred outside the memory array (e.g., near-memory or logic computing regions), and such data transfer incurs high costs.

[0042] 3. Limited scalability. Traditional high-precision MUX-based addition is difficult to directly integrate into the DRAM core array, which limits the deep integration and performance improvement of SC in DRAM-PIM.

[0043] It can be seen that in traditional DRAM-based stochastic computing (SC) systems, the lack of support for directly performing high-precision stochastic addition within DRAM becomes a significant bottleneck. Existing SC architectures cannot directly execute addition operations within the DRAM array while maintaining high computational precision, so data needs to be transferred to near-memory units for computation. This data movement incurs additional latency and energy consumption. To address this issue, the present disclosure proposes a novel SA (Sense Amplifier)-based stochastic adder that can directly perform stochastic scaled addition operations within the DRAM core.

[0044] As Figure 4 shown, a typical DRAM structure mainly includes the following units:

[0045] (1) Memory cell array

[0046] Each DRAM memory cell consists of a transistor and a capacitor (1T1C structure). The transistor serves as an access switch, and the capacitor is used to store data;

[0047] The memory cells are arranged in rows and columns to form a memory array. The transistor gates of each row of memory cells are connected to the word line, and each column of memory cells is connected to the bit line. Specific rows of memory cells are accessed by controlling the word line, and data is read or written through the bit line.

[0048] (2) Bank

[0049] A DRAM Bank is a collection of memory cell arrays, and each Bank can perform read and write operations independently.

[0050] (3) Auxiliary circuit

[0051] Sense Amplifier - It is used to detect minute voltage changes on the bit line to read the data in the storage cell. In a standard read operation, first, BL and BLB are precharged to VDD / 2 through precharging. Then, WL is turned on, and the storage capacitor and the BL capacitor start charge sharing. If the storage capacitor stores a "1", the voltage of BL will increase from VDD / 2. At this time, the potential of BLB is still VDD / 2, and SA will compare the two potentials and further raise the voltage of BL to "1", that is, read out "1". If the storage capacitor stores a "0", the voltage of BL will decrease from VDD / 2. At this time, the potential of BLB is still VDD / 2, and SA will compare the two potentials and further pull down the voltage of BL to "0", that is, read out "0".

[0052] According to one or more embodiments, the SA-based adder proposed by the present disclosure, as Figure 2 (a) shows, performs scaled addition by storing each bit of the addend 1 and the addend 2 in two cells in different word lines (WL) on the same bit line (BL). After activating these two word lines, the charge between the cells will be shared with the BL line. SA compares the bit line voltage with the precharged bit line BLB (voltage is VDD / 2). If both cells store "1", the bit line voltage will exceed VDD / 2, and SA outputs "1". If both cells store "0", the bit line voltage will be lower than VDD / 2, and SA outputs "0". For mixed inputs (i.e., "0" and "1"), the bit line voltage is close to VDD / 2 and enters the "fuzzy detection region" (as Figure 2 (b) shows), and SA will randomly output "0" or "1", which introduces probabilistic behavior.

[0053] Figure 2 (a) is an adder based on a sense amplifier (SA), where the addends are stored in 1T1C (single transistor single capacitor) storage cells along the bit line (BL), and the complementary bit line (BLB) is preset to VDD / 2. (b) Bit line (BL) voltage regions during the operation of the sense amplifier (SA): "detected as '1'" region, "detected as '0'" region, and "fuzzy detection region". Related English terms include:

[0054] SA - Sense Amplifier

[0055] BL - Bit Line

[0056] BLB - Bit Line Bar

[0057] WL - Word Line

[0058] Addend - Addend

[0059] 1T1C - One Transistor One Capacitor

[0060] Detected as ‘1’ Region - The region detected as "1"

[0061] Detected as ‘0’ Region - The region detected as "0"

[0062] Ambiguous Detection Zone - The ambiguous detection area

[0063] BL Voltage - Bit line voltage

[0064] Time - Time

[0065] Figure 2 (a) The adder structure based on the sense amplifier (SA) includes:

[0066] Each bit of the addend 1 and addend 2 is stored in two cells in different word lines (WL) on the same bit line (BL). This design allows for random addition of two numbers on the same bit line;

[0067] When these two word lines are activated, the charge between the memory cells will be shared through the bit line;

[0068] The sense amplifier (SA) compares the voltage on the bit line with the pre - charged complementary bit line (BLB, voltage of 0.5V).

[0069] Figure 2 (b) describes three regions of the bit line (BL) voltage during the operation of the sense amplifier (SA):

[0070] Detected as “1” Region - If both cells store “1”, the bit line voltage will exceed 0.5V, and the sense amplifier outputs “1”.

[0071] Detected as “0” Region - If both cells store “0”, the bit line voltage will be lower than 0.5V, and the sense amplifier outputs “0”.

[0072] Ambiguous Detection Region - For mixed inputs (i.e., “0” and “1”), the bit line voltage is close to 0.5V, entering the ambiguous detection region, and the sense amplifier will randomly output “0” or “1”, which introduces probabilistic behavior.

[0073] This method can directly utilize the inherent SA inside the DRAM to complete random addition operations inside the DRAM without the need for additional hardware, thereby improving the computing efficiency and reducing the hardware overhead. This adder structure based on the sense amplifier inside the DRAM realizes a new type of in-memory computing (PIM) architecture, avoiding the overhead of traditional DRAM-PIM that requires data transfer to the outside of the DRAM for addition operations for random addition operations.

[0074] The internal scaled adder based on the Sense Amplifier in the embodiments of the present disclosure realizes addition operations directly inside the DRAM, reducing the hardware overhead, energy consumption, and latency, while improving the computing accuracy and system efficiency. It fully utilizes the existing resources inside the DRAM, not only optimizing the hardware design but also greatly improving the system performance, and is particularly suitable for efficient random computing and memory-intensive applications.

[0075] The present disclosure further verifies the embodiments. Table 1 compares the theoretical outputs of the proposed SA-based adder with existing random scaled adders. For inputs of "0" and "0" or "1" and "1", all adders output consistent results. For mixed inputs, the OR-based adder always outputs "1", while the APC-based adder generates outputs according to the "AND-then-OR" operation. The MUX-based adder achieves higher accuracy by selecting input bits based on a third random input. Similarly, the SA-based adder also generates probabilistic outputs ("0 / 1"), reflecting the inherent randomness in random addition.

[0076] Table 1 is a comparison of the adder output results.

[0077]

[0078] The English terms in Table 1 include:

[0079] Addend Bit - Addend digit

[0080] OR-based Adder - OR-gate based adder

[0081] MUX-based Adder - Multiplexer based adder

[0082] APC-based Adder(AND-then-OR) - Arithmetic Logic Unit based adder (AND-then-OR) Proposed SA-based Adder - The SA-based adder proposed in the present disclosure

[0083] To evaluate the computational error between this method and traditional methods, 10,000 simulation runs were conducted using Python. In each simulation, 4,096 pairs of random bitstreams with a length of 128 bits were randomly generated, followed by random scaling addition, and the error of the result was calculated. As Figure 3 shown in (a), the horizontal axis is the relative error between the random addition and the exact binary addition, and the vertical axis is the cumulative probability distribution of the 10,000 simulation results. The results show that the SA-based adder is comparable in accuracy to the MUX-based adder and outperforms the OR and APC-based adders. Different from the MUX-based adder, the latter requires additional logic outside the DRAM, while the SA-based adder performs the scaling addition entirely within the DRAM, which improves the processing efficiency, reduces the hardware overhead, and maintains high accuracy at the same time.

[0084] Figure 3 is the comparison of the random addition proposed by this method with the three commonly used traditional random additions (a) Comparison of simulation results; (b) Feature comparison. Figure 3 The English terms in it include:

[0085] CDF - Cumulative Distribution Function

[0086] Error Rate - Error rate

[0087] Input dimension - Input dimension

[0088] Bitstream length - Bitstream length

[0089] Proposed SA-based Adder - The sense amplifier-based adder proposed in this disclosure OR gate-based Adder - OR gate-based adder

[0090] MUX-based Adder - Multiplexer-based adder

[0091] APC-based Adder - Arithmetic logic unit-based adder

[0092] From Figure 3 (a), the cumulative distribution function (CDF) of the error rate of different adders in processing random calculations can be seen. Four different adder designs are compared in the figure:

[0093] (1) OR gate-based Adder, which has a relatively high error rate when processing random calculations.

[0094] (2) MUX-based Adder, which performs well in terms of accuracy and is comparable to the proposed SA-based Adder.

[0095] (3) APC-based Adder, which has a relatively low error rate but is not as good as the MUX-based and SA-based Adders.

[0096] (4) Proposed SA-based Adder, which is comparable to the MUX-based Adder in terms of accuracy and superior to the OR-gate and APC-based Adders.

[0097] Figure 3 (b) shows the characteristic comparison of scaled adders, highlighting the advantages of the proposed SA-based Adder, including:

[0098] The SA-based Adder fully performs scaled addition within DRAM, improving processing efficiency;

[0099] Reduces the need for additional hardware because no additional logic is required outside DRAM;

[0100] Maintains high accuracy and is comparable to the MUX-based Adder.

[0101] Therefore, the SA-based Adder proposed in this disclosure is comparable to the MUX-based Adder in terms of accuracy and superior to the other two adders. In addition, since this adder fully performs within DRAM, it can improve processing efficiency and reduce hardware overhead, which is a significant advantage in stochastic computing applications.

[0102] Therefore, the internal scaled adder based on Sense Amplifier proposed in the embodiments of this disclosure has the following remarkable advantages:

[0103] 1. Reduce hardware overhead.

[0104] Traditional stochastic computing (SC) adders usually require additional hardware modules (such as multiplexers) to perform addition operations, especially when performing high-precision addition. However, this disclosure directly utilizes the existing hardware resources (sense amplifier SA) within DRAM to complete the addition operation without an additional adder circuit, thus significantly reducing the hardware complexity and area overhead.

[0105] 2. Improve energy efficiency.

[0106] Since the addition operation is directly completed inside the DRAM, data does not need to be frequently transferred to external computing units, which reduces the energy consumption caused by data transfer.

[0107] 3. Reduce latency.

[0108] In traditional systems, the addition operation of data usually requires moving the data to an external processing unit, resulting in a high latency. The internal adder based on SA can directly execute the addition inside the DRAM, avoiding the frequent transfer of data, thus effectively reducing the latency and improving the computing speed. This is especially important for high-performance computing and enables faster random computing operations.

[0109] 4. High precision and reliability.

[0110] The adder based on SA realizes the addition operation through the charge sharing mechanism, ensuring a high computing precision.

[0111] 5. Reduce area overhead.

[0112] Since the SA adder directly utilizes the existing circuit resources of the DRAM (such as bit lines and memory cells) instead of adding additional external adder circuits, the area consumption of the chip is reduced.

[0113] References:

[0114] [1] Z.Xia, J.Chen, Q.Huang, J.Luo, and J.Hu, “Neural synaptic plasticity-inspired computing: A high computing efficient deep convolutional neural network accelerator,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 68, no. 2, pp. 728–740, 2020.

[0115] [2] Z.Chen, Y.Ma, and Z.Wang, “Hybrid stochastic-binary computing for low-latency and high-precision inference of cnns,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 69, no. 7, pp. 2707–2720, 2022

[0116] [3]S. Li, D. Niu, K. T. Malladi, H. Zheng, B. Brennan, and Y. Xie. DRISA: ADRAM-based Reconfigurable In-Situ Accelerator. In Proceedings of the 50th Annual IEEE / ACM Inter-national Symposium on Microarchitecture, MICRO-50’17, pages 288–301, New York, NY, USA, 2017. ACM.

[0117] [4]F. Devaux. The true Processing In Memory accelerator. In 2019 IEEE HotChips31 Sympo-sium (HCS), pages 1–24, 2019.

[0118] [5]Y.-C. Kwon, S. H. Lee, J. Lee, S.-H. Kwon, J. M. Ryu, J.-P. Son, O. Seongil, H.-S. Yu, H. Lee, S. Y. Kim, Y. Choi, J. G. Kim, J. Choi, H.-S. Shin, J. Kim, B. Phuah, H. Kim, M. J. Song, A. Choi, D. Kim, S. Kim, E.-B. Kim, D. Wang, S. Kang, Y. Ro, S. Seo, J. Song, J. Youn, K. Sohn, and N. S. Kim. 25.4A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications. In 2021 IEEE International Solid-State Circuits Con-ference (ISSCC), volume 64, pages 350–352, 2021.

[0119] [6]S. Lee, K. Kim, S. Oh, J. Park, G. Hong, D. Ka, K. Hwang, J. Park, K. Kang, J. Kim, J. Jeon, N. Kim, Y. Kwon, K. Vladimir, W. Shin, J. Won, M. Lee, H. Joo, H. Choi, J. Lee, D. Ko, Y. Jun, K. Cho, I. Kim, C. Song, C. Jeong, D. Kwon, J. Jang, I. Park, J. Chun, and J. Cho. A 1ynm1.25V 8Gb, 16Gb / s / pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications. In 2022 IEEE International Solid-State Circuits Conference (ISSCC), volume 65, pages 1–3, 2022.

[0120] It should be understood that in the embodiments of the present disclosure, the term "and / or" is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: the case where A exists alone, the case where A and B exist simultaneously, and the case where B exists alone. Additionally, in this text, the character " / " generally represents an "or" relationship between the associated objects before and after.

[0121] It is worth noting that although the foregoing has described the spirit and principles of the present disclosure creation with reference to several specific embodiments, it should be understood that the present disclosure is not limited to the specific embodiments disclosed, and the division of each aspect does not mean that the features in these aspects cannot be combined. This division is only for the convenience of expression. The present disclosure aims to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A random adder, characterized in that, The adder is based on a memory cell array. The memory cells of the memory cell array are connected by word lines and bit lines to form an array. The first addend input to the adder is stored in the memory cells on the first word line. The second addend input to the adder is stored in the memory cells on the second word line. The memory cell array simultaneously activates the first word line and the second word line under the drive of the control logic by the row decoder to implement a random addition operation on the first addend and the second addend.

2. The random adder according to claim 1, wherein The memory cell array sequentially activates the first word line and the second word line under the drive of the control logic by the row decoder and maintains the first word line and the second word line in a simultaneously activated state.

3. The random adder according to claim 1, characterized in that, The memory cell is a DRAM cell memory cell with a 1T1C structure.

4. The random adder according to claim 3, wherein The same corresponding bit line and the complementary bit line of the memory cell are connected to the input end of the sense amplifier corresponding to the bit line.

5. The random adder according to claim 3, wherein The memory cell includes the drain of the first transistor corresponding to the first addend bit and the drain of the second transistor corresponding to the second addend bit, which are connected in parallel and then connected to the input end of the sense amplifier.

6. The random adder according to claim 1, wherein, The scaled addition implemented by the random adder is applied to random calculations.

7. An in-memory computing integrated circuit, characterized in that, It includes the random adder as described in claim 1.

8. The in-memory computing integrated circuit according to claim 7, wherein This in-memory computing integrated circuit is based on DRAM-PIM.

9. A random calculation circuit, characterized in that, This random computing circuit includes the random adder as described in claim 1.

10. A method for designing a random adder, characterized in that, This method includes: Based on a DRAM memory cell array, Store the first addend input to the adder in the memory cells on the first word line. Store the second addend input to the adder in the memory cells on the second word line. The memory cell array simultaneously activates the first word line and the second word line under the drive of the control logic by the row decoder to implement a random addition operation on the first addend and the second addend. Connect the same corresponding bit line and the complementary bit line of the memory cell to the input end of the sense amplifier corresponding to the bit line.

Images