Self-adaptive frequency modulation method and device

Abstract

The embodiment of the invention discloses a self-adaptive frequency modulation method and device which are used for improving the frequency modulation accuracy of a processor. The method comprises the steps that the computing device collects real-time monitoring data of the processor, the real-time monitoring data comprises one or more events monitored by a performance monitoring unit (PMU) of the processor, and the events comprise one or more of the following items: the number of instruction execution times, the cache hit rate and the branch prediction error rate. A predicted performance change rate of the processor is calculated based on the real-time monitoring data, the predicted performance change rate is determined based on a current performance change rate of the processor, the current performance change rate is determined based on the real-time monitoring data, and the predicted performance change rate is used for indicating the proportion of a reference performance value to an operation performance value of the processor. And determining a target frequency of the processor based on the target performance loss rate and the predicted performance change rate, wherein the target performance loss rate is used for indicating the predicted performance change rate tolerable by the processor.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and in particular, to an adaptive frequency modulation method and device. Background Art

[0002] With the development of cloud computing technology, one of the main problems faced by computing devices is the cost of energy consumption, which is particularly evident in supercomputing systems. Many supercomputing device clusters are limited by the total operating power and need to reduce power consumption and improve the energy efficiency ratio. Among computing devices, the power consumption of the central processing unit (CPU) often accounts for more than half of the total power consumption of the computing device. Therefore, energy conservation needs to focus on the power consumption of the central processing unit.

[0003] In the current energy-saving solutions for central processing units, since the central processing units of computing devices basically support dynamic frequency adjustment, the computing device can effectively reduce the processor power consumption by reducing the processor frequency. However, in the process of adjusting the frequency of the current computing device, the frequency is often adjusted based on the utilization rate of the CPU. For example, when the utilization rate of the CPU increases, the computing device can increase the frequency, and when the utilization rate of the CPU decreases, the computing device can reduce the frequency.

[0004] However, in the actual task processing process, the utilization rate of the CPU cannot fully reflect the actual performance of the processor, and the frequency adjustment of the computing device based on the utilization rate of the CPU will result in poor frequency modulation accuracy and high processor power consumption of the computing device. Summary of the Invention

[0005] The embodiments of the present application provide an adaptive frequency modulation method. The computing device can obtain the events collected by the performance monitoring unit (PMU) of the processor and perform frequency adjustment based on the PMU events collected, so as to improve the accuracy of frequency adjustment and reduce the processor power consumption. The embodiments of the present application also provide an adaptive frequency modulation device, a computing device, a chip, a computer-readable storage medium, and a computer program product corresponding to the adaptive frequency modulation method.

[0006] In a first aspect, an embodiment of the present application provides an adaptive frequency modulation method. This method can be executed by a computing device, or by components of the computing device, such as the processor, chip, or chip system of the computing device, etc., or can also be implemented by a logic module or software that can implement all or part of the functions of the computing device. Taking the computing device as an example, the method provided in the first aspect includes: The computing device collects real-time monitoring data of the processor. The real-time monitoring data includes one or more events monitored by the processor's performance monitoring unit (PMU). The events include one or more of the following: the number of instruction executions, cache hit rate, and branch prediction error rate. The computing device calculates the predicted performance change rate of the processor based on the real-time monitoring data. The predicted change rate is determined based on the current performance change rate of the processor, and the current performance change rate is determined based on the real-time monitoring data. The predicted performance change rate is used to indicate the ratio of the reference performance value of the processor to the running performance value. The reference performance value is the performance value corresponding to the maximum frequency of the processor, and the running performance value is the processor performance value corresponding to the current frequency. The computing device determines the target frequency of the processor based on the target performance loss rate and the predicted performance change rate. The target performance loss rate is used to indicate the tolerable predicted performance change rate of the processor.

[0007] In the embodiment of the present application, the computing device can calculate the current performance change rate of the processor based on one or more events monitored by the processor's performance monitoring unit (PMU), calculate the predicted performance change rate of the processor according to the current performance change rate of the processor, and further determine the target frequency based on the target performance loss rate and the predicted performance change rate. Compared with adjusting the frequency of the processor according to the utilization rate of the processor in the prior art, in the embodiment of the present application, based on the PMU events, it can more accurately reflect the performance of the processor. Adjusting the frequency based on the PMU events improves the accuracy of the target frequency and reduces the power consumption of the processor.

[0008] In a possible implementation manner, during the process that the computing device calculates the predicted performance change rate of the processor based on the real-time monitoring data, the computing device calculates the current performance change rate of the processor based on the real-time monitoring data and the performance change fitting relationship. Among them, the performance change fitting relationship is used to indicate the correlation relationship between the performance change rate and the monitoring data. The computing device calculates the predicted performance change rate according to the current performance change rate and the frequency change rate. The frequency change rate is the ratio of the reference frequency to the running frequency, where the reference frequency is the maximum frequency of the processor and the running frequency is the frequency at the previous moment.

[0009] In the embodiment of the present application, the computing device can calculate the current performance change rate corresponding to the real-time monitoring data based on the performance change fitting relationship, and further calculate the predicted performance change rate of the processor according to the current performance change rate and the frequency change rate, thereby improving the accuracy of the predicted performance change rate.

[0010] In a possible implementation, the current performance change rate is used to indicate the ratio of the performance value corresponding to the frequency at the previous moment to the performance value corresponding to the frequency at the current moment. When the computing device calculates the predicted performance change rate based on the current performance change rate and the frequency change rate, the computing device calculates the frequency change rate based on the reference frequency and the frequency at the previous moment, and then the computing device calculates the predicted performance change rate based on the current performance change rate and the frequency change rate. The predicted performance change rate is used to indicate the ratio between the reference performance value of the processor and the performance value corresponding to the frequency at the current moment.

[0011] In the embodiments of the present application, the computing device can calculate the predicted performance change rate of the processor based on the ratio of the processor performance value at the previous moment to the processor performance value at the current moment, and the frequency change rate corresponding to the current moment, thereby improving the feasibility of the solution for calculating the predicted performance change rate of the computing processor.

[0012] In a possible implementation, the computing device obtains historical monitoring data, and the historical monitoring data includes one or more events monitored by the performance monitoring unit (PMU) of the processor at different frequencies. The computing device fits a formula for the performance change fitting relationship of the processor based on the historical monitoring data, which can also be referred to as the performance change formula. The performance change formula is used to indicate the correlation between the current performance change rate and the events. Specifically, the computing device fits the performance change formula of the processor based on the historical monitoring data and the corresponding performance change rate.

[0013] The computing device in the embodiments of the present application can fit the processor change formula according to the historical monitoring data, thereby establishing the correlation between the current performance change rate of the processor and the PMU events, and improving the accuracy of the computing device in calculating the current performance change rate of the computing processor.

[0014] In a possible implementation, before the computing device fits the performance change formula of the processor based on the historical monitoring data, the computing device determines the PMU events related to the current performance change rate. Specifically, the computing device uses the PMU events whose correlation degree with the current performance change rate exceeds the threshold as the associated PMU events, and the computing device fits the performance change formula of the processor based on the associated PMU events and the current performance change rate of the processor corresponding to the associated PMU events.

[0015] In the embodiments of the present application, the computing device can use the PMU events whose correlation degree with the current performance change rate of the processor exceeds the threshold as the associated PMU events, thereby reducing the complexity of the computing device in fitting the performance change formula of the processor based on the historical monitoring data, and improving the fitting efficiency of the performance change formula of the processor.

[0016] In a possible implementation, the computing device establishes an association relationship between the processor performance loss rate and the frequency change rate based on historical monitoring data. The association relationship includes a blocking coefficient, which is used to indicate the weight of the processor performance value affected by the frequency. The computing device can calculate the blocking coefficient based on the current frequency and the performance loss rate corresponding to the predicted performance change rate. The blocking coefficient is also used to calculate the target frequency of the processor according to the target performance loss rate.

[0017] In the embodiments of the present application, the computing device can establish an association relationship between the processor performance loss rate and the frequency based on historical monitoring data, so that the computing device can calculate the target frequency of the processor based on the target performance loss rate, thereby improving the feasibility of calculating the target frequency of the computing device.

[0018] In a possible implementation, when the computing device determines the target frequency of the processor based on the target performance loss rate and the performance change rate, the computing device calculates the blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and the frequency change rate of the processor. The predicted performance change rate indicates the ratio of the performance value corresponding to the reference frequency to the performance value corresponding to the current frequency, and the frequency change rate indicates the ratio of the reference frequency of the processor to the current frequency. The computing device determines the target frequency according to the target performance loss rate and the blocking coefficient, and the target frequency is the frequency that the processor needs to adjust at the next moment.

[0019] In the embodiments of the present application, the computing device can calculate the blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and the frequency change rate of the processor, and determine the target frequency based on the target performance loss rate and the blocking coefficient, thereby improving the calculation efficiency of the target frequency.

[0020] In a possible implementation, when the predicted performance change rate of the processor is greater than or equal to the performance change rate corresponding to the target performance loss rate, that is, the performance loss rate corresponding to the current frequency is greater than or equal to the target performance loss rate, the frequency of the processor is increased. When the predicted performance change rate of the processor is less than the performance change rate corresponding to the target performance loss rate, that is, the performance loss rate corresponding to the current frequency is less than the target performance loss rate, the frequency of the processor is decreased.

[0021] In the embodiments of the present application, the computing device can calculate the predicted performance change rate of the processor corresponding to the frequency by adjusting the frequency, and compare the predicted performance change rate with the predicted performance change rate corresponding to the target performance loss rate, thereby adjusting the frequency of the processor, and thus improving the accuracy of the target frequency.

[0022] In a possible implementation, the real-time monitoring data collected by the computing device can be events collected by the Architecture Performance Monitoring Unit (AMU) in addition to PMU events. The real-time monitoring data can also be the utilization rate of the central processing unit or other scenario-related performance metrics. Other scenario-related performance metrics such as the number of transactions per second in a database scenario.

[0023] In the embodiments of the present application, the computing device can collect different types of real-time monitoring data in different application scenarios, and determine the predicted performance change rate of the processor based on different real-time monitoring data, thereby improving the calculation accuracy of the predicted performance change rate of the processor.

[0024] In a second aspect, an embodiment of the present application provides an adaptive frequency modulation device, which includes an acquisition unit and a processing unit. Among them, the acquisition unit is used to collect real-time monitoring data of the processor. The real-time monitoring data includes one or more events monitored by the Performance Monitoring Unit (PMU) of the processor. The events include one or more of the following: the number of instruction executions, cache hit rate, and branch prediction error rate. The processing unit is used to calculate the predicted performance change rate of the processor based on the real-time monitoring data. The predictive change rate is determined based on the current performance change rate of the processor. The current performance change rate is determined based on the real-time monitoring data. The predicted performance change rate is used to indicate the ratio of the reference performance value of the processor to the running performance value. The processing unit is further used to determine the target frequency of the processor based on the target performance loss rate and the predicted performance change rate. The target performance loss rate is used to indicate the tolerable predicted performance change rate of the processor.

[0025] In a possible implementation, the processing unit is specifically configured to calculate the current performance change rate of the processor based on the real-time monitoring data and the performance change fitting relationship. The performance change fitting relationship is used to indicate the correlation between the performance change rate and the monitoring data. Calculate the predicted performance change rate based on the current performance change rate and the frequency change rate. The frequency change rate is the ratio of the reference frequency to the running frequency.

[0026] In a possible implementation, the current performance change rate is used to indicate the ratio of the performance value corresponding to the frequency at the previous moment to the performance value corresponding to the frequency at the current moment. The processing unit is specifically configured to calculate the frequency change rate based on the reference frequency and the frequency at the previous moment, and calculate the predicted performance change rate based on the current performance change rate and the frequency change rate. The predicted performance change rate is used to indicate the ratio between the reference performance value of the processor and the performance value corresponding to the frequency at the current moment.

[0027] In a possible implementation, the processing unit is specifically configured to calculate the blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and the frequency change rate, and determine the target frequency based on the target performance loss rate and the blocking coefficient.

[0028] In a possible implementation, the processing unit is further configured to increase the frequency of the processor when the predicted performance change rate is greater than or equal to the performance change rate corresponding to the target performance loss rate, and decrease the frequency of the processor when the predicted performance change rate is less than the performance change rate corresponding to the target performance loss rate.

[0029] In a possible implementation, the processing unit is further configured to obtain historical monitoring data, where the historical monitoring data includes one or more events monitored by a performance monitoring unit (PMU) of the processor at different frequencies, and fit a performance change fitting relationship based on the historical monitoring data.

[0030] In a possible implementation, the processing unit is further configured to establish an association relationship between the performance loss rate and the frequency change rate based on the historical monitoring data. The association relationship includes a blocking coefficient, and the blocking coefficient is used to indicate the weight of the performance value of the processor affected by the frequency.

[0031] In a third aspect, an embodiment of the present application provides a computing device, which includes a processor. The processor is coupled to a memory. The processor is configured to store instructions. When the instructions are executed by the processor, the computing device is caused to execute the method described in the first aspect or any possible implementation of the first aspect.

[0032] In a fourth aspect, an embodiment of the present application provides a chip, which includes one or more processing circuits. The processing circuits are coupled to a storage circuit. The processing circuits are configured to store instructions. When the instructions are executed by the processing circuits, the chip is caused to execute the method described in the first aspect or any possible implementation of the first aspect.

[0033] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, on which instructions are stored. When the instructions are executed, a computer is caused to execute the method described in the first aspect or any possible implementation of the first aspect.

[0034] In a sixth aspect, an embodiment of the present application provides a computer program product, which includes instructions. When the instructions are executed, a computer is caused to implement the method described in the first aspect or any possible implementation of the first aspect.

[0035] It can be understood that the beneficial effects that can be achieved by any of the above-provided adaptive frequency modulation devices, computing devices, chips, computer-readable media, or computer program products can refer to the beneficial effects in the corresponding methods, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 FIG. is a schematic diagram of the system architecture of an adaptive frequency modulation system provided by an embodiment of the present application;

[0037] Figure 2Flow diagram of an adaptive frequency modulation method provided by an embodiment of the present application;

[0038] Figure 3 Flow diagram of another adaptive frequency modulation method provided by an embodiment of the present application;

[0039] Figure 4 Flow diagram of another adaptive frequency modulation method provided by an embodiment of the present application;

[0040] Figure 5 Flow diagram of another adaptive frequency modulation method provided by an embodiment of the present application;

[0041] Figure 6 Structural diagram of an adaptive frequency modulation device provided by an embodiment of the present application;

[0042] Figure 7 Structural diagram of a computing device provided by an embodiment of the present application;

[0043] Figure 8 Structural diagram of a chip provided by an embodiment of the present application. Detailed implementation manners

[0044] An embodiment of the present application provides an adaptive frequency modulation method and device for improving the accuracy of frequency adjustment of a computing device and reducing the power consumption of a processor.

[0045] Terms such as "first", "second", "third", "fourth", etc. (if any) in the specification, claims and above-mentioned drawings of the present application are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these process, method, product or device.

[0046] In the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0047] First, some terms involved in the embodiments of the present application are introduced to facilitate those skilled in the art to understand the technical solutions.

[0048] The performance monitoring unit (PMU) counter is a hardware component on the central processing unit used to measure the performance and resource utilization of the system. The PMU counter can record various events of the processor, such as the number of instruction executions, cache hit rate, memory access times, etc.

[0049] To make the technical solutions of the present application clearer and easier to understand, the system architecture of the present application will be introduced below with reference to the accompanying drawings.

[0050] Please refer to Figure 1 , Figure 1 which is a schematic diagram of the system architecture of an adaptive frequency modulation system provided by an embodiment of the present application. In Figure 1 the illustrated example, the adaptive frequency modulation system 10 includes a system file interface module 101, a processor frequency modulation module 102, and a processor hardware module 103. Among them, the processor frequency modulation module includes a frequency modulation management sub-module 1021, a frequency modulation core sub-module 1022, and a frequency modulation driver sub-module 1023. The specific functions of each module in the adaptive frequency modulation system 10 will be introduced in detail below.

[0051] The system file interface module 101 provides an interface for users to access the processor frequency modulation module 102 in the user space, also known as the sysfs module. The user's application program can obtain information about various devices, drivers, and sub-modules in the processor frequency modulation module 102 in the form of files through the system file interface module 101, and configure or adjust the processor frequency modulation module 102. For example, the user's application program can query or set the frequency of the central processing unit through the system file interface module 101.

[0052] The processor frequency modulation module 102 is also known as the CPUfreq module. The processor frequency modulation module 102 is used to control the frequency of the central processing unit in the kernel space. The processor frequency modulation module 102 includes a frequency modulation management sub-module 1021, a frequency modulation core sub-module 1022, a frequency modulation driver sub-module 1023, and a frequency modulation data statistics sub-module 1024.

[0053] Among them, the frequency modulation management sub-module 1021 is also called the CPUfreq governor sub-module. The frequency modulation management sub-module 1021 is used to select the frequency policy of the processor according to the load condition of the central processing unit. The frequency policies include, for example, the performance priority (performance) policy, the power consumption priority (powersave) policy, the user-defined frequency (userspace) policy, the on-demand allocation (ondemand) policy, the smooth adjustment (conservatie) policy, and the load frequency modulation (schedutil) policy, etc.

[0054] The frequency modulation core sub-module 1022 is also called the CPUfreq core sub-module. The frequency modulation core sub-module 1022 is used to implement the overall management and control of the processor frequency modulation module 102, including the initialization of the CPUfreq framework, callback registration, event management, and driver management, etc. The frequency modulation core sub-module 1022 can provide general control interfaces and algorithms to coordinate the interaction operations between different sub-modules of the processor frequency modulation module 102.

[0055] For example, the frequency modulation core sub-module 1022 can receive the query or setting requests of the user for the frequency of the central processing unit and the frequency policy through the system file interface module 101. The frequency modulation core sub-module 1022 can also manage and modify the frequency policy of the frequency modulation management sub-module 1021, and control the frequency modulation driver sub-module 1023 to perform frequency adjustment according to the frequency policy. The frequency modulation core sub-module 1022 can also monitor the load condition and power consumption requirement of the central processing unit.

[0056] The frequency modulation driver sub-module 1023 is also called the CPUfreq driver module. The frequency modulation driver sub-module 1023 is used to implement the frequency modulation or voltage regulation mechanism of the central processing unit. The frequency modulation driver sub-module 1023 interacts with the processor hardware module 103 and adjusts the frequency of the central processing unit according to the frequency policy selected by the frequency modulation management sub-module 1021. The frequency modulation driver sub-module 1023 can also read the current frequency value of the central processing unit from the processor hardware module 103 and adjust the frequency of the central processing unit to reach the required performance or power consumption target.

[0057] For example, a driver for interacting with the processor hardware module 103 can be integrated in the frequency modulation driver sub-module 1023 to implement reading and setting the main frequency of the central processing unit. The frequency modulation driver sub-module 1023 can also read the operating performance points (OPP) of the system energy consumption to obtain the gear information of the frequency and voltage.

[0058] The FM data statistics sub-module 1024, also known as the CPUfreq stats sub-module, is used to collect statistical information on the processor frequency and can provide real-time and historical data on the processor frequency. For example, the FM data statistics sub-module 1024 can track the running time of the processor at different frequencies, record the number of processor frequency conversions, and calculate the proportion and duration of each frequency. The FM data statistics sub-module 1024 can also record and save the historical data of the processor frequency, retain the data after the system restarts, and provide an interface for querying the historical data.

[0059] The processor hardware module 103 includes hardware components that interact with the processor frequency modulation module 102. The processor hardware module 103 can receive frequency acquisition or frequency adjustment instructions from the frequency modulation driver sub-module 1023. The processor hardware module 103 includes, for example, the power management module of the central processor, power consumption-related registers, and a power control unit (PCU), which are not specifically limited.

[0060] For another example, the processor hardware module 103 also includes a performance monitoring unit (PMU) counter. In the embodiments of the present application, the processor frequency modulation module 102 can interact with the PMU counter to obtain the performance data of the processor. By analyzing the data of the PMU counter, the processor frequency modulation module 102 can obtain data such as the processor load, cache hit rate, power consumption, and performance metrics, and accordingly determine whether it is necessary to adjust the working frequency of the processor.

[0061] Based on Figure 1 the adaptive frequency modulation system 10 shown, the present application also provides an adaptive frequency modulation method. The following describes the adaptive frequency modulation method provided in the embodiments of the present application in combination with embodiments.

[0062] Please refer to Figure 2 , Figure 2 , which Figure 2 is a schematic flowchart of an adaptive frequency modulation method provided in the embodiments of the present application. In the

[0063] example shown, the method includes the following steps:

[0064] Before the computing device in the embodiment of the present application performs adaptive frequency modulation, it is necessary to perform initialization work before frequency modulation. During the frequency modulation initialization stage of the computing device, the computing device needs to construct two formulas, namely the real-time performance change formula and the performance loss change formula. The following specifically introduces the frequency modulation initialization work of the computing device in the initialization stage;

[0065] First, introduce the construction of the real-time performance change formula by the computing device in the initialization stage of the embodiment of the present application.

[0066] During the process of the computing device constructing the real-time performance change formula, the computing device periodically collects monitoring data during the operation of the processor. These monitoring data can be called historical monitoring data. The monitoring data collected by the computing device includes one or more events monitored by the performance monitoring unit PMU, also called PMU events. PMU events include the number of instruction executions, cache hit rate, and branch prediction error rate. Among them, the number of instruction executions refers to the actual number of instructions executed by the processor during execution, which can reflect the execution efficiency and performance of the processor. The cache hit rate refers to the proportion of successfully obtaining data or instructions from the cache, which can reflect the utilization rate of the cache by the processor. The branch prediction error rate refers to the accuracy rate of predicting whether to execute a branch when there are branch instructions in the program, which can also reflect the execution efficiency of the processor.

[0067] During the process of the computing device collecting monitoring data of the processor, the computing device can set the main frequency of the central processing unit to a fixed value and record the correspondence between the frequency, processor performance value, and PMU events of the central processing unit during the execution of tasks within a period of time. After that, the computing device readjusts the main frequency of the central processing unit and continues to record the correspondence between the frequency, processor performance value, and PMU events of the central processing unit during the execution of tasks within a period of time.

[0068] The computing device repeats the above collection process to obtain multiple sets of correspondence data of frequency, processor performance value, and PMU events. These relationship data can form a PMU event set. Among them, the performance value of the processor can be throughput, execution time, traffic, latency, etc., which is not specifically limited.

[0069] After the computing device can obtain multiple sets of correspondence data of frequency, processor performance value, and PMU events, based on the correlation coefficient analysis algorithm, these correspondence data are analyzed to determine one or more PMU events whose correlation degree with the current performance change rate of the processor is higher than the threshold. The current performance change rate refers to the ratio of the processor performance value at the previous moment to the processor performance value at the current moment. These PMU events can constitute an event set for fitting the real-time performance change formula. The correlation coefficient analysis algorithm is, for example, the Pearson correlation coefficient analysis algorithm or the Spearman correlation coefficient analysis algorithm.

[0070] After the computing device obtains the event set of PMU events, the computing device fits a relational expression between the current performance change rate of the processor and the PMU events in the PMU event set based on a regression model. The regression model can be a linear regression model, a logistic regression model, a polynomial regression model, etc. This relational expression is the real-time performance change formula, and the real-time performance change formula satisfies the following formula:

[0071]

[0072] Where Y is the current performance change rate of the processor, X is the PMU event, is the coefficient of the PMU event, and this coefficient is obtained by fitting based on the regression model.

[0073] In a possible implementation, the computing device obtains historical monitoring data, and the historical monitoring data includes one or more events monitored by the performance monitoring unit (PMU) of the processor at different frequencies. The computing device establishes an association relationship between the processor performance loss rate and the frequency change rate based on the historical monitoring data. The association relationship includes a blocking coefficient, and the blocking coefficient is used to indicate the weight of the processor performance value affected by the frequency.

[0074] Second, this application embodiment introduces how the computing device constructs a performance loss change formula in the initialization stage.

[0075] In the process of the computing device constructing the performance loss change formula, the performance loss rate σ can be represented by the ratio of Q(f max ) to Q(f), where Q(f max ) represents the performance value corresponding to the maximum frequency f max , and Q(f) represents the performance value corresponding to the current frequency f. The ratio of Q(f max ) to Q(f) can also be represented by the inverse ratio of the execution time, that is, the ratio of T(f) to T(f max ), where T(f) is the execution time at the current frequency f, and T(f max ) represents the execution time at the maximum frequency f max . Therefore, the performance loss change formula satisfies the following formula:

[0076]

[0077] Where can be the inverse ratio of the real-time performance change of the task, that is

[0078] In the embodiments of the present application, the performance loss of the processor can also be expressed by a formula related to the blocking coefficient β. Among them, the blocking coefficient β represents the weight of the actual performance of the processor directly affected by frequency modulation, and the value of the blocking coefficient β is between (0, 1). The larger the blocking coefficient β, the greater the impact of the actual performance on the frequency. The smaller the blocking coefficient β, the less the actual performance of the processor is affected by frequency modulation. The performance loss of the processor and the blocking coefficient β satisfy the following formula:

[0079]

[0080] Please refer to Figure 3 , Figure 3 which is a schematic flowchart of another adaptive frequency modulation method provided by the embodiments of the present application. In steps a to b of the example shown in Figure 3 during the initialization stage of adaptive frequency modulation of the computing device, it is necessary to construct a real-time performance change formula and a performance loss formula based on historical monitoring data. Among them, the real-time performance change formula is used to indicate the relationship between the processor performance value and the PMU event, and the performance loss change formula is used to indicate the calculation formula of the performance loss rate.

[0081] Please refer to Figure 4 , Figure 4 which is a schematic flowchart of an adaptive frequency modulation provided by the embodiments of the present application. In steps a to b of the embodiment shown in Figure 4 during the initialization stage of adaptive frequency modulation of the computing device, the computing device needs to analyze the collected historical monitoring data to determine the PMU events related to the current performance change rate of the processor. The computing device uses these PMU events and the current performance change rate of the processor corresponding to the PMU events to fit the relationship between the current performance change rate and the PMU events. During the initialization stage of adaptive frequency modulation of the computing device, the computing device can calculate the current performance change rate of the processor based on the relationship between these performance values and the PMU events.

[0082] The above introduces the initialization work of the computing device before frequency modulation in the embodiments of the present application. Next, the frequency modulation operation stage of the computing device will be continued to be introduced.

[0083] During the frequency modulation operation stage of the computing device, the computing device collects real-time monitoring data of the processor. The real-time monitoring data includes one or more events monitored by the performance monitoring unit PMU of the processor, and the events include the number of instruction executions, cache hit rate, and branch prediction error rate. The real-time monitoring data of the processor collected by the computing device can be PMU events at different times and different frequencies. For example, the real-time monitoring data is the PMU event at the current moment now and the PMU event at the previous moment pre.

[0084] In a possible implementation, the real-time monitoring data collected by the computing device, in addition to PMU events, can also be events collected by an architectural performance monitoring unit (AMU), which can be called AMU events. In addition, the real-time monitoring data can also be the utilization rate of the central processing unit or other performance metrics related to other scenarios. Other performance metrics related to other scenarios, for example, the transactions per second (TPS) in a database scenario.

[0085] 202. The computing device calculates the predicted performance change rate of the processor based on the real-time monitoring data. The predicted performance change rate is used to indicate the ratio of the reference performance value of the processor to the running performance value.

[0086] The computing device calculates the predicted performance change rate of the processor at different frequencies based on the real-time monitoring data, where the predicted performance change rate can indicate the ratio of the reference performance value of the processor to the running performance value. Among them, the reference performance value of the processor is the performance value corresponding to the maximum frequency of the processor, and the running performance value is the performance value corresponding to the current frequency.

[0087] Specifically, the computing device can calculate the current performance change rate based on the above real-time performance change formula, and then further calculate the predicted performance change rate according to the current performance change rate. The following details the process of the computing device calculating the predicted performance change rate:

[0088] In a possible implementation, during the process of the computing device calculating the predicted performance change rate of the processor at different frequencies based on the real-time monitoring data, the computing device calculates the current performance change rate of the processor based on the real-time monitoring data and the performance change fitting relationship. The current performance change rate indicates the ratio of the performance value corresponding to the previous moment frequency to the performance value corresponding to the current frequency. Among them, the performance change fitting relationship is used to indicate the correlation between the performance change rate and the monitoring data. At the same time, the computing device calculates the ratio of the reference frequency to the previous moment frequency to obtain the frequency change rate, where the reference frequency is the maximum frequency of the processor. The computing device further calculates the predicted performance change rate based on the current performance change rate and the frequency change rate.

[0089] For example, the computing device collects the PMU events at the previous moment pre and the PMU events at the current moment now, and calculates the ratio of Q(f pre ) to Q(f now ) based on formula (1). Further, through the ratio of the maximum frequency f max to the previous moment frequency f pre and the ratio of Q(f pre ) and Q(f now ) to calculate Q(fmax ) and Q(f now ). Among them, the ratio of Q(f max ) and Q(f now ) is calculated to satisfy the following formula.

[0090]

[0091] 203. The computing device determines the target frequency of the processor based on the target performance loss rate and the predicted performance change rate, and the target performance loss rate is used to indicate the tolerable predicted performance change rate of the processor.

[0092] After the computing device calculates the predicted performance change rate of the processor, it determines the target frequency of the processor based on the target performance loss rate, and the target performance loss rate is used to indicate the tolerable predicted performance change rate of the processor. Specifically, during the frequency modulation process, the computing device needs to set the target performance loss rate, which is the allowable performance loss rate of the processor, and the target performance loss rate can also be called the performance loss threshold.

[0093] There are two ways for the computing device to determine the target frequency of the processor based on the target performance loss rate. In the first way to determine the target frequency, the computing device can first calculate the blocking coefficient and then calculate the target frequency according to the target performance loss rate and the blocking coefficient. In the second way to determine the target frequency, the computing device adjusts the frequency to calculate the performance loss rate, and when the performance loss rate reaches the target performance loss rate, the target frequency can be determined. The following introduces these two ways to determine the target frequency respectively:

[0094] In the first way to determine the target frequency, during the process of the computing device determining the target frequency of the processor based on the target performance loss rate, the computing device calculates the blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and the frequency change rate of the processor, and the frequency change rate indicates the ratio of the reference frequency of the processor to the current frequency. The computing device determines the target frequency according to the target performance loss rate and the blocking coefficient.

[0095] For example, when the computing device adjusts the target frequency of the next moment based on the PMU events at the previous moment pre and the current moment now, the computing device collects the PMU events at the previous moment pre and the current moment now, and calculates Q(f pre ) and Q(f now ) respectively based on formula (1). After obtaining the ratio, based on the above formula (4), the ratio of Q(f max ) and Q(f now ) can be calculated, and this ratio is the predicted performance change rate of the processor. And based on the above formula (2) and formula (3), it can be known that Q(f max ) and Q(fnow ) The relationship between the ratio and the blocking coefficient β satisfies the following formula:

[0096]

[0097] Therefore, the computing device can calculate a blocking coefficient β based on the ratio of Q(f max ) and Q(f now ), and the ratio of the maximum frequency f max to the current moment frequency f now . Then, update the original blocking coefficient. After that, the computing device continues to calculate the target frequency f target at the next moment based on the blocking coefficient β and the set target performance loss rate σ target . The relationship between the target performance loss rate σ target and the target frequency f target satisfies the following formula:

[0098]

[0099] When the computing device determines the target frequency according to the target performance loss rate σ target and the blocking coefficient β, the computing device can calculate the target frequency f target based on the target performance loss rate σ target in formula (6), and f target is the target frequency adjusted at the next moment.

[0100] Please continue to refer to Figure 3 , in step c of the example shown in Figure 3 , the computing device collects real-time monitoring data during the operation phase, updates the blocking coefficient based on the real-time monitoring data, and sets the target frequency based on the updated blocking coefficient and the target performance loss rate. For example, the computing device calculates the ratio of the performance value Q(f pre ) at the previous moment and the performance value Q(f now ) at the current moment based on the above formula (1), that is and further calculates the predicted performance change rate based on the above formula (4). At the same time, the blocking coefficient β is calculated according to the above formula (5).

[0101] In the example shown in Figure 3 , after the computing device calculates the blocking coefficient β, according to the set target performance loss rate σ target , the target frequency f target can be calculated based on the above formula (6).

[0102] Please continue to refer to Figure 4 , in Figure 4In steps c to e of the illustrated example, the computing device first sets a target performance loss rate, and then collects real-time monitoring data. The real-time monitoring data includes the previous PMU event and the current PMU event. The computing device calculates the current performance change rate based on the real-time monitoring data, that is, the ratio of the performance value at the previous moment to the performance value at the current moment, and calculates the predicted performance change rate based on the current performance change rate. The predicted performance change rate is the ratio of the performance value at the maximum frequency to the performance value at the current moment.

[0103] In Figure 4 In steps f to g of the illustrated example, the computing device further calculates the blocking coefficient according to the ratio of the performance value at the maximum frequency to the performance value at the current moment and the target performance loss rate. The computing device calculates the target frequency according to the blocking coefficient and sets the target frequency for the next moment.

[0104] In the second method for determining the target frequency, when the computing device determines the target frequency of the processor based on the target performance loss rate, if the predicted performance change rate of the processor is greater than the predicted performance change rate corresponding to the target performance loss rate, the frequency of the processor is increased. If the predicted performance change rate of the processor is less than the predicted performance change rate corresponding to the target performance loss rate, the frequency of the processor is decreased.

[0105] For example, when the computing device adjusts the target frequency for the next moment based on the PMU event at the previous moment pre and the PMU event at the current moment now, the computing device collects the PMU event at the previous moment pre and the PMU event at the current moment now, and calculates the ratio of Q(f pre ) and Q(f now ) respectively based on formula (1). After that, based on the above formula (4), the ratio of Q(f max ) to Q(f now ) is calculated. Since the ratio of Q(f max ) to Q(f now ) satisfies the following formula with the performance loss:

[0106]

[0107] Therefore, the computing device compares the ratio of Q(f max ) to Q(f now ) with 1 + σ target . When the ratio of Q(f max ) to Q(f now ) is greater than or equal to 1 + σ target , the computing device needs to increase the frequency of the processor by one level. When the ratio of Q(f max ) to Q(f now ) is less than 1 + σ target, the computing device needs to reduce the frequency of the processor by one level to achieve adaptive adjustment of the processor frequency.

[0108] Please refer to Figure 5 , Figure 5 which is another schematic flow chart of adaptive frequency modulation provided by the embodiments of the present application. In Figure 5 steps a to e of the example shown, after the computing device sets the target performance loss rate, it also needs to calculate the current performance change rate based on real-time monitoring data, that is, the ratio of the performance value at the previous moment to the performance value at the current moment, and calculate the predicted performance change rate according to the ratio of the performance value at the previous moment to the performance value at the current moment. The specific calculation process is similar to steps a to e of the example shown above Figure 4 and will not be elaborated here.

[0109] In Figure 5 steps f to h of the example shown, after the computing device calculates the predicted performance change rate corresponding to the current frequency, and calculates the performance loss rate corresponding to the current frequency based on the predicted performance change rate corresponding to the current frequency. If the performance loss corresponding to the current frequency is greater than or equal to the target performance loss rate, the computing device increases the current frequency by one level. If the performance loss corresponding to the current frequency is less than the target performance loss rate, the computing device reduces the current frequency by one level.

[0110] It can be seen from the above embodiments that in the embodiments of the present application, the computing device can calculate the current performance change rate of the processor based on one or more events monitored by the performance monitoring unit PMU of the processor, calculate the predicted performance change rate of the processor according to the current performance change rate of the processor, and further determine the target frequency according to the target performance loss rate and the predicted performance change rate. Since the PMU event can more accurately reflect the performance value of the processor, the accuracy of the target frequency is improved and the power consumption of the processor is reduced.

[0111] Based on the above method embodiments, the embodiments of the present application also provide an adaptive frequency modulation device. The adaptive frequency modulation device provided by the embodiments of the present application will be specifically introduced below.

[0112] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of an adaptive frequency modulation device provided by the embodiments of the present application. In Figure 6 the example shown, the adaptive frequency modulation device 600 is used to implement each step executed by the computing device in the above embodiments. The adaptive frequency modulation device 600 includes an acquisition unit 601 and a processing unit 602.

[0113] Among them, the acquisition unit 601 is used to collect real-time monitoring data of the processor. The real-time monitoring data includes one or more events monitored by the performance monitoring unit PMU of the processor. The events include one or more of the following: the number of instruction executions, the cache hit rate, and the branch prediction error rate. The processing unit 602 is used to calculate the predicted performance change rate of the processor based on the real-time monitoring data. The predicted change rate is determined based on the current performance change rate of the processor. The current performance change rate is determined based on the real-time monitoring data. The predicted performance change rate is used to indicate the ratio of the reference performance value of the processor to the running performance value. The processing unit 602 is also used to determine the target frequency of the processor based on the target performance loss rate and the predicted performance change rate. The target performance loss rate is used to indicate the tolerable predicted performance change rate of the processor.

[0114] In a possible implementation, the processing unit 602 is specifically configured to calculate the current performance change rate of the processor based on the real-time monitoring data and the performance change fitting relationship. The performance change fitting relationship is used to indicate the correlation between the performance change rate and the monitoring data. The predicted performance change rate is calculated based on the current performance change rate and the frequency change rate. The frequency change rate is the ratio of the reference frequency to the running frequency.

[0115] In a possible implementation, the current performance change rate is used to indicate the ratio of the performance value corresponding to the frequency at the previous moment to the performance value corresponding to the frequency at the current moment. The processing unit 602 is specifically configured to calculate the frequency change rate based on the reference frequency and the frequency at the previous moment, and calculate the predicted performance change rate based on the current performance change rate and the frequency change rate. The predicted performance change rate is used to indicate the ratio between the reference performance value of the processor and the performance value corresponding to the frequency at the current moment.

[0116] In a possible implementation, the processing unit 602 is specifically configured to calculate the blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and the frequency change rate, and determine the target frequency based on the target performance loss rate and the blocking coefficient.

[0117] In a possible implementation, the processing unit 602 is also used to increase the frequency of the processor when the predicted performance change rate is greater than or equal to the performance change rate corresponding to the target performance loss rate. When the predicted performance change rate is less than the performance change rate corresponding to the target performance loss rate, the frequency of the processor is decreased.

[0118] In a possible implementation, the processing unit 602 is also used to obtain historical monitoring data. The historical monitoring data includes one or more events monitored by the performance monitoring unit PMU of the processor at different frequencies. The performance change fitting relationship is obtained by fitting based on the historical monitoring data.

[0119] In a possible implementation manner, the processing unit 602 is further configured to establish an association relationship between a performance loss rate and a frequency change rate based on historical monitoring data, where the association relationship includes a blocking coefficient, and the blocking coefficient is used to indicate the weight of the performance value of the processor affected by the frequency.

[0120] It can be understood that the acquisition unit 601 and the processing unit 602 in the adaptive frequency modulation device 600 can be used as functional modules and Figure 1 there is a mapping with each module in the adaptive frequency modulation system 10 in, so as to implement the functions of each module in the task processing system 10.

[0121] It should be understood that the division of units in the above device is only a division of logical functions. In actual implementation, they can be all or partially integrated into a physical entity, or physically separated. And the units in the device can all be implemented in the form of software called by processing elements; they can also all be implemented in the form of hardware; they can also be partially implemented in the form of software called by processing elements and partially implemented in the form of hardware. For example, each unit can be a separately established processing element, or can be integrated in a certain chip of the device. In addition, it can also be stored in the memory in the form of a program, and the function of the unit is called and executed by a certain processing element of the device. In addition, all or part of these units can be integrated together or can be independently implemented. The processing element described here can also be a processor, which can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each of the above units can be implemented by the integrated logic circuit of the hardware in the processor element or in the form of software called by the processing element.

[0122] It is worth noting that for the above method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by this application.

[0123] Other reasonable combinations of steps that those skilled in the art can think of based on the above description also fall within the protection scope of this application. Secondly, those skilled in the art should also be familiar that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by this application.

[0124] Please refer to Figure 7 , Figure 7 which is a schematic structural diagram of a computing device provided by an embodiment of this application. As Figure 7As shown, the computing device 700 includes: a processor 701, a memory 702, a communication interface 703, and a bus 704. The processor 701, the memory 702, and the communication interface 703 are coupled through a bus (not labeled in the figure). The memory 702 stores instructions. When the execution instructions in the memory 702 are executed, the computing device 700 executes the methods performed by the computing device in the above method embodiments.

[0125] The computing device 700 may be one or more integrated circuits configured to implement the above methods. For example: one or more application specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms. Again, when the units in the device can be implemented in the form of a processing element scheduler, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processors that can call programs. Again, these units may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0126] The processor 701 may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0127] The memory 702 can be a volatile memory, a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0128] Executable program code is stored in the memory 702, and the processor 701 executes the executable program code to implement the functions of the foregoing units or modules respectively, thereby implementing the foregoing adaptive frequency modulation method. That is to say, instructions for executing the foregoing adaptive frequency modulation method are stored on the memory 702.

[0129] The communication interface 703 uses a transceiver module such as, but not limited to, a network interface card, a transceiver, etc., to implement communication between the computing device 700 and other devices or communication networks.

[0130] In addition to including a data bus, the bus 704 may further include a power bus, a control bus, a status signal bus, and the like. The bus may be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus may be divided into an address bus, a data bus, a control bus, and the like.

[0131] Please refer to Figure 8 , Figure 8 which is a schematic structural diagram of a chip provided by an embodiment of the present application. As Figure 8 shown, the chip 800 includes a processing circuit 801 and a storage circuit 802. Instructions for executing the above-mentioned adaptive frequency modulation method may be stored in the storage circuit 702 in the chip 800. When the instructions are executed by the processing circuit, the chip executes the above-mentioned adaptive frequency modulation method.

[0132] In another embodiment of the present application, a computer-readable storage medium is further provided. Computer-executable instructions are stored in the computer-readable storage medium. When the processor of the device executes the computer-executable instructions, the device executes the method executed by the computing device in the above-mentioned method embodiment.

[0133] In another embodiment of the present application, a computer program product is further provided. The computer program product includes computer-executable instructions, and the computer-executable instructions are stored in a computer-readable storage medium. When the processor of the device executes the computer-executable instructions, the device executes the method executed by the computing device in the above-mentioned method embodiment.

[0134] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0135] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be in electrical, mechanical, or other forms.

[0136] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0137] In addition, each functional unit in various embodiments of the present application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0138] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROM, read-only memory), random access memories (RAM, random access memory), magnetic disks, or optical discs and other various media that can store program codes.

Claims

1. An adaptive frequency modulation method, characterized in that, The method includes: Collecting real-time monitoring data of the processor, where the real-time monitoring data includes one or more events monitored by a performance monitoring unit (PMU) of the processor, and the events include one or more of the following: the number of instruction executions, cache hit rate, and branch misprediction rate; Calculating a predicted performance change rate of the processor based on the real-time monitoring data, where the predicted change rate is determined based on a current performance change rate of the processor, the current performance change rate is determined based on the real-time monitoring data, and the predicted performance change rate is used to indicate a ratio of a reference performance value of the processor to a running performance value; Determining a target frequency of the processor based on a target performance loss rate and the predicted performance change rate, where the target performance loss rate is used to indicate a tolerable predicted performance change rate of the processor.

2. The method according to claim 1, characterized in that, The calculating the predicted performance change rate of the processor based on the real-time monitoring data includes: Calculating the current performance change rate of the processor based on the real-time monitoring data and a performance change fitting relationship, where the performance change fitting relationship is used to indicate an association relationship between a performance change rate and monitoring data; Calculating the predicted performance change rate according to the current performance change rate and a frequency change rate, where the frequency change rate is a ratio of a reference frequency to a running frequency.

3. The method according to claim 2, wherein The current performance change rate is used to indicate a ratio of a performance value corresponding to a frequency at a previous moment to a performance value corresponding to a frequency at the current moment. The calculating the predicted performance change rate according to the current performance change rate and the frequency change rate includes: Calculating the frequency change rate according to the reference frequency and the frequency at the previous moment; Calculating the predicted performance change rate according to the current performance change rate and the frequency change rate, where the predicted performance change rate is used to indicate a ratio between a reference performance value of the processor and a performance value corresponding to the frequency at the current moment.

4. The method according to any one of claims 2 or 3, characterized in that, The determining the target frequency of the processor based on the target performance loss rate and the predicted performance change rate includes: Calculating a blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and the frequency change rate; Determining the target frequency according to the target performance loss rate and the blocking coefficient.

5. The method according to any one of claims 1 to 3, characterized in that The method further includes: When the predicted performance change rate is greater than or equal to a performance change rate corresponding to the target performance loss rate, increasing the frequency of the processor; When the predicted performance change rate is less than the performance change rate corresponding to the target performance loss rate, decreasing the frequency of the processor.

6. The method according to any one of claims 2 to 5, characterized in that, The method further includes: Obtaining historical monitoring data, where the historical monitoring data includes one or more events monitored by a performance monitoring unit (PMU) of the processor at different frequencies; Fitting the performance change fitting relationship based on the historical monitoring data.

7. The method according to claim 4, characterized in that The method further includes: Establishing an association relationship between the performance loss rate and the frequency change rate based on the historical monitoring data, where the association relationship includes the blocking coefficient, and the blocking coefficient is used to indicate a weight by which a performance value of the processor is affected by the frequency.

8. An adaptive frequency modulation device, characterized in that, The device includes: An acquisition unit for collecting real-time monitoring data of a processor, the real-time monitoring data including one or more events monitored by a performance monitoring unit (PMU) of the processor, the events including one or more of the following: the number of instruction executions, cache hit rate, and branch prediction error rate; A processing unit for calculating a predicted performance change rate of the processor based on the real-time monitoring data, the predicted change rate being determined based on a current performance change rate of the processor, the current performance change rate being determined based on the real-time monitoring data, the predicted performance change rate being used to indicate a ratio of a reference performance value of the processor to a running performance value; The processing unit is further configured to determine a target frequency of the processor based on a target performance loss rate and the predicted performance change rate, the target performance loss rate being used to indicate a tolerable predicted performance change rate of the processor.

9. The device according to claim 8, characterized in that, Specifically, the processing unit is configured to: Calculate the current performance change rate of the processor based on the real-time monitoring data and a performance change fitting relationship, the performance change fitting relationship being used to indicate an association relationship between a performance change rate and monitoring data; Calculate the predicted performance change rate according to the current performance change rate and a frequency change rate, the frequency change rate being a ratio of a reference frequency to a running frequency.

10. The device according to claim 9, characterized in that, The current performance change rate is used to indicate a ratio of a performance value corresponding to a frequency at a previous moment to a performance value corresponding to a frequency at the current moment. Specifically, the processing unit is configured to: Calculate the frequency change rate according to the reference frequency and the frequency at the previous moment; Calculate the predicted performance change rate according to the current performance change rate and the frequency change rate, the predicted performance change rate being used to indicate a ratio between a reference performance value of the processor and a performance value corresponding to the frequency at the current moment.

11. The device according to any one of claims 9 or 10, characterized in that, Specifically, the processing unit is configured to: Calculate a blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and the frequency change rate; Determine a target frequency according to the target performance loss rate and the blocking coefficient.

12. The device according to any one of claims 8 to 11, characterized in that, The processing unit is further configured to: When the predicted performance change rate is greater than or equal to a performance change rate corresponding to the target performance loss rate, increase the frequency of the processor; When the predicted performance change rate is less than a performance change rate corresponding to the target performance loss rate, decrease the frequency of the processor.

13. The device according to any one of claims 9 to 12, characterized in that The processing unit is further configured to: Acquire historical monitoring data, the historical monitoring data including one or more events monitored by a performance monitoring unit (PMU) of the processor at different frequencies; Obtain the performance change fitting relationship by fitting based on the historical monitoring data.

14. The device according to claim 11, characterized in that, The processing unit is further configured to: Establish an association relationship between the performance loss rate and the frequency change rate based on the historical monitoring data, the association relationship including the blocking coefficient, the blocking coefficient being used to indicate a weight of the performance value of the processor affected by the frequency.

15. A computing device, characterized in that, Including a processor, the processor being coupled to a memory, the memory being configured to store instructions, which when executed by the processor, cause the computing device to execute the method according to any one of claims 1 to 7.

16. A chip, characterized in that, Including a processing circuit, the processing circuit is coupled to a storage circuit, and the storage circuit is used to store instructions. When the instructions are executed by the processing circuit, the chip is caused to execute the method according to any one of claims 1 to 7.

17. A computer-readable storage medium having instructions stored thereon, characterized in that, When the instructions are executed, the computer is caused to execute the method according to any one of claims 1 to 7.

18. A computer program product, the computer program product including instructions, characterized in that, When the instructions are executed, the computer is caused to implement the method according to any one of claims 1 to 7.

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