An adaptive frequency modulation method and apparatus

Abstract

The embodiment of the present application discloses a self-adaptive frequency modulation method and device, which is used to improve the frequency modulation accuracy of a processor. The method of the embodiment of the present application comprises: a computing device collects real-time monitoring data of the processor, the real-time monitoring data comprises one or more events monitored by a performance monitoring unit (PMU) of the processor, the events comprise one or more of the following: instruction execution times, cache hit rate and branch prediction error rate. The predicted performance change rate of the processor is calculated based on the real-time monitoring data, the predicted performance change rate is determined based on the current performance change rate of the processor, the current performance change rate is determined based on the real-time monitoring data, and the predicted performance change rate is used to indicate the proportion of the reference performance value of the processor relative to the running performance value. The target frequency of the processor is determined based on the target performance loss rate and the predicted performance change rate, and the target performance loss rate is used to indicate the predicted performance change rate that can be tolerated by the processor.

Description

[0001] This application is a divisional application. The original application has the application number 202410138157.4 and the original application date is January 30, 2024. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computers, and more particularly to an adaptive frequency modulation method and apparatus. Background Technology

[0003] With the development of cloud computing technology, one of the main problems facing computing devices is the cost of energy consumption, which is particularly evident in supercomputing systems. Many supercomputing clusters are limited by their total operating power, requiring them to reduce power consumption and improve energy efficiency. In computing devices, the power consumption of the central processing unit (CPU) often accounts for more than half of the total power consumption of the computing device; therefore, energy saving requires a focus on CPU power consumption.

[0004] In current power-saving solutions for central processing units (CPUs), since most computing devices support dynamic frequency adjustment, the device can effectively reduce processor power consumption by lowering the processor frequency. However, current computing devices often adjust the frequency based on CPU utilization; for example, when CPU utilization increases, the computing device can increase the frequency, and when CPU utilization decreases, the computing device can decrease the frequency.

[0005] However, in actual task processing, CPU utilization cannot fully reflect the actual performance of the processor, and the frequency adjustment of computing devices based on CPU utilization will lead to poor frequency adjustment accuracy and high processor power consumption. Summary of the Invention

[0006] This application provides an adaptive frequency modulation method. A computing device can acquire events collected by the processor's performance monitoring unit (PMU) and adjust the frequency based on these PMU events, thereby improving the accuracy of frequency adjustment and reducing processor power consumption. This application also provides an adaptive frequency modulation device, computing device, chip, computer-readable storage medium, and computer program product corresponding to the adaptive frequency modulation method.

[0007] In a first aspect, embodiments of this application provide an adaptive frequency modulation method. This method can be executed by a computing device, or by a component of the computing device, such as a processor, chip, or chip system, or by a logic module or software capable of implementing all or part of the functions of the computing device. Taking a computing device as an example, the method provided in the first aspect includes: the computing device collecting real-time monitoring data of the processor, the real-time monitoring data including one or more events monitored by the processor's performance monitoring unit (PMU), the events including one or more of the following: instruction execution count, cache hit rate, and branch prediction error rate. The computing device calculates a predicted performance change rate of the processor based on the real-time monitoring data, the predicted performance change rate being determined based on the processor's current performance change rate, which in turn is determined based on the real-time monitoring data. The predicted performance change rate is used to indicate the ratio of a reference performance value to a running performance value, where the reference performance value is the performance value corresponding to the processor's maximum frequency, and the running performance value is the processor performance value corresponding to the current frequency. The computing device determines a target frequency of the processor based on a target performance loss rate and the predicted performance change rate, where the target performance loss rate is used to indicate the tolerable predicted performance change rate of the processor.

[0008] In this embodiment, the computing device can calculate the current performance change rate of the processor based on one or more events monitored by the processor's performance monitoring unit (PMU), and calculate the predicted performance change rate of the processor based on the current performance change rate. At the same time, the target frequency is further determined based on the target performance loss rate and the predicted performance change rate. Compared with the prior art of adjusting the processor frequency based on the processor utilization, this embodiment can more accurately reflect the processor performance based on PMU events. Frequency adjustment based on PMU events improves the accuracy of the target frequency and reduces the processor's power consumption.

[0009] In one possible implementation, during the process of calculating the predicted performance change rate of the processor based on real-time monitoring data, the computing device calculates the current performance change rate of the processor based on the real-time monitoring data and a performance change fitting relationship, wherein the performance change fitting relationship is used to indicate the correlation between the performance change rate and the monitoring data. The computing device calculates the predicted performance change rate based on the current performance change rate and the frequency change rate, where the frequency change rate is the ratio of a reference frequency to the operating frequency, and the reference frequency is the processor's maximum frequency, while the operating frequency is the frequency at the previous moment.

[0010] In this embodiment of the application, the computing device can calculate the current performance change rate corresponding to the real-time monitoring data based on the performance change fitting relationship, and further calculate the predicted performance change rate of the processor based on the current performance change rate and the frequency change rate, thereby improving the accuracy of the predicted performance change rate.

[0011] In one possible implementation, the current performance change rate is used to indicate the ratio of the performance value corresponding to the frequency at the previous moment to the performance value corresponding to the frequency at the current moment. During the process of the computing device calculating the predicted performance change rate based on the current performance change rate and the frequency change rate, the computing device calculates the frequency change rate based on the reference frequency and the frequency at the previous moment. Then, the computing device calculates the predicted performance change rate based on the current performance change rate and the frequency change rate. The predicted performance change rate is used to indicate the ratio between the processor's reference performance value and the performance value corresponding to the frequency at the current moment.

[0012] In the embodiments of this application, the computing device can calculate the predicted performance change rate of the processor based on the ratio of the processor performance value at the previous moment to the processor performance value at the current moment, and the frequency change rate corresponding to the current moment, thereby improving the feasibility of the scheme for calculating the predicted performance change rate of the processor.

[0013] In one possible implementation, the computing device acquires historical monitoring data, which includes one or more events monitored by the processor's performance monitoring unit (PMU) at different frequencies. Based on the historical monitoring data, the computing device fits a formula to determine the relationship between the processor's performance changes; this formula, also known as the performance change formula, indicates the correlation between the current performance change rate and the events. Specifically, the computing device fits the processor's performance change formula based on the historical monitoring data and the corresponding performance change rate.

[0014] The computing device in this application embodiment can fit a processor change formula based on historical monitoring data, thereby establishing a correlation between the current performance change rate of the processor and PMU events, and improving the accuracy of the computing device in calculating the current performance change rate of the processor.

[0015] In one possible implementation, before fitting a processor performance change formula based on historical monitoring data, the computing device identifies PMU events related to the current performance change rate. Specifically, the computing device identifies PMU events whose correlation with the current performance change rate exceeds a threshold as associated PMU events, and then fits the processor performance change formula based on the associated PMU events and the corresponding current processor performance change rates.

[0016] In the embodiments of this application, the computing device can use PMU events whose correlation with the current rate of change of processor performance exceeds a threshold as associated PMU events, thereby reducing the complexity of the computing device in fitting the processor performance change formula based on historical monitoring data and improving the fitting efficiency of the processor performance change formula.

[0017] In one possible implementation, the computing device establishes a correlation between the processor performance loss rate and the frequency change rate based on historical monitoring data. This correlation includes a blocking coefficient, which indicates the weight by which the processor performance value is affected by the frequency. The computing device can calculate the blocking coefficient based on the current frequency and the performance loss rate corresponding to the predicted performance change rate. The blocking coefficient is also used to calculate the target frequency of the processor based on the target performance loss rate.

[0018] In this embodiment of the application, the computing device can establish a correlation between processor performance loss rate and frequency based on historical monitoring data, thereby enabling the computing device to calculate the target frequency of the processor based on the target performance loss rate, thus improving the feasibility of the computing device to calculate the target frequency.

[0019] In one possible implementation, during the process of determining the target frequency of the processor based on the target performance loss rate and the performance change rate, the computing device calculates a blocking coefficient corresponding to real-time monitoring data based on the processor's predicted performance change rate and frequency change rate. The predicted performance change rate indicates the ratio of the performance value corresponding to the reference frequency to the performance value corresponding to the current frequency, and the frequency change rate indicates the ratio of the processor's reference frequency to the current frequency. The computing device determines the target frequency based on the target performance loss rate and the blocking coefficient; the target frequency is the frequency at which the processor will adjust in the next moment.

[0020] In this embodiment of the application, the computing device can calculate the blocking coefficient corresponding to the real-time monitoring data based on the processor's predicted performance change rate and frequency change rate, and determine the target frequency based on the target performance loss rate and the blocking coefficient, thereby improving the calculation efficiency of the target frequency.

[0021] In one possible implementation, when the processor's predicted performance change rate is greater than or equal to the performance change rate corresponding to the target performance loss rate (i.e., the performance loss rate at the current frequency is greater than or equal to the target performance loss rate), the processor frequency is increased. When the processor's predicted performance change rate is less than the performance change rate corresponding to the target performance loss rate (i.e., the performance loss rate at the current frequency is less than the target performance loss rate), the processor frequency is decreased.

[0022] In this embodiment of the application, the computing device can adjust the frequency to calculate the predicted performance change rate of the processor and compare the predicted performance change rate with the predicted performance change rate corresponding to the target performance loss rate, thereby adjusting the processor frequency and improving the accuracy of the target frequency.

[0023] In one possible implementation, the real-time monitoring data collected by the computing device can be events collected by the Architecture Performance Monitoring Unit (AMU) in addition to PMU events. Real-time monitoring data can also include CPU utilization or other scenario-related performance metrics, such as transactions per second in a database scenario.

[0024] In the embodiments of this application, computing devices can collect different types of real-time monitoring data in different application scenarios, and determine the processor's predicted performance change rate based on different real-time monitoring data, thereby improving the accuracy of the processor's predicted performance change rate calculation.

[0025] Secondly, embodiments of this application provide an adaptive frequency modulation device, which includes an acquisition unit and a processing unit. The acquisition unit is used to collect real-time monitoring data of the processor. The real-time monitoring data includes one or more events monitored by the processor's performance monitoring unit (PMU). These events include one or more of the following: instruction execution count, cache hit rate, and branch prediction error rate. The processing unit is used to calculate a predicted performance change rate of the processor based on the real-time monitoring data. The predicted performance change rate is determined based on the processor's current performance change rate, which is also determined based on the real-time monitoring data. The predicted performance change rate indicates the ratio of the processor's reference performance value to its operating performance value. The processing unit is also used to determine a target frequency of the processor based on a target performance loss rate and the predicted performance change rate. The target performance loss rate indicates the tolerable predicted performance change rate of the processor.

[0026] In one possible implementation, the processing unit is specifically used to calculate the current performance change rate of the processor based on real-time monitoring data and a performance change fitting relationship, the performance change fitting relationship being used to indicate the correlation between the performance change rate and the monitoring data, and to calculate the predicted performance change rate based on the current performance change rate and the frequency change rate, the frequency change rate being the ratio of the reference frequency to the operating frequency.

[0027] In one possible implementation, the current performance change rate is used to indicate the ratio of the performance value corresponding to the frequency at the previous moment to the performance value corresponding to the frequency at the current moment. Specifically, the processing unit is used to calculate the frequency change rate based on the reference frequency and the frequency at the previous moment, and to calculate the predicted performance change rate based on the current performance change rate and the frequency change rate. The predicted performance change rate is used to indicate the ratio between the processor's reference performance value and the performance value corresponding to the frequency at the current moment.

[0028] In one possible implementation, the processing unit is specifically used to calculate the blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and frequency change rate, and to determine the target frequency based on the target performance loss rate and the blocking coefficient.

[0029] In one possible implementation, the processing unit is further configured to increase the processor frequency when the predicted performance change rate is greater than or equal to the performance change rate corresponding to the target performance loss rate, and decrease the processor frequency when the predicted performance change rate is less than the performance change rate corresponding to the target performance loss rate.

[0030] In one possible implementation, the processing unit is further configured to acquire historical monitoring data, which includes one or more events monitored by the processor's performance monitoring unit (PMU) at different frequencies, and to fit a performance change relationship based on the historical monitoring data.

[0031] In one possible implementation, the processing unit is further configured to establish a correlation between the performance loss rate and the frequency change rate based on historical monitoring data. The correlation includes a blocking coefficient, which indicates the weight by which the processor's performance value is affected by the frequency.

[0032] Thirdly, embodiments of this application provide a computing device including a processor coupled to a memory. The processor stores instructions, which, when executed by the processor, cause the computing device to perform the method described in the first aspect or any possible implementation thereof.

[0033] Fourthly, embodiments of this application provide a chip including one or more processing circuits coupled to a storage circuit. The processing circuits are used to store instructions, and when the instructions are executed by the processing circuits, the chip performs the method described in the first aspect or any possible implementation of the first aspect.

[0034] Fifthly, embodiments of this application provide a computer-readable storage medium having instructions stored thereon, which, when executed, cause a computer to perform the method described in the first aspect or any possible implementation thereof.

[0035] Sixthly, embodiments of this application provide a computer program product including instructions that, when executed, cause a computer to implement the method described in the first aspect or any possible implementation thereof.

[0036] It is understood that the beneficial effects achieved by any of the adaptive frequency modulation devices, computing devices, chips, computer-readable media or computer program products provided above can be referred to the beneficial effects in the corresponding methods, and will not be repeated here. Attached Figure Description

[0037] Figure 1 A schematic diagram of the system architecture of an adaptive frequency modulation system provided in this application embodiment;

[0038] Figure 2A flowchart illustrating an adaptive frequency modulation method provided in an embodiment of this application;

[0039] Figure 3 A flowchart illustrating another adaptive frequency modulation method provided in an embodiment of this application;

[0040] Figure 4 A flowchart illustrating another adaptive frequency modulation method provided in an embodiment of this application;

[0041] Figure 5 A flowchart illustrating another adaptive frequency modulation method provided in an embodiment of this application;

[0042] Figure 6 This is a schematic diagram of the structure of an adaptive frequency modulation device provided in an embodiment of this application;

[0043] Figure 7 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0044] Figure 8 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0045] This application provides an adaptive frequency adjustment method and apparatus to improve the accuracy of frequency adjustment in computing devices and reduce processor power consumption.

[0046] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0048] First, some of the terms used in the embodiments of this application are introduced to facilitate understanding of the technical solutions by those skilled in the art.

[0049] A performance monitoring unit (PMU) counter is a hardware component on the central processing unit (CPU) used to measure system performance and resource utilization. The PMU counter can record various processor events, such as instruction execution counts, cache hit rates, and memory access counts.

[0050] To make the technical solution of this application clearer and easier to understand, the system architecture of this application will be described below with reference to the accompanying drawings.

[0051] Please see Figure 1 , Figure 1 This is a schematic diagram of the system architecture of an adaptive frequency modulation system provided in an embodiment of this application. Figure 1 In the example shown, the adaptive frequency modulation system 10 includes a system file interface module 101, a processor frequency modulation module 102, and a processor hardware module 103. The processor frequency modulation module includes a frequency modulation management submodule 1021, a frequency modulation core submodule 1022, and a frequency modulation driver submodule 1023. The specific functions of each module in the adaptive frequency modulation system 10 are described below.

[0052] The system file interface module 101 provides the user space with an interface to access the processor frequency modulation module 102, also known as the sysfs module. User applications can use the system file interface module 101 to obtain information about various devices, drivers, and submodules within the processor frequency modulation module 102 in the form of files, and to configure or adjust the processor frequency modulation module 102. For example, user applications can use the system file interface module 101 to query or set the frequency of the central processing unit.

[0053] The processor frequency modulation module 102, also known as the CPUfreq module, is used to control the frequency of the central processing unit in kernel space. The processor frequency modulation module 102 includes a frequency modulation management submodule 1021, a frequency modulation core submodule 1022, a frequency modulation driver submodule 1023, and a frequency modulation data statistics submodule 1024.

[0054] The frequency regulation management submodule 1021, also known as the CPUfreq governor submodule, is used to select the processor's frequency strategy based on the CPU's load. Frequency strategies include performance priority strategy, power save strategy, user space strategy, on-demand allocation strategy, conservation strategy, and schedutil strategy.

[0055] The frequency modulation core submodule 1022, also known as the CPUfreq core submodule, is used to implement the overall management and control of the processor frequency modulation module 102, including the initialization of the CPUfreq framework, callback registration, event management, and driver management. The frequency modulation core submodule 1022 can provide a general control interface and algorithms to coordinate the interactive operations between different submodules of the processor frequency modulation module 102.

[0056] For example, the frequency modulation core submodule 1022 can receive user queries or setting requests for the central processing unit (CPU) frequency and frequency policy through the system file interface module 101. The frequency modulation core submodule 1022 can also manage and modify the frequency policy of the frequency modulation management submodule 1021, and control the frequency modulation drive submodule 1023 to adjust the frequency according to the frequency policy. The frequency modulation core submodule 1022 can also monitor the CPU load and power consumption requirements.

[0057] The frequency modulation driver submodule 1023, also known as the CPUfreq driver module, is used to implement the frequency or voltage modulation mechanism of the central processing unit (CPU). The frequency modulation driver submodule 1023 interacts with the processor hardware module 103 and adjusts the CPU frequency according to the frequency strategy selected by the frequency modulation management submodule 1021. The frequency modulation driver submodule 1023 can also read the current frequency value of the CPU from the processor hardware module 103 and adjust the CPU frequency to achieve the required performance or power consumption targets.

[0058] For example, the frequency modulation driver submodule 1023 can integrate a driver that interacts with the processor hardware module 103 to read and set the main frequency of the central processing unit. The frequency modulation driver submodule 1023 can also read the system operating performance points (OPP) to obtain frequency and voltage level information.

[0059] The frequency modulation data statistics submodule 1024, also known as the CPUfreq stats submodule, is used to collect statistical information about the processor frequency, providing real-time and historical data. For example, it can track the processor's operating time at different frequencies, record the number of frequency transitions, and calculate the percentage and duration of each frequency. Furthermore, it can record and save historical processor frequency data, retaining the data after a system restart and providing an interface for querying historical data.

[0060] The processor hardware module 103 includes hardware components that interact with the processor frequency modulation module 102. The processor hardware module 103 can receive frequency acquisition or frequency adjustment commands from the frequency modulation drive submodule 1023. The processor hardware module 103 may include, for example, a processor power management module, power consumption-related registers, and a power control unit (PCU), but is not specifically limited to any particular component.

[0061] For example, the processor hardware module 103 also includes a performance monitoring unit (PMU) counter. In this embodiment, the processor frequency adjustment module 102 can interact with the PMU counter to obtain processor performance data. By analyzing the data of the PMU counter, the processor frequency adjustment module 102 can obtain data such as processor load, cache hit rate, power consumption and performance indicators, and decide whether to adjust the processor's operating frequency accordingly.

[0062] based on Figure 1 The adaptive frequency modulation system 10 shown in this application also provides an adaptive frequency modulation method. The adaptive frequency modulation method provided in this application will be described below with reference to embodiments.

[0063] Please see Figure 2 , Figure 2 This is a flowchart illustrating an adaptive frequency modulation method provided in an embodiment of this application. Figure 2 In the example shown, the method includes the following steps:

[0064] 201. The computing device acquires real-time monitoring data of the processor, which includes one or more events monitored by the processor's performance monitoring unit (PMU). The events include one or more of the following: instruction execution count, cache hit rate, and branch prediction error rate.

[0065] In this embodiment, before performing adaptive frequency modulation, the computing device needs to perform pre-modulation initialization. During the frequency modulation initialization phase, the computing device needs to construct two formulas: a real-time performance change formula and a performance loss change formula. The frequency modulation initialization process of the computing device during the initialization phase is described in detail below.

[0066] First, the formula for real-time performance change of the computing device during the initialization phase in the embodiments of this application is introduced.

[0067] In the process of constructing real-time performance change formulas, computing devices periodically collect monitoring data during processor operation. This monitoring data can be called historical monitoring data. The monitoring data collected by the computing device includes one or more events monitored by the Performance Monitoring Unit (PMU), also known as PMU events. PMU events include instruction execution count, cache hit rate, and branch prediction error rate. Instruction execution count refers to the number of instructions actually executed by the processor during execution, reflecting the processor's execution efficiency and performance. Cache hit rate refers to the proportion of data or instructions successfully fetched from the cache, reflecting the processor's cache utilization. Branch prediction error rate refers to the accuracy of predicting whether to execute a branch when it exists in the program, also reflecting the processor's execution efficiency.

[0068] During the data acquisition and monitoring process, the computing device can set the CPU's clock speed to a fixed value and record the correspondence between the CPU's frequency, processor performance values, and PMU events during task execution over a period of time. Afterward, the computing device readjusts the CPU's clock speed and continues to record the correspondence between the CPU's frequency, processor performance values, and PMU events during task execution over a further period.

[0069] By repeating the above data acquisition process, the computing device can obtain multiple sets of data relating frequency, processor performance values, and PMU events. This data can form a PMU event set. The processor performance values ​​can include throughput, execution time, traffic volume, latency, etc., without specific limitations.

[0070] Once a computing device can acquire multiple sets of correlation data between frequency, processor performance values, and PMU events, it analyzes this data using a correlation coefficient analysis algorithm to identify one or more PMU events whose correlation with the processor's current performance change rate is higher than a threshold. The current performance change rate refers to the ratio of the processor's performance value at the previous moment to its current moment. These PMU events can form an event set used to fit a formula for real-time performance change. Examples of correlation coefficient analysis algorithms include Pearson correlation coefficient analysis and Spearman correlation coefficient analysis.

[0071] After acquiring the event set of PMU events, the computing device fits a regression model to determine the relationship between the processor's current performance change rate and the PMU events in the event set. The regression model can be linear regression, logistic regression, multinomial regression, etc. This relationship is the real-time performance change formula, which satisfies the following formula:

[0072] , ; (1)

[0073] in, This represents the current rate of change in processor performance. For the PMU incident, The coefficients for PMU events are obtained based on a regression model fit.

[0074] In one possible implementation, the computing device acquires historical monitoring data, which includes one or more events monitored by the processor's performance monitoring unit (PMU) at different frequencies. Based on the historical monitoring data, the computing device establishes a correlation between the processor performance loss rate and the frequency change rate. This correlation includes a blocking coefficient, which indicates the weight by which the processor performance value is affected by the frequency.

[0075] Second, this application introduces the formula for performance loss variation in the computing device during the initialization phase in the embodiments of this application.

[0076] The performance loss rate during the process of constructing the performance loss change formula for computing devices It can be done and The ratio represents, where, Indicates the maximum frequency The corresponding performance values, Indicates the current frequency The corresponding performance values. and The ratio can also be expressed as the inverse ratio of execution time, i.e. and The ratio, where, Current frequency The execution time below, Indicates the maximum frequency The execution time. Therefore, the formula for performance loss change satisfies the following formula:

[0077] (2)

[0078] in, It can be the inverse of the real-time performance changes of the task, that is... .

[0079] In this embodiment, the processor performance loss can also be expressed as a factor related to the blocking coefficient. The relevant formulas. Among them, the blocking coefficient... The blocking coefficient represents the weight by which the processor's actual performance is directly affected by frequency modulation. The value is between (0, 1). Blocking coefficient. The larger the value, the greater the impact of frequency on actual performance. Blocking coefficient The smaller the value, the less the processor's actual performance is affected by frequency modulation. Processor performance loss and blocking coefficient. Satisfy the following formula:

[0080] (3)

[0081] Please see Figure 3 , Figure 3 This is a flowchart illustrating another adaptive frequency modulation method provided in an embodiment of this application. Figure 3 In steps a to b of the example shown, during the initialization phase of adaptive frequency modulation, the computing device needs to construct a real-time performance change formula and a performance loss formula based on historical monitoring data. The real-time performance change formula is used to indicate the relationship between processor performance values ​​and PMU events, and the performance loss change formula is used to indicate the calculation formula for the performance loss rate.

[0082] Please see Figure 4 , Figure 4 This is a schematic flowchart illustrating an adaptive frequency modulation method provided in an embodiment of this application. Figure 4 In steps a to b of the illustrated embodiment, during the initialization phase of adaptive frequency modulation, the computing device needs to analyze the collected historical monitoring data to determine the PMU events related to the current performance change rate of the processor. The computing device uses these PMU events and the corresponding current performance change rate of the processor to fit a relationship between the current performance change rate and the PMU events. During the initialization phase of adaptive frequency modulation, the computing device can calculate the current performance change rate of the processor based on this relationship between performance values ​​and PMU events.

[0083] The above describes the initialization work of the computing device before frequency modulation in the embodiments of this application. The following describes the frequency modulation operation stage of the computing device.

[0084] During the frequency modulation operation phase, the computing device collects real-time monitoring data from the processor. This data includes one or more events monitored by the processor's Performance Monitoring Unit (PMU), such as instruction execution count, cache hit rate, and branch prediction error rate. The real-time monitoring data collected by the computing device can be PMU events at different times and frequencies. For example, the real-time monitoring data could be the PMU events at the current time (now) and the PMU events at the previous time (pre).

[0085] In one possible implementation, the real-time monitoring data collected by the computing device, in addition to PMU events, can also be events collected by the architectural performance monitoring unit (AMU), which can be referred to as AMU events. Furthermore, real-time monitoring data can also be CPU utilization or other scenario-related performance metrics, such as transactions per second (TPS) in a database scenario.

[0086] 202. The computing device calculates the predicted performance change rate of the processor based on real-time monitoring data. The predicted performance change rate is used to indicate the ratio of the processor's reference performance value to its operating performance value.

[0087] The computing device calculates the predicted performance change rate of the processor at different frequencies based on real-time monitoring data. This predicted performance change rate indicates the ratio of the processor's reference performance value to its operating performance value. The reference performance value is the performance value corresponding to the processor's maximum frequency, while the operating performance value is the performance value corresponding to the current frequency.

[0088] Specifically, the computing device can calculate the current performance change rate based on the aforementioned real-time performance change formula, and then further calculate the predicted performance change rate based on the current performance change rate. The process of the computing device calculating the predicted performance change rate is detailed below:

[0089] In one possible implementation, during the process of calculating the predicted performance change rate of the processor at different frequencies based on real-time monitoring data, the computing device calculates the current performance change rate of the processor based on the real-time monitoring data and the performance change fitting relationship. The current performance change rate indicates the ratio of the performance value corresponding to the previous frequency to the performance value corresponding to the current frequency, wherein the performance change fitting relationship is used to indicate the correlation between the performance change rate and the monitoring data. Simultaneously, the computing device calculates the ratio of the reference frequency to the previous frequency to obtain the frequency change rate, where the reference frequency is the processor's maximum frequency. The computing device further calculates the predicted performance change rate based on the current performance change rate and the frequency change rate.

[0090] For example, the computing device collects the PMU events at the previous time "pre" and the current time "now", and calculates the PMU events based on formula (1). and The proportion. Furthermore, through the maximum frequency Frequency compared to the previous time proportion and and Proportion Calculation and The proportion. Among them, and The proportion is calculated according to the following formula.

[0091] ; (4)

[0092] 203. The computing device determines the target frequency of the processor based on the target performance loss rate and the predicted performance change rate, wherein the target performance loss rate is used to indicate the predicted performance change rate that the processor can tolerate.

[0093] After calculating the predicted rate of change in processor performance, the computing device determines the target frequency of the processor based on the target rate of performance loss. The target rate of performance loss indicates the tolerable rate of change in predicted performance for the processor. Specifically, during frequency tuning, the computing device needs to set the target rate of performance loss, which is the allowable rate of performance loss for the processor; the target rate of performance loss can also be called the performance loss threshold.

[0094] There are two methods for computing devices to determine the target frequency of a processor based on a target performance loss rate. In the first method, the computing device first calculates the blocking coefficient, and then calculates the target frequency based on the target performance loss rate and the blocking coefficient. In the second method, the computing device calculates the performance loss rate by adjusting the frequency; when the performance loss rate reaches the target performance loss rate, the target frequency can be determined. These two methods for determining the target frequency are described below:

[0095] In the first method of determining the target frequency, during the process of determining the processor's target frequency based on the target performance loss rate, the computing device calculates a blocking coefficient corresponding to real-time monitoring data based on the processor's predicted performance change rate and frequency change rate. The frequency change rate indicates the ratio of the processor's reference frequency to the current frequency. The computing device determines the target frequency based on the target performance loss rate and the blocking coefficient.

[0096] For example, when a computing device adjusts the target frequency for the next time step based on the PMU event of the previous time step *pre* and the PMU event of the current time step *now*, the computing device collects the PMU event of the previous time step *pre* and the PMU event of the current time step *now*, and calculates the target frequency based on formula (1). and After determining the proportion, the following formula (4) can be used to calculate the result. and The proportion, which is the predicted rate of change in processor performance. Based on the above formulas (2) and (3), it can be seen that... and Ratio and blocking coefficient The relationship between them satisfies the following formula:

[0097] ; (5)

[0098] Therefore, computing devices can be based on and The proportion and the maximum frequency Frequency at the current moment A blocking coefficient is obtained by proportional calculation. The original blocking coefficient is then updated. Afterwards, the computing device continues to update the data based on the blocking coefficient. and the set target performance loss rate The target frequency at the next moment is calculated. Target performance loss rate With target frequency The relationship between them satisfies the following formula:

[0099] ; (6)

[0100] The computing device is based on the target performance loss rate and blocking coefficient In determining the target frequency, the computing device can use the target performance loss rate in formula (6) as a basis. Calculated target frequency , This is the target frequency to be adjusted in the next moment.

[0101] Please continue reading. Figure 3 ,exist Figure 3 In step c of the example shown, the computing device collects real-time monitoring data during the operation phase, updates the blocking coefficient based on the real-time monitoring data, and sets the target frequency based on the updated blocking coefficient and the target performance loss rate. For example, the computing device calculates the performance value of the previous moment based on the above formula (1). and the performance value at the current moment The proportion, i.e. And based on the above formula (4), the predicted performance change rate is further calculated. Meanwhile, the blocking coefficient is calculated using the above formula (5). .

[0102] exist Figure 3 In the example shown, the computing device calculates the blocking coefficient. Then, based on the set target performance loss rate Based on the above formula (6), the target frequency can be calculated. .

[0103] Please continue reading. Figure 4 ,exist Figure 4 In steps c to e of the example, the computing device first sets the target performance loss rate, and then collects real-time monitoring data, which includes the PMU event at the previous moment and the PMU event at the current moment. The computing device calculates the current performance change rate based on the real-time monitoring data, which is the ratio of the performance value at the previous moment to the performance value at the current moment, and calculates the predicted performance change rate based on the current performance change rate, which is the ratio of the performance value at the maximum frequency to the performance value at the current moment.

[0104] exist Figure 4 In steps f to g of the example, the computing device further calculates the blocking coefficient based on the ratio of the performance value at the maximum frequency to the performance value at the current moment and the target performance loss rate. The computing device calculates the target frequency based on the blocking coefficient and sets the target frequency as the frequency at the next moment.

[0105] In the second method of determining the target frequency, during the process of determining the processor's target frequency based on the target performance loss rate, the processor frequency is increased when the predicted performance change rate of the processor is greater than the predicted performance change rate corresponding to the target performance loss rate. Conversely, the processor frequency is decreased when the predicted performance change rate of the processor is less than the predicted performance change rate corresponding to the target performance loss rate.

[0106] For example, when a computing device adjusts the target frequency for the next time step based on the PMU event of the previous time step *pre* and the PMU event of the current time step *now*, the computing device collects the PMU event of the previous time step *pre* and the PMU event of the current time step *now*, and calculates the target frequency based on formula (1). and After determining the proportion, the result is calculated based on the above formula (4). and The proportion. Due to and The ratio and performance loss satisfy the following formula:

[0107] ; (7)

[0108] Therefore, computing devices will and proportion and When comparing, and The ratio is greater than or equal to 1+ Then the computing device needs to increase the processor frequency by one level. and The proportion is less than 1+ If so, the computing device needs to reduce the processor frequency by one level to achieve adaptive adjustment of the processor frequency.

[0109] Please see Figure 5 , Figure 5 This is a schematic diagram illustrating another adaptive frequency modulation process provided in an embodiment of this application. Figure 5 In steps a to e of the example shown, after setting the target performance loss rate, the computing device also needs to calculate the current performance change rate based on real-time monitoring data, that is, the ratio of the performance value at the previous moment to the performance value at the current moment, and calculate the predicted performance change rate based on the ratio of the performance value at the previous moment to the performance value at the current moment. The specific calculation process is the same as described above. Figure 4 Steps a through e in the example shown are similar and will not be repeated here.

[0110] exist Figure 5 In steps f to h of the example shown, after the computing device calculates the predicted performance change rate corresponding to the current frequency, it calculates the performance loss rate corresponding to the current frequency based on the predicted performance change rate corresponding to the current frequency. If the performance loss corresponding to the current frequency is greater than or equal to the target performance loss rate, the computing device increases the current frequency by one level. If the performance loss corresponding to the current frequency is less than the target performance loss rate, the computing device decreases the current frequency by one level.

[0111] As can be seen from the above embodiments, in the embodiments of this application, the computing device can calculate the current performance change rate of the processor based on one or more events monitored by the processor's performance monitoring unit (PMU), and calculate the predicted performance change rate of the processor based on the current performance change rate of the processor. Furthermore, the target frequency is determined based on the target performance loss rate and the predicted performance change rate. Since the performance value of the processor can be more accurately reflected based on PMU events, the accuracy of the target frequency is improved and the power consumption of the processor is reduced.

[0112] Based on the above method embodiments, this application also provides an adaptive frequency modulation device, which is described in detail below.

[0113] Please see Figure 6, Figure 6 This is a schematic diagram of an adaptive frequency modulation device provided in an embodiment of this application. Figure 6 In the example shown, the adaptive frequency modulation device 600 is used to implement the various steps performed by the computing device in the above embodiments. The adaptive frequency modulation device 600 includes an acquisition unit 601 and a processing unit 602.

[0114] The acquisition unit 601 is used to collect real-time monitoring data of the processor. This real-time monitoring data includes one or more events monitored by the processor's performance monitoring unit (PMU). These events include one or more of the following: instruction execution count, cache hit rate, and branch prediction error rate. The processing unit 602 is used to calculate the processor's predicted performance change rate based on the real-time monitoring data. The predicted performance change rate is determined based on the processor's current performance change rate, which in turn is determined based on the real-time monitoring data. The predicted performance change rate indicates the proportion of the processor's reference performance value relative to its operating performance value. The processing unit 602 is also used to determine the processor's target frequency based on the target performance loss rate and the predicted performance change rate. The target performance loss rate indicates the tolerable predicted performance change rate for the processor.

[0115] In one possible implementation, the processing unit 602 is specifically used to calculate the current performance change rate of the processor based on real-time monitoring data and a performance change fitting relationship, wherein the performance change fitting relationship is used to indicate the correlation between the performance change rate and the monitoring data, and to calculate the predicted performance change rate based on the current performance change rate and the frequency change rate, wherein the frequency change rate is the ratio of the reference frequency to the operating frequency.

[0116] In one possible implementation, the current performance change rate is used to indicate the ratio of the performance value corresponding to the frequency at the previous moment to the performance value corresponding to the frequency at the current moment. The processing unit 602 is specifically used to calculate the frequency change rate based on the reference frequency and the frequency at the previous moment, and to calculate the predicted performance change rate based on the current performance change rate and the frequency change rate. The predicted performance change rate is used to indicate the ratio between the processor's reference performance value and the performance value corresponding to the frequency at the current moment.

[0117] In one possible implementation, the processing unit 602 is specifically used to calculate the blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and frequency change rate, and to determine the target frequency based on the target performance loss rate and the blocking coefficient.

[0118] In one possible implementation, the processing unit 602 is further configured to increase the processor frequency when the predicted performance change rate is greater than or equal to the performance change rate corresponding to the target performance loss rate, and decrease the processor frequency when the predicted performance change rate is less than the performance change rate corresponding to the target performance loss rate.

[0119] In one possible implementation, the processing unit 602 is further configured to acquire historical monitoring data, which includes one or more events monitored by the processor's performance monitoring unit (PMU) at different frequencies, and to obtain a performance change fitting relationship based on the historical monitoring data.

[0120] In one possible implementation, the processing unit 602 is further configured to establish a correlation between the performance loss rate and the frequency change rate based on historical monitoring data. The correlation includes a blocking coefficient, which is used to indicate the weight of the processor's performance value affected by the frequency.

[0121] It is understandable that the acquisition unit 601 and processing unit 602 in the adaptive frequency modulation device 600 can function as functional modules. Figure 1 The various modules in the adaptive frequency modulation system 10 are mapped to each other, thereby realizing the functions of each module in the adaptive frequency modulation system 10.

[0122] It should be understood that the division of units in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, all units in the device can be implemented entirely through software calls from processing elements; all units can be implemented entirely in hardware; or some units can be implemented through software calls from processing elements, and others in hardware. For example, each unit can be a separate processing element, or it can be integrated into a chip within the device. Alternatively, it can be stored as a program in memory, called and executed by a processing element of the device. Moreover, these units can be fully or partially integrated together, or implemented independently. The processing element mentioned here can also be called a processor, which can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each of the above units can be implemented through integrated logic circuits in the processor element or through software calls from processing elements.

[0123] It is worth noting that, for the sake of simplicity, the above method embodiments are described as a series of actions. However, those skilled in the art should know that this application is not limited to the order of the described actions. Furthermore, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by this application.

[0124] Other reasonable combinations of steps that can be conceived by those skilled in the art based on the above description also fall within the scope of protection of this application. Furthermore, those skilled in the art should also be aware that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to this application.

[0125] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Figure 7 As shown, the computing device 700 includes a processor 701, a memory 702, a communication interface 703, and a bus 704. The processor 701, memory 702, and communication interface 703 are coupled via the bus (not shown in the figure). The memory 702 stores instructions. When the instructions in the memory 702 are executed, the computing device 700 performs the method executed by the computing device in the above method embodiment.

[0126] The computing device 700 may be one or more integrated circuits configured to implement the methods described above, such as: one or more application-specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these forms of integrated circuits. Furthermore, when the units in the device can be implemented in the form of a processing element scheduler, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor capable of calling programs. Alternatively, these units may be integrated together to implement a system-on-a-chip (SOC).

[0127] The processor 701 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0128] The memory 702 can be volatile memory or non-volatile memory, or it can include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0129] The memory 702 stores executable program code, and the processor 701 executes the executable program code to implement the functions of the aforementioned units or modules, thereby realizing the adaptive frequency modulation method described above. That is, the memory 702 stores instructions for executing the adaptive frequency modulation method described above.

[0130] The communication interface 703 uses transceiver modules, such as, but not limited to, network interface cards and transceivers, to enable communication between the computing device 700 and other devices or communication networks.

[0131] In addition to the data bus, the 704 bus can also include a power bus, a control bus, and a status signal bus. The bus can be a Peripheral Component Interconnect Express (PCIe) bus, an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (Ubus or UB), a Compute Express Link (CXL) bus, a Cache Coherent Interconnect for Accelerators (CCIX) bus, etc. The bus can be divided into address bus, data bus, and control bus.

[0132] Please see Figure 8 , Figure 8 This is a schematic diagram of a chip structure provided in an embodiment of this application. Figure 8 As shown, the chip 800 includes a processing circuit 801 and a storage circuit 802. The storage circuit 802 in the chip 800 can store instructions for executing the above-described adaptive frequency modulation method. When the instructions are executed by the processing circuit, the chip executes the above-described adaptive frequency modulation method.

[0133] In another embodiment of this application, a computer-readable storage medium is also provided, which stores computer-executable instructions. When the processor of the device executes the computer-executable instructions, the device executes the method executed by the computing device in the above method embodiment.

[0134] In another embodiment of this application, a computer program product is also provided, which includes computer-executable instructions stored in a computer-readable storage medium. When the processor of the device executes the computer-executable instructions, the device performs the method executed by the computing device in the above method embodiments.

[0135] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0136] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0137] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0138] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0139] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. An adaptive frequency modulation method, characterized in that, The method includes: The processor collects real-time monitoring data, which includes one or more events, including one or more of the following: instruction execution count, cache hit rate, and branch prediction error rate; wherein the events are monitored by the processor's performance monitoring unit (PMU). The predicted performance change rate of the processor is calculated based on the real-time monitoring data. The predicted performance change rate is used to indicate the ratio of the processor's reference performance value to its operating performance value. The predicted performance change rate is determined based on the processor's current performance change rate, which is determined based on the real-time monitoring data. The target frequency of the processor is determined based on the target performance loss rate and the predicted performance change rate, wherein the target performance loss rate is used to indicate the predicted performance change rate that the processor can tolerate.

2. The method according to claim 1, characterized in that, The calculation of the predicted performance change rate of the processor based on the real-time monitoring data includes: The current performance change rate of the processor is calculated based on the real-time monitoring data and the performance change fitting relationship, which is used to indicate the correlation between the performance change rate and the monitoring data; The predicted performance change rate is calculated based on the current performance change rate and the frequency change rate, wherein the frequency change rate is the ratio of the reference frequency to the operating frequency.

3. The method according to claim 2, characterized in that, The current performance change rate is used to indicate the ratio of the performance value corresponding to the frequency at the previous time to the performance value corresponding to the frequency at the current time. Calculating the predicted performance change rate based on the current performance change rate and the frequency change rate includes: The rate of change of frequency is calculated based on the reference frequency and the frequency at the previous moment; The predicted performance change rate is calculated based on the current performance change rate and the frequency change rate. The predicted performance change rate is used to indicate the ratio between the processor's reference performance value and the performance value corresponding to the current frequency.

4. The method according to any one of claims 2 or 3, characterized in that, Determining the target frequency of the processor based on the target performance loss rate and the predicted performance change rate includes: Calculate the blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and the frequency change rate; The target frequency is determined based on the target performance loss rate and the blocking coefficient.

5. The method according to any one of claims 1 to 3, characterized in that, The method further includes: If the predicted performance change rate is greater than or equal to the performance change rate corresponding to the target performance loss rate, then the frequency of the processor is increased; If the predicted performance change rate is less than the performance change rate corresponding to the target performance loss rate, then the frequency of the processor is reduced.

6. The method according to claim 4, characterized in that, The method further includes: Acquire historical monitoring data, which includes one or more events monitored by the processor's performance monitoring unit (PMU) at different frequencies; The performance change fitting relationship is obtained by fitting the historical monitoring data.

7. The method according to claim 6, characterized in that, The method further includes: A correlation is established between the performance loss rate and the frequency change rate based on the historical monitoring data. The correlation includes the blocking coefficient, which is used to indicate the weight of the processor's performance value affected by the frequency.

8. An adaptive frequency modulation device, characterized in that, The device includes: The acquisition unit is used to collect real-time monitoring data of the processor. The real-time monitoring data includes one or more events, which include one or more of the following: instruction execution count, cache hit rate, and branch prediction error rate; wherein the events are monitored by the processor's performance monitoring unit (PMU). A processing unit is configured to calculate a predicted performance change rate of the processor based on the real-time monitoring data, wherein the predicted performance change rate is used to indicate the ratio of a reference performance value of the processor to a running performance value; wherein the predicted performance change rate is determined based on the current performance change rate of the processor, and the current performance change rate is determined based on the real-time monitoring data. The processing unit is further configured to determine the target frequency of the processor based on the target performance loss rate and the predicted performance change rate, wherein the target performance loss rate is used to indicate the tolerable predicted performance change rate of the processor.

9. The apparatus according to claim 8, characterized in that, The processing unit is specifically used for: The current performance change rate of the processor is calculated based on the real-time monitoring data and the performance change fitting relationship, which is used to indicate the correlation between the performance change rate and the monitoring data; The predicted performance change rate is calculated based on the current performance change rate and the frequency change rate, wherein the frequency change rate is the ratio of the reference frequency to the operating frequency.

10. The apparatus according to claim 9, characterized in that, The current performance change rate is used to indicate the ratio of the performance value corresponding to the frequency at the previous time to the performance value corresponding to the frequency at the current time. The processing unit is specifically used for: The rate of change of frequency is calculated based on the reference frequency and the frequency at the previous moment; The predicted performance change rate is calculated based on the current performance change rate and the frequency change rate. The predicted performance change rate is used to indicate the ratio between the processor's reference performance value and the performance value corresponding to the current frequency.

11. The apparatus according to any one of claims 9 or 10, characterized in that, The processing unit is specifically used for: Calculate the blocking coefficient corresponding to the real-time monitoring data based on the predicted performance change rate and the frequency change rate; The target frequency is determined based on the target performance loss rate and the blocking coefficient.

12. The apparatus according to any one of claims 8 to 10, characterized in that, The processing unit is also used for: If the predicted performance change rate is greater than or equal to the performance change rate corresponding to the target performance loss rate, then the frequency of the processor is increased; If the predicted performance change rate is less than the performance change rate corresponding to the target performance loss rate, then the frequency of the processor is reduced.

13. The apparatus according to claim 11, characterized in that, The processing unit is also used for: Acquire historical monitoring data, which includes one or more events monitored by the processor's performance monitoring unit (PMU) at different frequencies; The performance change fitting relationship is obtained by fitting the historical monitoring data.

14. The apparatus according to claim 13, characterized in that, The processing unit is also used for: A correlation is established between the performance loss rate and the frequency change rate based on the historical monitoring data. The correlation includes the blocking coefficient, which is used to indicate the weight of the processor's performance value affected by the frequency.

15. A computing device, characterized in that, The device includes a processor coupled to a memory for storing instructions which, when executed by the processor, cause the computing device to perform the method of any one of claims 1 to 7.

16. A chip, characterized in that, The device includes a processing circuit coupled to a storage circuit for storing instructions which, when executed by the processing circuit, cause the chip to perform the method of any one of claims 1 to 7.

17. A computer-readable storage medium having instructions stored thereon, characterized in that, When the instructions are executed, they cause the computer to perform the method of any one of claims 1 to 7.

18. A computer program product, the computer program product comprising instructions, characterized in that, When the instructions are executed, they cause the computer to perform the method of any one of claims 1 to 7.

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