Memory processing system, method and device, medium and program product

Abstract

The invention discloses a memory processing system, method and device, a medium and a program product in the technical field of computers. In the application, the plurality of memory devices are used as extended memories of the plurality of computing devices in the host. The switching devices are connected between the computing devices and the memory devices and can determine the memory devices connected with downstream ports, record corresponding memory connection relations and send the memory connection relations to a main management controller in a host; when any computing device reads and writes the memory abnormally, the main management controller locates the abnormal memory device based on all the received memory connection relationships, and sends a hot removal command to the switching device connected with the abnormal memory device through the network device, so that the corresponding switching device responds to the hot removal command and performs hot removal on the abnormal memory device. Therefore, global memory connection topology identification, fault detection and hot removal are realized for the memory device, and normal operation of host services is not affected.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and particularly to a memory processing system, method, device, medium, and program product. Background Art

[0002] Currently, a memory resource pool serves as the extended memory of a host. When a faulty memory appears in the memory resource pool, it is necessary for the operation and maintenance personnel to manually power off the host and power down the corresponding memory module. This process requires manual operation by personnel, increasing the maintenance time and cost, and also affecting the host services.

[0003] Therefore, how to handle faulty memory without affecting the host services is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a memory processing system, method, device, medium, and program product to handle faulty memory without affecting the host services. [[ID=...]]

[0005] In a first aspect, this application provides a memory processing system, including: a host, multiple switching devices, and multiple memory devices; the host, multiple switching devices, and multiple memory devices are all connected to a network device; the host includes: a main management controller and multiple computing devices connected to the main management controller; the multiple computing devices are connected to the multiple memory devices through the multiple switching devices to achieve memory expansion of the multiple computing devices; the multiple switching devices are configured to: record the currently managed memory connection relationships and send the memory connection relationships to the main management controller; the main management controller is configured to: when any computing device has an abnormal memory read or write, locate the abnormal memory device based on the received memory connection relationships, and send a hot removal command to the switching device connected to the abnormal memory device through the network device; the switching device is configured to: in response to the hot removal command, perform hot removal on the abnormal memory device.

[0006] In a second aspect, this application provides a memory processing method applied to a memory processing system, where the memory processing system includes: a host, multiple switching devices, and multiple memory devices; the host, multiple switching devices, and multiple memory devices are all connected to a network device; the host includes: a main management controller and multiple computing devices connected to the main management controller; the multiple computing devices are connected to the multiple memory devices through the multiple switching devices to achieve memory expansion of the multiple computing devices; the memory processing method includes: the multiple switching devices are configured to: record the currently managed memory connection relationships and send the memory connection relationships to the main management controller; the main management controller is configured to: when any computing device has an abnormal memory read or write, locate the abnormal memory device based on the received memory connection relationships, and send a hot removal command to the switching device connected to the abnormal memory device through the network device; the switching device responds to the hot removal command and performs hot removal on the abnormal memory device.

[0007] In a third aspect, the present application provides an electronic device, including: a memory for storing a computer program; a processor for executing the computer program to implement the memory processing method disclosed above.

[0008] In a fourth aspect, the present application provides a non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the memory processing method disclosed above.

[0009] In a fifth aspect, the present application provides a computer program product including computer program / instructions, which, when executed by a processor, implement the steps of the memory processing method disclosed above.

[0010] As can be seen from the above solutions, the present application provides a memory processing system, including: a host, a plurality of switching devices, and a plurality of memory devices; the host, the plurality of switching devices, and the plurality of memory devices are all connected to a network device; the host includes: a main management controller and a plurality of computing devices connected to the main management controller; the plurality of computing devices are connected to the plurality of memory devices through the plurality of switching devices to achieve memory expansion of the plurality of computing devices; the plurality of switching devices are configured to: record the currently managed memory connection relationship and send the memory connection relationship to the main management controller; the main management controller is configured to: when any computing device has an abnormal memory read / write, locate the abnormal memory device based on the received memory connection relationship, and send a hot removal command to the switching device connected to the abnormal memory device through the network device; the switching device is configured to: in response to the hot removal command, perform hot removal on the abnormal memory device.

[0011] It can be seen that the beneficial effects of the present application are as follows: a plurality of memory devices serve as extended memories for a plurality of computing devices in the host. The plurality of switching devices connected between the plurality of computing devices and the plurality of memory devices can determine the memory devices connected to their downstream ports, record the corresponding memory connection relationships, and send the memory connection relationships to the main management controller in the host; when any computing device has an abnormal memory read / write, the main management controller in the host locates the abnormal memory device based on all the received memory connection relationships, and sends a hot removal command to the switching device connected to the abnormal memory device through the network device, so that the corresponding switching device performs hot removal on the abnormal memory device in response to the hot removal command. Thus, the main management controller in the host automatically locates the abnormal memory device based on the global memory connection relationship, realizes global memory connection topology recognition and fault detection for the memory device, and also realizes hot removal of the abnormal memory device without powering off the host, without affecting the normal operation of the host service.

[0012] Correspondingly, a memory processing method, device, medium, and program product provided by the present application also have the above technical effects. Description of the Drawings

[0013] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.

[0014] Figure 1 Schematic diagram of a memory processing system disclosed in the present application; Figure 2 Another schematic diagram of a memory processing system disclosed in the present application; Figure 3 Flowchart of a memory processing method disclosed in the present application; Figure 4 Another schematic diagram of a memory processing system disclosed in the present application; Figure 5 Schematic diagram of an electronic device disclosed in the present application; Figure 6 Structure diagram of a server provided by the present application; Figure 7 Structure diagram of a terminal provided by the present application. Detailed implementation manners

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0016] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0017] To enable those skilled in the art of the present technology to better understand the solution of the present application, the following will further elaborate on the present application in conjunction with the drawings and specific implementation manners.

[0018] Currently, the memory resource pool serves as the extended memory of the host. When there is faulty memory in the memory resource pool, it is necessary for the operation and maintenance personnel to manually power off the host and power down the corresponding memory module. This process requires manual operation by personnel, increasing the maintenance time and cost, and also affecting the host services. Therefore, this application provides a memory processing solution that can handle faulty memory without affecting the host services.

[0019] See Figure 1 As shown, an embodiment of this application discloses a memory processing system, including: a host, multiple switching devices, and multiple memory devices; the host, multiple switching devices, and multiple memory devices are all connected to a network device; the host includes: a main management controller and multiple computing devices (such as GPUs) connected to the main management controller; the multiple computing devices are connected to the multiple memory devices through the multiple switching devices to achieve memory expansion of the multiple computing devices. The multiple computing devices share the multiple memory devices. There can be multiple hosts.

[0020] Among them, the multiple switching devices are used to: record the currently managed memory connection relationships and send the memory connection relationships to the main management controller. Specifically, the switching device determines the memory devices connected to its downstream ports, records the corresponding memory connection relationships, and sends the memory connection relationships to the main management controller.

[0021] The main management controller is used to: when any computing device reads or writes memory abnormally, locate the faulty memory device based on the received memory connection relationships, and send a hot removal command to the switching device connected to the faulty memory device through the network device. Specifically, the main management controller constructs a global memory topology map based on the received memory connection relationships. When any computing device reads or writes memory abnormally, it locates the faulty memory device based on the global memory topology map and sends a hot removal command to the switching device connected to the faulty memory device through the network device.

[0022] The switching device is used to: in response to the hot removal command, perform hot removal on the faulty memory device.

[0023] It should be noted that the host may include: a host processor, a main management controller, and multiple computing devices; the host processor is respectively connected to the main management controller and the multiple computing devices. Each switching device includes: a switching processor, a switching management controller, and a switching connector (i.e., a Switch chip); the switching processor is respectively connected to the switching management controller and the switching connector. Each memory device includes: a memory management controller and multiple memory devices, and each memory device includes a controller MXC (Memory Expander Controller) and multiple memory modules. Among them, the main management controller, the switching management controller, and the memory management controller may all be BMCs (Baseboard Management Controllers), and these three can communicate through a network device (such as a network switch); moreover, the host, the multiple switching devices, and the multiple memory devices are connected through the cache coherence protocol CXL (Compute ExpressLink).

[0024] In one implementation, any switching device includes: a switching processor, a switching management controller, and a switching connector; the switching processor is connected to the switching management controller and the switching connector; the switching processor is configured to: perform connection configuration for the downstream ports of the switching connector and transmit the corresponding connection configuration information to the switching management controller; the switching management controller is configured to: determine the memory devices connected to the downstream ports of its own switching device based on the connection configuration information and record the memory connection relationship; in response to the topology acquisition command sent by the main management controller, send the memory connection relationship to the main management controller. Thus, the host can collect the connection relationships between all downstream devices to construct a global memory topology map.

[0025] In one implementation, the host further includes: a host processor; the host processor is connected to the main management controller and multiple computing devices; the host processor is configured to: use the basic input / output system to detect whether there are read / write memory exceptions in the multiple computing devices; if any read / write memory exception is detected in a computing device, determine the device identification information (such as BDF) and the silk screen information of the abnormal memory device, and send the device identification information and the silk screen information to the main management controller; the main management controller is configured to: locate the abnormal memory device in the global memory topology map based on the device identification information and the silk screen information. BDF (Bus Device Function) includes: bus number, device number, and function number, and is used to uniquely identify a memory device.

[0026] It should be noted that the global memory topology graph records relevant information such as the host ports to which the computing devices are connected, the device information of the computing devices, the upstream and downstream ports of the switching devices, and the memory devices connected to the downstream ports. That is to say: The global memory topology graph records all the connection paths from the host ports to the most downstream memory devices and the identification information of each device associated with the connection path. In one implementation, the main management controller is used to: query the upstream port and the corresponding downstream port of the switching device corresponding to the device identification information and the silk screen information in the global memory topology graph to locate the abnormal memory device.

[0027] To achieve hot removal of the memory device, in one implementation, the switching processor is used to: in response to a hot removal command, configure the current switching device port to which the abnormal memory device is connected to a releasable state; correspondingly, the switching connector is used to: if it detects the releasable state of any downstream port in the current switching device, send a corresponding interrupt notification signal to the switching processor so that the switching processor feeds back a port successfully released message to the switching management controller; the switching management controller is used to: feed back the port successfully released message to the main management controller; the main management controller is used to: send an alarm message to the abnormal memory device through the network device to power down the abnormal memory device. Among them, the switching processor is used to: in response to a hot removal command, configure the current switching device port to which the abnormal memory device is connected to a releasable state by configuring the address routing register and the upstream and downstream port configuration registers in the current switching device.

[0028] In one implementation, the memory management controller in any memory device is used to: after receiving the alarm message sent by the main management controller, power down the memory device corresponding to the alarm message (that is, the current memory device). After detecting a new memory device, send an access message to the main management controller; the main management controller is used to: in response to the access message, send an access command to the switching device to which the new memory device is connected so that the switching device connects to the new memory device.

[0029] To achieve real-time updates of the global memory topology map, any switching device is used to: update the currently managed memory connection relationship accordingly after connecting to a new memory device, and send the updated memory connection relationship to the main management controller, and the main management controller updates the global memory topology map based on the received memory connection relationship. In one implementation, the switching connector is used to: send an access interrupt message to the switching processor after detecting a new memory device; the switching processor is used to: in response to the access interrupt message, identify the new memory device using the downstream port corresponding to the new memory device in the current switching device, and configure the downstream port of the current switching device to which the new memory device is connected to an available state by configuring the address routing register and the upstream and downstream port configuration registers in the current switching device. Among them, the switching processor is used to: send the available state of the new memory device to the switching management controller; the switching management controller is used to: feedback the available state of the new memory device to the main management controller.

[0030] In one implementation, the memory management controller is used to: collect the operation status information of the memory devices in the memory device to which it belongs, and send the operation status information to the main management controller. For example: the memory management controller collects information such as the read / write frequency and temperature of the memory devices, memory modules, or MXC under its jurisdiction as the operation status information. Accordingly, the main management controller is used to: detect whether there is an abnormal memory device based on the received operation status information; among them, if any memory device, memory module, or MXC in a memory device fails, it can be considered that the memory device fails; of course, the power-on and power-off management of each memory device in a memory device can also be performed in a fine-grained manner. Among them, any memory device includes: multiple memory devices; the memory management controller in the current memory device is connected to multiple memory devices.

[0031] It can be seen that in this embodiment, multiple memory devices serve as the extended memory of multiple computing devices in the host. Multiple switching devices connected between multiple computing devices and multiple memory devices can determine the memory devices connected to their downstream ports, record the corresponding memory connection relationships, and send the memory connection relationships to the main management controller in the host; the main management controller constructs a global memory topology map based on the received memory connection relationships, and when any computing device reads and writes memory abnormally, locates the abnormal memory device based on the global memory topology map, and sends a hot removal command to the switching device connected to the abnormal memory device through the network device, so that the corresponding switching device responds to the hot removal command and performs hot removal on the abnormal memory device. Thus, the main management controller in the host automatically locates the abnormal memory device based on the global memory topology map, realizes topology recognition and fault detection for the memory device, and also realizes hot removal of the abnormal memory device without powering off the host, without affecting the normal operation of the host service.

[0032] Please refer to Figure 2, a memory processing architecture includes: a host node, a CXL Switch Box node (i.e., a switching device), and a memory node (i.e., a memory device); the memory node includes multiple memory devices (i.e., multiple memory modules), and each memory device includes: an MXC and multiple memory strips; the CXL Switch Box node includes: a BMC, an mCPU, and a CXL Switch chip. The BMCs in different nodes are interconnected through a network switch. In this processing architecture, the memory node serves as the extended memory of the GPU, and the BMC in the host maintains and manages all GPUs used by this machine and their downstream memory devices to achieve memory fault control.

[0033] In the CXL memory node, the MXC is a memory controller, which is connected to the CXL memory module (i.e., the memory device supporting CXL) through DDR (Double Data Rate, double data rate synchronous dynamic random access memory) and SMBus (System Management Bus, system management bus), and is used to monitor and manage the CXL memory module. The CXL bus of the CXL memory module is connected to the CXL Switch node. The CXL memory module is connected to the MXC through the SMBus, and the MXC monitors and manages the CXL memory module. Specifically, the BMC is connected to the memory controller MXC through the SMBus, and interacts with the MXC through the SMBus protocol to obtain sensor information such as the temperature information, voltage information, and power consumption information of the memory, which can be used as its operating status information; it can also poll and monitor whether this information is within the permitted range, and if it exceeds the threshold, a fault report will be made, and the abnormal memory device will be confirmed accordingly. Specifically, the BMC interacts with the MXC through the MCTP over SMBus (Management Component Transport Protocol over SMBus, management component transport protocol over SMBus) protocol to poll and obtain the MailboxEvent Record information during the memory operation. If there are serious or fatal log alarms in it, a fault report will be made, that is: send a Redfish command to the BMC in the CXL Switch Box node. Specific abnormal types include: General Media Event Record, DRAM Event Record, Memory Module Event Record, Physical Switch Event, Record, Virtual Switch Event Record, MLD Port Event Record, and Dynamic Capacity EventRecord, etc.

[0034] In the CXL Switch Box node, the switching processor mCPU (management CPU, memory resource management CPU) controls the CXL Switch connector CXL SWITCH chip to perform CXL memory resource management configuration. The switch management controller BMC is connected to the mCPU through LPC and interacts with the mCPU to obtain and configure memory resource allocation information and memory slice configuration information.

[0035] In the host node, the BIOS runs on the host processor CPU. The CPU is connected to the downstream GPU computing device through PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard). The host management controller BMC is connected to the CPU through LPC (Low Pin Count, a parallel bus protocol) or ESPI (Enhanced Serial Peripheral Interface) to enable information interaction between the BMC and the BIOS (Basic Input Output System) and implement the reporting of GPU memory fault exceptions recognized by the BIOS. Specifically, the BIOS sends IPMI (Intelligent Platform Management Interface, a standard for Intel architecture) commands to the BMC through the LPC or ESPI bus for interaction. After the host is powered on, the BIOS identifies whether a PCIe exception alarm is triggered in the local GPU and sends an IPMI command to the BMC. After the BMC recognizes the GPU exception, it parses the fault GPU silk screen information corresponding to the exception, accesses the abnormal GPU through the SMBus or PCIe link, grabs the GPU register, and analyzes whether there is a memory read / write exception in the southbound interface.

[0036] Please refer to Figure 3, in a single-host scenario, after the system boots up, the mCPUs in each CXL Switch Box node configure the upstream and downstream ports and the memory address space routing of the CXL Switch chip through I2C (Inter-Integrated Circuit, a bus used to connect microcontrollers and their peripheral devices) and PCIe links, and send IPMI commands through the LPC link to transfer the port topology relationship of the current CXL Switch Box node to the BMC of the CXL Switch Box node. The BMC of the host node sends protocol commands such as Redfish or IPMI to each CXL Switch Box node through the network to obtain the port topology relationship (i.e., the corresponding memory connection relationship) of each CXL Switch Box node, and stores it to construct a global memory topology map. The connection between the southbound port of the GPU and the ports of each CXL Switch is a hardware cable connection. During the operation of the host node, when a read / write exception fault occurs in the CXL extended memory used by the GPU, the host BIOS recognizes the abnormal read / write of the GPU device memory and reports the BDF information of the abnormal GPU and the silk screen information in the host node to the BMC of the host node. The BMC of the host node finds the monitoring configuration of the corresponding GPU device according to the obtained silk screen information of the abnormal GPU, and then obtains the log register information of the abnormal GPU through the I2C or PCIe physical link, parses to obtain which southbound port of this GPU has a memory read / write exception, and then according to the hardware cable connection relationship, correspondingly finds which port of which CXL Switch Box node the southbound port of the GPU is connected to, so as to locate which downstream port the CXL memory module corresponding to the port of this CXL Switch Box node is in, and then confirm which memory node this CXL memory module is in, completing the fault memory location. After that, the BMC of the host node sends Redfish or IPMI commands to the BMC of the corresponding CXL Switch Box node, so that the BMC notifies the mCPU to trigger the thermal removal process of the faulty memory module. The memory management software in the mCPU notifies the CXL Switch chip to trigger the thermal removal operation of the corresponding memory module through the I2C or PCIe link. Specifically, the memory management software in the mCPU configures the address routing register and the upstream and downstream port configuration registers of the CXL Switch chip through I2C instructions, configures the memory device of the corresponding memory DSP port as Unbind, and then the maintenance personnel can perform the thermal removal operation. After the thermal removal, the CXL Switch chip sends an MSI interrupt event to the mCPU to notify the mCPU management software that the abnormal memory has been removed.It can be seen that in this embodiment, each CXL memory module in a single memory device can be independently managed. These CXL memory modules have their corresponding connection ports in the CXL SwitchBox node. Each CXL memory module in the same memory device can respectively implement power-on and power-off management, achieving more precise fine-grained memory management.

[0037] Furthermore, the BMC of the host node sends a memory exception alarm to the BMC of the abnormal memory node. Then, the BMC reports the memory fault alarm to the maintenance personnel and controls the power-off process of the abnormal memory module. After the maintenance personnel repair or replace the faulty memory, the memory module is re-inserted and powered on to trigger the faulty memory recovery process. Among them, after the faulty memory is repaired or replaced, the BMC of the host node sends Redfish or IPMI commands to the BMC of the corresponding CXL Switch Box node, and then informs the corresponding mCPU to trigger the hot plug-in process for the faulty memory module. The memory management software in the mCPU uses the I2C or PCIe link to inform the CXL Switch chip to trigger the controlled hot plug-in operation of the corresponding memory module, completing the reconnection of the faulty memory.

[0038] For the memory exception identified by the MXC monitored by the BMC of the memory node, the BMC of this node sends the exception information to the BMC of the host node through the network. The BMC of the host node determines whether this memory is the extended memory of the local GPU according to the port topology relationship of each CXL Switch Box node. If so, it triggers the hot removal operation of this memory module. After the maintenance personnel replace and repair the abnormal memory module, the hot plug-in operation is triggered again.

[0039] For a multi-host scenario, after the entire system is powered on, the mCPUs of each CXL Switch Box node configure the upstream and downstream port configurations and memory address space routing configurations of the CXL Switch through I2C and PCIe links, and send IPMI commands through the LPC link to transfer the current CXL Switch node port topology relationship to the BMC of the CXL Switch Box node. Under this system, the GPUs of each host node can share memory resources. Therefore, the BMC of each host node needs to send protocol commands such as Redfish or IPMI to each CXL Switch Box node through the network to obtain the CXL Switch node port topology relationship configuration information of each CXL Switch Box node, and store them separately. When a memory failure of the GPU expansion of a single host node is triggered, it is processed according to the aforementioned single-host scenario. Since the GPUs of the host nodes can share this memory, all Hosts using this faulty memory will no longer be able to use this memory resource after performing the memory hot removal process. For memory anomalies identified by the memory node BMC monitoring the MXC, the memory node BMC sends the anomaly information to the BMCs of each host node through the network. Each host node BMC determines whether this memory is used by the GPU expansion memory of this host according to the CXL Switch Box node port topology relationship information. If so, it triggers the hot removal operation of this memory module. After the maintenance personnel replace and repair the faulty memory module, the hot insertion operation is triggered again. If the BMC of the CXL Switch Box node receives repeated hot removal and hot insertion operations for the same memory module, only one operation is performed.

[0040] Please refer to Figure 4 , if there are two hosts, with 4 GPUs under each host, and these 8 GPUs are all connected to 6 CXL Switch Box nodes, thus connecting to the memory pool. The memory pool includes multiple memory nodes. In this architecture, the network is used for the overall system management between the hosts, CXL Switch Box nodes, and memory pool, realizing the construction of the overall system topology. The host BMC, as the management center, is responsible for monitoring and collecting all memory devices participating in the use, and at the same time integrating the memory topology relationship, which can achieve accurate location and hot plug of faulty memory, and can also remove the corresponding abnormal memory module from the topology to ensure the continuity of the host service; minimize the possibility of data loss, protect the integrity and availability of important data assets; different GPUs share all memory, giving full play to the computing power of the GPUs, optimizing the performance of the entire system, and improving the utilization rate of memory resources.

[0041] Next, a memory processing method provided by an embodiment of the present application will be introduced. The memory processing method described below can be referred to each other with other embodiments described in this article.

[0042] An embodiment of the present application discloses a memory processing method, which is applied to a memory processing system. The memory processing system includes: a host, multiple switching devices, and multiple memory devices; the host, multiple switching devices, and multiple memory devices are all connected to a network device; the host includes: a main management controller and multiple computing devices connected to the main management controller; the multiple computing devices are connected to the multiple memory devices through the multiple switching devices to implement memory expansion of the multiple computing devices.

[0043] Specifically, the memory processing method provided by the embodiment of the present application includes: the multiple switching devices determine the memory devices connected to their downstream ports, record the corresponding memory connection relationships, and send the memory connection relationships to the main management controller; the main management controller constructs a global memory topology map based on the received memory connection relationships, and when any computing device has an abnormal memory read or write, locates the abnormal memory device based on the global memory topology map, and sends a hot removal command to the switching device connected to the abnormal memory device through the network device; the switching device responds to the hot removal command and performs hot removal on the abnormal memory device.

[0044] In one embodiment, any switching device includes: a switching processor, a switching management controller, and a switching connector; the switching processor is connected to the switching management controller and the switching connector; the switching processor is used for: configuring the connection of the downstream port of the switching connector, and transmitting the corresponding connection configuration information to the switching management controller; the switching management controller is used for: determining the memory devices connected to the downstream ports of its own switching device based on the connection configuration information, and recording the memory connection relationships; in response to the topology acquisition command sent by the main management controller, sending the memory connection relationships to the main management controller.

[0045] In one embodiment, the host further includes: a host processor; the host processor is connected to the main management controller and the multiple computing devices; the host processor is used for: detecting whether there is an abnormal memory read or write in the multiple computing devices by using the basic input / output system; if it is detected that any computing device has an abnormal memory read or write, determining the device identification information and the silk screen information of the abnormal memory device, and sending the device identification information and the silk screen information to the main management controller; the main management controller is used for: locating the abnormal memory device in the global memory topology map based on the device identification information and the silk screen information.

[0046] In one embodiment, the main management controller is used for: querying the upstream port and the corresponding downstream port of the switching device corresponding to the device identification information and the silk screen information in the global memory topology map to locate the abnormal memory device.

[0047] In one embodiment, the switching processor is configured to: in response to a thermal removal command, configure the current switching device port connected to the abnormal memory device to a releasable state; correspondingly, the switching connector is configured to: if it detects the releasable state of any downstream port in the current switching device, send a corresponding interrupt notification signal to the switching processor, so that the switching processor feeds back a port successfully released message to the switching management controller; the switching management controller is configured to: feed back the port successfully released message to the main management controller; the main management controller is configured to: send an alarm message to the abnormal memory device through a network device to power down the abnormal memory device.

[0048] In one embodiment, the switching processor is configured to: in response to a thermal removal command, configure the current switching device port connected to the abnormal memory device to a releasable state by configuring the address routing register and the upstream and downstream port configuration registers in the current switching device.

[0049] In one embodiment, the memory management controller in any memory device is configured to: after receiving the alarm message sent by the main management controller, power down the memory device corresponding to the alarm message.

[0050] In one embodiment, the memory management controller is configured to: after detecting a new memory device, send an access message to the main management controller; the main management controller is configured to: in response to the access message, send an access command to the switching device connected to the new memory device, so that the switching device connects to the new memory device.

[0051] In one embodiment, any switching device is configured to: after connecting to a new memory device, correspondingly update the currently managed memory connection relationship.

[0052] In one embodiment, the memory management controller is configured to: collect the operating status information of the memory device to which it belongs and send the operating status information to the main management controller.

[0053] In one embodiment, the main management controller is configured to: detect whether there is an abnormal memory device according to the received operating status information.

[0054] In one embodiment, the switching connector is configured to: after detecting a new memory device, send an access interrupt message to the switching processor; the switching processor is configured to: in response to the access interrupt message, identify the new memory device by using the downstream port corresponding to the new memory device in the current switching device, and configure the downstream port of the current switching device connected to the new memory device to an available state by configuring the address routing register and the upstream and downstream port configuration registers in the current switching device.

[0055] In one embodiment, the switching processor is configured to: send the available status of the new memory device to the switching management controller; the switching management controller is configured to: feedback the available status of the new memory device to the main management controller.

[0056] In one embodiment, any memory device includes: a plurality of memory devices; the memory management controller in the current memory device is connected to the plurality of memory devices.

[0057] In one embodiment, the plurality of computing devices, the plurality of switching devices, and the plurality of memory devices are connected through a cache coherence protocol.

[0058] In one embodiment, the plurality of computing devices share the plurality of memory devices.

[0059] Wherein, for the more specific working processes of each module and unit in this embodiment, reference may be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated herein.

[0060] It can be seen that this embodiment can locate the abnormal memory device based on the global memory topology map when any computing device reads and writes memory abnormally, and perform hot removal on the abnormal memory device. Thus, topology identification, fault detection, and hot removal of the memory device are achieved, without affecting the normal operation of the host service.

[0061] Next, an electronic device provided by an embodiment of the present application will be introduced. The electronic device described below can be referred to in mutual reference with other embodiments described herein.

[0062] See Figure 5 As shown, an embodiment of the present application discloses an electronic device, including:

[0063] A memory 501, configured to store a computer program;

[0064] A processor 502, configured to execute the computer program to implement the method disclosed in any of the foregoing embodiments.

[0065] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: determine the memory device connected to the downstream port of the switching device, record the corresponding memory connection relationship, and send the memory connection relationship to the main management controller.

[0066] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: construct a global memory topology map based on the received memory connection relationship, when any computing device reads and writes memory abnormally, locate the abnormal memory device based on the global memory topology map, and send a hot removal command to the switching device connected to the abnormal memory device through the network device.

[0067] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: in response to a thermal removal command, perform thermal removal on an abnormal memory device.

[0068] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: perform connection configuration on the downstream ports of the switching connector, and transmit the corresponding connection configuration information to the switching management controller.

[0069] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: determine the memory device connected to the downstream port of the switching device based on the connection configuration information, and record the memory connection relationship; in response to the topology acquisition command sent by the main management controller, send the memory connection relationship to the main management controller.

[0070] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: use the basic input / output system to detect whether there are read / write memory anomalies in multiple computing devices; if any read / write memory anomaly of a computing device is detected, determine the device identification information and silk screen information of the abnormal memory device, and send the device identification information and silk screen information to the main management controller.

[0071] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: locate the abnormal memory device in the global memory topology diagram based on the device identification information and silk screen information.

[0072] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: in the global memory topology diagram, query the upstream port and the corresponding downstream port of the switching device corresponding to the device identification information and silk screen information to locate the abnormal memory device.

[0073] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: if the releasable state of any downstream port in the current switching device is detected, send a corresponding interrupt notification signal to the switching processor, so that the switching processor feeds back a port successfully released message to the switching management controller.

[0074] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: feed back the port successfully released message to the main management controller.

[0075] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: sending an alarm message to the abnormal memory device through a network device to power down the abnormal memory device.

[0076] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: in response to a thermal removal command, by configuring the address routing register and the uplink / downlink port configuration register in the current switching device, configuring the current switching device port connected to the abnormal memory device to a releasable state.

[0077] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: after receiving the alarm message sent by the main management controller, power down the memory device corresponding to the alarm message.

[0078] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: after detecting a new memory device, sending an access message to the main management controller.

[0079] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: in response to the access message, sending an access command to the switching device connected to the new memory device so that the switching device connects to the new memory device.

[0080] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: after connecting to the new memory device, correspondingly updating the currently managed memory connection relationship.

[0081] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: collecting the operating status information of the memory device and sending the operating status information to the main management controller.

[0082] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: detecting whether there is an abnormal memory device according to the received operating status information.

[0083] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: after detecting a new memory device, sending an access interrupt message to the switching processor.

[0084] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: in response to an access interruption message, identify the new memory device using the downstream port corresponding to the new memory device in the current switching device, and configure the address routing register and the upstream and downstream port configuration registers in the current switching device to configure the downstream port of the current switching device to which the new memory device is connected to an available state.

[0085] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: send the available state of the new memory device to the switching management controller.

[0086] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: feedback the available state of the new memory device to the main management controller.

[0087] Further, an embodiment of the present application further provides an electronic device. Among them, the above electronic device may be either a Figure 6 server as shown, or a Figure 7 terminal as shown. Figure 6 and Figure 7 are both structural diagrams of electronic devices shown according to an exemplary embodiment, and the content in the figure cannot be considered as any limitation on the scope of use of the present application.

[0088] Figure 6 FIG. is a schematic structural diagram of a server provided by an embodiment of the present application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. Among them, the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the relevant steps in the memory processing disclosed in any of the foregoing embodiments.

[0089] In this embodiment, the power supply is used to provide working voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and no specific limitation is imposed here; the input / output interface is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitation is made here.

[0090] In addition, as a carrier for resource storage, the memory may be a read-only memory, a random access memory, a magnetic disk, or an optical disc, etc., and the resources stored thereon include an operating system, a computer program, and data, etc., and the storage method may be temporary storage or permanent storage.

[0091] Among them, the operating system is used to manage and control each hardware device and computer program on the server, so as to implement the operation and processing of data in the memory by the processor. It can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the memory processing method disclosed in any of the foregoing embodiments, the computer program can further include computer programs that can be used to complete other specific tasks. In addition to data such as update information of the application program, the data can also include data such as developer information of the application program.

[0092] Figure 7 FIG. is a schematic structural diagram of a terminal provided by an embodiment of the present application. The terminal may specifically include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, etc.

[0093] Generally, the terminal in this embodiment includes: a processor and a memory.

[0094] Among them, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may further include an AI (Artificial Intelligence) processor, and the AI processor is used to process computing operations related to machine learning.

[0095] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, as well as non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory is at least used to store the following computer programs. After the computer programs are loaded and executed by the processor, the relevant steps in the memory processing method executed by the terminal side disclosed in any of the foregoing embodiments can be implemented. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be transient storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, update information of the application program.

[0096] In some embodiments, the terminal may further include a display screen, an input / output interface, a communication interface, sensors, a power supply, and a communication bus.

[0097] Those skilled in the art can understand that Figure 7 the structure shown in does not constitute a limitation on the terminal, and it may include more or fewer components than shown in the figure.

[0098] Next, a non-volatile storage medium provided by an embodiment of the present application will be introduced. The non-volatile storage medium described below may be referred to each other with other embodiments described herein.

[0099] A non-volatile storage medium is used to store a computer program. When the computer program is executed by a processor, the memory processing method disclosed in the foregoing embodiments is implemented. Among them, the non-volatile storage medium is a computer-readable non-volatile storage medium. As a carrier for storing resources, it may be a read-only memory, a random access memory, a disk, or an optical disc, etc. The resources stored thereon include an operating system, a computer program, and data, etc., and the storage method may be transient storage or permanent storage.

[0100] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: determining the memory device connected to the downstream port of the switching device, recording the corresponding memory connection relationship, and sending the memory connection relationship to the main management controller.

[0101] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: constructing a global memory topology map based on the received memory connection relationship, when any computing device reads and writes memory abnormally, locating the abnormal memory device based on the global memory topology map, and sending a hot removal command to the switching device connected to the abnormal memory device through the network device.

[0102] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: in response to a thermal removal command, perform thermal removal on the abnormal memory device.

[0103] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: perform connection configuration on the downstream ports of the switching connector, and transmit the corresponding connection configuration information to the switching management controller.

[0104] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: determine the memory device connected to the downstream port of the switching device based on the connection configuration information, and record the memory connection relationship; in response to the topology acquisition command sent by the main management controller, send the memory connection relationship to the main management controller.

[0105] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: use the basic input / output system to detect whether multiple computing devices have read / write memory anomalies; if any computing device is detected with read / write memory anomalies, determine the device identification information and silk screen information of the abnormal memory device, and send the device identification information and silk screen information to the main management controller.

[0106] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: locate the abnormal memory device in the global memory topology diagram based on the device identification information and silk screen information.

[0107] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: in the global memory topology diagram, query the upstream port and the corresponding downstream port of the switching device corresponding to the device identification information and silk screen information to locate the abnormal memory device.

[0108] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: if the releasable state of any downstream port in the current switching device is detected, send a corresponding interrupt notification signal to the switching processor, so that the switching processor feeds back the port successfully released message to the switching management controller.

[0109] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: feed back the port successfully released message to the main management controller.

[0110] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: sending an alarm message to the abnormal memory device through a network device to power down the abnormal memory device.

[0111] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: in response to a thermal removal command, by configuring the address routing register and the uplink / downlink port configuration register in the current switching device, configuring the current switching device port connected to the abnormal memory device to a releasable state.

[0112] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: after receiving the alarm message sent by the main management controller, power down the memory device corresponding to the alarm message.

[0113] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: after detecting a new memory device, sending an access message to the main management controller.

[0114] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: in response to the access message, sending an access command to the switching device connected to the new memory device to enable the switching device to connect to the new memory device.

[0115] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: after connecting to the new memory device, correspondingly updating the currently managed memory connection relationship.

[0116] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: collecting the operating status information of the memory device and sending the operating status information to the main management controller.

[0117] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: detecting whether there is an abnormal memory device according to the received operating status information.

[0118] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: after detecting a new memory device, sending an access interrupt message to the switching processor.

[0119] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: in response to an access interrupt message, identify the new memory device using the downstream port corresponding to the new memory device in the current switching device, and configure the downstream port of the current switching device to which the new memory device is connected to an available state by configuring the address routing register and the upstream and downstream port configuration registers in the current switching device.

[0120] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: send the available state of the new memory device to the switching management controller.

[0121] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: feedback the available state of the new memory device to the main management controller.

[0122] Next, a computer program product provided by an embodiment of the present application will be introduced. The computer program product described below may be referred to each other with other embodiments described herein.

[0123] A computer program product includes computer programs / instructions, and when the computer programs / instructions are executed by a processor, the steps of the memory processing method disclosed above are implemented.

[0124] Another embodiment of the present application further provides a computer program product, including a non-volatile computer-readable storage medium for storing a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments are implemented.

[0125] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments may be referred to each other.

[0126] The steps of the method or algorithm described in combination with the embodiments disclosed herein may be directly implemented by hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of non-volatile storage medium well-known in the technical field.

[0127] In this text, specific examples are used to illustrate the principle and implementation of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A memory processing system, characterized in that, Including: A host, multiple switching devices, and multiple memory devices; The host, the multiple switching devices, and the multiple memory devices are all connected to a network device; The host includes: a main management controller and multiple computing devices connected to the main management controller; the multiple computing devices are connected to the multiple memory devices through the multiple switching devices to achieve memory expansion of the multiple computing devices; The multiple switching devices are used for: recording the currently managed memory connection relationship and sending the memory connection relationship to the main management controller; The main management controller is used for: when a memory read / write exception occurs in any computing device, locating the abnormal memory device based on the received memory connection relationship, and sending a hot removal command to the switching device connected to the abnormal memory device through the network device; The switching device is used for: in response to the hot removal command, performing hot removal on the abnormal memory device.

2. The system according to claim 1, wherein Any switching device includes: a switching processor, a switching management controller, and a switching connector; the switching processor is connected to the switching management controller and the switching connector; The switching processor is used for: performing connection configuration on the downstream ports of the switching connector and transmitting the corresponding connection configuration information to the switching management controller; The switching management controller is used for: determining the memory devices connected to the downstream ports of its own switching device based on the connection configuration information and recording the memory connection relationship; in response to the topology acquisition command sent by the main management controller, sending the memory connection relationship to the main management controller.

3. The system according to claim 1, wherein The host further includes: a host processor; the host processor is connected to the main management controller and the multiple computing devices; The host processor is used for: detecting whether a memory read / write exception occurs in the multiple computing devices by using the basic input / output system; if a memory read / write exception is detected in any computing device, determining the device identification information and the silk screen information of the abnormal memory device, and sending the device identification information and the silk screen information to the main management controller; The main management controller is used for: based on the device identification information and the silk screen information, querying the upstream port and the corresponding downstream port of the switching device corresponding to the device identification information and the silk screen information in the received memory connection relationship to locate the abnormal memory device.

4. The system according to claim 1, characterized in that, The main management controller is used for: constructing a global memory topology map based on the received memory connection relationship, and locating the abnormal memory device based on the global memory topology map when a memory read / write exception occurs in any computing device.

5. The system according to claim 2, wherein The switching processor is used for: in response to the hot removal command, configuring the downstream port of the current switching device connected to the abnormal memory device to a releasable state; Correspondingly, the switching connector is used for: if it detects the releasable state of any downstream port in the current switching device, sending a corresponding interrupt notification signal to the switching processor, so that the switching processor feeds back a port successfully released message to the switching management controller; The switching management controller is used for: feeding back the port successfully released message to the main management controller; The main management controller is used to: send an alarm message to the abnormal memory device through the network device to power down the abnormal memory device.

6. The system according to claim 5, wherein The switching processor is used to: in response to the hot removal command, configure the address routing register and the upstream and downstream port configuration registers in the current switching device to configure the current switching device port connected to the abnormal memory device to a releasable state.

7. The system according to claim 5, wherein The memory management controller in any memory device is used to: after receiving the alarm message sent by the main management controller, power down the current memory device.

8. The system according to claim 7, characterized in that, The memory management controller is used to: after detecting that the memory device to which it belongs is powered on, send an access message to the main management controller; The main management controller is used to: in response to the access message, send an access command to the switching device connected to the corresponding memory device to enable the switching device to connect to the corresponding memory device.

9. The system according to claim 8, wherein Any switching device is used to: after connecting to a new memory device, correspondingly update the currently managed memory connection relationship and send the updated memory connection relationship to the main management controller.

10. The system according to claim 8, wherein The memory management controller is used to: collect the operation status information of the memory device to which it belongs and send the operation status information to the main management controller.

11. The system according to claim 8, wherein The main management controller is used to: detect whether there is an abnormal memory device according to the received operation status information.

12. The system according to claim 8, characterized in that, The switching connector is used to: after detecting a new memory device, send an access interrupt message to the switching processor; The switching processor is used to: in response to the access interrupt message, identify the new memory device by using the downstream port corresponding to the new memory device in the current switching device, and configure the downstream port of the current switching device connected to the new memory device to an available state by configuring the address routing register and the upstream and downstream port configuration registers in the current switching device.

13. The system according to claim 12, wherein The switching processor is used to: send the available state of the new memory device to the switching management controller; The switching management controller is used to: feedback the available state of the new memory device to the main management controller.

14. The system according to claim 7, wherein The memory management controller in any memory device is connected to multiple memory devices.

15. The system according to any one of claims 1 to 14, characterized in that Among the multiple computing devices, the multiple switching devices, and the multiple memory devices, they are connected through a cache coherence protocol.

16. The system according to any one of claims 1 to 14, characterized in that, The multiple computing devices share the multiple memory devices.

17. A memory processing method, characterized in that, Applied to a memory processing system, the memory processing system includes: a host, multiple switching devices, and multiple memory devices; the host, the multiple switching devices, and the multiple memory devices are all connected to a network device; The host includes: a main management controller and multiple computing devices connected to the main management controller; the multiple computing devices are connected to the multiple memory devices through the multiple switching devices to realize the memory expansion of the multiple computing devices; This memory processing method includes: The multiple switching devices record the currently managed memory connection relationship and send the memory connection relationship to the main management controller; When the main management controller detects a memory read / write exception in any computing device, it locates the abnormal memory device based on the received memory connection relationship, and sends a hot removal command to the switching device connected to the abnormal memory device through the network device; In response to the hot removal command, the switching device performs a hot removal of the abnormal memory device.

18. An electronic device, characterized in that, Comprising: A memory for storing computer programs; A processor for executing the computer programs to implement the method as claimed in claim 17.

19. A non-volatile storage medium, characterized in that, For saving computer programs, wherein the computer programs, when executed by a processor, implement the method as claimed in claim 17.

20. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by a processor, it implements the method as claimed in claim 17.

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