Fault analysis and cross-domain optimization methods, systems and media for human-machine collaborative function testing

Abstract

The present invention discloses a method, system and medium for fault analysis and cross-domain optimization of human-machine collaborative functional testing, which relates to the field of electronic information technology, including: constructing a fault tree, based on reverse quantitative analysis of the fault tree structure, converting the test ratio of intermediate events corresponding to test items into the test ratio of bottom events, calculating the product of the probability of occurrence of the bottom event and the test ratio of the bottom event without functional testing, and obtaining the probability of the motherboard being missed and defective; constructing a test ratio optimization model for the motherboard functional testing process, constructing the objective function of the test ratio optimization model based on the test ratio of the test items and the probability of the motherboard being missed and defective, solving the test ratio optimization model to obtain the optimal motherboard functional testing strategy, so as to test the motherboard; the cross-domain overall optimization method for functional testing improves the cross-domain overall optimization capability, and realizes cost reduction and efficiency improvement in the motherboard functional testing process.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to a method, system and medium for fault analysis and cross-domain optimization of human-machine collaborative function testing. Background Art

[0002] Functional testing is a crucial process for evaluating the functionality of electronic products to ensure product quality. It primarily consists of two processes: motherboard testing and rework. These processes are widely used across various electronic product production lines. The motherboard testing process performs preliminary testing on the motherboard, while the motherboard rework process conducts further testing to ensure finished product quality. Because functional testing requires mixed testing of motherboards from different batches and models, it is a typical flexible manufacturing process. Reducing costs and increasing efficiency in this process is fundamental to achieving flexible intelligent manufacturing of motherboards.

[0003] As integrated circuits increase in complexity, the cost of functional testing increases. This cost is comprised of the time required for both testing and repair processes. Because motherboard functional testing strategies directly impact the testing and repair time costs of defective motherboards or finished products, optimizing the motherboard testing and repair processes across multiple domains to achieve an efficient testing strategy is key to reducing costs and increasing efficiency during motherboard functional testing.

[0004] Selective testing of test items is a common approach to test strategy design. Because motherboard modules are interconnected, test results for corresponding test items are often similar. Using clustering algorithms to group test items for selective testing has proven to be an effective method for reducing costs and increasing efficiency. However, existing methods only process sample attributes independently and fail to consider attribute importance. This results in inaccurate optimization models and makes it difficult to develop effective, cross-domain, holistic optimization strategies.

[0005] In addition, system fault information is important information in the functional testing process and has a significant impact on the time cost of testing and rework, and is therefore the basis for achieving cross-domain overall optimization. Fault analysis is an effective way to obtain system fault information. Fault tree analysis is an important type of fault analysis method. Compared with other methods, fault tree analysis can construct an intuitive tree diagram in the process of analyzing the root cause of system faults, and can perform qualitative analysis and quantitative calculations at the same time. Therefore, it is more widely used in fault analysis of various systems. Although there have been studies on fault tree analysis for the motherboard functional testing process, the existing methods only process sample attributes independently and do not consider the importance of attributes. This will lead to insufficient accuracy of the optimization model and it is difficult to provide an effective cross-domain overall optimization strategy. Summary of the Invention

[0006] Based on the technical problems existing in the background technology, the present invention proposes a method, system and medium for human-machine collaborative functional testing fault analysis and cross-domain optimization, which improves the overall cross-domain optimization capability and achieves cost reduction and efficiency improvement in the motherboard functional testing process.

[0007] The human-machine collaborative function test fault analysis and cross-domain optimization method proposed in the present invention includes:

[0008] Constructing a fault tree, wherein the fault tree has a mainboard function test failure as a top event, a mainboard test item failure as an intermediate event, and a root cause of the mainboard test item failure as a bottom event;

[0009] Based on the reverse quantitative analysis of the fault tree structure, the test ratio of the corresponding test items of the intermediate events is converted into the test ratio of the bottom event. The product of the probability of occurrence of the bottom event and the test ratio of the bottom event without functional testing is calculated to obtain the probability of the motherboard being missed and defective.

[0010] A test ratio optimization model for the motherboard functional test process is constructed. The objective function of the test ratio optimization model is constructed based on the test ratio of the test items and the probability of missed detection and defective motherboards. The test ratio optimization model is solved to obtain the optimal motherboard functional test strategy for testing the motherboard.

[0011] Furthermore, the test ratio of the corresponding test item of the intermediate event is converted into the test ratio of the bottom event, specifically:

[0012] The product of the test proportions of the intermediate events of the bottom event and the corresponding test items that are not tested is used as the test proportion of the bottom event that is not functionally tested;

[0013] The test ratio of the bottom event can be calculated based on the test ratio of the bottom event without performing the functional test.

[0014] Furthermore, the probability of the occurrence of the calculated bottom event is multiplied by the test ratio of the bottom event without functional testing, so as to obtain the probability of the motherboard being missed and defective, which is specifically:

[0015] Classify the bottom event according to whether it occurs and whether the bottom event has been functionally tested, and classify the bottom event as a Class D bottom event if the bottom event has occurred and the bottom event has not been functionally tested;

[0016] Calculate the product of the probability of occurrence of a Class D bottom event and the proportion of Class D bottom events that do not undergo functional testing to obtain the probability of occurrence of a missed bottom event;

[0017] By calculating the probability that all bottom events are not missed bottom events, we can use this probability as the probability of non-missed defective motherboards.

[0018] The complement of the probability of non-missed defective motherboards is taken as the probability of the motherboard being missed and defective.

[0019] Furthermore, the objective function of the test ratio optimization model is the sum of average test time cost and average rework time cost.

[0020] Furthermore, the average test time cost is equal to the sum of the average test time costs of each test item on the mainboard, and the average test time cost of the test item is equal to the product of the average test time of the test item and the test ratio of the test item;

[0021] The sum of the average repair time costs is equal to the product of the probability that the motherboard is missed and defective and the repair time cost of each defective motherboard;

[0022] A constraint function is set for the test ratio optimization model, and the test ratio optimization model with the objective function and constraint conditions is solved to obtain the optimal motherboard function test strategy.

[0023] Furthermore, the constraint function includes an average test time constraint, a missed defective motherboard rate constraint, and upper and lower limit constraints on the test ratio of the test items;

[0024] The average test time constraint formula is as follows:

[0025] ;

[0026] in, The maximum average test time for each motherboard, Functional Testing Strategy Average test time cost of the motherboard;

[0027] The constraint formula for the missed detection defective motherboard rate is as follows:

[0028] ;

[0029] in, Functional testing strategy Lower the missed detection rate of defective motherboards, The maximum missed defective motherboard rate during motherboard function testing is set based on expert experience. The missed defective motherboard rate is equal to the proportion of missed defective motherboards among all defective motherboards.

[0030] The upper and lower limit constraint formulas of the test ratio of the test items are as follows:

[0031] ;

[0032] in, For the The test ratio of the intermediate event, which corresponds to the The test ratio of each test item.

[0033] Furthermore, the upper and lower limits of the test ratio of the test items in the constraint function are optimized based on the density peak clustering algorithm, specifically:

[0034] Based on the density peak clustering algorithm, the clustering decision value corresponding to the mainboard function test items is obtained;

[0035] The clustering decision values ​​corresponding to the mainboard function test items are normalized. The maximum clustering decision value is normalized to the original test ratio upper limit of the test ratio optimization model, the minimum clustering decision value is normalized to the original test ratio lower limit of the test ratio optimization model, and the clustering decision values ​​corresponding to other test items are normalized to between the original test ratio upper and lower limit constraints of the test ratio optimization model.

[0036] Furthermore, the formula for optimizing the upper and lower limits of the test ratio of the test items in the objective function is as follows:

[0037] ,when is the cluster center measurement item;

[0038] ,when It is a non-cluster center measurement item;

[0039] in, For measurement items Initial clustering decision value, is the minimum value among all the cluster decision values ​​corresponding to the measurement items. is the maximum value of the cluster decision values ​​corresponding to all measurement items, The upper limit of the original test ratio for the test ratio optimization model, The lower bound of the original test proportion for the test proportion optimization model.

[0040] Human-machine collaborative functional test fault analysis and cross-domain optimization system, including fault tree construction module, reverse quantitative analysis module and mainboard test module;

[0041] The fault tree construction module is used to construct a fault tree, wherein the fault tree has a mainboard function test failure as a top event, a mainboard test item failure as an intermediate event, and a root cause of the mainboard test item failure as a bottom event;

[0042] The reverse quantitative analysis module converts the test ratio of the corresponding test items of the intermediate events into the test ratio of the bottom events based on the reverse quantitative analysis of the fault tree structure, calculates the product of the probability of occurrence of the bottom events and the test ratio of the bottom events without functional testing, and obtains the probability of the motherboard being missed and defective.

[0043] The motherboard test module is used to construct a test ratio optimization model for the motherboard functional test process, construct the objective function of the test ratio optimization model based on the test ratio of the test items and the probability of the motherboard being missed and defective, and solve the test ratio optimization model to obtain the optimal motherboard functional test strategy to test the motherboard.

[0044] A computer-readable storage medium stores a plurality of classification programs, wherein the plurality of classification programs are used to be called by a processor and execute the optimization method described above.

[0045] The advantages of the human-machine collaborative functional test fault analysis and cross-domain optimization method, system and medium provided by the present invention are: fault tree analysis is performed based on expert experience to establish a fault tree analysis model for the mainboard functional test stage, and then a reverse quantitative analysis method is designed based on the fault tree structure to convert the test ratio of the corresponding test items of the intermediate events into the test ratio of the corresponding bottom events, thereby improving the accuracy of the key indicator calculation method of the test ratio optimization model and achieving cost reduction and efficiency improvement in the mainboard functional test process. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a schematic diagram of the process of the present invention;

[0047] Figure 2 This is a typical business notebook computer motherboard circuit module connection diagram;

[0048] Figure 3 Schematic diagram of the fault tree analysis model for the mainboard functional testing phase. DETAILED DESCRIPTION

[0049] The technical solutions of the present invention are described in detail below through specific embodiments. Numerous specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0050] like Figures 1 to 3 As shown, the human-machine collaborative function test fault analysis and cross-domain optimization method proposed by the present invention includes steps 1 to 3:

[0051] Step 1: Construct a fault tree, wherein the fault tree has a mainboard function test failure as the top event, a mainboard test item failure as the middle event, and the root cause of the mainboard test item failure as the bottom event;

[0052] Step 2: Based on the reverse quantitative analysis of the fault tree structure, the test proportions of the corresponding test items of the intermediate events are converted into the test proportions of the bottom events. The product of the probability of the bottom events occurring and the test proportion of the bottom events not undergoing functional testing is calculated to obtain the probability of the motherboard being missed and defective.

[0053] Step 3. Construct a test ratio optimization model for the motherboard functional test process. Construct the objective function of the test ratio optimization model based on the test ratio of the test items and the probability of the motherboard being missed and defective. The test ratio optimization model must be solved to obtain the optimal motherboard functional test strategy to test the motherboard.

[0054] To solve the problem that existing methods independently process sample attributes and do not consider the importance of attributes, resulting in insufficient accuracy of the optimization model and difficulty in providing an effective cross-domain overall optimization strategy. This embodiment uses steps one to three, takes a typical business laptop motherboard as the object, and conducts fault tree analysis based on expert experience to establish a fault tree analysis model for the motherboard functional testing stage. Then, based on the fault tree structure, a reverse quantitative analysis method is designed to convert the test ratio of the corresponding test items of the intermediate events into the test ratio of the corresponding bottom events, thereby improving the accuracy of the key indicator calculation method of the test ratio optimization model. Based on this embodiment, a motherboard functional testing strategy with cross-domain overall optimization capabilities is designed to achieve cost reduction and efficiency improvement in the motherboard functional testing process.

[0055] In one embodiment, step 1, constructing a fault tree, is specifically as follows:

[0056] Figure 2 Shows the typical business notebook computer motherboard circuit module connection diagram, Figure 3 A fault tree analysis model for the motherboard functional testing phase is presented. In fault tree analysis, events are categorized into top events, intermediate events, and bottom events based on causal relationships. Top events are unexpected system failure states, bottom events are events for which further investigation of the fault's cause is impossible or unnecessary, and intermediate events are factors other than bottom events that lead to the top event. Based on the aforementioned fault tree analysis theory and the composition and connection relationships of the various components in the motherboard circuit, a fault tree was constructed with a motherboard functional test failure as the top event (denoted as T), a motherboard test item failure as the intermediate event, and the root cause of the motherboard test item failure as the bottom event.

[0057] During the motherboard functional test, the components outside the circuit diagram will be tested for their functions. Each component corresponds to a motherboard functional test item. A failure in any motherboard test item will result in a failure in the motherboard functional test. Therefore, each motherboard functional test item corresponds to an intermediate event in the fault tree. Each test item failure is connected to the top event through a logical OR gate as an intermediate event. Typical business laptop motherboard intermediate events and their corresponding functional test items are shown in Table 1, where 、 、 and It is an intermediate event that occurs during the fault tree analysis process. Its corresponding components are not tested during the mainboard functional test phase, so this intermediate event has no corresponding mainboard functional test item.

[0058] Table 1 Typical business notebook computer motherboard intermediate events and their corresponding functional test items

[0059]

[0060] The fault tree is constructed step by step according to the fault tree analysis process, starting from the top event, then progressing to the intermediate event, and finally to the bottom event. The top event T includes all the test item failures during the motherboard functional test (as shown in Table 1). Based on expert experience, the causes of the motherboard component failures corresponding to each test item failure can be summarized as follows:

[0061] First, a test item failure may be due to a fault in the corresponding motherboard component. For example, a touchpad may not function properly due to a manufacturing defect or physical damage. In this case, even if other related components and connecting lines are normal, a problem with the touchpad component itself can still cause the touchpad to fail.

[0062] Secondly, other motherboard components connected to the component corresponding to the test item may also be the root cause of the failure. These connected motherboard components may not be directly tested for functionality, but if they fail, they will also cause the corresponding functional test results of the connected components to fail. For example, if the embedded controller (EC) on the motherboard fails, even if the touchpad components themselves are not faulty, the touchpad functional test result will still be failed due to the inability to properly transmit control signals. In other words, there is a mutual dependence between motherboard components and other connected components, and the failure of one component can affect other components.

[0063] A third possible cause of the problem is a faulty connection between this component and other motherboard components. This fault can include poor soldering or physical damage. For example, if the connection between the touchpad and the EC is poorly soldered, the touchpad will not function properly, even if neither the touchpad nor the EC is faulty.

[0064] For motherboard components other than those listed in Table 1 for functional testing, such as the central processing unit (CPU), platform controller hub (PCH) chipset, audio codec, and embedded controller (EC), these components are not directly tested for functional testing and are primarily composed of chips. Based on expert experience, the causes of component failure can be broken down into the following two sub-aspects:

[0065] The first sub-aspect is a possible chip failure. Minor defects or electrostatic damage during the chip manufacturing process can cause the chip to malfunction. For example, if the PCH chipset chip experiences an internal short circuit, open circuit, or electrostatic damage during manufacturing, this defect can prevent the PCH chipset from properly controlling or coordinating other components on the motherboard, leading to poor functional test results for related items.

[0066] Second, poor soldering between the chip and the motherboard is another possible cause of failure. During the soldering process, inadequate soldering, cracked solder joints, and poor solder quality can all lead to poor soldering. This poor soldering can cause unreliable contact between the chip and the motherboard, leading to unstable or interrupted electrical signal transmission, which can cause component malfunction. For example, during motherboard functional testing of the PCH chipset, poor soldering between the PCH chipset chip and the motherboard can cause unstable or even disconnected communication between the PCH chip and other motherboard components, leading to failures in related test items.

[0067] Based on the expert experience, the causes of the above test item failures were obtained. Based on this, a fault tree analysis was performed on all the intermediate events in Table 1 to obtain the bottom events contained in all the intermediate events. All the bottom events contained in the fault tree with the mainboard test failure as the top event are shown in Table 2. Then, the mainboard test failure was taken as the top event, the failure of each test item was taken as the intermediate event, and the root cause of each test item failure obtained by analysis was taken as the bottom event. A fault tree analysis model for the mainboard function test stage was constructed, as shown in the figure below. Figure 3 The intermediate events corresponding to each component failure and the bottom events they contain are shown in Table 3.

[0068] Table 2. Bottom events of the fault tree analysis model for a typical business laptop motherboard

[0069]

[0070] Table 3 Symbols of intermediate events corresponding to bottom events in the fault tree analysis model for the mainboard functional test phase

[0071]

[0072] In one embodiment, step 2 is based on reverse quantitative analysis of the fault tree structure. The test ratio of the corresponding test items of the intermediate event is converted into the test ratio of the bottom event. The product of the probability of occurrence of the bottom event and the test ratio of the bottom event without functional testing is calculated to obtain the probability of the motherboard being missed and defective. Specifically, it is:

[0073] The probability of a motherboard being missed and defective directly affects the calculation results of the rework time cost, which in turn affects the calculation of the objective function of the test ratio optimization model. Accurately calculating the probability of a motherboard being missed and defective is a key step in determining the objective function. Different intermediate events in the fault tree may contain multiple identical bottom events. When the test item corresponding to a certain intermediate event does not undergo functional testing, but another test item with the same bottom event as the intermediate event corresponding to the test item undergoes functional testing, and the actual fault of the test item undergoing functional testing is the same bottom event, the test results of the test items corresponding to the intermediate events with the same bottom event are all bad. This is because the bottom events and intermediate events in the fault tree for motherboard functional testing are connected through a logical OR gate. When the same bottom event fails, the test items corresponding to the intermediate events containing the bottom event will all fail. In this case, although some test items do not undergo functional testing, their test results can be inferred from the test results of the test items with the same bottom event that are tested.

[0074] Therefore, there is a certain error in calculating the probability of missed detection and defective motherboards using the test ratio of intermediate events corresponding to test items and the probability of intermediate events occurring. This calculation method independently calculates the missed detection situation of some test items that may fail at the same time, which makes the calculated probability of missed detection and defective motherboards biased, thereby affecting the time cost of motherboard rework and the accuracy of the objective function of the test ratio optimization model.

[0075] To eliminate the errors that occur when using the test ratios of intermediate events corresponding to test items and the probability of intermediate events occurring to calculate the probability of a motherboard being missed and defective, the test ratios of bottom events and the probability of bottom events occurring are used to calculate the probability of a motherboard being missed and defective. Because different bottom events in a fault tree are independent of each other, the occurrence of a bottom event is unrelated to the test results of other bottom events. Therefore, using bottom event-related indicators instead of intermediate event-related indicators for calculations will not result in errors. Furthermore, based on the fact that intermediate events in the fault tree analysis model for the motherboard functional testing phase contain bottom event relationships, the test ratios of intermediate events corresponding to test items can be converted into bottom event test ratios. This allows the bottom event test ratios to change in accordance with the changes in the test ratios corresponding to intermediate events during the test ratio optimization process, thus meeting the requirements of the test ratio optimization process.

[0076] The test ratio of the bottom event can be calculated based on the test ratio of the intermediate event to the test item. In the fault tree for the mainboard function test phase, an intermediate event contains multiple bottom events, and a bottom event may correspond to multiple intermediate events. According to the relationship between the intermediate event and the bottom event, any bottom event corresponds to all intermediate events, as shown in Table 4. 、 、 and It is only an intermediate event that occurs during the fault tree analysis. It has no corresponding mainboard functional test items. Therefore, this type of intermediate event does not have a corresponding test ratio and will not affect the calculation of the bottom event test ratio. Therefore, this type of intermediate event is not included in the analysis of the bottom event corresponding intermediate event.

[0077] Table 4 Intermediate event numbers corresponding to the bottom events of the fault tree analysis model for the mainboard functional test phase

[0078]

[0079] This embodiment obtains the probability of the mainboard being missed and defective by calculating the product of the probability of occurrence of the bottom event and the test proportion of the bottom event without performing a functional test. Specifically, the product of the test proportions of the corresponding test items of the intermediate events of the bottom event without performing a test is used as the test proportion of the bottom event without performing a functional test; the test proportion of the bottom event can be calculated based on the test proportion of the bottom event without performing a functional test.

[0080] Specifically, for a certain bottom event, when all the intermediate events containing the bottom event do not perform functional tests on the corresponding test items, the bottom event actually does not perform functional tests. It is the product of the test proportions of the intermediate events including the bottom event, where no test items are tested. The calculation formula is:

[0081] ;

[0082] in, is the bottom event number, Includes bottom event The set of intermediate events, For the The test ratio of each test item.

[0083] The proportion of tests that do not perform functional testing based on bottom events Calculate the test proportion of the bottom event , the calculation formula is as follows:

[0084] .

[0085] Based on the above formula and the relationship between the intermediate events and the bottom events in the fault tree analysis model for the mainboard functional test phase, the test ratio of the test items corresponding to the intermediate events can be converted into the test ratio of the bottom events.

[0086] In this embodiment, the probability of a motherboard being missed and defective can be calculated based on the test ratio of bottom events, specifically: the bottom events are classified according to whether they occur and whether the bottom events are functionally tested, and the bottom events that have occurred and the bottom events that have not been functionally tested are classified as Class D bottom events; the probability of occurrence of a missed bottom event is calculated by multiplying the probability of the Class D bottom event and the ratio of the Class D bottom events that are not functionally tested to obtain the probability of occurrence of a missed bottom event; the probability of occurrence of all bottom events that are not missed bottom events is calculated as the probability of a non-missed defective motherboard; and the complement of the probability of a non-missed defective motherboard is taken as the probability of a missed and defective motherboard.

[0087] Specifically, the probability of the motherboard being missed and defective is:

[0088] The motherboard can be classified according to whether the motherboard performs functional testing during the motherboard functional test and whether the motherboard is faulty, as shown in Table 5;

[0089] Table 5 Mainboard classification based on mainboard function test status

[0090]

[0091] Class A and C motherboards undergo functional testing and are therefore not missed. Class B motherboards, while not undergoing functional testing, are in good condition and do not result in an increase in the number of missed defective motherboards. Class D motherboards are faulty, and not undergoing functional testing for them increases the number of missed defective motherboards, thus affecting the probability of missed detection and failure. Therefore, calculating the probability of a Class D motherboard appearing during the motherboard functional testing yields the probability of a missed detection and failure.

[0092] Based on the fault tree analysis model for the motherboard functional testing phase, motherboard functional testing includes several bottom-event tests. The occurrence of any bottom-event will result in a top-event fault in the fault tree, namely, a motherboard functional test failure. Therefore, the bottom-event test scenario corresponding to a Class D motherboard is that a bottom-event failure occurs during the bottom-event test for this type of motherboard, and this bottom-event failure is not functionally tested. Therefore, a motherboard is considered a non-missed-test failure if and only if all bottom-events are non-missed-test failure bottom-events. Based on the above analysis, the probability of a Class D motherboard appearing during motherboard functional testing is related to the probability of a missed-test bottom-event.

[0093] Similar to the mainboard classification, bottom events can be classified based on whether the bottom event occurs and whether the bottom event is functionally tested, as shown in Table 6;

[0094] Table 6 Basic event classification table of the fault tree analysis model for the mainboard functional test phase

[0095]

[0096] Among them, Class A and Class C bottom events participate in functional testing and will not be missed. Class B bottom events do not undergo functional testing but have not occurred, which will not lead to an increase in the number of missed bottom events. Class D bottom events have occurred and this type of bottom event has not participated in functional testing, which will lead to an increase in the number of missed bottom events, thereby affecting the probability of missed bottom events. Based on the above analysis, the probability of Class D bottom events is the probability of missed bottom events. , which is equal to the product of the probability of occurrence of the bottom event and the proportion of the bottom event that does not undergo functional testing. The calculation formula is as follows:

[0097] ;

[0098] in, It is the bottom event The probability of occurrence, is the test ratio of the bottom event.

[0099] Since any bottom event will lead to a poor motherboard function test, if a Class D bottom event occurs on any motherboard during the motherboard function test, the motherboard is considered to be poor and missed. Therefore, when a bottom event included in the intermediate event corresponding to any test item on the motherboard occurs and is missed, the motherboard is considered a poor motherboard; when the bottom events included in the intermediate event corresponding to all test items on the motherboard do not occur or are not missed, the motherboard is considered a good motherboard. Based on the above analysis, the probability of a motherboard being a poor motherboard is is the probability that all the bottom events it contains are not type D bottom events, and the calculation formula is as follows:

[0100] ;

[0101] in, is the bottom number of events.

[0102] The probability of the motherboard being missed and defective It is the probability that all the bottom events contain a Class D bottom event, that is, the complement of the probability that the main board is a non-missed defective main board. The calculation formula is as follows:

[0103] ;

[0104] Therefore, according to the proposed inverse quantitative analysis method based on the fault tree structure, the probability of the motherboard being missed and defective can be calculated, and the objective function and constraint function of the test ratio optimization model for the motherboard functional test process can be further determined accordingly.

[0105] In this embodiment, step three is to construct a test ratio optimization model for the motherboard function test process. The objective function of the test ratio optimization model is constructed based on the test ratio of the test items and the probability of the motherboard being missed and defective. Specifically, it is:

[0106] The objective function is a core component of the test ratio optimization model, defining the goal and direction of the optimization problem. The objective function quantifies the optimization objective and compares the strengths and weaknesses of different solutions to the test ratio optimization model, ultimately selecting the optimal solution. A good objective function fully reflects the actual problem requirements and ensures that the optimization results meet practical application requirements. In the motherboard functional test ratio optimization problem, reducing the functional test time cost is the primary goal of the optimization process. To achieve cost reduction and efficiency improvement in the motherboard functional test process, it is necessary to comprehensively consider test costs and rework costs for overall cross-domain optimization. Therefore, the return value of the objective function should be set as the average total test time cost per motherboard. The average total test time cost includes the average test time cost and the average rework time cost. The test time cost refers to the cost of functional testing each motherboard test item. The rework time cost refers to the cost of returning the product to the factory for repair due to the failure of functional testing to effectively detect a test item failure. Both the test time cost and the rework time cost are measured using time cost. The average test time cost is related to the test ratio of functional test items, and the average repair time cost is related to the missed detection rate of defective motherboards. Therefore, the objective function can be designed as a function of the test ratio of test items and the missed detection rate of defective motherboards.

[0107] The average test time cost of the motherboard is equal to the sum of the average test time costs of each test item on the motherboard. The average test time cost of the test item is equal to the product of the average test time of the test item and its test ratio. Therefore, in the test strategy Average test time cost of motherboards under for:

[0108] ;

[0109] in, Indicates the number of test items, Indicates the The average test time for each test item, Indicates the The proportion of functional tests for each test item, According to the test strategy A set of test proportions for functional testing of each test item.

[0110] The average repair time cost of the motherboard is equal to the product of the probability of the motherboard being missed and defective and the repair time cost of each defective motherboard. Average repair time cost of motherboards under for:

[0111] ;

[0112] in, is the probability of the mainboard being missed and defective, is the average repair time cost of each defective motherboard.

[0113] When the motherboard is defective and has not been tested for functionality, the motherboard will incur a repair time cost, so the functional testing strategy The average repair time cost of the motherboard is the product of the probability of the motherboard being missed and defective and the average repair time cost of each defective motherboard. The calculation formula is as follows:

[0114] .

[0115] The average total test time cost of each motherboard is the sum of the average total test time cost and the average total repair time cost. Average total test time cost per motherboard under for:

[0116] .

[0117] Therefore, based on the functional testing strategy The formula for calculating the average total test time cost of each motherboard under the functional test strategy is Under the test scale optimization model objective function The final expression is as follows:

[0118] .

[0119] The objective function design fully considers the most important optimization goal of the motherboard functional test process, and achieves cross-domain overall optimization by comprehensively considering the test cost and rework cost. In the rework time cost calculation process, the bottom event test ratio is used instead of the test ratio of the corresponding test items of the intermediate event, making the rework time cost calculation more accurate and reasonable, thereby ensuring the accuracy and rationality of the test ratio optimization model.

[0120] In this embodiment, the constraint function in the test ratio optimization model defines a solution space that satisfies all constraints. This helps the optimization model search for solutions within the solution space to avoid ineffective searches and ensures that the solution to the optimization problem satisfies the constraints of the actual problem. The constraint function also helps the optimization model balance multiple objectives, simplifying the optimization problem by converting certain objectives into constraints. To ensure the feasibility and effectiveness of the optimization results of the test ratio optimization model during motherboard functional testing, the constraint functions of the test ratio optimization model are set to the average test time constraint, the missed defective motherboard rate constraint, and the upper and lower limit constraints of the test item ratio, based on the actual requirements of the motherboard functional testing process and expert experience.

[0121] The average test time of the motherboard directly affects the average test time cost of the motherboard. The average test time cost of the motherboard is an important indicator to measure the quality of the motherboard functional test strategy. Therefore, the motherboard functional test process has certain requirements for the average test time of the motherboard. If no constraints are set for this indicator, the optimization results of the test ratio optimization model will not be effective in the motherboard functional test process. Based on the above analysis, the average test time constraint is set to ensure that the functional test of each motherboard is completed within a reasonable time. For a given maximum average test time of each motherboard , based on the requirements of the motherboard functional test process, the percentage of functional tests performed based on expert experience and test items ,but The calculation formula is:

[0122] ;

[0123] in, Indicates the The average test time for each test item.

[0124] According to the functional testing strategy The average test time cost of the motherboard under test, the average test time constraint can be expressed as:

[0125] ;

[0126] Right now,

[0127] ;

[0128] in, Is the maximum average test time for each given motherboard. If the test strategy If the average test time cost of the motherboard satisfies the inequality constraint, then the test ratio is a solution to the optimization function; otherwise, the average test time exceeds the given maximum value and the test ratio is invalid.

[0129] By setting the missed detection rate constraint for defective motherboards, we can ensure that the test ratio interception capability of defective motherboards is within the required range of the functional test process. The calculation formula is as follows:

[0130] ;

[0131] in, It is the bottom event probability of occurrence.

[0132] Based on the probability of a good motherboard The probability of motherboard failure can be obtained , the calculation formula is as follows:

[0133] ;

[0134] The ratio of missed and defective motherboards to defective motherboards is the missed defective motherboard rate. , the calculation formula is as follows:

[0135] ;

[0136] Based on the above process, the missed detection defective motherboard rate is calculated, and the optimization process is in the test strategy The lower missed defective motherboard rate constraint can be expressed as:

[0137] ;

[0138] in, It is the maximum missed detection rate of defective motherboards during the motherboard function test process based on expert experience. If the missed defective motherboard rate satisfies the inequality constraint, then the test ratio is a solution to the optimization function; otherwise, the missed defective motherboard rate exceeds the given maximum value and the test ratio is invalid.

[0139] By setting upper and lower limits on the test ratio of test items, we can ensure that the test ratio of each test item is within a reasonable range. When there are requirements for the test ratio of some test items, the test ratio of the corresponding test items will be adjusted to within the specified range to meet the actual requirements of the functional testing process. When there are no requirements for the test ratio of each test item in the motherboard functional test, the test ratio of each test item is uniformly set between 0 and 1. The upper and lower limit constraints on the test ratio of the test items can be expressed as:

[0140] .

[0141] In summary, the final expression of the constraint function of the test ratio optimization model is as follows:

[0142] ;

[0143] The design of this constraint function fully considers the important indicators and expert experience of the motherboard functional testing process, ensuring that the optimization results meet the actual requirements of the motherboard functional testing. In the calculation process of the missed defective motherboard rate constraint condition, the bottom event test ratio is used instead of the intermediate time corresponding test item test ratio, making the constraint condition calculation more accurate and reasonable, thereby ensuring the accuracy and rationality of the test ratio optimization model.

[0144] In one embodiment, the upper and lower limits of the test ratio of the test items in the constraint function are optimized based on the density peak clustering algorithm: the clustering decision values ​​corresponding to the mainboard function test items are obtained based on the density peak clustering algorithm; the clustering decision values ​​corresponding to the mainboard function test items are normalized, the maximum clustering decision value is normalized to the original test ratio upper limit of the test ratio optimization model, the minimum clustering decision value is normalized to the original test ratio lower limit of the test ratio optimization model, and the clustering decision values ​​corresponding to other test items are normalized to between the original test ratio upper and lower limit constraints of the test ratio optimization model.

[0145] Specifically, the design of the constraints in the test ratio optimization model is related to the size of the solution space of the optimization model. Reasonable constraint design can help the optimization algorithm search for solutions in the solution space, so that the optimization solution meets the requirements of the actual problem. For the design of the upper and lower limits of the test ratio in the test ratio optimization model, the design of the upper and lower limits of the test ratio in the original test ratio optimization model only considers the rationality of the optimal solution, and uniformly sets the upper and lower limits of the test ratio to This constraint does not distinguish the importance of attributes based on expert guidance and cannot effectively guide the optimization direction of the test strategy.

[0146] In the cluster groupings derived from the density peak clustering algorithm, the cluster center attribute has a strong correlation with other attributes within the same cluster group. Compared to other non-cluster center attributes, the cluster center attribute sample data can effectively reflect the distribution of the sample data for that cluster group. Therefore, based on expert guidance, it can be seen that the cluster center attribute is more important than non-cluster center attributes in the motherboard functional test ratio optimization model. Increasing the test ratio of cluster center test items and reducing the test ratio of non-cluster center test items is an effective way to reduce the total time cost of functional testing.

[0147] Density peak clustering algorithm based on local density of different attributes , relative distance Calculate the decision value to determine the cluster center and cluster grouping results, cluster decision value The calculation formula is as follows:

[0148] .

[0149] With the local density of the item as the horizontal axis and the relative distance as the vertical axis, the item in the coordinate system is its projection onto the coordinate system. The local density reflects the number of other items surrounding the item. The denser the number of items in the cluster center, the greater the probability that an item with a high local density will become a cluster center. The relative distance reflects the distance from the item to other items with a higher local density. The relative distance between cluster centers is generally higher to ensure sufficient distance between different cluster groups. Therefore, items with high relative distances have a greater probability of becoming a cluster center. Based on the above analysis, since the decision value is the product of the local density of the item and the relative distance, the higher the decision value of the item, the greater its probability of becoming a cluster center.

[0150] Normalize the clustering decision values ​​corresponding to the test items in the cluster grouping. Normalize the maximum clustering decision value to the upper limit of the original test ratio of the test optimization model. Normalize the minimum clustering decision value to the lower limit of the original test ratio of the test ratio optimization model. Normalize the clustering decision values ​​corresponding to other attributes to the original test ratio constraints of the test ratio optimization model. The formula is as follows:

[0151] ;

[0152] in, is the test ratio boundary value corresponding to the normalized attribute, is the initial clustering decision value of the attribute, is the minimum value among all attribute corresponding clustering decision values, is the maximum value of the clustering decision values ​​corresponding to all attributes, The upper limit of the original test ratio for the test ratio optimization model, The lower bound of the original test proportion for the test proportion optimization model.

[0153] In a fault tree for the motherboard functional test process, intermediate events corresponding to different attributes may contain the same underlying event. Expert experience shows that the more underlying events different intermediate events contain, the greater their mechanism correlation, and thus the greater the mixed correlation metric between these intermediate events. Consequently, the greater the local density and relative distance calculated based on the correlation metric, and the larger the clustering decision value. Based on the above analysis, the more underlying events are shared between corresponding intermediate events, the greater the probability that the attribute corresponding to that intermediate event will become a cluster center. The number of underlying events shared by intermediate events corresponding to the cluster center attribute and intermediate events corresponding to other attributes is greater than that of non-cluster center attributes. Therefore, increasing the lower limit of the test ratio range corresponding to the cluster center attribute and lowering the upper limit of the test ratio range corresponding to the non-cluster center attribute can strengthen the constraint function of the test ratio optimization model, concentrating the optimal solution in the optimal region of the objective function. This, in turn, increases the coverage of the optimal solution for the attribute's test ratio relative to the optimal solution for the underlying event test variables, further effectively reducing the critical indicator.

[0154] Based on the above analysis, increasing the lower limit of the test ratio of cluster center test items in the test ratio optimization model can ensure that the cluster center test items are fully covered during the test process, improve the comprehensiveness of the test process, and reduce the risk of increased rework time costs due to insufficient testing. At the same time, lowering the upper limit of the test ratio of non-cluster center test items in the test ratio optimization model can reduce redundant testing of marginal test items and reduce the time cost of functional testing. Therefore, based on expert guidance, the lower limit of the test ratio of cluster center test items in the test ratio optimization model is lowered. The adjustment is made from the lower limit of the original test ratio to the normalized result of the cluster decision value corresponding to the test item. The calculation formula is as follows:

[0155] ,when is the cluster center measurement item;

[0156] in, For the The initial clustering decision value of each test item.

[0157] At the same time, based on expert guidance, the upper limit of the test ratio of non-cluster center items was increased from the original upper limit of the test ratio Adjust to the normalized result of the cluster decision value corresponding to the measurement item. The calculation formula is as follows:

[0158] ,when It is a non-cluster center measurement item.

[0159] Based on the above method of adjusting the upper and lower limits of the test ratio in the test ratio optimization model corresponding to different attributes based on density peak clustering, the constraint conditions of the test ratio optimization model are reconstructed. The upper and lower limit constraint expressions of the adjusted test ratio optimization model are:

[0160] ,when is the cluster center measurement item;

[0161] ,when It is a non-cluster center measurement item.

[0162] Based on the above expert guidance, the upper and lower limit constraints of the test ratio optimization model are reconstructed to fully consider the number of the same base events contained in the intermediate events corresponding to the different attributes contained in the clustering results, as well as the test redundancy caused by the same base event test, and further optimize the design of the test ratio optimization model.

[0163] This embodiment solves the problem that existing methods independently process sample attributes and do not consider the importance of attributes, resulting in insufficient accuracy of the test ratio optimization model and difficulty in providing an effective cross-domain overall optimization strategy.

[0164] This embodiment designs a fault tree based on expert experience and employs a top-down reverse quantitative analysis method based on the fault tree structure. Furthermore, the method utilizes the clustering results of an improved density peak clustering algorithm to determine attribute importance through expert guidance, and then designs constraints accordingly. The method proposed in this embodiment can be used to design a motherboard functional testing strategy with cross-domain overall optimization capabilities, helping to reduce costs and increase efficiency during motherboard functional testing.

[0165] This example uses three parameters as evaluation indicators: missed defective motherboard rate, average test time, and average total test time cost. These indicators reflect the test strategy's ability to intercept defective motherboards, its time efficiency, and its overall time cost. The missed defective motherboard rate is the ratio of missed defective motherboards to the total number of defective motherboards, the average test time is the average test time per motherboard, and the average total test time cost is the sum of the average repair time and the average test time.

[0166] The optimization method (FTA-DPC-FM) of this embodiment is compared with the following four methods in turn:

[0167] Comparison method 1 is the density peak clustering algorithm based on hybrid modeling (Hybrid-DPC-S). This algorithm is a binary selection method that implements density peak clustering of motherboard functional test items by performing hybrid modeling on the correlation of test items, and determines the motherboard functional test strategy based on the clustering results. For specific method details, please refer to patent CN118194059A.

[0168] The second comparative method is a traditional test ratio optimization method (TPO-FM) that optimizes modeling based only on the test ratio of the corresponding test items of intermediate events. This method is the ablation experiment of this embodiment. This method does not use the inverse quantitative analysis method based on the fault tree structure proposed in this embodiment to analyze the bottom event test ratio, and does not reconstruct the optimization model constraints based on the clustering decision value. It only optimizes the test ratio of the mainboard function test items based on the test ratio of the test items.

[0169] Comparative method three is a test strategy design method based on fault tree structure reverse quantitative analysis and optimization modeling (FTA-FM). This method is the ablation experiment of this embodiment. This method uses the fault tree structure reverse quantitative analysis method proposed in this embodiment, and does not use the proposed optimization model constraint reconstruction method based on clustering decision values. This method optimizes the test ratio of mainboard functional test items based on the obtained bottom event test ratio.

[0170] Comparative method four is a traditional test ratio optimization method (TPO-DPC-FM) based on clustering decision value constraint reconstruction. This method is the ablation experiment of this embodiment. This method does not use the fault tree structure-based reverse quantitative analysis method proposed in this embodiment. It uses the optimization model constraint reconstruction method based on clustering decision value proposed in this embodiment on the basis of comparative method two, strengthens the constraint conditions of the optimization model, and optimizes the mainboard function test item test ratio based on the test item test ratio.

[0171] The comparison of test strategies and performance indicators based on five different methods is shown in Tables 7 and 8;

[0172] Table 7 Test strategies obtained by the optimization method and comparison method of this embodiment

[0173]

[0174] Table 8 Performance comparison of the test strategies obtained by the optimization method of this embodiment and the comparative method

[0175]

[0176] The results show that the average test time of the proposed FTA-DPC-FM method is higher than that of the Hybrid-DPC-S method, but its missed defective motherboard rate is significantly lower than that of the Hybrid-DPC-S method, making the average total test time cost of the FTA-FM method and the TPO-FM method lower. This shows that compared with the binary selection method, the proposed test ratio optimization method can achieve accurate allocation of test resources by solving the continuous optimal solution of the motherboard functional test strategy, thereby fully reducing redundant tests in the motherboard functional test process, and thus can further reduce the total time cost of the motherboard functional test.

[0177] The missed defective motherboard rate of the FTA-FM method is slightly higher than that of the TPO-FM method, but its average test time is significantly lower than that of the TPO-FM method, making the average total test time cost of the FTA-FM method lower than that of the TPO-FM method. This shows that the proposed FTA-FM method can effectively reduce the calculation error of the key indicators of the test ratio optimization model, thereby reducing the average total test time cost of the motherboard.

[0178] The FTA-DPC-FM method has a significantly lower missed defective motherboard rate than the Hybrid-DPC-S method and a higher rate than the TPO-DPC-FM method. The average test time of the FTA-DPC-FM method is significantly lower than that of the TPO-DPC-FM method and higher than that of the Hybrid-DPC-S method, resulting in a significantly lower average total test time cost for the FTA-DPC-FM method than both the Hybrid-DPC-S and TPO-DPC-FM methods. Furthermore, the FTA-DPC-FM method has a slightly lower missed defective motherboard rate and average test time than the FTA-FM method, resulting in a lower average total test time cost for the FTA-DPC-FM method. This demonstrates that the proposed FTA-DPC-FM method can effectively strengthen the constraints of the optimization model, thereby substantially reducing the average total test time cost for motherboards.

[0179] The above analysis shows that the proposed FTA-DPC-FM method improves the design of the objective function and constraint conditions of the motherboard functional test ratio optimization model by reducing the calculation error of key indicators and compressing the value range of decision variables. The proposed method can fully reduce the total time cost of motherboard functional testing and provide a continuous optimal solution to the time cost optimization problem of motherboard functional testing.

[0180] The method proposed in this embodiment performs fault tree analysis based on expert experience, conducts reverse quantitative analysis on the obtained fault tree structure, and compresses the upper and lower limits of the test ratio based on expert guidance, effectively reducing the calculation error of the key indicators of the test ratio optimization model and enhancing the constraint conditions of the test ratio optimization model, thereby improving the cross-domain overall optimization capability of the motherboard functional test strategy design. The test strategy obtained based on the method of this embodiment significantly reduces the rate of missed detection of defective motherboards while slightly increasing the average test time of the motherboard, thereby fully reducing the average total time cost of the motherboard test and achieving cost reduction and efficiency improvement in the motherboard functional test process.

[0181] As an embodiment;

[0182] Taking a typical business laptop motherboard as the test object, we first establish a fault tree analysis model for the motherboard functional test phase based on the typical business laptop motherboard circuit module connection diagram. Then, we design a reverse quantitative analysis method based on the fault tree structure, converting the test ratio of the intermediate event corresponding to the test item into the test ratio of the corresponding bottom event. Based on this, we design the objective function and constraints and establish an optimization model for the motherboard functional test process. Finally, based on the clustering decision value, we compress the upper and lower limits of the test ratio corresponding to different attributes, adjust the constraints, and perform the optimization solution. The specific implementation steps are as follows:

[0183] A1. Based on the electronic components and physical connections between components in a typical business notebook motherboard, construct Figure 2The following is a typical business notebook computer motherboard circuit module connection diagram;

[0184] A2. Build a fault tree analysis model for the motherboard functional testing phase, with the motherboard test failure as the top event, each test item failure as the intermediate event, and the root cause of each test item failure obtained through fault analysis as the bottom event.

[0185] A3. Based on the fault tree structure in the fault tree analysis model for the mainboard functional test phase (such as Figure 3 Design of reverse quantitative analysis method;

[0186] A4. Based on the reverse quantitative analysis method in A3 and the relationship between the base events and the intermediate events in Table 4, convert the test proportions of the corresponding measurement items of the intermediate events into the test proportions of the corresponding base events;

[0187] A5. Based on the bottom event test ratio obtained in A4, calculate the key indicators of the test ratio optimization model, including the probability of missed inspection and defective motherboards and the average repair time cost of motherboards;

[0188] A6. Design objective functions and constraint functions based on the key indicators of the test ratio optimization model, and establish a test ratio optimization model for the motherboard functional test process;

[0189] A7. Using the density peak clustering algorithm, we obtain cluster decision values ​​corresponding to each motherboard function test item. We then normalize these cluster decision values, normalizing the maximum cluster decision value to the upper limit of the original test ratio in the test ratio optimization model, and the minimum cluster decision value to the lower limit of the original test ratio in the test ratio optimization model. We also normalize the cluster decision values ​​corresponding to other test items to within the original test ratio constraints of the optimization model.

[0190] A8. Adjust the lower limit of the test ratio for the cluster center measurement item in the test ratio optimization model from the original lower limit to the normalized result of the cluster decision value corresponding to the measurement item;

[0191] A9. Adjust the upper limit of the test ratio for non-cluster center items in the optimization model from the original upper limit to the normalized result of the cluster decision value corresponding to the item;

[0192] A10. Based on the upper and lower limit adjustment methods for the test ratio optimization model corresponding to different test items in A8 and A9, reconstruct the constraints of the test ratio optimization model and perform an optimization solution;

[0193] A11. Compare and evaluate the test strategies obtained by the optimization method of this embodiment and the comparative method based on the evaluation indicators to verify the effectiveness of the method proposed in this embodiment.

[0194] In this embodiment, a human-machine collaborative functional test fault analysis and cross-domain optimization system is set up, including a fault tree construction module, a reverse quantitative analysis module and a mainboard test module;

[0195] The fault tree construction module is used to construct a fault tree, wherein the fault tree has a mainboard function test failure as a top event, a mainboard test item failure as an intermediate event, and a root cause of the mainboard test item failure as a bottom event;

[0196] The reverse quantitative analysis module converts the test ratio of the corresponding test items of the intermediate events into the test ratio of the bottom events based on the reverse quantitative analysis of the fault tree structure, calculates the product of the probability of occurrence of the bottom events and the test ratio of the bottom events without functional testing, and obtains the probability of the motherboard being missed and defective.

[0197] The motherboard test module is used to construct a test ratio optimization model for the motherboard functional test process, construct the objective function of the test ratio optimization model based on the test ratio of the test items and the probability of the motherboard being missed and defective, and solve the test ratio optimization model to obtain the optimal motherboard functional test strategy to test the motherboard.

[0198] In addition, in this embodiment, a computer-readable storage medium is provided, on which a plurality of classification programs are stored. The plurality of classification programs are used to be called by a processor and execute the optimization method described above.

[0199] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk, etc. Various media that can store program codes.

[0200] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. The method for fault analysis and cross-domain optimization of human-machine collaborative function testing is characterized by: include: Constructing a fault tree, wherein the fault tree has a mainboard function test failure as a top event, a mainboard test item failure as an intermediate event, and a root cause of the mainboard test item failure as a bottom event; Based on the reverse quantitative analysis of the fault tree structure, the test ratio of the corresponding test items of the intermediate events is converted into the test ratio of the bottom events. The bottom events are classified according to whether they have occurred and whether they have undergone functional testing. The bottom events that have occurred or have not undergone functional testing are classified as Class D bottom events; Calculate the product of the probability of occurrence of a Class D bottom event and the proportion of Class D bottom events that do not undergo functional testing to obtain the probability of a missed bottom event; calculate the probability that all bottom events are not missed bottom events as the probability of a non-missed defective motherboard; take the complement of the probability of a non-missed defective motherboard as the probability of a missed and defective motherboard; A test ratio optimization model for the motherboard functional test process is constructed. The objective function of the test ratio optimization model is constructed based on the test ratio of the test items and the probability of missed detection and defective motherboards. The test ratio optimization model is solved to obtain the optimal motherboard functional test strategy for testing the motherboard.

2. The method for fault analysis and cross-domain optimization of human-machine collaborative function testing according to claim 1, characterized in that: The conversion of the test ratio of the corresponding test item of the intermediate event into the test ratio of the bottom event is specifically as follows: The product of the test proportions of the intermediate events of the bottom event and the corresponding test items that are not tested is used as the test proportion of the bottom event that is not functionally tested; The test ratio of the bottom event can be calculated based on the test ratio of the bottom event without performing the functional test.

3. The method for fault analysis and cross-domain optimization of human-machine collaborative function testing according to claim 1, characterized in that: The objective function of the test ratio optimization model is the sum of the average test time cost and the average rework time cost; The average test time cost is equal to the sum of the average test time costs of each test item on the mainboard, and the average test time cost of the test item is equal to the product of the average test time of the test item and the test ratio of the test item; The sum of the average repair time costs is equal to the product of the probability that the mainboard is missed and defective and the repair time cost of each defective mainboard.

4. The method for fault analysis and cross-domain optimization of human-machine collaborative function testing according to claim 1, characterized in that: A constraint function is set for the test ratio optimization model, and the test ratio optimization model with the objective function and constraint conditions is solved to obtain the optimal motherboard function test strategy.

5. The method for fault analysis and cross-domain optimization of human-machine collaborative function testing according to claim 4 is characterized in that: The constraint function includes the average test time constraint, the missed detection defective motherboard rate constraint and the upper and lower limit constraints of the test ratio of the test items; The average test time constraint formula is as follows: ； in, The maximum average test time for each motherboard, Functional Testing Strategy Average test time cost of the motherboard; The constraint formula for the missed detection defective motherboard rate is as follows: ； in, Functional testing strategy Lower the missed detection rate of defective motherboards, The maximum missed defective motherboard rate during motherboard function testing is set based on expert experience. The missed defective motherboard rate is equal to the proportion of missed defective motherboards among all defective motherboards. The upper and lower limit constraint formulas of the test ratio of the test items are as follows: ； in, For the The test ratio of the intermediate event, which corresponds to the The test ratio of each test item.

6. The method for fault analysis and cross-domain optimization of human-machine collaborative function testing according to claim 5, characterized in that: Based on the density peak clustering algorithm, the upper and lower limits of the test ratio of the test items in the constraint function are optimized, specifically: Based on the density peak clustering algorithm, the clustering decision value corresponding to the mainboard function test items is obtained; The clustering decision values ​​corresponding to the mainboard function test items are normalized. The maximum clustering decision value is normalized to the original test ratio upper limit of the test ratio optimization model, the minimum clustering decision value is normalized to the original test ratio lower limit of the test ratio optimization model, and the clustering decision values ​​corresponding to other test items are normalized to between the original test ratio upper and lower limit constraints of the test ratio optimization model.

7. The method for fault analysis and cross-domain optimization of human-machine collaborative function testing according to claim 6, characterized in that: The formula after optimizing the upper and lower limits of the test ratio of the test items in the objective function is as follows: ,when is the cluster center measurement item; ,when It is a non-cluster center measurement item; in, For measurement items Initial clustering decision value, is the minimum value among all the cluster decision values ​​corresponding to the measurement items. is the maximum value of the cluster decision values ​​corresponding to all measurement items, The upper limit of the original test ratio for the test ratio optimization model, The lower bound of the original test proportion for the test proportion optimization model.

8. Human-machine collaborative function test fault analysis and cross-domain optimization system, characterized by: Includes fault tree construction module, reverse quantitative analysis module and mainboard test module; The fault tree construction module is used to construct a fault tree, wherein the fault tree has a mainboard function test failure as a top event, a mainboard test item failure as an intermediate event, and a root cause of the mainboard test item failure as a bottom event; The reverse quantitative analysis module converts the test ratio of the corresponding test items of the intermediate events into the test ratio of the bottom events based on the reverse quantitative analysis of the fault tree structure, and classifies the bottom events according to whether the bottom events have occurred and whether the bottom events have been functionally tested. The bottom events that have occurred and the bottom events that have not been functionally tested are classified as Class D bottom events; Calculate the product of the probability of occurrence of a Class D bottom event and the proportion of Class D bottom events that do not undergo functional testing to obtain the probability of a missed bottom event; calculate the probability that all bottom events are not missed bottom events as the probability of a non-missed defective motherboard; take the complement of the probability of a non-missed defective motherboard as the probability of a missed and defective motherboard; The motherboard test module is used to construct a test ratio optimization model for the motherboard functional test process, construct the objective function of the test ratio optimization model based on the test ratio of the test items and the probability of the motherboard being missed and defective, and solve the test ratio optimization model to obtain the optimal motherboard functional test strategy to test the motherboard.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a plurality of classification programs, which are used to be called by a processor and execute the optimization method according to any one of claims 1 to 7.

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