Simulation modeling system based on UVM

Abstract

The invention relates to a simulation modeling system based on a UVM. The system comprises a component library management module, an incentive library management module, a top layer generation module, a graphical modeling module, a script generation module, a coverage rate statistics module and a server calling module, wherein the component library management module is used for managing a UVM component model; the incentive library management module is used for managing the incentive model; the top layer generation module is used for generating a corresponding top layer module according to the top layer file; the graphical modeling module is used for modeling according to the UVM component model; the coverage rate counting module is used for counting coverage rate data in the verification test process; the script generation module is used for generating various modeling files; and the server calling module is used for completing simulation of the modeling file. Therefore, the UVM can be directly used to realize random generation of test vectors, automatic comparison of test results and automatic statistics of code coverage rate and function coverage rate, and the FPGA test coverage rate and quality are greatly improved.

Description

Technical Field

[0001] This application relates to the field of simulation technology, and particularly to a simulation modeling system based on UVM. Background Art

[0002] With the improvement of chip functions and performance, the difficulty of chip verification is also increasing. Traditional Field-Programmable Gate Array (FPGA) simulation verification is a process of testing FPGA software. The Universal Verification Methodology (UVM) can realize the random generation of test stimuli and the statistics of functional coverage, but UVM has a set of complex mechanisms, which are difficult to learn and use, and it is difficult for designers and evaluators to master in a short time.

[0003] In traditional technologies, the process of building a simulation environment under the UVM mechanism is as follows: when creating subclasses such as drivers and sequencers, a UVM tree structure will be automatically formed. After the simulation environment is built, this UVM tree and the test environment together form a test system for the Device Under Test (DUT).

[0004] However, the above process of building a simulation environment is relatively complex, time-consuming, and requires high capabilities of testers. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a simulation modeling system based on UVM that can realize the random generation of test vectors, the automatic comparison of test results, the automatic statistics of code coverage and functional coverage, and greatly improve the FPGA test coverage and quality.

[0006] In a first aspect, this application provides a simulation modeling system based on UVM, and the system includes: a component library management module, an excitation library management module, a top-level generation module, a graphical modeling module, a script generation module, a coverage statistics module, and a server call module, where:

[0007] The component library management module is used to manage the UVM component models;

[0008] The excitation library management module is used to manage the excitation models;

[0009] The top-level generation module is used to generate a corresponding top-level module according to the top-level file;

[0010] The graphical modeling module is used to perform modeling according to the UVM component models;

[0011] The coverage statistics module is used to count the coverage data during the verification test;

[0012] The script generation module is used to generate various modeling files, and the modeling files include: test script files, test instance files, and environment variable files;

[0013] The server call module is used to call the simulation tool on the remote server to complete the simulation of the modeling files.

[0014] In one embodiment, the component library management module is specifically used for: performing at least one of the operations of editing, adding, and deleting the UVM component model; where,

[0015] The editing operation is used to set and / or modify the attributes of the UVM component model, and the attributes of the UVM component model include: the type of the component, the verification framework code corresponding to the component, and the component description information;

[0016] The adding operation is used to customize and create a new UVM component model, and after setting the relevant attributes and framework code, add it to the UVM component model library;

[0017] The deleting operation is used to delete the existing component models in the UVM component model library.

[0018] In one embodiment, the stimulus library management module is specifically used for: performing at least one of the operations of editing, adding, and deleting the stimulus model; where,

[0019] The editing operation is used to set the attributes of the stimulus, and the attributes of the stimulus include: stimulus type, stimulus code, and stimulus description information;

[0020] The adding operation is used to customize and create a new stimulus model, and after setting the relevant attributes and framework code, add it to the stimulus model library;

[0021] The deleting operation is used to delete the existing stimulus models in the stimulus model library.

[0022] In one embodiment, the top-level generation module is specifically used to perform at least one of the following functions:

[0023] Identify top-level files in different formats;

[0024] Identify and process Verilog and VHDL language codes in the top-level file, identify the code hierarchy in the top-level file, and automatically obtain the input / output interfaces, clock signals, and reset signals in the top-level file, and automatically complete the modeling of the top-level module and its external interfaces;

[0025] Set the attributes of the top - level module according to the simulation verification requirements; the attributes of the top - level module include: clock signal, reset signal, simulation time, special interface module, chip model, and test instance;

[0026] Set the clock signal and its attributes. The attributes of the clock signal include: clock signal name, clock start value, clock duty cycle, clock frequency, and clock period; among them, for the clock frequency, the numerical value of the clock frequency and its unit need to be filled in, and for the clock period, the numerical value of the clock period and its unit need to be filled in;

[0027] Set the reset signal and its attributes. The attributes of the reset signal include: reset signal name, reset valid value, and reset accuracy;

[0028] Set the simulation time, time accuracy, and simulation accuracy. The time accuracy includes: time accuracy value and time accuracy unit; the simulation accuracy includes: simulation accuracy value and simulation accuracy unit;

[0029] Set the special interface, which refers to a timing interface that generates specific combined signals during the FPGA simulation verification process and jointly forms a timing interface with a specific function;

[0030] Set the chip model used for simulation;

[0031] Select the VCS server used for simulation and save the selected server information;

[0032] Set the test instance name, and after inputting the code of the connect_phase function and the report_phase function, generate a test instance file;

[0033] During the process of setting the attributes of the top - level module, delete the relevant set attributes; or, in the case where the test needs to be remodeled, delete through the generated top - level module;

[0034] Insert the code generated according to the input information into the corresponding verification code of the top - level module, preview the verification code, and provide a manual method to modify the verification code.

[0035] In one of the embodiments, the graphical modeling module is specifically used to perform at least one of the following functions:

[0036] According to the simulation verification requirements, place the UVM component model in the modeling area by dragging or double - clicking the selected method to instantiate the UVM component model; and / or, perform move / delete operations on the already instantiated UVM component model as needed;

[0037] According to the simulation verification requirements, set the parameters of the UVM component model. The parameters of the UVM component model include: name, transceiver attribute, external interface, and whether to count coverage;

[0038] According to the simulation verification requirements, place the stimulus model in the modeling area by dragging or double-clicking to select, and perform instantiation operations on the stimulus model to complete the modeling; and / or, perform move / delete operations on the already instantiated stimulus model as needed;

[0039] According to the simulation verification requirements, set the parameters of the stimulus model. The parameters of the stimulus model include: name, transceiver attribute, external interface;

[0040] According to the simulation verification requirements, configure the connection relationships among the component model, stimulus model, and top-level module placed in the modeling area. The connection relationships are used to represent the input / output relationships and data flow directions of data among the component model, stimulus model, and top-level module;

[0041] During the modeling process, the set attributes and configured connection relationships are automatically added to the verification code corresponding to the UVM component model;

[0042] During or after the modeling process, manually edit the verification code; among them, for different component models, prompt the positions where code needs to be added.

[0043] In one embodiment, the coverage statistics module is specifically used to perform at least one of the following functions:

[0044] During the simulation process, track and count the current coverage situation by generating corresponding coverage collection files;

[0045] According to the simulation verification requirements, support selecting whether to count the coverage of the UVM component model;

[0046] According to the simulation verification requirements, support collecting the coverage of target signals, and after setting coverage points and adding corresponding coverage collection statement codes, automatically count the hit situations and hit times of each coverage point;

[0047] Based on the obtained coverage situation of the coverage points, set and adjust the design constraints, and monitor the change of coverage in real time;

[0048] According to the need, view and modify the coverage collection code corresponding to the current UVM component model.

[0049] In one embodiment, the script generation module is specifically used to perform at least one of the following functions:

[0050] During the modeling process, a Makefile is automatically generated.

[0051] According to the selected ISE version and chip version information, a synopsys_sim.setup file is automatically generated.

[0052] According to the naming and modeling information, a test_lib.sv file is automatically generated.

[0053] According to the instantiated UVM component models and their attributes, verification code, and connection relationships, the corresponding UVM component model sv files are automatically generated.

[0054] According to the coverage collection information set during the modeling process, a coverage collection file is generated, and the coverage information is collected in real time during the subsequent VCS tool simulation process; the coverage collection file includes: basic information for coverage collection.

[0055] According to the instantiated env component model and related modeling information, an environment file is automatically generated. Among them, for the UVM component models instantiated during the modeling process, the corresponding instantiation code will be added to the verification code of the generated environment file.

[0056] A global variable file is generated, and the global variable file includes: global variables named during the modeling process and coverage collection events.

[0057] A top-level module file is generated, and the top-level module file includes: my_if.sv file and top_tb.sv file; the my_if.sv file includes: a full interface module and a special interface module; the top_tv.sv file includes: clock signal setting information, reset signal setting information, precision setting information, and top-level module call content.

[0058] In one of the embodiments, the server call module is specifically used for:

[0059] According to the selected saved server information, the VCS simulation environment on the server is automatically connected, and simulation verification is performed based on the generated modeling files; the versions of the simulation environments installed on the server include: VCS2011, VCS2014, and VCS2016.

[0060] The above UVM-based simulation modeling system realizes the functions of the FPGA integrated simulation verification architecture by setting up a system including a component library management module, an excitation library management module, a top-level generation module, a graphical modeling module, a script generation module, a coverage statistics module, and a server call module. By using the graphical modeling technology, users can directly use UVM to realize the random generation of test vectors, the automatic comparison of test results, the automatic statistics of code coverage and functional coverage without understanding the UVM mechanism, greatly improving the FPGA test coverage and quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the accompanying drawings required for describing the embodiments of the present application or related technologies. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can be obtained based on these drawings.

[0062] Figure 1 It is a schematic diagram of the architecture of the UVM-based integrated simulation modeling system in an embodiment;

[0063] Figure 2 It is a modeling flowchart of the UVM-based simulation modeling method in an embodiment;

[0064] Figure 3 It is a schematic diagram of the structure of the simulation system after modeling in an embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0065] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0066] Those skilled in the art of the present technology can understand that unless specifically stated otherwise, the singular forms "a", "an", "the" and "said" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present invention means the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups.

[0067] Exemplarily, such as Figure 1As shown, an integrated simulation modeling system based on UVM is provided. The system may include: a component library management module, an incentive library management module, a top-level generation module, a graphical modeling module, a script generation module, a coverage statistics module, and a server call module. Among them: The component library management module is used to manage UVM component models; the incentive library management module is used to manage incentive models; the top-level generation module is used to generate corresponding top-level modules according to top-level files; the graphical modeling module is used to model according to UVM component models; the coverage statistics module is used to count coverage data during the verification test process; the script generation module is used to generate various modeling files, and the modeling files include: test script files, test instance files, and environment variable files; the server call module is used to call simulation tools on a remote server to complete the simulation of modeling files.

[0068] In this embodiment, each modeling project corresponds to a specific test case and a configuration environment class. The specific number of transactions, simulation time, fault type, etc. are set through the environment class. The test case is initiated from the transaction component model. The transaction component model generates random transactions for the driver component model through constrained incentives. The driver component model generates specific physical signals for the device under test (DUT) according to the transactions passed by the transaction. The monitor component model will monitor the transactions received by the driver and generate expected output results to the scoreboard component model. At the same time, the monitor component model will collect the output results of the device under test and give them to the scoreboard component model. The scoreboard component model will compare the expected output with the actual output, make a judgment result, and record it. The functional coverage will collect information in the entire verification platform. If the functional coverage does not reach 100%, the transactions generated by the generator can be adjusted by adjusting the random constraints in the test environment or the functional coverage can be increased through directed incentives.

[0069] Exemplarily, the component library management module is specifically used for: performing at least one of the operations of editing, adding, and deleting on the UVM component model; among them, the editing operation is used to set and / or modify the attributes of the UVM component model, and the attributes of the UVM component model include: the type of the component, the verification framework code corresponding to the component, and the component description information; the adding operation is used to customize and create a new UVM component model, and after setting relevant attributes and framework codes, add it to the UVM component model library; the deleting operation is used to delete the existing component models in the UVM component model library.

[0070] In this embodiment, the UVM component model includes: an agent module, a scoreboard module, a transaction module, an env module, a sequencer module, a monitor module, a driver module, and a transaction module, etc.

[0071] Exemplarily, the excitation library management module is specifically configured to perform at least one of the following operations on the excitation model: an editing operation, an adding operation, and a deleting operation; wherein, the editing operation is used to set the attributes of the excitation, and the attributes of the excitation include: excitation type, excitation code, and excitation description information; the adding operation is used to customize and create a new excitation model, and after setting the relevant attributes and framework code, add it into the excitation model library; the deleting operation is used to delete the existing excitation model in the excitation model library.

[0072] In this embodiment, the excitation types include: AD conversion, synchronous and asynchronous interfaces, memory chips, image compression, 1553 buses, CPCI interfaces, processor interfaces, etc., covering the excitations commonly used in the FPGA verification field.

[0073] Exemplarily, the top-level generation module is specifically configured to perform at least one of the following functions: identify top-level files in different formats, identify and process Verilog and VHDL language codes in the top-level files, identify the code hierarchy in the top-level files, and automatically obtain input / output interfaces, clock signals, and reset signals in the top-level files, and automatically complete the modeling of the top-level module and its external interfaces; set the attributes of the top-level module according to the simulation verification requirements; the attributes of the top-level module include: clock signals, reset signals, simulation time, special interface modules, chip models, and test instances; set the clock signals and the attributes of the clock signals, and the attributes of the clock signals include: clock signal names, clock start values, clock duty cycles, clock frequencies, and clock periods; among them, the clock frequency needs to fill in the value of the clock frequency and the unit of the clock frequency, and the clock period needs to fill in the value of the clock period and the unit of the clock period; set the reset signals and the attributes of the reset signals, and the attributes of the reset signals include: reset signal names, reset valid values, and reset accuracies; set the simulation time, time accuracy, and simulation accuracy, and the time accuracy includes: time accuracy value and time accuracy unit; the simulation accuracy includes: simulation accuracy value and simulation accuracy unit; set special interfaces, where special interfaces refer to those used to generate specific combined signals during the FPGA simulation verification process and jointly form a timing interface with a specific function; set the chip model used for simulation; select the VCS server used for simulation and save the selected server information; set the test instance name, and after inputting the codes of the connect_phase function and the report_phase function, generate a test instance file; during the process of setting the attributes of the top-level module, delete the relevant set attributes; or, in the case where the test needs to be remodeled, delete through the generated top-level module; insert the code generated according to the input information into the verification code corresponding to the top-level module, preview the verification code, and provide a manual method to modify the verification code.

[0074] The top-level files in this embodiment include: v files and vhd files. The units of the clock frequency can be: GHz, MHz, KHz, Hz. The units of the clock period can be: ps, ns, us, ms, s. The units of the reset accuracy can be: ns, us, ms. The units of the time accuracy can be: ns, ps, us. The units of the simulation accuracy can be: ns, ps, us.

[0075] The chip models used for simulation in this embodiment include: Xilinx chips, Actel chips, and Altera chips.

[0076] Exemplarily, the graphical modeling module is specifically used to perform at least one of the following functions: placing the UVM component model in the modeling area by dragging or double-clicking selection according to the simulation verification requirements, and instantiating the UVM component model; and / or, performing move / delete operations on the already instantiated UVM component model as needed; setting the parameters of the UVM component model according to the simulation verification requirements, where the parameters of the UVM component model include: name, transceiver attribute, external interface, whether to count coverage; placing the stimulus model in the modeling area by dragging or double-clicking selection according to the simulation verification requirements, and performing an instantiation operation on the stimulus model to complete the modeling; and / or, performing move / delete operations on the already instantiated stimulus model as needed; setting the parameters of the stimulus model according to the simulation verification requirements, where the parameters of the stimulus model include: name, transceiver attribute, external interface; configuring the connection relationship among the component model, stimulus model, and top-level module placed in the modeling area according to the simulation verification requirements, and the connection relationship is used to represent the input / output relationship and data flow direction of data among the component model, stimulus model, and top-level module; during the modeling process, the set attributes and configured connection relationships are automatically added to the verification code corresponding to the UVM component model; during or after the modeling process, the verification code is edited manually; among them, for different component models, a prompt is given for the position where code needs to be added.

[0077] Exemplarily, the coverage statistics module is specifically used to perform at least one of the following functions: during the simulation process, tracking and statistically analyzing the current coverage situation by generating a corresponding coverage collection file; supporting the selection of whether to statistically analyze the coverage of the UVM component model according to the simulation verification requirements; supporting the collection of coverage for the target signal according to the simulation verification requirements, and automatically statistically analyzing the hit situation and hit times of each coverage point after setting the coverage points and adding the corresponding coverage collection statement code; setting and adjusting the design constraints based on the obtained coverage of the coverage points, and monitoring the change of coverage in real time; viewing and modifying the coverage collection code corresponding to the current UVM component model as needed.

[0078] Exemplarily, the script generation module is specifically configured to perform at least one of the following functions: during the modeling process, automatically generate a Makefile; automatically generate a synopsys_sim.setup file according to the selected ISE version and chip version information; automatically generate a test_lib.sv file according to the naming and modeling information; automatically generate a corresponding UVM component model sv file according to the instantiated UVM component model, its attributes, verification code, and connection relationships; generate a coverage collection file according to the coverage collection information set during the modeling process, and collect coverage information in real time during the subsequent VCS tool simulation process; the coverage collection file includes: basic information for coverage collection; automatically generate an environment file according to the instantiated env component model and related modeling information, where corresponding instantiation code will be added to the verification code of the generated environment file for all UVM component models instantiated during the modeling process; generate a global variable file, and the global variable file includes: global variables named during the modeling process and coverage collection events; generate a top-level module file, and the top-level module file includes: a my_if.sv file and a top_tb.sv file; the my_if.sv file includes: a full interface module and a special interface module; the top_tv.sv file includes: clock signal setting information, reset signal setting information, precision setting information, and top-level module call content.

[0079] Exemplarily, the server call module is specifically configured to: automatically connect to the VCS simulation environment on the server according to the selected and saved server information, and perform simulation verification based on the generated modeling file; the versions of the simulation environments installed on the server include: VCS2011, VCS2014, and VCS2016.

[0080] It should be understood that the simulation environments of the above versions all support the UVM verification platform.

[0081] In the embodiments of the present application, by setting up a system including a component library management module, an incentive library management module, a top-level generation module, a graphical modeling module, a script generation module, a coverage statistics module, and a server call module, the functions of the FPGA integrated simulation verification architecture are realized, and using the graphical modeling technology, users can directly use UVM to realize random generation of test vectors, automatic comparison of test results, automatic statistics of code coverage and functional coverage without understanding the UVM mechanism, greatly improving the FPGA test coverage and quality.

[0082] Exemplarily, as Figure 2 shown, a modeling flowchart of a simulation modeling method based on UVM is provided, and the method includes the following steps:

[0083] Step 1: Generate the top-level module: After the tester selects the top-level file (DUT), the top-level module is automatically generated in the modeling area. The tester selects the top-level module and edits information such as its clock signal, reset signal, simulation time, special interface module, chip model, etc. After completing the editing of the top-level module information, preview the verification code of the top-level module.

[0084] Step 2: Create the sender module: Select the required sender component models (transaction, driver, agent, sequencer, etc.) and complete the instantiation operation by dragging them into the modeling area or double-clicking them with the right mouse button. Then perform property editing operations on the instantiated component models, setting properties including component name, interface name, etc. The main tasks completed by the sender component module include defining thread communication signals, initializing the generator function and running the generator, initializing the driver function, transaction mapping tasks, and running the driver.

[0085] Step 3: Create the receiver module: Select the required receiver components (monitor, etc.) and complete the instantiation operation by dragging them into the modeling area or double-clicking them with the right mouse button. Then perform property editing operations on the instantiated component models, setting properties including component name, interface name, etc. The main tasks completed by the receiver component module include monitor initialization, monitoring of the output interface, and running the monitor.

[0086] Step 4: Create the scoreboard module: After both the sender module and the receiver module are added, select the scoreboard module and complete the instantiation operation by dragging it into the modeling area or double-clicking it with the right mouse button. Set properties including component name, interface name, etc. When the input stimulus is driving the transmission, push the expected results into the expected stack. At the same time, build the measured model through the receiving module and push the received measured results into the measured stack. Reasonably connect the two stacks to form the get_port port and the analysis_port port, which are used to receive and compare the data from the sender and the receiver, so as to verify whether the relevant functions of the object under test are correctly implemented. The main tasks completed by the scoreboard module include comparing the data from the sender and the receiver, and reporting the error records of the interface transmission and reception after running.

[0087] Step 5: Create the env environment module: Select the env environment component and complete the instantiation operation by dragging it into the modeling area or double-clicking it with the right mouse button. The env environment module generates random configurations and uses a constrained random method to generate the number of peripheral devices, the number of error types, the error injection ratio, the data length, the latency mode, etc. After the instantiation operation is completed, the instantiation operation codes corresponding to the modules in Step 2, Step 3, and Step 4 are automatically added to the env framework code. Configure the mailboxes for communication between the component models and connect the monitor, coverage statistics code, driver, scoreboard, monitor and scoreboard, etc. through callback functions. Start component models such as the driver and monitor through the fork…join_none process mode.

[0088] Step 6: Create the stimulus module: Select the required stimulus module and complete the instantiation operation by dragging it into the modeling area or double-clicking it with the right mouse button, and perform attribute editing operations on the instantiated stimulus model. The stimulus module generates signals and loads them onto the driver, and after being converted by the driver and subsequent components, physical signals are generated and driven to the top-level module.

[0089] Step 7: Configure the connection relationship: According to the data flow relationship between each component module, stimulus module, and top-level module during the simulation process, connect the interfaces between the component module, stimulus module, and top-level module to represent the data flow during the simulation process. While connecting the interfaces between the modules, the codes corresponding to the connection relationship and data input / output relationship are automatically added to the verification codes corresponding to each module.

[0090] Step 8: Coverage setting: According to the simulation requirements, set the coverage-related attributes for the component modules that need to perform coverage statistics, and input the coverage collection code statements into the verification codes corresponding to the component modules. After the above steps are completed, the modeling operation is completed, and the structure of the established simulation model is as Figure 3 shown.

[0091] Step 9: Set the test instance: Input the test instance information, including the name of the input test instance, and input the codes of the connect_phase and report_phase functions, and the test instance-related information will be saved. In the code "templates" of the methods and tasks of the already encapsulated component models, specific modeling codes are written. The corresponding interface codes are input into the driver component, and the corresponding data structure codes are input into the transaction component.

[0092] Step 10: Generate the modeling files: According to the modeling information in the above steps, generate the makefile file, test script file, test instance file, sv file corresponding to the component model, coverage collection file, environment file, global variable file, and top-level module file in sequence.

[0093] Step 11. Simulation: Invoke the VCS simulation tool on the server to perform FPGA simulation verification based on the modeling file generated in Step 10. During the simulation verification process, automatically invoke the information reporting mechanism of UVM, that is, call the report method of each component model to report various information during the simulation verification process. Functionally, it is mainly divided into two parts. One is to control the information reporting redundancy level through the ID of the information, and perform different behavior controls for each redundancy level. The other is to perform formatted output of the information reporting.

[0094] In this embodiment, the simulation verification process can be modeled by combining graphical technology with the UVM method, which is simple and easy to master. According to the functional coverage statistics information feedback in real time during the simulation process, the test stimulus can also be adjusted to converge the coverage rate. In addition, during the modeling process, the instantiation objects of the component models can be dynamically added and deleted, so that the simulation architecture can change dynamically, the architecture is configurable; the component models are reconfigurable and have strong reusability.

[0095] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are displayed in sequence according to the arrows, these steps do not necessarily need to be executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages do not necessarily need to be executed at the same time, but can be executed at different times. The execution order of these steps or stages does not necessarily need to be sequential, but can be executed alternately or alternately with at least a part of other steps or steps in other steps.

[0096] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this application.

[0097] The above-described embodiments only express several implementation manners of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the patent scope of this application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several deformations and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of this application should be subject to the appended claims.

Claims

1. A simulation modeling system based on UVM, characterized in that, The system includes: a component library management module, an incentive library management module, a top-level generation module, a graphical modeling module, a script generation module, a coverage statistics module, and a server call module, where: The component library management module is used to manage UVM component models; The incentive library management module is used to manage incentive models; The top-level generation module is used to generate a corresponding top-level module according to the top-level file; The graphical modeling module is used to perform modeling based on UVM component models; The coverage statistics module is used to count the coverage data during the verification test process; The script generation module is used to generate various modeling files, and the modeling files include: test script files, test instance files, and environment variable files; The server call module is used to call the simulation tool on the remote server to complete the simulation of the modeling files.

2. The UVM-based simulation modeling system according to claim 1, characterized in that, The component library management module is specifically used for: performing at least one of the operations of editing, adding, and deleting UVM component models; where The editing operation is used to set and / or modify the attributes of the UVM component model, and the attributes of the UVM component model include: the type of the component, the verification framework code corresponding to the component, and the component description information; The adding operation is used to customize and create a new UVM component model, and after setting the relevant attributes and framework code, add it to the UVM component model library; The deleting operation is used to delete the existing component models in the UVM component model library.

3. The simulation modeling system based on UVM according to claim 1, wherein The incentive library management module is specifically used for: performing at least one of the operations of editing, adding, and deleting incentive models; where The editing operation is used to set the attributes of the incentive, and the attributes of the incentive include: incentive type, incentive code, and incentive description information; The adding operation is used to customize and create a new incentive model, and after setting the relevant attributes and framework code, add it to the incentive model library; The deleting operation is used to delete the existing incentive models in the incentive model library.

4. The UVM-based simulation modeling system according to claim 1, characterized in that, The top-level generation module is specifically used to perform at least one of the following functions: Identify top-level files in different formats; Identify and process Verilog language and VHDL language codes in the top-level file, identify the code hierarchy in the top-level file, and automatically obtain the input / output interfaces, clock signals, and reset signals in the top-level file, and automatically complete the modeling of the top-level module and its external interfaces; Set the attributes of the top-level module according to the simulation verification requirements; the attributes of the top-level module include: clock signal, reset signal, simulation time, special interface module, chip model, and test instance; Set the clock signal and the attributes of the clock signal, and the attributes of the clock signal include: clock signal name, clock start value, clock duty cycle, clock frequency, and clock period; where the clock frequency needs to fill in the value of the clock frequency and the unit of the clock frequency, and the clock period needs to fill in the value of the clock period and the unit of the clock period; Set the reset signal and the attributes of the reset signal, and the attributes of the reset signal include: reset signal name, reset valid value, and reset accuracy; Set the simulation time, time precision, and simulation precision. The time precision includes: a time precision value and a time precision unit; the simulation precision includes: a simulation precision value and a simulation precision unit. Set a special interface, which refers to a timing interface that generates specific combined signals and has a specific function during the FPGA simulation verification process. Set the chip model used for simulation. Select the VCS server used for simulation and save the selected server information. Set the test instance name and generate a test instance file after inputting the code of the connect_phase function and the report_phase function. During the property setting process of the top-level module, delete the relevant set properties; or, in the case where the test needs to be remodeled, delete through the generated top-level module. Insert the code generated according to the input information into the corresponding verification code of the top-level module, preview the verification code, and provide a manual method to modify the verification code.

5. The UVM-based simulation modeling system according to any one of claims 1 to 4, characterized in that The graphical modeling module is specifically used to perform at least one of the following functions: According to the simulation verification requirements, place the UVM component model in the modeling area by dragging or double-clicking to select, and instantiate the UVM component model; and / or, perform move / delete operations on the already instantiated UVM component model as needed. According to the simulation verification requirements, set the parameters of the UVM component model. The parameters of the UVM component model include: name, transceiver attribute, external interface, and whether to count coverage. According to the simulation verification requirements, place the stimulus model in the modeling area by dragging or double-clicking to select, and perform an instantiation operation on the stimulus model to complete the modeling; and / or, perform move / delete operations on the already instantiated stimulus model as needed. According to the simulation verification requirements, set the parameters of the stimulus model. The parameters of the stimulus model include: name, transceiver attribute, external interface. According to the simulation verification requirements, configure the connection relationship between the component model, stimulus model, and top-level module placed in the modeling area. The connection relationship is used to represent the input / output relationship and data flow direction of data between the component model, stimulus model, and top-level module. During the modeling process, set the properties and configured connection relationships and automatically add them to the verification code corresponding to the UVM component model. During or after the modeling process, edit the verification code manually; among them, prompt the position where code needs to be added for different component models.

6. The UVM-based simulation modeling system according to any one of claims 1 to 4, characterized in that, The coverage statistics module is specifically used to perform at least one of the following functions: During the simulation process, track and count the current coverage situation by generating a corresponding coverage collection file. According to the simulation verification requirements, support selecting whether to count the coverage of the UVM component model. According to the simulation verification requirements, support collecting the coverage of the target signal, and after setting the coverage points and adding the corresponding coverage collection statement code, automatically count the hit situation and hit times of each coverage point. Set and adjust design constraints based on the obtained coverage point coverage, and monitor the coverage change in real time; View and modify the coverage collection code corresponding to the current UVM component model as needed.

7. The UVM-based simulation modeling system according to any one of claims 1 to 4, characterized in that The script generation module is specifically used to perform at least one of the following functions: Automatically generate a Makefile during the modeling process; Automatically generate a synopsys_sim.setup file according to the selected ISE version and chip version information; Automatically generate a test_lib.sv file according to the naming and modeling information; Automatically generate the corresponding UVM component model sv file according to the instantiated UVM component model, its attributes, verification code, and connection relationship; Generate a coverage collection file according to the coverage collection information set during the modeling process, and collect coverage information in real time during the subsequent VCS tool simulation process; The coverage collection file includes: basic information for coverage collection; Automatically generate an environment file according to the instantiated env component model and related modeling information. Among them, for the UVM component models instantiated during the modeling process, corresponding instantiation codes will be added to the verification code of the generated environment file; Generate a global variable file, and the local variable file includes: global variables named during the modeling process and coverage collection events; Generate a top-level module file, and the top-level module file includes: my_if.sv file and top_tb.sv file; the my_if.sv file includes: a full interface module and a special interface module; the top_tv.sv file includes: clock signal setting information, reset signal setting information, precision setting information, and top-level module call content.

8. The simulation modeling system based on UVM according to claim 4, wherein The server call module is specifically used for: Automatically connect to the VCS simulation environment on the server according to the selected saved server information, and perform simulation verification based on the generated modeling files; among them, the versions of the simulation environments installed on the server include: VCS2011, VCS2014, and VCS2016.

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